5962-9756301HXC [ADI]
10-Bit, 100 MSPS A/D Converter; 10位， 100 MSPS A / D转换器
| 型号： | 5962-9756301HXC |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 100 MSPS A/D Converter |
| 文件： | 总16页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 100 MSPS
A/D Converter
a
AD9070
FEATURES
FUNCTIONAL BLOCK DIAGRAM
10-Bit, 100 MSPS ADC
Low Power: 600 mW Typical at 100 MSPS
On-Chip Track/Hold
VREF
IN
VREF
REF
OUT COMP BYPASS
230 MHz Analog Bandwidth
SINAD = 54 dB @ 41 MHz
On–Chip Reference
1 V p-p Analog Input Range
Single Supply Operation: +5 V or –5 V
Differential Clock Input
SOIC (BR)
PACKAGE
ONLY
–2.5V
AD9070
AIN
ADC
DAC
ADC
T/H
10
AIN
D9 – D0
ENCODE
LOGIC
SUM
AMP
Available in Standard Military Drawing Version
OR
ENCODE
TIMING
APPLICATIONS
Digital Communications
Signal Intelligence
Digital Oscilloscopes
Spectrum Analyzers
Medical Imaging
Radar
DIP
PACKAGE
ONLY
ENCODE
GND
V
EE
HDTV
GENERAL DESCRIPTION
The input amplifier supports single-ended interfaces. An
internal –2.5 V reference is included in the SOIC packaged
device (an external voltage reference is required for the DIP
version).
The AD9070 is a monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and ECL
digital interfaces. The product operates at a 100 MSPS
conversion rate with outstanding dynamic performance over
its full operating range.
Fabricated on an advanced bipolar process, the AD9070
is available in a plastic SOIC package specified over the
industrial temperature range (–40°C to +85°C), and a full
MIL-PRF-38534 QML version (–55°C to +125°C) in a
ceramic Dual-in-Line Package (DIP).
The ADC requires only a single –5 V supply and an encode
clock for full performance operation. The digital outputs are
ECL compatible, while a differential clock input accommodates
a wide range of logic levels. The AD9070 may be operated in a
Positive ECL (PECL) environment with a single +5 V supply.
An Out-of-Range output (OR) is available in the DIP version to
indicate that a conversion result is outside the operating range.
In both package styles, the output data are held at saturation
levels during an out-of-range condition.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(VEE = –5 V, ENCODE = 100 MSPS, outputs loaded with 100 ⍀ to –2 V unless
otherwise noted)
AD9070–SPECIFICATIONS
Test
Temp Level Min
AD9070BR
5962-9756301HXC
Parameter
Typ
Max
Min
Typ
Max
Units
RESOLUTION
10
10
Bit
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
Full
+25°C
Full
I
VI
I
VI
VI
I
VI
V
0.6
0.7
0.6
+1.25/–1.0
+1.5/–1.0
1.5
0.6
0.9
0.6
1.5
+1.25/–1.0 LSB
+2.00/–1.0 LSB
Integral Nonlinearity
1.5
2.25
LSB
LSB
0.9
Guaranteed
1
No Missing Codes
Gain Error1
Guaranteed
4
1
2
130
4
6
% FS
% FS
Gain Tempco1
Full
115
ppm/°C
ANALOG INPUT
Input Voltage Range (with Respect to AIN)
Common-Mode Voltage
Input Offset Voltage
Full
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
Full
V
V
I
I
I
I
V
I
I
V
512
–2.5 0.2
512
–2.5 0.2
mV p-p
V
mV
mV
kΩ
7
8
40
40
3
75
75
230
18
7
9
40
40
3
75
75
230
18
20
Input Resistance
10
10
10
kΩ
pF
µA
µA
Input Capacitance
Input Bias Current
200
200
200
Analog Bandwidth, Full Power
+25°C
MHz
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
Full
Full
VI
V
–2.4
100
–2.5
170
–2.6
N/A
N/A
V
ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulse Width High (tEH
Encode Pulse Width Low (tEL
Aperture Delay (tA)
Full
Full
+25°C IV
+25°C IV
+25°C
+25°C
Full
Full
Full
Full
VI
IV
100
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
40
13
13
40
13
13
)
)
4.5
4.5
4.5
4.5
V
V
VI
VI
VI
VI
0.85
2.5
2.6
3.0
0.5
0.5
0.85
2.5
2.6
3.0
0.5
0.5
Aperture Uncertainty (Jitter)
Output Valid Time (tV)2
1.5
1.5
2
Output Propagation Delay (tPD
Output Rise Time (tR)
Output Fall Time (tF)
)
4.0
4.0
1.2
1.2
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full
Full
Full
Full
IV
IV
VI
VI
V
–1.1
–0.4
–1.5
10
–1.1
–0.4
–1.5
10
V
V
µA
µA
pF
10
10
+25°C
3
3
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Output Coding
Full
Full
VI
VI
–1.1
–1.15
V
V
–1.65
–1.60
Twos Complement
Twos Complement
POWER SUPPLY
VEE Supply Current (VEE = –5 V)
Full
Full
+25°C
VI
VI
I
80
400
120
600
0.005
150
750
0.012
80
400
120
600
0.005
150
750
0.012
mA
mW
V/V
Power Dissipation3
Power Supply Sensitivity4
REV. B
–2–
AD9070
Test
AD9070BR
5962-9756301HXC
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Units
DYNAMIC PERFORMANCE5
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
+25°C
+25°C
V
V
3
4
3
4
ns
ns
fIN = 10.3 MHz
+25°C
Full
+25°C
Full
I
V
I
55
54
57
56
56
55
55
54
57
55
56
54
dB
dB
dB
dB
f
IN = 41 MHz
V
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
fIN = 10.3 MHz
+25°C
Full
+25°C
Full
I
V
I
54
51
56
55
54
53
54
51
56
54
54
52
dB
dB
dB
dB
f
IN = 41 MHz
V
Effective Number of Bit
fIN = 10.3 MHz
fIN = 41 MHz
+25°C
+25°C
I
I
8.8
8.3
9.2
8.9
8.8
8.3
9.2
8.9
Bits
Bits
2nd Harmonic Distortion
fIN = 10.3 MHz
fIN = 41 MHz
+25°C
+25°C
I
I
63
58
70
63
63
58
70
63
dBc
dBc
3rd Harmonic Distortion
fIN = 10.3 MHz
fIN = 41 MHz
+25°C
+25°C
I
I
65
57
71
61
65
57
71
61
dBc
dBc
Two-Tone Intermod Distortion (IMD)
fIN = 10.3 MHz
fIN = 41 MHz
+25°C
+25°C
V
V
70
60
70
60
dBc
dBc
NOTES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed –2.5 V external reference).
2tV and tPD are measured from the threshold crossing of the ENCODE input to the 50% levels of the digital outputs. The output ac load during test is 10 pF.
3Power dissipation is measured under the following conditions: fS 100 MSPS, analog input is –1 dBfs at 10.3 MHz. Power dissipation does not include the current of
the external ECL pull-down resistors that set the current in the ECL output followers.
4A change in input offset voltage with respect to a change in VEE
.
5SNR/harmonics based on an analog input voltage of –1.0 dBfs referenced to a 1.024 V full-scale input range.
Typical thermal impedance for the R style (SOIC) 28-lead package:
θ
JC = 23°C/W, θCA = 48°C/W, θJA = 71°C/W.
Typical thermal impedance for the DH style (Ceramic DIP) 28-lead package:
θJC = 8°C/W, θCA = 43°C/W, θJA = 51°C/W.
Contact DSCC to obtain the latest revision of the 5962-9756301 drawing.
Specifications subject to change without notice.
SAMPLE N–1
SAMPLE N
SAMPLE N+3
SAMPLE N+4
AIN
SAMPLE N+1
1/fs
SAMPLE N+2
tA
tEH
tEL
ENCODE
ENCODE
tPD
tV
D9–D0
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
DATA N+1
Figure 1. Timing Diagram
REV. B
–3–
AD9070
ABSOLUTE MAXIMUM RATINGS*
Table I. Output Coding
Twos
VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . VEE –1 V to +1.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0.0 V
VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . VEE to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
Step
AIN–AIN
Code
Complement
OR
1024
1023
1022
≥ 0.512 V
0.511 V
0.510 V
>511
511
01 1111 1111
01 1111 1111
1
0
0
•
•
•
0
0
0
•
•
•
510
01 1111 1110
•
•
•
•
•
•
•
•
•
•
•
1
•
513
512
511
•
0.001 V
0.000 V
–0.001 V
•
00 0000 0001
00 0000 0000
11 1111 1111
•
0
–1
•
•
•
•
•
•
•
•
•
EXPLANATION OF TEST LEVELS
Test Level
1
–0.511 V
–0.512 V
≤ –0.513 V
–511
–512
<512
10 0000 0001
10 0000 0000
10 0000 0000
0
0
1
0
–1
I
– 100% production tested.
II – 100% production tested at +25°C and sample tested at
specified temperatures.
III – Sample tested only.
ORDERING GUIDE
Temperature Range Package Option*
IV – Parameter is guaranteed by design and characterization
testing.
Model
AD9070BR
AD9070/PCB
5962-9756301HXC –55°C to +125°C
–40°C to +85°C
+25°C
R-28
Evaluation Board
DH-28
V
– Parameter is a typical value only.
VI – 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes
for military devices.
*DH = Ceramic DIP; R = Small Outline IC (SOIC).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9070 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–4–
AD9070
PIN FUNCTION DESCRIPTIONS
Function
Pin Numbers
AD9070BR
AD9070DIP
D Package
R Package
Name
1, 7, 12, 21, 23
1, 7, 9, 14, 21
VEE
Negative Power Supply. Nominally –5.0 V.
Ground.
2, 8, 11, 20, 22
2, 6, 8, 10, 13, 15, 22 GND
3
N/A
VREF OUT
Internal Reference Output (–2.5 V typical); Bypass with 0.1 µF to Ground.
4
3
VREF IN
COMP
Reference Input for ADC (–2.5 V typical).
5
N/A
Internal Amplifier Compensation, 0.1 µF to VEE.
6
N/A
REF BYPASS Reference Bypass Node, 0.1 µF to VEE.
9
4
AIN
Analog Input – Complement.
10
5
AIN
Analog Input – True.
13
11
ENCODE
ENCODE
D9–D0
OR
Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE).
Encode Clock Complement (ADC Samples on Falling Edge of ENCODE).
Digital Outputs of ADC. D9 is the MSB. Data is twos complement.
14
12
28–24, 19–15
N/A
27–23, 20–16
28
Out-of-Range Output. Goes HIGH when the converted sample is more
positive than 1FFh or more negative than 200h (Twos Complement Coding).
PIN CONFIGURATIONS
Ceramic DIP
SOIC
28 OR
28 D9 (MSB)
27 D8
26 D7
25 D6
24 D5
23
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
V
EE
V
EE
27 D9 (MSB)
26 D8
GND
VREF IN
AIN
GND
VREF OUT
VREF IN
25 D7
24 D6
AIN
COMP
23 D5
GND
REF BYPASS
V
EE
AD9070DIP
TOP VIEW
(Not to Scale)
AD9070BR
TOP VIEW
(Not to Scale)
22
21
20
19
18
17
16
15
22
21
20
19
18
17
16
15
GND
GND
V
V
EE
EE
GND
V
GND
V
EE
EE
D4
GND
D4
V
AIN
EE
GND 10
D3
AIN 10
ENCODE 11
D2
GND 11
D3
12
D1
V
12
13
14
D2
ENCODE
EE
GND 13
D0 (LSB)
GND
D1
ENCODE
V
ENCODE
D0 (LSB)
14
EE
REV. B
–5–
AD9070–Typical Circuit Applications
AIN
AIN
D9 – D0
OR
V
V
EE
EE
Figure 5. Equivalent Digital Output Circuit
Figure 2. Equivalent Analog Input Circuit
VREF
OUT
VREF IN
V
EE
V
EE
Figure 6. Equivalent Reference Output Circuit
Figure 3. Equivalent Reference Input Circuit
ENCODE
ENCODE
V
EE
Figure 4. Equivalent Encode Input Circuit
REV. B
–6–
Typical Performance Characteristics–AD9070
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
FUNDAMENTAL = –1.0dBfs
SNR = 58.5dB
SINAD = 58.0dB
2nd HARMONIC = –76.8dB
3rd HARMONIC = –68.1dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
F1 = 40.1MHz
F2 = 41.0MHz
F1 = F2 = –7.0dBfs
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
MHz
MHz
Figure 10. Two Tone Intermodulation Distortion
Figure 7. Spectrum: fS = 100 MSPS, fIN = 10 MHz
60
55
0
FUNDAMENTAL = –1.0dBfs
SNR = 56.8dB
–10
SINAD = 55.0dB
2nd HARMONIC = –66.6dB
3rd HARMONIC = –60.8dB
SNR
–20
50
–30
45
–40
–50
–60
–70
–80
–90
–100
SINAD
40
NYQUIST
FREQUENCY
(50 MHz)
35
30
25
20
0
20
40
60
80
100
120
140
160
0
5
10
15
20
25
30
35
40
45
50
F
– MHz
MHz
IN
Figure 8. Spectrum: fS = 100 MSPS, fIN = 40 MHz
Figure 11. SNR vs. fIN; fS = 100 MSPS
60
58
56
54
52
50
48
46
44
42
40
0
F1 = 9.57MHz
F2 = 10.3MHz
F1 = F2 = –7.0dBfs
–10
SNR
–20
SINAD
–30
–40
–50
–60
–70
–80
–90
–100
0
20
40
60
80
– MSPS
100
120
140
160
0
5
10
15
20
25
MHz
30
35
40
45
50
F
S
Figure 12. SNR vs. fS: fIN = 10.3 MHz
Figure 9. Two Tone Intermodulation Distortion
REV. B
–7–
AD9070
60
59
58
57
56
55
54
53
52
51
50
60
59
58
57
SNR
SINAD
56
55
F
F
= 100MSPS
= 10.1MHz
S
F
F
= 100MSPS
= 10.1MHz
S
IN
54
53
52
IN
51
50
0
1
2
3
4
5
6
7
8
9
10
ENCODE PULSEWIDTH – ns
–60 –40 –20
0
20
40
– ؇C
60
80
100 120 140
T
C
Figure 13. SNR vs. TC: BR Package (SOIC)
Figure 15. SNR vs. Clock Pulse Width (tEH
)
60
0
–1
–2
59
58
57
SNR
SINAD
56
55
NYQUIST
FREQUENCY
50MHz
–3
F
F
= 100MSPS
= 10.1MHz
S
54
53
52
IN
–4
–5
51
50
0
50
100
150
– MHz
200
250
300
–60 –40 –20
0
20
40
– ؇C
60
80
100 120 140
F
IN
T
C
Figure 14. SNR vs. TC: DIP Package
Figure 16. Frequency Response
REV. B
–8–
AD9070
recommended. A better approach is to develop the required
voltage from the internal or external converter voltage reference
(VREF OUT).
APPLICATION NOTES
Theory of Operation
The AD9070 employs a two-step subranging architecture with
digital error correction.
Very small timing errors can reduce the performance of an A/D
dramatically. Total jitter of only 3.2 ps will limit the perfor-
mance of an A/D sampling a full-scale 50 MHz signal to nine
effective bits. The AD9070’s specified aperture jitter of 2.5 ps
leaves only 2.0 ps of jitter budget for the clock source (an RSS
calculation).
The sampling and conversion process is initiated by a rising
edge at the ENCODE input. The analog input signal is
buffered by a high speed differential amplifier and applied to a
track-and-hold (T/H) circuit that captures the value of the
input at the sampling instant and maintains it for the duration
of the conversion.
The cleanest clock source is only a crystal oscillator producing a
pure sine wave. In this configuration, or with any roughly
symmetrical clock input, the input can be ac coupled and biased
to a reference voltage that also provides the ENCODE input
(Figure 17). This ensures that the reference voltage is centered
on the ENCODE signal.
The coarse quantizer (ADC) produces a five-bit estimate of the
input value. Its digital output is reconverted to analog form by
the reconstruction DAC and subtracted from the input signal in
the SUM AMP. The second stage quantizer generates a six-bit
representation of the difference signal. The eleven bits are
presented to the ENCODE LOGIC, which corrects for range
overlap errors and produces an accurate ten-bit result.
Digital Outputs
The digital outputs are compatible with 10K ECL logic. The
suggested pull-down is 100 Ω to –2 V. However, to reduce
power consumption, higher value pull-down resistors can be
used when driving very low capacitance loads or at reduced
encode rates. The falling edge slew rate of the output bits will be
degraded with higher value pull-down resistors.
Data are strobed to the output on the rising edge of the ENCODE
input, with the data from sample N appearing on the output
following ENCODE rising edge N+3.
USING THE AD9070
ENCODE Input
Analog Input
Any high speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A Track/Hold circuit is
essentially a mixer, and any noise, distortion or timing jitter on
the clock will be combined with the desired signal at the A/D
output. For that reason, considerable care has been taken in the
design of the ENCODE input of the AD9070 and the user is
advised to give commensurate thought to the clock source.
The analog input to the AD9070 is a differential amplifier, but
the design has been optimized for a single-ended input. The
AIN input should be connected or bypassed to the ground
reference of the input signal. For best dynamic performance,
impedances at AIN and AIN should match.
The circuit in Figure 18 illustrates a simple ac-coupled inter-
face. The midscale input voltage and the AIN levels are both
provided by the internal reference (VREF OUT).
The ENCODE input is fully differential and may be operated in
a differential or a single-ended mode. It has a common-mode
range of –1 V to –3 V, and is easily driven by a differential ECL
driver. Proper termination at the A/D is important.
0.1F
GND
V
IN
1Vp-p
–5V
AIN
AD9070
500⍀
R
AIN
T
D9
(MSB) D9
500⍀
510⍀
V
GND
EE
(OR 100⍀ TO –2V)
VREF OUT
VREF IN
0.1F
AD9070
–5V
0.1F
CLK
IN
(1Vp-p)
ENCODE
(LSB) D0
D0
ENCODE
ENCODE
ENCODE
510⍀
(OR 100⍀ TO –2V)
10k⍀
1k⍀
R
T
ENCODE
REF
EE BYPASS
ENCODE
V
COMP
–5V
0.1F
3k⍀
–5V
0.1F
0.1F
Figure 17. Single-Ended ENCODE: AC Coupled
–5V
In single-ended mode, the ENCODE input must be tied to an
appropriate reference voltage, generally midway between the
high and the low levels of the incoming logic signal. Many ECL
circuits provide a VBB reference voltage intended for this
purpose. If a reference voltage is produced by dividing the
power supply voltage, any noise on the supply used will couple
to the clock input and then to the output data. This is not
Figure 18. AD9070 in –5 V (ECL) Environment
REV. B
–9–
AD9070
Figure 19 shows typical connections for the analog inputs when
using the AD9070 in a dc-coupled system with single-ended
signals. The AD820 is used to offset the ground referenced
input signal to the level required by the AD9070. A very high
performance amplifier, such as the AD9631, is required to avoid
degrading the analog signal presented to the ADC. A buffered
ac interface is easily implemented, with even fewer components
(Figure 20).
The input is protected to one volt outside of the power supply
rails. For nominal power (–5 V and ground), the analog input
will not be damaged with signals ranging from –6.0 V to +1.0 V.
Voltage Reference
A stable and accurate –2.5 V voltage reference is built into the
AD9070 (VREF OUT) in the SOIC (BR) package. In normal
operation, the internal reference is used by strapping Pins 3
and 4 of the AD9070 together. The internal reference can
provide 100 µA of extra drive current that may be used for other
circuits.
–5V
350⍀
+5V
Some applications may require greater accuracy, improved
temperature performance or adjustment of the gain of the
AD9070, which cannot be obtained by using the internal
reference. For these applications, an external –2.5 V reference
can be connected to VREF IN, which requires 5 µA of drive
current (Figure 21).
V
GND
350⍀
EE
V
IN
؎0.5V
AIN
R
T
AD9631
–5V
AD9070
0.1F
1k⍀
1k⍀
–5V
AIN
AD820
–5V
0.1F
1k⍀
VREF OUT
VREF IN
GND
V
EE
VREF OUT
NC
0.1F
+V
IN
AD9070
AD780
GND
VREF IN
V
OUT
Figure 19. DC-Coupled Input
0.1F
1.25k⍀
–5V
350⍀
–5V
Figure 21. Using the AD780 Voltage Reference
+5V
V
EE GND
V
350⍀
0.1F
IN
0.1F
1Vp-p
The input range can be adjusted by varying the reference
voltage applied to the AD9070. No appreciable degradation in
performance occurs when the reference is adjusted 4%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
AIN
R
T
AD9631
500⍀
500⍀
–5V
AD9070
AIN
0.1F
Timing
VREF OUT
VREF IN
The performance of the AD9070 is insensitive to the duty cycle
of the clock over a wide range of operating conditions: pulse
width variations of as much as 20% will cause no degradation
in performance (see Figure 15).
0.1F
Figure 20. AC-Coupled Input
The AD9070 provides latched data outputs, with three pipeline
Special care was taken in the design of the analog input section
of the AD9070 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is –1.988 V to
–3.012 V (1.024 V p–p centered at –2.5 V). Out-of-range
comparators detect when the analog input signal is out of this
range and set the OR output signal HIGH. The digital outputs
are locked at plus or minus full scale (1FFh or 200h) for
voltages that are out of range but between –1 V and –5 V. Input
voltages outside of this range may result in invalid codes at the
ADCs output.
delays. Data outputs are available one propagation delay (tPD
after the rising edge of the encode command (Figure 1). The
length of the output data lines and loads placed on them should
be minimized to reduce transients within the AD9070; these
transients can detract from the converter’s dynamic performance.
)
The minimum guaranteed conversion rate of the AD9070 is
40 MSPS. At clock rates below 40 MSPS, dynamic performance
may degrade. The AD9070 will operate in bursts, but the user
must flush the internal pipeline each time the clock restarts.
Valid data will be produced on the fourth rising edge of the
ENCODE signal after the clock is restarted.
When the analog input signal returns to the nominal range, the
out-of-range comparators return the ADC to its active mode
and the device recovers in approximately 3 ns.
REV. B
–10–
AD9070
+5 V Operation
Package Options
The AD9070 may be operated above ground, with a single +5 V
power supply. All power supply ground pins are connected to
+5 V, and VEE pins are connected to ground (Figure 22). Care
must be taken in connecting signals and determining bypass rails.
The AD9070 is available in two packages. The BR package is a
standard 28-lead Small Outline IC (SOIC). The DIP package is
a ceramic Dual-in-Line Hybrid. The SOIC is offered in a commer-
cial grade, and specified over the industrial (–40°C to +85°C)
temperature range. The DIP is a full MIL-PRF-38534 QML
version that operates from (–55°C to +125°C).
The reference voltage (REF OUT) is still generated with respect
to the positive rail, which is now +5 V. It is nominally +2.5 V,
but its voltage with respect to ground will vary directly with
changes in the power supply voltage (for example, if the power
supply goes to +5.1 V, the reference becomes +2.6 V). The
reference input is likewise processed with respect to +5 V. This
dictates that these pins be bypassed to +5 V as well. However,
the COMP and REF BYPASS pins must continue to be
bypassed to the most negative supply, which is now ground. The
AIN input must still be connected or bypassed to the ground
reference of the input signal.
The SOIC version includes the on-chip voltage reference,
whereas the DIP does not. The DIP, however, provides the
Overrange (OR) output, and includes reference and power
supply bypassing, along with an internal compensation capacitor.
Equivalent performance may be obtained with either part
though, due to the internal bypassing, the DIP is not as sensitive
to board layout and parasitics.
+5V
0.1F
V
GND
IN
1Vp-p
AIN
R
500⍀
T
AD9070
AIN
10H
D9
(MSB) D9
VREF OUT
VREF IN
510⍀
(OR 100⍀ TO +3V)
0.1F
0.1F
+5V
D0
510⍀
(OR 100⍀ TO +3V)
(LSB) D0
REF
ENCODE
ENCODE
ENCODE
ENCODE
V
EE
BYPASS
COMP
0.1F
0.1F
Figure 22. AD9070 in +5 V (PECL) Environment
REV. B
–11–
AD9070
Data Out
AD9070BR EVALUATION BOARD
Data goes single-ended into the 10H116 flip flops but comes
out differentially. The data coming out of the AD9070 is in twos
complement format, but is changed to straight binary by
inverting the MSB at the connector (on the schematic Bit 1 and
Bit 1B are swapped).
E1
AD780 REFERENCE
E2
E3
VREF OUT
VREF IN
1 OF 2
10H176
1k⍀
AIN
TO CARD
HEX D FF CONNECT
COMP
1k⍀
–5V
Voltage Reference
50⍀
BYPASS
The AD9070 can be operated using its internal bandgap
reference (connect E2 to E3) or the on board AD780 external
reference (connect E1 to E3). The board is shipped utilizing the
internal voltage reference.
AIN
AD9070
1 OF 4
AIN
10H116
ENC ENC
CLK
J2
J4
10H176
ECL
Layout
50⍀
RECVR
The AD9070 is not layout sensitive if some important guide-
lines are met. The evaluation board layout provides an
example where these guidelines have been followed to
optimize performance.
E4
E6
E5
PIN 2
E19
E9
CLKB
BUFFERED
AND
LATCHED
ON-CARD
ENCODE
E8
CARD
CONNECTOR
50⍀
• Provide a good ground plane connecting the analog and
digital sections.
E7
• Excellent bypassing is essential. Chip caps with 0.1 µF values
and 0603 dimensions are placed flush against the pins.
Placing any of the caps on the bottom of the board can
degrade performance. These techniques reduce the amount
of parasitic inductance which can impact the bypassing ability
of the caps.
PIN 21
Figure 23.
The AD9070 evaluation board is a convenient and easy way to
evaluate the performance of the AD9070 in the SOIC package.
The board consists of an AD780 voltage reference (configured
for –2.5 V), two 10H176 (hex D flip flop) for capturing data
from the A/D converter and five 10H116 triple line receivers for
buffering the encode signal and driving the data via the edge
connector. Termination resistors (RP11, RP12, and RP14) are
provided for the data leaving the board via the connector; (they
can be removed if termination resistors are already provided by
the user).
• Separate power planes and supplies for the analog and digital
sections are recommended.
The AD9070 evaluation board is provided as a design example
for customers of Analog Devices. ADI makes no warranties
express, statutory, or implied regarding merchantability or
fitness for a particular purpose.
Analog Input
The evaluation board requires a 1 V peak-to-peak signal
centered at ground (J1). This signal is ac coupled and then dc
shifted –2.5 V before it is input to the A/D converter.
Encode
The AD9070 encode inputs can be driven single ended
(connect E9 to E19 and drive J2 with an ECL signal) or
differentially (connect E8 to E19 and drive J2 and J4 with
differential ECL signals). The board is shipped in single ended
configuration. The differential encode signal leaving the board
via the connector can be inverted by interchanging E4, E5, E6,
and E7 (connect E4 to E7 and E5 to E6 or E4 to E6 and E7 to
E5). This ensures that the user will be able to capture the data
coming from the evaluation board.
REV. B
–12–
AD9070
Figure 24. Evaluation Board Schematic
REV. B
–13–
AD9070
Figure 25. Component Side
Figure 27. Bottom Side Trace + Components
Figure 28. Analog/Digital Split Power Plane
Figure 26. Component Side Signal Traces
REV. B
–14–
AD9070
Table II. Evaluation Board Bill of Materials
DESCRIPTION
ITEM QTY
REFD
1
2
3
5
2
4
U7–U11
U5, U15
RP11, RP12, RP14, RP15
10H116 – TRIPLE DIFFERENTIAL LINE RECEIVER
10H176 – 10KH HIGH SPEED ECL
10PT-5.2 – 10P TER RES NTWK
4
1
RP9
6PB-5.2 – 6P BUSED RES NTWK
5
6
2
3
TB1, TB2
RP1, RP2, RP7
8291Z2 – 2-PIN TERMINAL BLOCK
8PB-5.2 – 8P BUSED RES NTWK
7
8
1
1
U2
U1
AD780N – HIGH PREC VOLT REF
AD9070R – AD9070 SOIC ECL ADC
9
10
10
24
C3, C4, C6, C7, C8, C32, C34, C35, C37, C52 BCAP0603 – CER CHIP CAP 0603, .1 µF
C11, C12, C14–C18, C20, C22–C26, C28,
BCAP0805 – CER CHIP CAP 0805, .1 µF
C38–C44
C29, C58
J1, J2, J4
R1
R16
R4, R6
11
12
13
14
15
16
17
18
2
3
1
1
2
1
4
1
BCAPTAJD – CHIP TANT CAP, 10 µF
BNC – BNC COAX CONN PCMT
BRES1206 – SURF MT RES 1206, 1.25K
BRES1206 – SURF MT RES 1206, 160
BRES1206 – SURF MT RES 1206, 1K
BRES1206 – SURF MT RES 1206, 260
BRES1206 – SURF MT RES 1206, 50
C37DRPF – 37P D CONN RT ANG PLASTIC PCMT
FEMALE
R15
R2, R3, R5, R10
CON1
19
20
1
10
C2
T330A – TANT CAP, 1 µF
W-HOLE – WIRE HOLE
E1–E9, E19
REV. B
–15–
AD9070
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28–Lead SOIC
(R–28)
0.7125 (18.10)
0.6969 (17.70)
28
15
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
28-Lead Hermetic Ceramic DIP
(DH-28)
28
15
0.595 0.010
(15.11 0.25)
1
14
PIN 1 IDENTIFIERS
0.050 0.010
(1.27 0.25)
1.400 0.014
(35.56 0.35)
0.225
(5.72)
MAX
0.150
(3.81)
MIN
0.010 0.002
(0.25 0.05)
0.600 (15.24)
REF
0.100 (2.54)
TYP
0.018 0.002
(0.46 0.05)
0.05 (1.27)
TYP
SEATING
PLANE
–16–
REV. B
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