AD1317KZ [ADI]
Ultrahigh Speed Window Comparator with Latch; 超高速窗口比较器与锁存器
| 型号： | AD1317KZ |
| 厂家： | 
ADI |
| 描述： | Ultrahigh Speed Window Comparator with Latch |
| 文件： | 总12页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultrahigh Speed
Window Comparator with Latch
a
AD1317
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Full Window Comparator
2.0 pF max Input Capacitance
9 V max Differential Input Voltage
2.5 ns Propagation Delays
Low Dispersion
Low Input Bias Current
Independent Latch Function
Input Inhibit Mode
80 dB CMRR
APPLICATIONS
High Speed Pin Electronic Receiver
High Speed Triggers
Threshold Detectors
Peak Detectors
PRODUCT DESCRIPTION
outputs are ECL compatible. The output stage is capable of
driving a 50 Ω line terminated to –2 V. The AD1317 also pro-
vides a latch function, allowing operation in a sample-hold
mode. The latch inputs can also be used to generate hysteresis.
The AD1317 is an ultrahigh speed window comparator with a
latch. It uses a high speed monolithic process to provide high dc
accuracy without sacrificing input voltage range. The AD1317
guarantees a 2.8 ns maximum propagation delay.
The comparator input can be switched into a high impedance
state through the inhibit mode feature, electrically removing the
comparator from the circuit. The bias current in inhibit mode is
typically 50 pA.
On-chip connection of the common input eliminates the contri-
butions of a second bonding pad and package pin to the input
capacitance, resulting in a maximum input capacitance of 2 pF.
The dispersion, or variation in propagation delay with input
overdrive levels and slew rates, is typically 350 ps for 5 V signals
and 200 ps for 1 V inputs.
The AD1317 is available in a small 16-lead, hermetically sealed
“gull-wing” surface mount package and operates over the com-
mercial temperature range, 0°C to +70°C.
The AD1317 employs a high precision differential input stage
with a common-mode range of 9 V. Its complementary digital
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1997
AD1317–SPECIFICATIONS (All specifications at +25؇C, free air. Outputs terminated into 50 ⍀ to –2 V,
with + VS = +10 V, –VS = 5.2 V unless otherwise noted)
AD1317KZ
Typ
Parameter
Symbol
Min
Max
Units
Comments
DC INPUT CHARACTERISTICS
Offset Voltage
Offset Drift
VINA/B Bias Currents
Active
Inhibit
VOS
dVOS/dT
–10
10
mV
µV/°C
CMV = 0 V
–2 V to +7 V
20
Ibca
Ibci
10
50
33
µA
pA
VINA, VINB Bias Currents
Active
–2 V to +7 V
Ibsa
5
16.5
µA
Inhibit
Ibsi
50
4
8
pA
VINA/B Resistance
VINA, VINB Resistance
Capacitance VINA/B, VINA, VINB
Voltage Range
Differential Voltage
Common-Mode Rejection Ratio
Rinc
Rins
CIN
VCM
VDIFF
CMRR
MΩ
MΩ
pF
Volts
Volts
dB
1.5
2.0
7
9
–2
70
See Note 5
80
–2 V to +7 V
LATCH ENABLE INPUTS
Input Voltage, Any Input
Differential Voltage
Logic “1” Current
–2.0
0.4
5.0
4
10
Volts
Volts
µA
IIH
IIL
Logic “0” Current
–200
µA
Capacitance
4
pF
INPUT ENABLE CURRENTS
Input Voltage, Any Input
Differential Voltage
Logic “1” Current
–2.0
0.4
5.0
4
20
Volts
Volts
µA
IIH
IIL
Logic “0” Current
–200
µA
Capacitance
4
pF
DIGITAL OUTPUTS
Logic “l” Voltage
Logic “0” Voltage
VOH
VOL
–0.98
Volts
Volts
–1.50
SWITCHING PERFORMANCE
Propagation Delays
Input to Output
Latch Enable to Output
Active to Inhibit
Inhibit to Active
Propagation Delay T.C.
Dispersion
See Figure 3
tPDR, tPDF
1.8
2.0
2.5
15
5
2.8
2.5
ns
ns
ns
ns
See Note 1
See Note 1
See Note 2
See Note 3
tLO
tIN
tIE
ps/°C
See Note 4
5 V Signal
See Figure 1
All Edges
Rising Edge
Falling Edge
1 V Signal
All Edges
Rising Edge
Falling Edge
450
350
350
600
400
ps
ps
ps
See Figure 2
250
200
200
ps
ps
ps
LATCH TIMING
Input Pulse Width
Setup Time
tPW
tS
tH
2.5
1.5
0
1.0
0.4
ns
ns
ns
Hold Time
POWER SUPPLIES
–VS to +VS Range
Positive Supply
Negative Supply
Positive Supply Current
Negative Supply Current
PSRR
15.2
10.0
–5.2
50
–70
75
15.6
11.0
–4.2
70
See Note 5
+VS
–VS
I+
8.0
–7.2
Volts
Volts
mA
mA
dB
I–
–100
65
Measured at ±2.5% of +VS and –VS
NOTES
1Propagation Delay is measured from the input threshold crossing at the 50% point of a 0 V to 5 V input to the output Q and Q crossing.
2Propagation Delay is measured from the input crossing of IE and IE to when the input bias currents drop to 10% of their nominal value.
3Propagation Delay is measured from the input crossing of IE and IE to when the input bias currents rise to 90% of their nominal value.
4Dispersion is measured with input slew rates of 0.5 V/ns and 2.5 V/ns for 5 V swings, 0.5 V/ns and 1 V/ns for 1 V swings.
5The comparator input voltage range is specified for –2 V to +7 V for typical power supply values of -5.2 V and +10.0 V but can be offset for different input ranges such as –1 V to
+8 V with power supplies of –4.2 V and +11 V, as long as the required headroom of 3 V is maintained between both VH and +VS and VL and +VS.
Specifications subject to change without notice.
–2–
REV. A
AD1317
ABSOLUTE MAXIMUM RATINGS1
Power Supply Voltage
WINDOW COMPARATOR PIN ASSIGNMENT
Pin No. Description
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –9 V
Difference from +VS to –VS . . . . . . . . . . . . . . . . . . . . +16 V
Inputs
VINA/B, VINA, VINB . . . . . . . +VS – 13.5 V, –VS + 13.7 V
LEA, LEA, LEB, LEB . . . . . . . . . . +VS – 14 V, –VS + 12 V
IE, IE . . . . . . . . . . . . . . . . . . . . . . +VS – 14 V, –VS + 10.3 V
Outputs2
1
VINA
Noninverting Comparator A Input
VINA/B Window Comparator Common Input
2
3
4
VINB
IE
Inverting Comparator B Input
Input Enable
5
IE
Input Enable
6
7
8
9
10
11
12
13
14
15
16
–VS
Negative Supply, –5.2V
Ground
Positive Supply, +10 V
Latch Enable B
QA, QA, QB, QB . . . . . . . . . . GND – 0.5 V, GND + 3.5 V
Operating Temperature Range . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature Range
GND
+VS
LEB
LEB
QB
After Soldering . . . . . . . . . . . . . . . . . . . . .–65°C to + 125°C
Lead Temperature Range (Soldering 20 sec)3 . . . . . . .+300°C
Latch Enable B
NOTES
Comparator B Output
Comparator B Output
Comparator A Output
Comparator A Output
Latch Enable A
1Stresses above those limits under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Limits apply for shorted output.
QB
QA
QA
LEA
LEA
3To ensure lead coplanarity (±0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in an environment at
24°C ±5°C (75°F ±10°F) with relative humidity not to exceed 65%.
Latch Enable A
ORDERING GUIDE
Temperature
Package
Option*
Model
Range
Description
Quantity
AD1317KZ
0°C to +70°C
16-Lead
Z-16A
1-24
Gull Wing
25–99
100+
*Z = Ceramic Leaded Chip Carrier.
CONNECTION DIAGRAMS
Dimensions shown in inches and (mm).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1317 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD1317
DEFINITION OF TERMS
VOL
IOH
IOL
LOGIC “0” OUTPUT VOLTAGE—The logic low
output voltage with a specified load.
Vos
INPUT OFFSET VOLTAGE—The voltage that
must be applied between either VINA and VINA/B or
VINB and VINA/B to obtain zero voltage between
outputs QA and QA, or QB and QB, respectively.
LOGIC “1” OUTPUT CURRENT—The logic high
output source current.
LOGIC “0” OUTPUT CURRENT—The logic low
output source current.
dVOS/dT OFFSET DRIFT—The ratio of the change in input
offset voltages, over the operating temperature range,
to the change in temperature.
I+
POSITIVE SUPPLY CURRENT—The current
required from the +VS supply.
Ibca
Ibci
Ibsa
Ibsi
INPUT BIAS CURRENT (VINA/B, ACTIVE)—
The bias current of the window comparator’s com-
mon input with inputs enabled.
I–
NEGATIVE SUPPLY CURRENT—The current
required from the –VS supply.
PSRR
POWER SUPPLY REJECTION RATIO—The ratio
of power supply voltage change to the peak-to-peak
change in input offset voltage.
INPUT BIAS CURRENT (VINA/B, INHIBIT)—
The bias current of the window comparator’s com-
mon input with inputs inhibited.
INPUT BIAS CURRENT (VINA or VINB,
ACTIVE)—The bias current of either single input
with inputs active.
AD1317 SWITCHING TERMS (See Figure 3)
tPDR
INPUT TO OUTPUT RISING EDGE DELAY—
The propagation delay measured from the time
VINA/B crosses either VINA or VINB, in a low to
high transition, to the time QA and QA or QB and
QB cross, respectively.
INPUT BIAS CURRENT (VINA or VINB,
INHIBIT)—The bias current of either single input
with inputs inhibited.
Rinc
INPUT RESISTANCE (VINA/B)—The input
resistance looking into the window comparator’s
common input.
tPDF
INPUT TO OUTPUT FALLING EDGE DELAY—
The propagation delay measured from the time
VINA/B crosses either VINA or VINB, in a high to
low transition, to the time QA and QA or QB and
QB cross, respectively.
Rins
CIN
INPUT RESISTANCE (VINA or VINB)—The
input resistance looking into either single input.
tS
MINIMUM LATCH SET-UP TIME—The minium
time before LE goes high with respect to LE that an
input signal change must be present in order to be
acquired and held at the outputs.
INPUT CAPACITANCE (VINA/B)—The capaci-
tance looking into the window comparator’s common
input.
VCM
INPUT COMMON-MODE VOLTAGE RANGE—
The range of voltages on the input terminals for
which the offset and propagation delay specifications
apply.
tH
MINIMUM LATCH HOLD TIME—The minium
time after LE goes high with respect to LE that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
VDIFF
INPUT DIFFERENTIAL VOLTAGE RANGE—
The maximum difference between any input terminal
voltages.
tPW
MINIMUM LATCH ENABLE PULSE WIDTH—
The minimum time that LE must be held high with
respect to LE in order to acquire and hold an input
change.
CMRR COMMON-MODE REJECTION RATIO—The
ratio of common-mode input voltage range to the
peak-to-peak change in input offset voltage over this
range.
tLO
LATCH ENABLE TO OUTPUT DELAY—The
time between when LE goes high with respect to LE
that QA and QA or QB and QB cross.
IIH
LOGIC “1” INPUT CURRENT—The logic high
current flowing into (+) or out of (–) a logic input.
tID
INPUT STAGE DISABLE TIME—The time be-
tween when IE goes high with respect to IE that the
input bias currents drop to 10% of their nominal
value.
IIL
LOGIC “0” INPUT CURRENT—The logic low
current flowing into (+) or out of (–) a logic input.
VOH
LOGIC “1” OUTPUT VOLTAGE—The logic high
output voltage with a specified load.
tIE
INPUT STAGE ENABLE TIME—The time be-
tween when IE goes high with respect to IE that the
input bias currents rise to 90% of their nominal values.
–4–
REV. A
AD1317
Figure 1. Dispersion Test Input Conditions—5 V Signal
Figure 2. Dispersion Test Input Conditions—1 V Signal
Figure 3. Timing Diagram
REV. A
–5–
AD1317
—Typical Performance Characteristics
Figure 7. Response to Overdrive Variation—Falling Edge
Figure 4. Response to Overdrive Variation—Rising Edge
Figure 5. Response to Various Signal Levels—Rising Edge
Figure 6. Propagation Delay vs. Slew Rate
Figure 8. Response to Various Signal Levels—Falling
Edge
Figure 9. Propagation Delay vs. Temperature—Rising
Edge
–6–
REV. A
AD1317
Figure 10. Propagation Delay
vs. Temperature—Falling Edge
Figure 11. Output Waveform vs. Load
Figure 12. Propagation Delay vs.
Common-Mode Voltage
Figure 13. Voltage Gain vs. Frequency
Figure 16. Common-Mode Range vs. Power Supply
Figure 17. Input Bias Current vs. Temperature
Figure 18. Input Bias Current vs. Input Voltage
Figure 14. Output Levels vs. Temperature
Figure 15. Input Bias Current vs. Input Voltage
REV. A
–7–
AD1317 —Typical Performance Characteristics
Figure 22. Output Voltage vs. Source Current
Figure 19. Change in Bias Current vs. Input Differential
Voltage (VINA/B – VINA, VINB)
Figure 23. Inhibit Input Bias Current vs. Common-Mode
Voltage
Figure 20. Power Supply Currents vs. Temperature
Figure 24. Inhibit Input Bias Current vs. Input Voltage
(VINA/B = –2 V)
Figure 21. Inhibit Input Bias Current vs. Input Voltage
(VINA/B = 7 V)
–8–
REV. A
AD1317
FUNCTIONAL DESCRIPTION
The AD1317 is an ultrahigh speed window comparator designed
for use in general purpose instrumentation and automatic test
equipment. The internal connections for windowing operation
keep the capacitance at the critical common input (VINA/B)
well below what could normally be obtained using separate input
pins.
Another key feature is that the front end circuitry may be dis-
abled, decreasing input bias currents to 50 pA (typical). This
enables sensitive dc current testing without having to physically
disconnect the AD1317’s input from the circuit. The comparator’s
outputs would normally be latched to maintain absolute logic
levels prior to inhibiting the input.
High speed comparators using bipolar process technology usu-
ally have input bias currents in the 1 µA to 20 µA range, and the
AD1317 is no exception in this regard. This occurs because the
input devices usually have low current gain but must be oper-
ated at high currents to obtain the widest possible bandwidth.
Careful design minimizes variations in the AD1317’s bias cur-
rent with respect to both differential and common-mode input
variations. This translates directly to a high equivalent input
resistance, the minimum of which occurs with zero differential
input. The typical input resistance of the AD1317’s common
input under this condition is on the order of 4 megohms.
Figure 25. Case-to-Ambient Thermal Resistance vs. Air
Flow
DISPERSION
Propagation delay dispersion is the change in device propagation
delay which results from changes in the input signal conditions.
Dispersion is an indicator of how well the comparator’s frontend
design balances the conflicting requirements of high gain and
wide bandwidth. High gain is needed to ensure that small over-
drives will produce valid logic outputs without an increase in
propagation delay, while wide bandwidth enables the compara-
tor to handle fast input slew rates. The input signal criteria used
to determine the AD1317’s dispersion performance are ampli-
tude, overdrive and slew rate for both standard CMOS and
ECL signal levels.
Many ATE applications have required input dividers/buffers to
reduce standard logic voltages to levels which can be processed
by “687” type comparators. These dividers have also reduced
the slew rates at which the comparators must properly function.
The AD1317’s 9 volt differential and common-mode input
ranges and 2.5 V/ns slew rate capability make these buffer cir-
cuits unnecessary in most applications.
Separate, complementary latch inputs are provided for each
comparator. These may be driven by differential or single-ended
sources ranging from ECL to HCMOS logic. When using the
comparator’s transparent mode, the latch inputs may be tied
anywhere within their common-mode range with a maximum
differential of 4 V. Symmetrical hysteresis may also be generated
by applying a small differential voltage to the latch inputs (see
HYSTERESIS).
HYSTERESIS
The customary technique for introducing hysteresis into a com-
parator uses positive feedback as shown in Figure 27. The major
problems with this approach are that the amount of hysteresis
varies with the output logic levels and that the hysteresis is not
symmetrical around zero.
The AD1317’s outputs are standard emitter followers with ECL-
compatible voltage swings. The recommended output termina-
tion is 50 Ω to –2 V. Larger value termination resistors connected
to –VS may be used, but will reduce edge fidelity. Typical
output rise and fall times (20%–80%) are 1 ns with a 50 Ω,
10 pF load. The maximum output source current is 40 mA.
The AD1317 does not use this technique. Instead, hysteresis is
generated by introducing a differential voltage between LE and
LE as shown in Figure 28. Hysteresis generated in this manner
is independent of output swing and is symmetrical around zero.
The variation of hysteresis with input voltage is shown in Figure
29; the useful hysteresis range is about 20 mV.
THERMAL CONSIDERATIONS
LAYOUT CONSIDERATIONS
The AD1317 is provided in a 0.450" × 0.450", 16-lead (bottom
brazed) gull wing, surface mount package with a typical θJC
(junction-to-case thermal resistance) of 17.5°C/W. Thermal
resistance θCA (case to ambient) vs. air flow for the AD1317 in
this package is shown in Figure 25. The improvement in thermal
Like any high speed device, the AD1317 requires careful layout
and bypassing to obtain optimum performance. Oscillations are
generally caused by coupling from an output to the high imped-
ance inputs. All drive impedances should be as low as possible,
and lead lengths should be minimized. A ground plane should
be used to provide low impedance return paths. Care should be
taken in selecting sockets for incoming or other testing to mini-
mize lead inductance, and sockets are not recommended for
production use.
resistance vs. air flow begins to flatten out just above 400 lfm1, 2
.
NOTES
1lfm is airflow in linear feet/minute.
2For convection cooled systems, the minimum recommended airflow is 400 lfm.
REV. A
–9–
AD1317
Output wire lengths should be kept below one inch. Longer
connections require the use of transmission line techniques to
prevent ringing and reflections. Lines should be terminated with
their characteristic impedance to –2 V. Thevenin-equivalent
termination to –VS is also possible.
High quality RF capacitors should be used for power supply
bypassing. These should be located as closely as possible to the
AD1317’s power pins and connections to the ground plane
should have the minimum possible length. Both +VS and –VS
must be bypassed with 470 pF capacitors located within 0.25
inches of the device’s supply pins. In addition, each supply
should be bypassed with 0.1 µF ceramic and 10 µF tantalum
capacitors. Low impedance power distribution techniques will
make the locations of these components less critical. Adding
470 pF capacitors at the VINA and VINB inputs, as close as
possible to the package, will improve circuit performance and
noise immunity in dc-compare applications.
Figure 28. Comparator Hysteresis Test Setup
Figure 26. Basic Circuit Decoupling
Figure 29. Typical Hysteresis Curve
Figure 30. Hysteresis
Figure 27. Typical Comparator Hysteresis
–10–
REV. A
AD1317
Figure 31. High Speed Digital Test System Block Diagram
REV. A
–11–
AD1317
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Ceramic Leaded Chip Carrier
(Z-16A)
–12–
REV. A
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ADI
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