AD13280AF_技术文档

a^{Dual Channel, 12-Bit, 80 MSPS A/D Converter}

with Analog Input Signal Conditioning

AD13280

and performance while still maintaining excellent isolation,

and providing for significant board area savings.

FEATURES

Dual, 80 MSPS Minimum Sample Rate

Channel-to-Channel Matching, ꢀ1% Gain Error

90 dB Channel-to-Channel Isolation

DC-Coupled Signal Conditioning

80 dB Spurious-Free Dynamic Range

Selectable Bipolar Inputs (ꢀ1 V and ꢀ0.5 V Ranges)

Integral Single-Pole Low-Pass Nyquist Filter

Two’s Complement Output Format

3.3 V Compatible Outputs

Multiple options are provided for driving the analog input,

including single-ended, differential, and optional series filtering.

The AD13280 also offers the user a choice of analog input

signal ranges to further minimize additional external signal

conditioning, while still remaining general purpose.

The AD13280 operates with 5.0 V for the analog signal condi-

tioning with a separate 5.0 V supply for the analog-to-digital

conversion, and 3.3 V digital supply for the output stage. Each

channel is completely independent allowing operation with

independent encode and analog inputs, and maintaining mini-

mal crosstalk and interference.

1.85 W per Channel

Industrial and Military Grade

APPLICATIONS

Radar Processing (Optimized for I/Q Baseband Operation)

Phased Array Receivers

Multichannel, Multimode Receivers

GPS Antijamming Receivers

Communications Receivers

The AD13280 is packaged in a 68-lead ceramic gull wing package.

Manufacturing is done on Analog Devices, Inc. MIL-38534

Qualified Manufacturers Line (QML) and components are

available up to Class-H (–40°C to +85°C). The components are

manufactured using Analog Devices, Inc. high-speed comple-

mentary bipolar process (XFCB).

PRODUCT DESCRIPTION

The AD13280 is a complete dual channel signal processing

solution including on board amplifiers, references, ADCs, and

output termination components to provide optimized system

performance. The AD13280 has on-chip track-and-hold circuitry

and utilizes an innovative multipass architecture to achieve 12-bit,

80 MSPS performance. The AD13280 uses innovative high-

density circuit design and laser-trimmed thin-film resistor networks

to achieve exceptional channel matching, impedance control,

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate of 80 MSPS.

2. Input signal conditioning included; gain and impedance match.

3. Single-ended, differential, or off-module filter options.

4. Fully tested/characterized full channel performance.

5. Compatible with 14-bit (up to) 65 MSPS family.

FUNCTIONAL BLOCK DIAGRAM

AMP-IN-B-2 AMP-IN-B-1

AMP-IN-A-1

AMP-IN-A-2

AMP-OUT-B

AMP-OUT-A

A–IN

B+IN

B–IN

A+IN

AD13280

DROUTA

(LSB) D0A

DROUTB

D1A

D2A

D3A

D4A

D5A

ENC

TIMING

ENC

VREF

DROUT

D11B (MSB)

D10B

DROUT

12

9

5

100ꢁ OUTPUTTERMINATORS

D6A

D7A

D8A

100ꢁ OUTPUTTERMINATORS

D9B

D8B

7

3

TIMING

D7B

ENC

D0B

(LSB)

ENC

D1B D2B D3B D4B D5B D6B

D9A D10A D11A

(MSB)

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(AV_CC= +5 V, AV_EE= –5 V, DV_CC= +3.3 V; applies to each ADC with Front-End

Amplifier unless otherwise noted.)

AD13280–SPECIFICATIONS

Test

Mil

Subgroup

AD13280AZ/BZ

Typ

Parameter

Temp

Level

Min

Max

Unit

RESOLUTION

12

Bits

DC ACCURACY¹

No Missing Codes

Offset Error

Full

25°C

Full

25°C

Full

25°C

Max

Min

IV

I

VI

I

VI

I

12

1

2, 3

1, 2, 3

1

2, 3

1

2

Guaranteed

1.0

–2.2

–1.0

–3

–5.0

–1.5

–3.0

–5

+2.2

+1.0

+1

+5.0

+1.5

+3.0

+5

% FS

%

% FS

%

1.0

0.1

–1.0

2.0

0.5

1.0

Offset Error Channel Match

Gain Error²

Gain Error Channel Match

VI

%

3

SINGLE-ENDED ANALOG INPUT

Input Voltage Range

AMP-IN-X-1

Full

V

0.5

1.0

V

AMP-IN-X-2

Input Resistance

AMP-IN-X-1

AMP-IN-X-2

Full

25°C

Full

IV

V

12

99

198

100

200

4.0

101

202

7.0

Ω

Capacitance

pF

MHz

Analog Input Bandwidth³

V

100

DIFFERENTIAL ANALOG INPUT

Analog Signal Input Range

A+IN to A–IN and B+IN to B–IN⁴

Input Impedance

Full

25°C

Full

V

1

618

50

V

Ω

MHz

Analog Input Bandwidth

ENCODE INPUT (ENC, ENC)¹

Differential Input Voltage

Differential Input Resistance

Differential Input Capacitance

Full

25°C

IV

V

12

0.4

80

V p-p

kΩ

10

2.5

pF

SWITCHING PERFORMANCE

Maximum Conversion Rate⁵

Minimum Conversion Rate⁵

Aperture Delay (t_A)

Aperture Delay Matching

Aperture Uncertainty (Jitter)

Full

25°C

VI

IV

V

IV

V

IV

V

4, 5, 6

12

MSPS

ns

ps

ps rms

ns

20

1.5

250

0.3

6.25

5

12

500

ENCODE Pulsewidth High at Max Conversion Rate 25°C

12

4.75

8

ENCODE Pulsewidth Low at Max Conversion Rate

Output Delay (t_OD

Encode, Rising to Data Ready, Rising Delay

25°C

Full

)

V

8.5

SNR^{1, 6}

Analog Input @ 10 MHz

Analog Input @ 21 MHz

Analog Input @ 37 MHz

25°C

Min

Max

25°C

Min

Max

25°C

Min

I

4

6

5

4

6

5

4

6

5

67.5

64.5

67.5

64

67.5

63.5

61.5

63.5

70

65

dBFS

II

I

II

I

II

Max

SINAD^{1, 7}

Analog Input @ 10 MHz

25°C

Min

Max

25°C

Min

Max

25°C

Min

I

4

6

5

4

6

5

4

6

5

67

63.5

67

65

63

65

54.5

53

54.5

69

dBFS

II

I

II

I

Analog Input @ 21 MHz

Analog Input @ 37 MHz

68.5

59

II

Max

–2–

REV. 0

AD13280

Test

Level

Mil

Subgroup

AD13280AZ/BZ

Typ

Parameter

Temp

Min

Max

Unit

SPURIOUS-FREE DYNAMIC RANGE^{1, 8}

Analog Input @ 10 MHz

25°C

Min

Max

25°C

Min

Max

25°C

Min

I

4

6

5

4

6

5

4

6

5

75

70

75

68

67

68

56

55

56

80

75

62

dBFS

II

I

II

I

Analog Input @ 21 MHz

Analog Input @ 37 MHz

dBFS

II

Max

SINGLE-ENDED ANALOG INPUT

Passband Ripple to 10 MHz

Passband Ripple to 25 MHz

25°C

V

0.05

0.1

dB

DIFFERENTIAL ANALOG INPUT

Passband Ripple to 10 MHz

Passband Ripple to 25 MHz

25°C

V

0.3

0.82

dB

TWO-TONE IMD REJECTION⁹

f_IN= 9.1 MHz and 10.1 MHz

f₁and f₂are –7 dB

25°C

Min

Max

25°C

I

4

6

5

4

75

71

75

80

dBc

II

V

f

_IN= 19.1 MHz and 20.7 MHz

77

60

dBc

f₁and f₂are –7 dB

f_IN= 36 MHz and 37 MHz

f₁and f₂are –7 dB

25°C

V

4

CHANNEL-TO-CHANNEL ISOLATION¹⁰

TRANSIENT RESPONSE

25°C

IV

V

12

90

dB

ns

25

DIGITAL OUTPUTS¹¹

Logic Compatibility

DVCC = 3.3 V

CMOS

Logic “1” Voltage

Logic “0” Voltage

DVCC = 5 V

Full

I

1, 2, 3

2.5

DVCC – 0.2

0.2

V

0.5

Logic “1” Voltage

Logic “0” Voltage

Output Coding

Full

V

DVCC – 0.3

0.35

Two’s Complement

V

POWER SUPPLY

AV_CCSupply Voltage¹²

I (AV_CC) Current

Full

IV

I

IV

I

IV

I

4.85

5.0

5.25

338

–4.75

49

3.465

46

V

mA

V

mA

V

mA

W

1, 2, 3

310

–5.0

38

3.3

34

369

3.72

0.01

AV_EESupply Voltage¹²

I (AV_EE) Current

–5.25

3.135

DV_CCSupply Voltage¹²

I (DV_CC) Current

1, 2, 3

I

_CC(Total) Supply Current per Channel

433

4.05

Power Dissipation (Total)

Power Supply Rejection Ratio (PSRR)

I

V

% FSR/% V_S

NOTES

¹All ac specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-X-1 = 1 V p-p, AMP-IN-X-2 = GND.

²Gain tests are performed on AMP-IN-X-1 input voltage range.

³Full Power Bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.

⁴For differential input: +IN = 1 V p-p and –IN = 1 V p-p (signals are 180° out of phase). For single-ended input: +IN = 2 V p-p and = –IN = GND.

⁵Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% 5%.

⁶Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR

is reported in dBFS, related back to converter full scale.

⁷Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is

reported in dBFS, related back to converter full scale.

⁸Analog Input signal at –1 dBFS; SFDR is ratio of converter full scale to worst spur.

⁹Both input tones at –7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.

¹⁰Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B Channel.

¹¹Digital output logic levels: DV_CC= 3.3 V, C_LOAD= 10 pF. Capacitive loads > 10 pF will degrade performance.

¹²Supply voltage recommended operating range. AV_CCmay be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range

AV_CC= 5.0 V to 5.25 V.

Specifications subject to change without notice.

–3–

REV. 0

AD13280

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

68-Lead Ceramic Leaded Chip Carrier

(ES-68C)

ELECTRICAL¹

AV_CCVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V

AV_EEVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V to 0 V

DV_CCVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V

Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . V_EEto V_CC

Analog Input Current . . . . . . . . . . . . . . –10 mA to +10 mA

Digital Input Voltage (ENCODE) . . . . . . . . . . . . . 0 to V_CC

ENCODE, ENCODE Differential Voltage . . . . . . . . 4 V max

Digital Output Current . . . . . . . . . . . . . . –10 mA to +10 mA

ENVIRONMENTAL²

Operating Temperature (Case) . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 175°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C

Storage Temperature Range (Ambient) . . –65°C to +150°C

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

10

11

12

13

14

AGNDA

PIN 1

IDENTIFIER

60

59

58

57

56

55

54

53

52

AGNDB

AV

A

EE

CC

AV

B

EE

B

CC

AGNDA

AGNDB

ENCODEB

ENCODEA

ENCODEA 15

16

AGNDA

AGNDB

DV

A

17

18

19

20

21

22

23

24

25

26

CC

AD13280

TOP VIEW

(Not to Scale)

DV

B

CC

NOTES

NC

D11B(MSB)

¹Absolute maximum ratings are limiting values applied individually, and beyond

which the serviceability of the circuit may be impaired. Functional operability is not

necessarily implied. Exposure to absolute maximum rating conditions for an

extended period of time may affect device reliability.

51 D10B

50 D9B

D0A(LSB)

D1A

49

48

47

46

45

44

D8B

D7B

D6B

D5B

D2A

²Typical thermal impedance for “ES” package: θ_JC2.2°C/W; θ_JA24.3°C/W.

D3A

D4A

D5A

D4B

DGNDB

DGNDA

TEST LEVEL

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

I

100% Production Tested.

II 100% Production Tested at 25°C, and sample tested at

specified temperatures. AC testing done on sample basis.

NC = NO CONNECT

III Sample Tested only.

IV Parameter is guaranteed by design and characterization

testing.

V

Parameter is a typical value only.

VI 100% production tested with temperature at 25°C: sample

tested at temperature extremes.

ORDERING GUIDE

Model

Temperature Range (Case)

Package Description

Package Option

AD13280AZ

AD13280AF

–25°C to +85°C

68-Lead Ceramic Leaded Chip Carrier

with Nonconductive Tie-Bar

ES-68C

5962-0053001HXA

AD13280/PCB

–40°C to +85°C

25°C

68-Lead Ceramic Leaded Chip Carrier

Evaluation Board with AD13280AZ

ES-68C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD13280 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. 0

AD13280

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

Function

1, 35

2, 3, 9, 10, 13, 16

SHIELD

AGNDA

Internal Ground Shield between Channels

A Channel Analog Ground. A and B grounds should be connected as close to

the device as possible.

4

A–IN

Inverting Differential Input (Gain = 1).

5

6

7

8

11

12

14

15

A+IN

Noninverting Differential Input (Gain = 1).

Single-Ended Amplifier Output (Gain = 2).

Analog Input for A Side ADC (Nominally 0.5 V).

Analog Input for A Side ADC (Nominally 1.0 V).

A Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).

A Channel Analog Positive Supply Voltage (Nominally 5.0 V).

Complement of Encode; Differential Input.

Encode Input; Conversion Initiated on Rising Edge.

A Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V).

No Connect.

AMP-OUT-A

AMP-IN-A-1

AMP-IN-A-2

AV_EEA

AV_CCA

ENCODEA

DV_CCA

17

18, 19, 37, 38

NC

20–25, 28–33

26, 27

34

36

39–42, 45–52

43, 44

53

D0A–D11A

DGNDA

DROUTA

DROUTB

D0B–D11B

DGNDB

DV_CCB

Digital Outputs for ADC A. D0 (LSB).

A Channel Digital Ground.

Data Ready A Output.

Data Ready B Output.

Digital Outputs for ADC B. D0 (LSB).

B Channel Digital Ground.

B Channel Digital Positive Supply Voltage (Nominally 5.0 V/ 3.3 V).

54, 57, 60, 61, 67, 68

AGNDB

B Channel Analog Ground. A and B grounds should be connected as close to the

device as possible.

55

56

58

59

62

63

64

65

66

ENCODEB

AV_CCB

Encode Input; Conversion Initiated on Rising Edge.

Complement of Encode; Differential Input.

B Channel Analog Positive Supply Voltage (Nominally 5.0 V).

B Channel Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).

Analog Input for B Side ADC (Nominally 1.0 V).

Analog Input for B Side ADC (Nominally 0.5 V).

Single-Ended Amplifier Output (Gain = 2).

AV_EEB

AMP-IN-B-2

AMP-IN-B-1

AMP-OUT-B

B+IN

Noninverting Differential Input (Gain = 1).

Inverting Differential Input (Gain = 1).

B–IN

REV. 0

–5–

–Typical Performance Characteristics

AD13280

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

ENCODE = 80MSPS

= 10MHz (–1dBFS)

SNR = 69.19dBFS

SFDR = 79.55dBc

ENCODE = 80MSPS

IN

SNR = 69.4dBFS

SFDR = 81.9dBc

A

= 5MHz (–1dBFS)

IN

–70

–80

–70

–80

3

5

3

2

5

2

4

–90

–100

–110

–120

–130

–90

–100

–110

–120

6

4

–130

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

FREQUENCY – MHz

TPC 1. Single Tone @ 5 MHz

TPC 4. Single Tone @ 10 MHz

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

ENCODE = 80MSPS

= 18MHz (–1dBFS)

SNR = 69.79dBFS

SFDR = 76.81dBc

ENCODE = 80MSPS

IN

SNR = 68.38dBFS

SFDR = 57.81dBc

A

IN

A

= 37MHz (–1dBFS)

2

3

–70

–80

–70

–80

5

6

–90

–100

–110

–120

–90

–100

–110

–120

–130

4

–130

0

5

10

15

20

25

30

35

40

5

10

15

20

25

30

35

40

FREQUENCY – MHz

TPC 2. Single Tone @ 18 MHz

TPC 5. Single Tone @ 37 MHz

0

–10

–20

–30

–40

–50

–60

0

–10

–20

–30

–40

–50

–60

ENCODE = 80MSPS

= 9MHz AND

10MHz (–7dBFS)

ENCODE = 80MSPS

= 19MHz AND

20MHz (–7dBFS)

A

IN

A

IN

SFDR = 82.77dBc

SFDR = 74.41dBc

–70

–80

–70

–80

–90

–100

–110

–120

–90

–100

–110

–120

–130

0

5

10

15

20

25

30

35

40

5

10

15

20

25

30

35

40

FREQUENCY – MHz

TPC 3. Two Tone @ 9 MHz/10 MHz

TPC 6. Two Tone @ 19 MHz/20 MHz

–6–

REV. 0

AD13280

3.0

3

ENCODE = 80MSPS

DNL MAX = 0.688 CODES

DNL MIN = 0.385 CODES

ENCODE = 80MSPS

INL MAX = 0.562 CODES

INL MIN = 0.703 CODES

2.5

2.0

1.5

1.0

0.5

0

2

1

0

–1

–2

–3

–0.5

–1.0

0

512

1024

1536

2048

2560

3072 3584

4096

0

512

1024

1536

2048

2560

3072 3584

4096

TPC 7. Differential Nonlinearity

TPC 9. Integral Nonlinearity

0

–1

–2

–3

ENCODE = 80MSPS

ROLL-OFF = 0.0459dB

–4

–5

–6

–7

–8

–9

–10

1.0

3.5

6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 26.0

FREQUENCY – MHz

TPC 8. Passband Ripple to 25 MHz

REV. 0

–7–

AD13280

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal

frequency drops by no more than 3 dB below the guaranteed limit.

DEFINITION OF SPECIFICATIONS

Analog Bandwidth

The analog input frequency at which the spectral power of the

fundamental frequency (as determined by the FFT analysis) is

reduced by 3 dB.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Aperture Delay

Output Propagation Delay

The delay between a differential crossing of ENCODE and

ENCODE command and the instant at which the analog input

is sampled.

The delay between a differential crossing of ENCODE and

ENCODE command and the time when all output data bits are

within valid logic levels.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Overvoltage Recovery Time

The amount of time required for the converter to recover to

0.02% accuracy after an analog input signal of the specified

percentage of full scale is reduced to midscale.

Differential Analog Input Resistance, Differential Analog

Input Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog

input port. The resistance is measured statically and the capaci-

tance and differential input impedances are measured with a

network analyzer.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in

power supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

Differential Analog Input Voltage Range

The ratio of the rms signal amplitude (set at 1 dB below full

scale) to the rms value of the sum of all other spectral compo-

nents, including harmonics but excluding dc. May be reported

in dB (i.e., degrades as signal level is lowered) or in dBFS

(always related back to converter full scale).

The peak-to-peak differential voltage that must be applied to the

converter to generate a full-scale response. Peak differential

voltage is computed by observing the voltage from the other pin,

which is 180 degrees out of phase. Peak-to-peak differential is

computed by rotating the inputs phase 180 degrees and taking

the peak measurement again. The difference is then computed

between both peak measurements.

Signal-to-Noise Ratio (without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full

scale) to the rms value of the sum of all other spectral compo-

nents, excluding the first five harmonics and dc. May be reported

in dB (i.e., degrades as signal level is lowered) or in dBFS

(always related back to converter full scale).

Differential Nonlinearity

The deviation of any code from an ideal 1 LSB step.

Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the

ENCODE pulse should be left in Logic “1” state to achieve

rated performance; pulsewidth low is the minimum time

ENCODE pulse should be left in low state. At a given clock

rate, these specs define an acceptable Encode duty cycle.

Spurious-Free Dynamic Range

The ratio of the rms signal amplitude to the rms value of the

peak spurious spectral component. The peak spurious compo-

nent may or may not be a harmonic.

Transient Response

Harmonic Distortion

The ratio of the rms signal amplitude to the rms value of the

worst harmonic component.

The time required for the converter to achieve 0.02% accuracy

when a one-half full-scale step function is applied to the ana-

log input.

Integral Nonlinearity

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value

of the worst third order intermodulation product; reported in dBc.

The deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a “best straight line”

determined by a least square curve fit.

t_A

N+3

N

A

IN

N+1

N+2

N+4

t_ENC

t_ENCH

N+1

t_ENCL

ENC, ENC

N

N+2

N+3

N+4

t_{E_DR}

t_OD

N–3

N–2

N–1

N

D[11:0]

DRY

Figure 1. Timing Diagram

–8–

REV. 0

AD13280

THEORY OF OPERATION

AMP-IN-X-1

AMP-IN-X-2

100ꢁ

The AD13280 is a high-dynamic range 12-bit, 80 MHz pipeline

delay (three pipelines) analog-to-digital converter. The custom

analog input section provides input ranges of 1 V and 2 V p-p

and input impedance configurations of 50 Ω, 100 Ω, and 200 Ω.

TO AD8037

Figure 2. Single-Ended Input Stage

The AD13280 employs four monolithic ADI components per

channel (AD8037, AD8138, AD8031, and a custom ADC IC),

along with multiple passive resistor networks and decoupling

capacitors to fully integrate a complete 12-bit analog-to-digital

converter.

LOADS

AV

CC

10kꢁ

In the single-ended input configuration the input signal is passed

through a precision laser trimmed resistor divider allowing

the user to externally select operation with a full-scale signal of

0.5 V, or 1.0 V by choosing the proper input terminal for the

application. The result of the resistor divider is to apply a full-

scale input approximately 0.4 V to the noninverting input of the

internal AD8037 amplifier.

ENCODE

10kꢁ

LOADS

Figure 3. ENCODE Inputs

The AD13280 analog input includes an AD8037 amplifier featur-

ing an innovative architecture that maximizes the dynamic range

capability on the amplifiers’ inputs and outputs. The AD8037

amplifier provides a high input impedance and gain for driving

the AD8138 in a single-ended to differential amplifier configura-

tion. The AD8138 has a –3 dB bandwidth at 300 MHz and

delivers a differential signal with the lowest harmonic distortion

available in a differential amplifier. The AD8138 differential

outputs help balance the differential inputs to the custom ADC

maximizing the performance of the device.

DV

CC

CURRENT MIRROR

DV

CC

V

REF

The AD8031 provides the buffer for the internal reference analog-

to-digital converter. The internal reference voltage of the custom

ADC is designed to track the offsets and drifts and is used to

ensure matching over an extended temperature range of operation.

The reference voltage is connected to the output common-mode

input on the AD8138. This reference voltage sets the output

common mode on the AD8138 at 2.4 V, which is the midsupply

level for the ADC.

DR OUT

CURRENT MIRROR

The custom ADC has complementary analog input pins, AIN

and AIN. Each analog input is centered at 2.4 V and should

swing 0.55 V around this reference. Since AIN and AIN are

180 degrees out of phase, the differential analog input signal is

2.2 V peak-to-peak. Both analog inputs are buffered prior to the

first track-and-hold.

Figure 4. Digital Output Stage

DV

CC

The custom ADC digital outputs drive 100 Ω series resistors (Fig-

ure 5). The result is a 12-bit parallel digital CMOS-compatible

word, coded as two’s complement.

CURRENT MIRROR

USING THE SINGLE-ENDED INPUT

DV

CC

The AD13280 has been designed with the user’s ease of opera-

tion in mind. Multiple input configurations have been included

on-board to allow the user a choice of input signal levels and

input impedance. The standard inputs are 0.5 V and 1.0 V.

The user can select the input impedance of the AD13280 on any

input by using the other inputs as alternate locations for the

GND. The following chart summarizes the impedance options

available at each input location.

V

REF

100ꢁ

D0–D11

AMP-IN-X-1 = 100 Ω when AMP-IN-X-2 is open.

AMP-IN-X-1 = 50 Ω when AMP-IN-X-2 is shorted to GND.

AMP-IN-X-2 = 200 Ω when AMP-IN-X-1 is open.

CURRENT MIRROR

Each channel has two analog inputs AMP-IN-A-1 and AMP-

IN-A-2 or AMP-IN-B-1 and AMP-IN-B-2. Use AMP-IN-A-1

Figure 5. Digital Output Stage

REV. 0

–9–

AD13280

or AMP-IN-B-1 when an input of 0.5 V full scale is desired. Use

AMP-IN-A-2 or AMP-IN-B-2 when 1 V full scale is desired.

Each channel has an AMP-OUT which must be tied to either a

noninverting or inverting input of a differential amplifier with the

remaining input grounded. For example, Side A, AMP-OUT-A

(Pin 6) must be tied to A+IN (Pin 5) with A–IN (Pin 5) tied to

ground for noninverting operation or AMP-OUT-A (Pin 6) tied

to A–IN (Pin 4) with A+IN (Pin 5) tied to ground for inverting

operation.

If a low jitter ECL/PECL clock is available, another option is to

ac-couple a differential ECL/PECL signal to the encode input

pins as shown below. A device that offers excellent jitter perfor-

mance is the MC100LVEL16 (or same family) from Motorola.

VT

0.1ꢂF

ENCODE

ECL/

PECL

AD13280

0.1ꢂF

ENCODE

USING THE DIFFERENTIAL INPUT

Each channel of the AD13280 was designed with two optional

differential inputs, A+IN, A–IN and B+IN, B–IN. The inputs

provide system designers with the ability to bypass the AD8037

amplifier and drive the AD8138 directly. The AD8138 differen-

tial ADC driver can be deployed in either a single-ended or

differential input configuration. The differential analog inputs

have a nominal input impedance of 620 Ω and nominal full-

scale input range of 1.2 V p-p. The AD8138 amplifier drives a

differential filter and the custom analog-to-digital converter. The

differential input configuration provides the lowest even-order

harmonics and signal-to-noise (SNR) performance improvement

of up to 3 dB (SNR = 73 dBFS). Exceptional care was taken in

the layout of the differential input signal paths. The differential

input transmission line characteristics are matched and balanced.

Equal attention to system level signal paths must be provided in

order to realize significant performance improvements.

VT

Figure 7. Differential ECL for Encode

Jitter Consideration

The signal-to-noise ratio (SNR) for any ADC can be predicted.

When normalized to ADC codes, Equation 1 accurately predicts

the SNR based on three terms. These are jitter, average DNL

error, and thermal noise. Each of these terms contributes to the

noise within the converter.





²^1/2













1+ ε

(

)

V_{NOISE RMS}







SNR = –20 × log

+(2 × π × f

× t_J_RMS)²+

ANALOG



(1)

2^N





 









f_ANALOG

t_{J RMS}

= analog input frequency

= rms jitter of the encode (rms sum of encode

source and internal encode circuitry)

ε

= average DNL of the ADC (typically 0.50 LSB)

= Number of bits in the ADC

APPLYING THE AD13280

Encoding the AD13280

N

The AD13280 encode signal must be a high quality, extremely

low phase noise source, to prevent degradation of performance.

Maintaining 12-bit accuracy at 80 MSPS places a premium on

encode clock phase noise. SNR performance can easily degrade

3 dB to 4 dB with 37 MHz input signals when using a high-jitter

clock source. See Analog Devices’ Application Note AN-501,

“Aperture Uncertainty and ADC System Performance” for

complete details. For optimum performance, the AD13280 must

be clocked differentially. The encode signal is usually ac-coupled

into the ENCODE and ENCODE pins via a transformer or

capacitors. These pins are biased internally and require no addi-

tional bias.

V_{NOISE RMS}= V rms noise referred to the analog input of the

ADC (typically 5 LSB)

For a 12-bit analog-to-digital converter like the AD13280, aper-

ture jitter can greatly affect the SNR performance as the analog

frequency is increased. The chart below shows a family of curves

that demonstrates the expected SNR performance of the AD13280

as jitter increases. The chart is derived from the above equation.

For a complete discussion of aperture jitter, please consult Ana-

log Devices’ Application Note AN-501, “Aperture Uncertainty

and ADC System Performance.”

71

Shown below is one preferred method for clocking the AD13280.

The clock source (low jitter) is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the transformer secondary limit clock excursions

into the AD13280 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to the other portions of the AD13280, and limits the

noise presented to the ENCODE inputs. A crystal clock oscillator

can also be used to drive the RF transformer if an appropriate

limited resistor (typically 100 Ω) is placed in the series with

the primary.

A

= 5MHz

IN

70

69

68

A

= 10MHz

IN

67

66

65

64

A

= 20MHz

= 37MHz

IN

63

62

61

60

59

58

A

IN

0.1ꢂF

ꢁ

100

T1-4T

CLOCK

SOURCE

ENCODE

AD13280

ENCODE

CLOCK JITTER – ps

HSMS2812

DIODES

Figure 8. SNR vs. Jitter

Figure 6. Crystal Clock Oscillator—Differential Encode

–10–

REV. 0

AD13280

Power Supplies

LAYOUT INFORMATION

Care should be taken when selecting a power source. Linear sup-

plies are strongly recommended. Switching supplies tend to have

radiated components that may be “received” by the AD13280.

Each of the power supply pins should be decoupled as closely as

possible to the package, using 0.1 µF chip capacitors.

The schematic of the evaluation board (Figure 10) represents a

typical implementation of the AD13280. The pinout of the

AD13280 is very straightforward and facilitates ease of use and

the implementation of high-frequency/high-resolution design

practices. It is recommended that high-quality ceramic chip

capacitors be used to decouple each supply pin to ground directly

at the device. All capacitors can be standard high-quality ceramic

chip capacitors.

The AD13280 has separate digital and analog power supply

pins. The analog supplies are denoted AV_CCand the digital

supply pins are denoted DV_CC. AV_CCand DV_CCshould be

separate power supplies because the fast digital output swings

can couple switching current back into the analog supplies.

Note that AV_CCmust be held within 5% of 5 V. The AD13280

is specified for DV_CC= 3.3 V as this is a common supply for

digital ASICs.

Care should be taken when placing the digital output runs.

Because the digital outputs have such a high slew rate, the

capacitive loading on the digital outputs should be minimized.

Circuit traces for the digital outputs should be kept short and

connect directly to the receiving gate. Internal circuitry buffers

the outputs of the ADC through a resistor network to eliminate

the need to externally isolate the device from the receiving gate.

Output Loading

Care must be taken when designing the data receivers for the

AD13280. The digital outputs drive an internal series resistor

(e.g., 100 Ω) followed by a gate like 75LCX574. To minimize

capacitive loading, there should be only one gate on each output

pin. An example of this is shown in the evaluation board sche-

matic shown in Figure 9. The digital outputs of the AD13280

have a constant output slew rate of 1 V/ns. A typical CMOS

gate combined with a PCB trace will have a load of approxi-

mately 10 pF. Therefore, as each bit switches, 10 mA (10 pF ×

1 V ÷ 1 ns) of dynamic current per bit will flow in or out of the

device. A full-scale transition can cause up to 120 mA (12 bits ×

10 mA/bit) of transient current through the output stages.

These switching currents are confined between ground and the

DV_CCpin. Standard TTL gates should be avoided since they

can appreciably add to the dynamic switching currents of the

AD13280. It should also be noted that extra capacitive loading

will increase output timing and invalidate timing specifications.

Digital output timing is guaranteed with 10 pF loads.

EVALUATION BOARD

The AD13280 evaluation board (Figure 9) is designed to

provide optimal performance for evaluation of the AD13280

analog-to-digital converter. The board encompasses everything

needed to ensure the highest level of performance for evaluating

the AD13280. The board requires an analog input signal, encode

clock, and power supply inputs. The clock is buffered on-board

to provide clocks for the latches. The digital outputs and out

clocks are available at the standard 40-pin connectors J1 and J2.

Power to the analog supply pins is connected via banana jacks.

The analog supply powers the associated components and the

analog section of the AD13280. The digital outputs of the

AD13280 are powered via banana jacks with 3.3 V. Contact the

factory if additional layout or applications assistance is required.

Figure 9. Evaluation Board Mechanical Layout

REV. 0

–11–

AD13280

Bill of Materials List for Evaluation Board

Qty. Component Name

Ref/Des

Value

Description

Manufacturing Part No.

2

1

2

10

2

74LCX16373MTD U7, U8

Latch

AD13280

Regulator

Banana Jacks

0805 SM Resistor

0805 SM Capacitor

74LCX16373MTD (Fairchild)

AD13280AZ

ADP3330ART-3.3RL7

108-0740-001 (Johnson Components)

ERJ-6GEYJ 240V

AD13280AZ

ADP3330

BJACK

U1

U5, U6

BJ1–BJ10

BRES0805

CAP2

R41, R53

25 Ω

33 kΩ

0.1 µF

4

28

R38, R39, R55, R56

C1, C2, C5–C10,

C12, C16–C18,

C20–C26, C28,

C30–C38

ERJ-6GEYJ 333V

GRM 40X7R104K025BL

2

6

4

2

8

CAP2

H40DM

IND2

MC10EL16

MC100ELT23

POLCAP2

C13, C27

J1, J2

L1–L6

U2, U4, U9, U11

U4, U10

C3, C4, C11, C14,

C15, C19, C29, C30

R47–R50

R1, R2, R5, R7, R8, R54

R3, R4, R6, R9, R12–R15,

R19–R28, R31–R36, R37,

R42, R43, R44–R46 R51, R52

J3–J14

0.47 µF

47 Ω

0805 SM Capacitor

2 × 20 40 Pin Male Connector

SM Inductor

Clock Drivers

ECL/TTL Clock Drivers

Tantalum Polar Caps

VJ1206U474MFXMB

TSW-120-08-G-D

2743019447

MC1016EP16D

SY100ELT23L

10 µF

T491C106M016A57280

4

6

36

RES2

0 Ω

50 Ω

100 Ω

0805 SM Resistor

ERJ-6GEY OR 00V

ERJ-6GEYJ 510V

ERJ-6GEYJ 101V

12

4

SMA

SMA Connectors

Standoff

Screws (Standoff)

AD13280 Eval Board (Rev. B)

142-0701-201

Standoff

Screws

PCB

313-2477-016 (Johnson Components)

MPMS 004 0005 PH (Building Fasteners)

GS03361

1

–12–

REV. 0

AD13280

J13

SMA

J6

E68

AGNDA

E67

AGNDB

E66

LIDA

SMA

J9

J8

SMA

J3

SMA

J14

SMA

AGNDA

AGNDB

E50

J4

E53

J7

SMA

E51

E54

AGNDB

AGNDA

E49

E70

E52

E85

E69

AGNDA

E86

AGNDB

AGNDA

10

–5VAB

C33

0.1ꢂF

–5VAA

60

C9

AGNDB

AGNDA

AGNDB

0.1ꢂF

11

12

59

58

–5VAA

–5.2VAB

AGNDA

AGNDB

+5VAA

C35

0.1ꢂF

+5VAA

AGNDA

ENCAB

ENCA

AGNDA

+3VDA

NC

+5VAB

C38

0.1ꢂF

13

14

57

56

C34

0.1ꢂF

C17

0.1ꢂF

AGNDB

ENCBB

ENCB

AGNDA

ENCAB

AGNDB

ENCBB

ENCB

15

16

17

18

19

20

21

22

23

24

25

26

55

54

53

52

51

50

49

48

47

46

45

44

ENCA

AGNDA

OUT 3.3VDA

AGNDB

OUT 3.3VDB

AGNDB

AGNDA

U1

+3.3VDB

C36

0.1ꢂF

C10

0.1ꢂF

C18

0.1ꢂF

C37

0.1ꢂF

AD13280

D11B(MSB)

D11B

D10B

D9B

D8B

D7B

D6B

D5B

NC0A

NC1A

NC

D10B

D9B

D0A(LSB)

D1A

D0A

D1A

DGNDA

DGNDB

D8B

D2A

D7B

D3A

D6B

D4A

D5B

D5A

D4B

DGNDA

DGNDB

NC = NO CONNECT

DRAOUT

DRBOUT

E56

E55

LIDB

E48

E65

E40

DGNDB

DGNDA

+3VAA

BJ6

–5VAA

47ꢁ

ꢀ20%

47ꢁ

ꢀ20% @100MHz

47ꢁ

+3VDA

BJ10

ꢀ20%@100MHz

BJ2

@100MHz

–5VAA

+5VAA

1

C11

10ꢂF

1

C3

10ꢂF

L3

U1

C20

L5

U1

C32

DUT 3.3VDA

1

L1

U7

C62

C29

10ꢂF

0.1ꢂF

AGNDA

DGNDA

47ꢁ

ꢀ20%

+5VAB

BJ5

47ꢁ

–5VAB

BJ1

47ꢁ

ꢀ20%@100MHz

+3VDB

BJ9

ꢀ20%@100MHz

@100MHz

+5VAB

–5VAB

DUT 3.3VDB

1

C4

10ꢂF

1

C19

10ꢂF

1

L4

U1

C21

L6

U1

C31

L2

U8

C16

C30

0.1ꢂF

10ꢂF

0.1ꢂF

AGNDB

DGNDB

Figure 10a. Evaluation Board

REV. 0

–13–

AD13280

U8

R47

H40DM

J1

DGNDA

LE2 OE2

0ꢁ

R18, DNI

R17, DNI

24

23

22

21

25

26

27

28

F0A

F1A

115

114

O15

O14

1

2

3

40

39

38

3.3VDA

R48

0ꢁ

MSB B11A

B10A

DGNDA

GND GND

R40, DNI

R44, DNI

C15

10ꢂF

F2A

F3A

NC0A

NC1A

113

112

O13

O12

4

5

37

36

20

19

18

17

16

15

14

29

30

31

32

33

34

35

B9A

B8A

B7A

DGNDA

6

35

DUT 3.3VDA

R45, 100ꢁ

VCC VCC

DGNDA

7

8

9

34

33

32

LSB D0A

D1A

B0A (LSB)

B1A

111

110

O11

O10

B6A

B5A

R46, 100ꢁ

R15, 100ꢁ

R14, 100ꢁ

R13, 100ꢁ

R15, 100ꢁ

R5

50ꢁ

DGNDA

GND GND

B4A

E61

10

11

31

30

D2A

19

O9

B2A

B3A

B4A

B5A

E59

E60

D3A

D4A

12

29

18

17

16

O8

O7

O6

13

12

11

B3A

B2A

B1A

36

37

38

39

13

14

15

16

28

27

26

25

D5A

GND GND

DGNDA

LSB B0A

F3A

R24, 100ꢁ

R23, 100ꢁ

10

9

D6A

D7A

B6A

B7A

15

14

O5

O4

17

18

24

23

40

41

42

43

F2A

8

F1A

F0A

DGNDA

DUT 3.3VDA

D8A

DUT 3.3VDA

R22, 100ꢁ

VCC VCC

19

20

22

21

7

B8A

B9A

13

12

O3

O2

6

D9A

DGNDA

R21, 100ꢁ

R20, 100ꢁ

R19, 100ꢁ

5

4

3

2

44

45

46

47

48

DGNDA

GND GND

DGNDA

B10A

D10A

11

10

O1

O0

MSB D11A

B11A (MSB)

DGNDA

LE1 OE1

R7

50ꢁ

1

LATCHA

E58

74LCX16374

U7

R49

J2

H40DN

DGNDB

LE2 OE2

0ꢁ

R11, DNI

R10, DNI

24

23

22

21

25

26

F0B

F1B

115

114

O15

O14

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

3.3VDB

R50

0ꢁ

27

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

DGNDB

MSB B11B

B10B

B9B

GND GND

R30, DNI

R29, DNI

28

C14

10ꢂF

F2B

F3B

NC0B

113

112

O13

O12

20

19

18

17

16

15

14

29

DGNDB

NC1B

DUT 3.3VDB

30

B8B

B7B

DUT 3.3VDB

R28, 100ꢁ

VCC VCC

31

32

33

34

35

DGNDB

B0B (LSB)

B1B

LSB D0B

D1B

111

110

O11

O10

B6B

B5B

B4B

R27, 100ꢁ

R26, 100ꢁ

R12, 100ꢁ

R9, 100ꢁ

R25, 100ꢁ

R2

DGNDB

GND GND

E64 50ꢁ

D2B

19

O9

B2B

B3B

B4B

B5B

E63

E62

D3B

D4B

18

17

16

O8

O7

O6

13

12

11

36

37

38

39

B3B

B2B

B1B

D5B

GND GND

DGNDB

R36, 100ꢁ

R35, 100ꢁ

LSB B0B

F3B

10

9

D6B

D7B

B6B

B7B

15

14

O5

O4

40

41

42

43

F2B

8

DUT 3.3VDB

D8B

DUT 3.3VDB

R34, 100ꢁ

VCC VCC

F1B

F0B

7

B8B

B9B

13

12

O3

O2

6

DGNDB

D9B

DGNDB

R33, 100ꢁ

R32, 100ꢁ

5

4

3

2

44

45

46

47

48

DGNDB

GND GND

DGNDB

D10B

B10B

11

10

O1

O0

R31, 100ꢁ

MSB D11B

B11B (MSB)

DGNDB

LE1 OE1

R8

50ꢁ

1

LATCHB

E57

74LCX16374

Figure 10b. Evaluation Board

–14–

REV. 0

AD13280

U5

5

NR

3

1

ERR

OUT

ADP3330

IN

2

5

+5VAA

SD

GND

4

AGNDA

+3.3VA

R42

C13

0.47ꢂF

100ꢁ

J5

8

1

2

3

4

BJ3

1

ENCODE

SMA

C7

C1

NC

VCC

AGNDB

AGNDA

0.1ꢂF

7

6

5

ENCAB

ENCA

D

Q

QB

U2

BJ4

1

DB

R1

50ꢁ

C8

0.1ꢂF

AGNDA

R43

VBB

VEE

100ꢁ

BJ7

1

AGNDA

DGNDB

DGNDA

MC10EL16

NC = NO CONNECT

AGNDA

DGNDB

R56

33kꢁ

J12

SMA

C2

0.1ꢂF

DGNDA

BJ8

1

C6

R55

33kꢁ

0.47ꢂF

DGND

C5

0.47ꢂF

R41

25ꢁ

DGNDA

AGNDA

1

8

R3

100ꢁ

+3.3VDA

NC

VCC

Q

1

8

2

3

4

7

6

E15 E16

+3.3VDA

D

NC

D

VCC

U3

LATCHA

E23

E7

E12

DGNDB

E8

AGNDA

2

3

4

7

6

5

QB

DB

Q0

Q1

U4

5

R4

DGNDA

DB

E19

BUFLATA

VBB

VEE

100ꢁ

DGNDA

VBB

VEE

MC10EL16

E11

DGNDA

NC = NO CONNECT

E39 E47

MC100EPT23

NC = NO CONNECT

DGNDA

DGNDB

E17 E18

E27 E28

E25 E26

E21 E20

E32 E31

E44 E43

E42 E41

5

NR

3

1

OUT

ERR

ADP3330

2

5

U6

IN

+5VAB

SD

E10

E9

GND

E33 E34

4

E6

E5

AGNDB

R52

C27

0.47ꢂF

DGNDA

AGNDA

100ꢁ

J10

ENCODE

SMA

8

7

1

C24

0.1ꢂF

C22

+3.3VB

NC

VCC

0.1ꢂF

E38 E37

E29 E30

2

3

U11

ENCBB

ENCB

D

Q

QB

6

5

E1

E2

DB

R54

50ꢁ

4

E36 E35

E14 E13

E45 E46

C28

0.1ꢂF

AGNDB

R51

100ꢁ

VBB

VEE

AGNDB

MC10EL16

NC = NO CONNECT

E3

E4

AGNDB

SO1 SO4

AGNDA

R38

33kꢁ

DGNDB

R39

33kꢁ

J11

SMA

C25

0.47ꢂF

C23

0.1ꢂF

DGNDB

SO5

SO6

SO2

SO3

C26

0.1ꢂF

1

8

R37

+3.3VDB

NC

VCC

Q

R53

25ꢁ

100ꢁ

1

8

2

3

4

7

6

+3.3VDA

D

NC

D

VCC

U9

LATCHB

E24

2

3

4

7

6

QB

DB

Q0

Q1

U10

5

R6

AGNDB

DB

E22

BUFLATB

VBB

VEE

100ꢁ

5

DGNDB

VBB

VEE

MC10EL16

NC = NO CONNECT

DGNDB

MC100EPT23

NC = NO CONNECT

Figure 10c. Evaluation Board

REV. 0

–15–

AD13280

Figure 11a. Top Silk

Figure 11b. Top Layer

–16–

REV. 0

AD13280

Figure 11c. GND1

Figure 11d. GND2

REV. 0

–17–

AD13280

Figure 11e. Bottom Silk

Figure 11f. Bottom Layer

–18–

REV. 0

AD13280

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

68-Lead Ceramic Leaded Chip Carrier

(ES-68C)

0.235 (5.97)

MAX

0.960 (24.38)

0.950 (24.13) SQ

0.940 (23.88)

0.010 (0.25)

0.008 (0.20)

0.007 (0.18)

60

44

61

43

PIN 1

1.190 (30.23)

1.180 (29.97) SQ

1.170 (29.72)

1.070

(27.18)

MIN

0.800

(20.32)

BSC

TOP VIEW

(PINS DOWN)

9

27

10

26

0.060 (1.52)

0.050 (1.27)

0.040 (1.02)

DETAIL A

0.055 (1.40)

0.050 (1.27)

0.045 (1.14)

0.020 (0.508)

0.017 (0.432)

0.014 (0.356)

0.175 (4.45)

MAX

REV. 0

–19–

AD13280

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

68-Lead Ceramic Leaded Chip Carrier With Non-Conductive Tie-Bar

(ES-68C)

0.960 (24.38)

0.950 (24.13) SQ

0.940 (23.88)

0.350

(8.89)

TYP

0.015 (0.3)

ꢄ 45ꢃ

3 PLS

0.055 (1.40)

0.050 (1.27)

0.045 (1.14)

PIN 1

2.000

(8.89)

TYP

TOP VIEW

(PINS DOWN)

0.020 (0.508)

0.017 (0.432)

0.014 (0.356)

0.040 (1.02)

ꢄ 45ꢃ

0.040 (1.02) R

TYP

0.800 (20.32)

BSC

0.175 (4.45)

MAX

0.235 (5.97)

MAX

DETAIL A

0.010 (0.25)

0.008 (0.20)

0.007 (0.18)

0.010 (0.254)

30ꢃ

0.050 (1.27)

0.020 (0.508)

DETAIL A

–20–

REV. 0


型号：	AD13280AF
厂家：	ADI
描述：	Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning 双通道， 12位， 80 MSPS A / D转换器的模拟输入信号调理转换器模数转换器
文件：	总20页 (文件大小：1352K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD13280AF [ADI]

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