AD14060BF-4_技术文档

®

Quad-SHARC

a

DSP Multiprocessor Family

AD14060/AD14060L

FUNCTIO NAL BLO CK D IAGRAM

PERFORMANCE FEATURES

ADSP-21060 Core Processor (. . .

؋

4)

480 MFLOPS Peak, 320 MFLOPS Sustained

25 ns Instruction Rate, Single-Cycle

Instruction Execution–Each of Four Processors

16 Mbit Shared SRAM (Internal to SHARCs)

4 Gigaw ords Addressable Off-Module Mem ory

Tw elve 40 Mbyte/ s Link Ports (Three per SHARC)

Four 40 Mbit/ s Independent Serial Ports (One from

Each SHARC)

LINK 0

LINK 2

LINK 5

TDO

LINK 0

LINK 2

LINK 5

TDI

CPA

SPORT 1

CPA

SPORT 1

TDI

SHARC_A

(ID = 1)

2-0

SHARC_B

(ID = 2)

2-0

One 40 Mbit/ s Com m on Serial Port

5 V and 3.3 V Operation

32-Bit Single Precision and 40-Bit Extended

Precision IEEE Floating Point Data Form ats, or

32-Bit Fixed Point Data Form at

IEEE J TAG Standard 1149.1 Test Access Port and

On-Chip Em ulation

AD14060/

AD14060L

SHARC BUS (ADDR

,

DATA

MS

, RD, WR, PAGE, ADRCLK, SW, ACK,

31-0

47-0

,

3-0

SBTS, HBR, HBG, REDY, BR , RPBA, DMAR , DMAG )

1.2

6-1

1.2

PACKAGING FEATURES

308-Lead Ceram ic Quad Flatpack (CQFP)

2.05" (52 m m ) Body Size

Cavity Up or Dow n, Configurable

Low Profile, 0.160" Height

Herm etic

SHARC_D

SHARC_C

(ID = 3)

2-0

CPA

SPORT 1

LINK 0

LINK 2

LINK 5

TDO

LINK 0

LINK 2

LINK 5

TDI

CPA

SPORT 1

(ID = 4)

2-0

25 Mil (0.65 m m ) Lead Pitch

29 Gram s (typical)

TDO

␪

= 0.36؇C/ W

J C

GENERAL D ESCRIP TIO N

T he ADSP-21060 link ports are interconnected to provide

direct communication among the four SHARCs as well as high

speed off-module access. Internally, each SHARC has a direct

link port connection. Externally, each SHARC has a total of

120 Mbytes/s link port bandwidth.

T he AD14060/AD14060L Quad-SHARC is the first in a family

of high performance DSP multiprocessor modules. T he core of

the multiprocessor is the ADSP-21060 DSP microcomputer.

T he AD14060/AD14060L modules have the highest perfor-

mance —density and lowest cost—performance ratios of any in

their class. T hey are ideal for applications requiring higher levels

of performance and/or functionality per unit area.

Multiprocessor performance is enhanced with embedded power

and ground planes, matched impedance interconnect, and opti-

mized signal routing lengths and separation. T he fully tested

and ready-to-insert multiprocessor also significantly reduces

board space.

T he AD14060/AD14060L takes advantage of the built-in multi-

processing features of the ADSP-21060 to achieve 480 peak

MFLOPS with a single chip type, in a single package. T he on-

chip SRAM of the DSPs provides 16 Mbits of on-module

shared SRAM. T he complete shared bus (48 data, 32 address)

is also brought off-module for interfacing with expansion

memory or other peripherals.

SHARC is a registered trademark of Analog Devices, Inc.

REV. A

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

Fax: 781/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

AD14060/AD14060L

D ETAILED D ESCRIP TIO N

Ar chitectur al Featur es

ADSP-21060 Cor e

T he SHARCs contain 4 Mbits of on-chip SRAM each, orga-

nized as two blocks of 2 Mbits, which can be configured for

different combinations of code and data storage. T he memory

can be configured as a maximum of 128K words of 32-bit data,

256K words of 16-bit data, 80K words of 48-bit instructions (or

40-bit data), or combinations of different word sizes up to

4 megabits. A 16-bit floating-point storage format is supported

which effectively doubles the amount of data that may be stored

on chip. Conversion between the 32-bit floating point and 16-

bit floating point formats is done in a single instruction. Each

memory block is dual-ported for single-cycle, independent

accesses by the core processor and I/O processor or DMA con-

troller. T he dual-ported memory and separate on-chip buses

allow two data transfers from the core and one from I/O, all in a

single cycle.

The AD14060/AD14060L is based on the powerful ADSP-21060

(SHARC) DSP chip. T he ADSP-21060 SHARC combines a

high performance floating-point DSP core with integrated, on-

chip system features including a 4 Mbit SRAM memory, host

processor interface, DMA controller, serial ports, and both link

port and parallel bus connectivity for glueless DSP multiprocess-

ing, (see Figure 1). It is fabricated in a high speed, low power

CMOS process, and has a 25 ns instruction cycle time. The arith-

metic/ logic unit (ALU), multiplier and shifter all perform single-

cycle instructions, and the three units are arranged in parallel,

maximizing computational throughput.

T he SHARC features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data, and the pro-

gram memory (PM) bus transfers both instructions and data.

T here is also an on-chip instruction cache which selectively

caches only those instructions whose fetches conflict with the

PM bus data accesses. T his combines with the separate program

and data memory buses to enable three-bus operation for fetch-

ing an instruction and two operands, all in a single cycle. T he

SHARC also contains a general purpose data register file, which

is a 10-port, 32-register (16 primary, 16 secondary) file. Each

SHARC’s core also implements two data address generators

(DAGs), implementing circular data buffers in hardware. T he

DAGs contain sufficient registers to allow the creation of up to

32 circular buffers. T he 48-bit instruction word accommodates a

variety of parallel operations, for concise programming. For ex-

ample, the ADSP-21060 can conditionally execute a multiply, an

add, a subtract, and a branch, all in a single instruction.

Shar ed Mem or y Multipr ocessing

T he AD14060/AD14060L takes advantage of the powerful

multiprocessing features built into the SHARC. The SHARCs are

connected to maximize the performance of this cluster-of-four

architecture, and still allow for off-module expansion. T he

AD14060/AD14060L in itself is a complete shared memory

multiprocessing system, as shown in Figure 3. T he unified ad-

dress space of the SHARCs allows direct interprocessor ac-

cesses of each SH ARCs’ internal memory. In other words, each

SHARC can directly access the internal memory and IOP registers

of each of the other SHARCs by simply reading or writing to the

appropriate address in multiprocessor memory space (see Figure

2)—this is called a direct read or direct write.

DUAL-PORTED SRAM

CORE PROCESSOR

INSTRUCTION

TIMER

JTAG

TWO INDEPENDENT

DUAL-PORTED BLOCKS

7

CACHE

32 x 48-BIT

TEST AND

EMULATION

PROCESSOR PORT

ADDR DATA

I/O PORT

DATA ADDR

DATA

ADDR

DATA

DAG1

8 x 4 x 32

DAG2

8 x 4 x 24

PROGRAM

SEQUENCER

EXTERNAL

PORT

IOD

48

IOA

17

PM ADDRESS BUS

24

32

48

ADDR BUS

MUX

DM ADDRESS BUS

PM DATA BUS

MULTIPROCESSOR

INTERFACE

48

BUS

CONNECT

(PX)

DATA BUS

MUX

DM DATA BUS 40/32

HOST PORT

4

6

DMA

DATA

REGISTER

FILE

IOP

REGISTERS

MEMORY MAPPED)

CONTROLLER

(

SERIAL PORTS

(2)

16 x 40-BIT

BARREL

SHIFTER

6

MULTIPLIER

ALU

CONTROL,

STATUS, AND

DATA BUFFERS

36

LINK PORTS

(6)

I/O PROCESSOR

Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14060)

REV. A

–2–

AD14060/AD14060L

0x0000 0000

0x0002 0000

0x0040 0000

IOP REGISTERS

INTERNAL

MEMORY

SPACE

(INDIVIDUAL

SHARCs)

BANK 0

MS

0

NORMAL WORD ADDRESSING

SHORT WORD ADDRESSING

DRAM

(OPTIONAL)

0x0004 0000

0x0008 0000

INTERNAL MEMORY SPACE

OF SHARC_A

BANK 1

BANK 2

MS

1

ID=001

0x0010 0000

0x0018 0000

INTERNAL MEMORY SPACE

OF SHARC_B

ID=010

INTERNAL

TO AD14060

MS

INTERNAL MEMORY SPACE

OF SHARC_C

2

ID=011

EXTERNAL

MEMORY

SPACE

0x0020 0000

0x0028 0000

INTERNAL MEMORY SPACE

OF SHARC_D

MULTIPROCESSOR

MEMORY SPACE

ID=100

MS

BANK 3

3

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=101

BANK SIZE IS

SELECTED BY

MSIZE BIT FIELD OF

SYSCON

EXTERNAL

TO AD14060

0x0030 0000

0x0038 0000

0x003F FFFF

INTERNAL MEMORY SPACE

OF ADSP-2106x

WITH ID=110

REGISTER.

BROADCAST WRITE

TO ALL

NONBANKED

ADSP-2106xs

NORMAL WORD ADDRESSING: 32-BIT DATA WORDS

48-BIT INSTRUCTION WORDS

SHORT WORD ADDRESSING: 16-BIT DATA WORDS

0xFFFF FFFF

Figure 2. AD14060/AD14060L Mem ory Map

SYSTEM EXPANSION

SHARC_A

SHARC_B

ADDR

DATA

CLKIN

1X CLOCK

31-0

LINKS 1, 3, & 4; LINKS 1, 3, & 4;

IRQ IRQ

;

2-0

47-0

RD

2-0

RESET

FLAGS 2 & 0;

TIMEXP,

SPORT1

FLAGS 2 & 0;

TIMEXP,

SPORT1

RPBA

WR

CPA

ACK

BOOTSELECT A

MS

3-0

PAGE

BOOTSELECT BCD

SBTS

SW

AD14060/AD14060L

(QUAD PROCESSOR

CLUSTER)

DMAR1,2

DMAG1,2

ADRCLK

CS

HBR

SHARC_D

SHARC_C

SPORT0

FLAG1

LINKS 1, 3, & 4; LINKS 1, 3, & 4;

IRQ IRQ

HBG

;

2-0

REDY

FLAGS 2 & 0;

TIMEXP,

SPORT1

FLAGS 2 & 0;

TIMEXP,

SPORT1

JTAG

BR

1-6

Figure 3. Com plete Shared Mem ory Multiprocessing System

REV. A

–3–

AD14060/AD14060L

off-module memory and peripherals (see Figure 5). T his port

consists of the complete external port bus of the SHARC, bused

together in common among the four SHARCs.

Bus arbitration is accomplished with the on-SHARC arbitration

logic. Each SHARC has a unique ID, and drives the Bus-Request

(BR) line corresponding to its ID, while monitoring all others.

BR1–BR4 are used within the AD14060/AD14060L, while BR5

and BR6 can be used for expansion. All bus requests (BR1–BR6)

are included in the module I/O.

T he 4-gigaword off-module address space is included in the

ADSP-14060’s unified address space. Addressing of external

memory devices is facilitated by each SH ARC internally de-

coding the high order address lines to generate memory bank

select signals. Separate control lines are also generated for sim-

plified addressing of page-mode DRAM. T he AD14060/

AD14060L also supports programmable memory wait states and

external memory acknowledge controls to allow interfacing to

DRAM and peripherals with variable access, hold and disable

time requirements.

T wo different priority schemes, fixed and rotating, are available

to resolve competing bus requests. The RPBA pin selects which

scheme is used: when RPBA is high, rotating priority bus arbitra-

tion is selected, and when RPBA is low, fixed priority is selected.

Table I. Rotating P riority Arbitration Exam ple

H ardware P rocessor ID s

Cycle ID 1 ID 2

ID 3

ID 4 ID 5 ID 6

Link P or t I/O

Each individual SHARC features six 4-bit link ports that facili-

tate SHARC-to-SHARC communication and external I/O inter-

facing. Each link port can be configured for either 1× or 2×

operation, allowing each to transfer either 4 or 8 bits per cycle.

T he link ports can operate independently and simultaneously,

with a maximum bandwidth of 40 MBytes/s each, or a total of

240 MBytes/s per SHARC.

1

2

3

4

5

M

4

5 BR

1 BR

1

2 BR

3

1

2

4

2

3

5

3

Initial Priority Assignments

Final Priority Assignments

5 BR M-BR

5 BR

M

1

3

4 BR

M

2

NOT ES

1–5 = Assigned Priority.

M = Bus Mastership (in that cycle).

BR = Requesting Bus Mastership with BRx.

T he AD14060/AD14060L optimizes the link port connections

internally, and brings a total of twelve of the link ports off-mod-

ule for user-defined system connections. Internally, each SHARC

has a connection to the other three SHARCs with a dedicated

link port interface. T hus, each SHARC can directly interface

with its nearest and next-nearest neighbor. T he remaining three

link ports from each SHARC are brought out independently

from each SH ARC. A maximum of 480 MBytes/s link port

bandwidth is then available off of the AD14060/AD14060L.

T he link port connections are detailed in Figure 4.

Bus mastership is passed from one SHARC to another during a

bus transition cycle. A bus transition cycle only occurs when the

current bus master deasserts its BR line and one of the slave

SHARCs asserts its BR line. T he bus master can therefore re-

tain bus mastership by keeping its BR line asserted. When the

bus master deasserts its BR line, and no other BR line is as-

serted, then the master will not lose any bus cycles. When more

than one SHARC asserts its BR line, the SHARC with the

highest priority request becomes bus master on the following

cycle. Each SHARC observes all of the BR lines, and therefore

tracks when a bus transition cycle has occurred, and which

processor has become the new bus master. Master processor

changeover incurs only one cycle of overhead. An example bus

transition sequence is shown in T able I.

1

3

4

1

3

4

5

2

5

2

SHARC_A

SHARC_B

Bus locking is possible, allowing indivisible read-modify-write

sequences for semaphores. In either the fixed or rotating priority

scheme, it is also possible to limit the number of cycles the

master can control the bus. T he AD14060/AD14060L also

provides the option of using the Core Priority Access (CPA)

mode of the SHARC. Using the CPA signal allows external bus

accesses by the core processor of a slave SHARC to take priority

over ongoing DMA transfers. Also, each SHARC can broadcast

write to all other SHARCs simultaneously, allowing the imple-

mentation of reflective semaphores.

0

1

3

4

1

3

4

2

5

2

5

SHARC_D

SHARC_C

T he bus master can communicate with slave SHARCs by writ-

ing messages to their internal IOP registers. T he MSRG0–

MSRG7 registers are general-purpose registers that can be used

for convenient message passing, semaphores and resource shar-

ing between the SHARCs. For message passing, the master

communicates with a slave by writing and/or reading any of the

eight message registers on the slave. For vector interrupts, the

master can issue a vector interrupt to a slave by writing the

address of an interrupt service routine to the slave’s VIRPT

register. T his causes an immediate high priority interrupt on the

slave which, when serviced, will cause it to branch to the speci-

fied service routine.

Figure 4. Link Port Connections

Link port 4, the boot link port, is brought off independently

from each SH ARC. Individual booting is then allowed, or

chained link port booting is possible as described under “Link

Port Booting.”

Link port data is packed into 32-bit or 48-bit words, and can

be directly read by the SH ARC core processor or DMA-

transferred to on-SH ARC memory.

Each link port has its own double-buffered input and output

registers. Clock/acknowledge handshaking controls link port

transfers. T ransfers are programmable as either transmit or

O ff-Module Mem or y and P er ipher als Inter face

The AD14060/AD14060L’s external port provides the interface to

receive.

REV. A

–4–

AD14060/AD14060L

AD14060/

AD14060L

1x

CLOCK

CLKIN

RESET

RPBA

ADDR

DATA

31–0

GLOBAL

MEMORY

DATA

47–0

RESET

AND

PERIPHERALS

(OPTIONAL)

RD

OE

WE

WR

ACK

MS

CS

3–0

CS

BMS

BOOT

EPROM

(OPTIONAL)

PAGE

ADDR

DATA

SBTS

SW

CONTROL

ADRCLK

CS

HBR

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

HBG

REDY

ADDR

DATA

SERIALS

LINKS

CPA

5

BR

2–6

DISCRETES

BR

1

ADSP-2106x #5

(OPTIONAL)

ADDR

31–0

47–0

CLKIN

DATA

RESET

RPBA

3

101

ID

2–0

CONTROL

CPA

5

BR

1, 2, 3, 4, 6

BR

5

ADSP-2106x #6

(OPTIONAL)

ADDR

DATA

CLKIN

31–0

47–0

RESET

RPBA

3

110

ID

2–0

CONTROL

CPA

BR

5

1–5

BR

6

Figure 5. Optional System Interconnections

REV. A

–5–

AD14060/AD14060L

Ser ial P or ts

Multipr ocessor Link Por t Booting

T he SHARC serial ports provide an inexpensive interface to a

wide variety of digital and mixed-signal peripheral devices. Each

SHARC has two serial ports. The AD14060/AD14060L provides

direct access to Serial Port 1 of each SH ARC. Serial Port 0

is bused together in common to each SH ARC, and brought

off-module.

Booting can also be accomplished from a single source through

the link ports. Link Buffer 4 must always be used for booting.

T o simultaneously boot all of the ADSP-21060s, a parallel

common connection is available through Link Port 4 on each of

the processors. Or, using the daisy chain connection that exists

between the processors’ link ports, each ADSP-21060 can boot

the next one in turn. In this case, the Link Assignment Register

(LAR) must be programmed to configure the internal link ports

with Link Buffer 4.

T he serial ports can operate at the full clock rate of the module,

providing each with a maximum data rate of 40 Mbit/s. Inde-

pendent transmit and receive functions provide more flexible

communications. Serial port data can be automatically trans-

ferred to and from on-SHARC memory via DMA, and each of

the serial ports offers time division multiplexed (T DM) multi-

channel mode.

Multipr ocessor Booting Fr om Exter na l Mem or y

If external memory contains a program after reset, then

SHARC_A should be set up for no boot mode; it will begin ex-

ecuting from address 0x0040 0004 in external memory. When

booting has completed, the other ADSP-21060s may be booted

by SHARC_A if they are set up for host booting, or they can

begin executing out of external memory if they are set up for no

boot mode. Multiprocessor bus arbitration will allow this booting

to occur in an orderly manner.

T he serial ports can operate with little-endian or big-endian

transmission formats, with word lengths selectable from 3 bits to

32 bits. They offer selectable synchronization and transmit modes

as well as optional µ-law or A-law companding. Serial port clocks

and frame syncs can be internally or externally generated.

H ost P r ocessor Inter face

P r ogr am Booting

T he AD14060/AD14060L’s host interface allows for easy con-

nection to standard microprocessor buses, both 16-bit and 32-

bit, with little additional hardware required. Asynchronous

transfers at speeds up to the full clock rate of the module are

supported. T he host interface is accessed through the AD14060/

AD14060L external port and is memory-mapped into the uni-

fied address space. Four channels of DMA are available for the

host interface; code and data transfers are accomplished with

low software overhead.

T he AD14060/AD14060L supports automatic downloading of

programs following power-up or a software reset. T he SHARC

offers four options for program booting: 1) from an 8-bit

EPROM; 2) from a host processor; 3) through the link ports;

and 4) no-boot. In no-boot mode, the SHARC starts executing

instructions from address 0x0040 0004 in external memory.

T he boot mode is selected by the state of the following signals:

BMS, EBOOT , and LBOOT .

On the AD14060/AD14060L, SHARC_A’s boot mode is sepa-

rately controlled, while SHARCs B, C, and D are controlled as

a group. With this flexibility, the AD14060/AD14060L can be

configured to boot in any of the following methods.

T he host processor requests the AD14060/AD14060L’s external

bus with the host bus request (HBR), host bus grant (HBG),

and ready (REDY) signals. T he host can directly read and write

the internal memory of the SHARCs, and can access the DMA

channel setup and mailbox registers. Vector interrupt support is

provided for efficient execution of host commands.

Multipr ocessor Host Booting

T o boot multiple ADSP-21060 processors from a host, each

ADSP-21060 must have its EBOOT , LBOOT and BMS pins

configured for host booting: EBOOT = 0, LBOOT = 0, and

BMS = 1. After system power-up, each ADSP-21060 will be in

the idle state and the BRx bus request lines will be deasserted.

T he host must assert the HBR input and boot each ADSP-21060

by asserting its CS pin and downloading instructions.

D ir ect Mem or y Access (D MA) Contr oller

T he SHARCs on-chip DMA control logic allows zero-overhead

data transfers without processor intervention. T he DMA con-

troller operates independently and invisibly to each SHARCs

processor core, allowing DMA operations to occur while the core

is simultaneously executing its program instructions.

Multipr ocessor EPROM Booting

DMA transfers can occur between SH ARC internal memory

and either external memory, external peripherals, or a host

processor. DMA transfers can also occur between the SHARC’s

internal memory and its serial ports or link ports. DMA trans-

fers between external memory and external peripheral devices are

another option. External bus packing to 16-, 32- or 48-bit words

is performed during DMA transfers.

T here are two methods of booting the multiprocessor system

from an EPROM.

SHARC_A Is Booted, Which Then Boots the Other s. T he

EBOOT pin on the SHARC_A must be set high for EPROM

booting. All other ADSP-21060s should be configured for host

booting (EBOOT = 0, LBOOT = 0, and BMS = 1), which

leaves them in the idle state at start-up and allows SHARC_A

to become bus master and boot itself. Only the BMS pin of

SH ARC_A is connected to the chip select of the EPROM.

When SH ARC_A has finished booting, it can boot the re-

maining ADSP-21060s by writing to their external port DMA

buffer 0 (EPB0) via multiprocessor memory space.

T en channels of DMA are available on the SHARCs—two via

the link ports, four via the serial ports, and four via the processor’s

external port (for either host processor, other SHARCs, memory,

or I/O transfers). Four additional link port DMA channels are

shared with serial port 1 and the external port. Programs can be

downloaded to the SHARCs using DMA transfers. Asynchronous

off-module peripherals can control two DMA channels using

DMA Request/Grant lines (DMAR1-2, DMAG1-2). Other

DMA features include interrupt generation upon completion of

DMA transfers and DMA chaining for automatic linked DMA

transfers.

All ADSP-21060s Boot in Tur n Fr om a Single EPROM.

T he BMS signals from each ADSP-21060 may be wire-ORed

together to drive the chip select pin of the EPROM. Each

ADSP-21060 can boot in turn, according to its priority. When

the last one has finished booting, it must inform the others

(which may be in the idle state) that program execution can begin.

REV. A

–6–

AD14060/AD14060L

D evelopm ent Tools

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC PC plug-in cards, multiprocessor

SHARC VME boards, and daughter card modules with multiple

SHARCs and additional memory. T hese modules are based on

the SHARCPAC module specification. T hird party software

tools include an Ada compiler, DSP libraries, operating systems

and block diagram design tools.

T he ADSP-14060 is supported with a complete set of software

and hardware development tools, including an EZ-LAB^®In-

Circuit Emulator, and development software.

Analog Devices’ ADSP-21000 Family Development Software

includes an easy to use Assembler based on an algebraic syntax,

an Assembly Library/Librarian, a Linker, an Instruction-Level

Simulator, an ANSI C optimizing Compiler, the CBug™ C

Source-Level Debugger, and a C Runtime Library including

DSP and mathematical functions. T he Optimizing Compiler

includes Numerical C extensions based on the work of the ANSI

Numerical C Extensions Group. Numerical C provides exten-

sions to the C language for array selection, vector math op-

erations, complex data types, circular pointers and variably

dimensioned arrays. T he ADSP-21000 Family Development

Software is available for both the PC and Sun platforms.

Q uad-SH ARC D evelopm ent Boar d

T he BlackT ip-MCM, AD14060 development board and soft-

ware, is available from Bittware Research Systems, Inc. This

board has one AD14060 BIT SI interface, PROM and SRAM

expansion options on an ISA card. It is supported by Bittware’s

SHARC software development package. Bittware can be con-

tacted at 1-800-848-0436.

T he SHARC EZ-KIT combines the ADSP-21000 Family De-

velopment Software for the PC and the EZ-LAB Development

Board in one package.

T he ADSP-2106x EZ-ICE^®Emulator uses the IEEE 1149.1

JT AG test access port of the ADSP-2106x processor to monitor

and control the target board processor during emulation. T he

EZ-ICE provides full-speed emulation, allowing inspection and

modification of memory, registers and processor stacks.

O ther P ackage D etails

T he AD14060/AD14060L contains 16 on-module 0.018 micro-

farad bypass capacitors. It is recommended that in the target

system at least four additional capacitors, of 0.018 microfarad

value, be placed around the module—one near each of the four

corners.

T he top surface, lid, of the AD14060/AD14060L is electrically

connected to GND on the industrial and military grade parts.

Nonintrusive in-circuit emulation is assured by the use of the

processor’s JT AG interface—the emulator does not affect target

system loading or timing.

Additional Infor m ation

T his data sheet provides a general overview of the AD14060/

AD14060L architecture and functionality. For detailed infor-

mation on the ADSP-2106x SH ARC and the ADSP-21000

Family core architecture and instruction set, refer to the ADSP-

2106x SHARC User’s Manual.

Further details and ordering information are available in the

ADSP-21000 Family Hardware & Software Development Tools

data sheet (ADDS-2100xx-T OOLS). T his data sheet can be

requested from any Analog Devices sales office or distributor,

or from the Literature Center.

EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.

CBug is a trademark of Analog Devices, Inc.

REV. A

–7–

AD14060/AD14060L

P IN FUNCTIO N D ESCRIP TIO NS

T CLKx, RCLKx, LxDAT_3-0, LxCLK, LxACK, T MS and

T DI)—these pins can be left floating. T hese pins have a logic-

level hold circuit that prevents the input from floating internally.

AD14060/AD14060L pin definitions are listed below. Inputs

identified as synchronous (S) must meet timing requirements

with respect to CLKIN (or with respect to T CK for T MS,

T DI). Inputs identified as asynchronous (A) can be asserted

asynchronously to CLKIN (or to T CK for TRST).

I = Input

P = Power Supply (A/D) = Active Drive

O = Output

G = Ground

S = Synchronous

A = Asynchronous

(O/D) = Open Drain

Unused inputs should be tied or pulled to V_DDor GND, except

for ADDR_31-0, DAT A_47-0, FLAG_2-0, SW, and inputs that have

internal pull-up or pull-down resistors (CPA, ACK, DT x, DRx,

T = Three-State (when SBTS is asserted, or when the AD14060/

AD14060L is a bus slave)

P in

Type

Function

ADDR_31-0

I/O/T

Exter nal Bus Addr ess. (Common to all SHARCs) T he AD14060/AD14060L outputs addresses for

external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs

addresses for read/writes on the internal memory or IOP registers of slave ADSP-2106xs. The AD14060/

AD14060L inputs addresses when a host processor or multiprocessing bus master is reading or writing

the internal memory or IOP registers of internal ADSP-21060s.

DAT A_47-0

I/O/T

O/T

Exter nal Bus D ata. (Common to all SHARCs) T he AD14060/AD14060L inputs and outputs data and

instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is trans-

ferred over bits 47-16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47-

8 of the bus. 16-bit short word data is transferred over bits 31-16 of the bus. In PROM boot mode, 8-bit

data is transferred over bits 23-16. Pull-up resistors on unused DAT A pins are not necessary.

MS_3-0

Mem or y Select Lines. (Common to all SHARCs) T hese lines are asserted (low) as chip selects for the

corresponding banks of external memory. Memory bank size must be defined in the individual ADSP-

21060’s system control registers (SYSCON). T he MS_3-0lines are decoded memory address lines that

change at the same time as the other address lines. When no external memory access is occurring the MS_3-0

lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether

or not the condition is true. MS₀can be used with the PAGE signal to implement a bank of DRAM memory

(Bank 0). In a multiprocessing system, the MS_3-0lines are output by the bus master.

RD

I/O/T

O/T

Mem or y Read Str obe. (Common to all SH ARCs) T his pin is asserted (low) when the AD14060/

AD14060L reads from external devices or when the internal memory of internal ADSP-2106xs is being

accessed. External devices (including other ADSP-2106xs) must assert RD to read from the AD14060/

AD14060L’s internal memory. In a multiprocessing system, RD is output by the bus master and is input

by all other ADSP-2106xs.

WR

Mem or y Wr ite Str obe. (Common to all SH ARCs) T his pin is asserted (low) when the AD14060/

AD14060L writes to external devices or when the internal memory of internal ADSP-2106xs is being ac-

cessed. External devices (including other ADSP-2106xs) must assert WR to write to the AD14060/

AD14060L’s internal memory. In a multiprocessing system WR is output by the bus master and is input by

all other ADSP-2106xs.

PAGE

D RAM P age Boundar y. (Common to all SHARCs) T he AD14060/AD14060L asserts this pin to signal

that an external DRAM page boundary has been crossed. DRAM page size must be defined in the indi-

vidual ADSP-21060’s memory control register (WAIT ). DRAM can only be implemented in external

memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system,

PAGE is output by the bus master.

ADRCLK

O/T

Clock O utput Refer ence. (Common to all SHARCs) In a multiprocessing system, ADRCLK is output

by the bus master.

SW

I/O/T

Synchr onous Wr ite Select. (Common to all SHARCs) T his signal is used to interface the AD14060/

AD14060L to synchronous memory devices (including other ADSP-2106xs). T he AD14060/AD14060L

asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR

is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output

by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory

access is a read or write. SW is asserted at the same time as the address output. A host processor using

synchronous writes must assert this pin when writing to the AD14060/AD14060L.

ACK

I/O/S

Mem or y Acknowledge. (Common to all SHARCs) External devices can deassert ACK (low) to add

wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other pe-

ripherals to hold off completion of an external memory access. T he AD14060/AD14060L deasserts

ACK, as an output, to add wait states to a synchronous access of its internal memory. In a multiprocess-

ing system, a slave ADSP-2106x deasserts the bus master’s ACK input to add wait state(s) to an access

of its internal memory. T he bus master has a keeper latch on its ACK pin that maintains the input at the

level it was last driven to.

REV. A

–8–

AD14060/AD14060L

P in

Type

Function

SBTS

I/S

Su spen d Bu s T h r ee- State. (Common to all SHARCs) External devices can assert SBTS (low) to

place the external bus address, data, selects, and strobes in a high impedance state for the following cycle.

If the AD14060/AD14060L attempts to access external memory while SBTS is asserted, the processor

will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be

used to recover from host processor/AD14060/AD14060L deadlock, or used with a DRAM controller.

HBR

HBG

I/A

I/O

H ost Bus Request. (Common to all SHARCs) Must be asserted by a host processor to request control

of the AD14060/AD14060L’s external bus. When HBR is asserted in a multiprocessing system, the

ADSP-2106x that is bus master will relinquish the bus and assert HBG. T o relinquish the bus, the

ADSP-2106x places the address, data, select, and strobe lines in a high impedance state. HBR has priority

over all ADSP-2106x bus requests (BR_6-1) in a multiprocessing system.

H ost Bus Gr ant. (Common to all SHARCs) Acknowledges an HBR bus request, indicating that the

host processor may take control of the external bus. HBG is asserted (held low) by the AD14060/AD14060L

until HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus master and is

monitored by all others.

CSA

I/A

O

Chip Select. Asserted by host processor to select SHARC_A.

Chip Select. Asserted by host processor to select SHARC_B.

Chip Select. Asserted by host processor to select SHARC_C.

Chip Select. Asserted by host processor to select SHARC_D.

CSB

CSC

CSD

REDY (O/D)

H ost Bus Acknowledge. (Common to all SHARCs) T he AD14060/AD14060L deasserts REDY (low)

to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain

output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP-

21060s to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted.

BR_6-1

I/O/S

I/S

Multipr ocessing Bus Requests. (Common to all SHARCs) Used by multiprocessing ADSP-2106xs to

arbitrate for bus mastership. An ADSP-2106x only drives its own BRx line (corresponding to the value of

its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the

unused BRx pins should be pulled high; BR_4-1must not be pulled high or low because they are outputs.

RPBA

Rotating P r ior ity Bus Ar bitr ation Select. (Common to all SHARCs) When RPBA is high, rotating

priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This

signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the

value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on

every ADSP-2106x.

CPAy (O/D)

I/O

Cor e P r ior ity Access. (y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an

ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus.

CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is

required. T he CPA pin of each internal ADSP-21060 is brought out individually. T he CPA pin has

an internal 5 kΩ pull-up resistor. If core access priority is not required in a system, the CPA pin

should be left unconnected.

DT 0

O/T

I

D ata Tr ansm it (Common Serial Ports 0 to all SHARCs, T DM). DT pin has a 50 kΩ internal pull-up

resistor.

DR0

D ata Receive (Common Serial Ports 0 to all SHARCs, T DM). DR pin has a 50 kΩ internal pull-up

resistor.

T CLK0

RCLK0

I/O

Tr an sm it C lock (Common Serial Ports 0 to all SH ARCs, T DM). T CLK pin has a 50 kΩ internal

pull-up resistor.

Receive Clock (Common Serial Ports 0 to all SHARCs, T DM). RCLK pin has a 50 kΩ internal pull-up

resistor.

T FS0

RFS0

DT y1

I/O

O/T

Tr ansm it Fr am e Sync (Common Serial Ports 0 to all SHARCs, T DM).

Receive Fr am e Sync (Common Serial Ports 0 to all SHARCs, T DM).

D ata Tr ansm it (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin

has a 50 kΩ internal pull-up resistor.

DRy1

I

D ata Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin

has a 50 kΩ internal pull-up resistor.

REV. A

–9–

AD14060/AD14060L

P in

Type

Function

T CLKy1

I/O

Transm it Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) T CLK

pin has a 50 kΩ internal pull-up resistor.

RCLKy1

I/O

Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK

pin has a 50 kΩ internal pull-up resistor.

T FSy1

RFSy1

I/O

Transm it Fram e Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)

Receive Fram e Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)

I/O

FLAGy0

I/O/A

Flag P ins. (FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-

ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-

put, it can be used to signal external peripherals.

FLAG1

FLAGy2

IRQy2-0

I/O/A

I/A

Flag P ins. (FLAG1 common to all SHARCs) Configured via control bits internal to individual ADSP-

21060s as either an input or output. As an input, it can be tested as a condition. As an output, it can be

used to signal external peripherals.

Flag P ins. (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is config-

ured via control bits as either an input or output. As an input, it can be tested as a condition. As an out-

put, it can be used to signal external peripherals.

Interrupt Request Lines. (Individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D)

May be either edge-triggered or level-sensitive.

DMAR1

DMAR2

DMAG1

DMAG2

LyxCLK

I/A

O/T

I/O

DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.

DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.

DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.

DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.

Link P or t Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)¹. Each LyxCLK pin has a 50 kΩ

internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the

ADSP-20160.

LyxDAT 3-0

LyxACK

I/O

I

Lin k P or t D ata (y = SH ARC_A, B, C, D; x = Link Ports 1, 3, 4)¹. Each LyxDAT pin has a

50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,

of the ADSP-21060.

Link P or t Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)¹. Each LyxACK pin has a

50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,

of the ADSP-21060.

EBOOT A

EP RO M Boot Select. (SHARC_A) When EBOOT A is high, SHARC_A is configured for booting from

an 8-bit EPROM. When EBOOT A is low, the LBOOT A and BMSA inputs determine booting mode

for SH ARC_A. See the following table. T his signal is a system configuration selection which should

be hardwired.

LBOOT A

I

Link Boot. When LBOOT A is high, SHARC_A is configured for link port booting. When LBOOT A is

low, SHARC_A is configured for host processor booting or no booting. See the following table. T his

signal is a system configuration selection which should be hardwired.

BMSA

I/O/T²

Boot Mem or y Select. Output: Used as chip select for boot EPROM devices (when EBOOT A = 1,

LBOOT A = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates

that no booting will occur and that SHARC_A will begin executing instructions from external memory.

See the following table. T his input is a system configuration selection which should be hardwired.

EBOOT BCD

LBOOT BCD

I

EP RO M Boot Select. (Common to SHARC_B, SHARC_C, SHARC_D) When EBOOT BCD is high,

SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOT BCD is low, the

LBOOT BCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following

table. T his signal is a system configuration selection which should be hardwired.

LINK Boot. (Common to SHARC_B, SHARC_C, SHARC_D) When LBOOTBCD is high, SHARC_B, C,

D are configured for link port booting. When LBOOT BCD is low, SHARC_B, C, D are configured for

host processor booting or no booting. See the following table. T his signal is a system configuration selec-

tion which should be hardwired.

REV. A

–10–

AD14060/AD14060L

P in

Type

Function

BMSBCD

I/O/T²

Boot Mem or y Select. Output: Used as chip select for boot EPROM devices (when EBOOT BCD = 1,

LBOOT BCD = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low,

indicates that no booting will occur and that SHARC_B, C, D will begin executing instructions from

external memory. See table below. T his input is a system configuration selection which should be

hardwired.

EBOOT

LBOOT

BMS

Booting Mode

1

0

1

0

1

0

1

Output

1 (Input) Host Processor

1 (Input) Link Port

0 (Input) No Booting. Processor executes from external memory.

0 (Input) Reserved

EPROM (Connect BMS to EPROM chip select)

x (Input) Reserved

T IMEXPy

CLKIN

O

I

Tim er Expired. (Individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Asserted

for four cycles when the timer is enabled and T COUNT decrements to zero.

Clock In. (Common to all SHARCs) External clock input to the AD14060/AD14060L. T he instruction

cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified

frequency.

RESET

T CK

T MS

T DI

I/A

I

Module Reset. (Common to all SHARCs) Resets the AD14060/AD14060L to a known state. T his input

must be asserted (low) at power-up.

Test Clock (JTAG). (Common to all SHARCs) Provides an asynchronous clock for JT AG boundary

scan.

I/S

Test Mode Select (JTAG). (Common to all SHARCs) Used to control the test state machine. T MS has

a 20 kΩ internal pull-up resistor.

Test D ata Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A.

T DI has a 20 kΩ internal pull-up resistor.

T DO

O

Test D ata O utput (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.

TRST

I/A

Test Reset (JTAG). (Common to all SHARCs) Resets the test state machine. TRST must be asserted

(pulsed low) after power-up or held low for proper operation of the AD14060/AD14060L. TRST has a

20 kΩ internal pull-up resistor.

EMU (O/D)

O

Em ulation Status. (Common to all SHARCs) Must be connected to the ADSP-2106x EZ-ICE target

board connector only.

V_DD

P

P ower Supply. Nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices (26 pins).

P ower Supply Retur n. (28 pins).

GND

G

NOT ES

FLAG3 is connected internally, common to SHARC_A, B, C, and D.

ID pins are hardwired internally as depicted in the block diagram.

¹LINK PORT S 0, 2 and 5 are connected internally as described earlier in Link Port I/O.

²T hree-statable only in EPROM boot mode (when BMS is an output).

REV. A

–11–

AD14060/AD14060L

T he 14-pin, 2-row pin strip header is keyed at the Pin 3 location;

Pin 3 must be removed from the header. T he pins must be

0.025 inch square and at least 0.20 inch in length. Pin spacing

should be 0.1 × 0.1 inches. Pin strip headers are available from

vendors such as 3M, McKenzie and Samtec.

TARGET BO ARD CO NNECTO R FO R EZ-ICE P RO BE

The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG

test access port of the ADSP-2106x to monitor and control the

target board processor during emulation. T he EZ-ICE probe

requires that the AD14060/AD14060L’s CLKIN (optional),

T MS, T CK, TRST, T DI, T DO, EMU and GND signals be

made accessible on the target system via a 14-pin connector (a

pin strip header) such as that shown in Figure 6. T he EZ-ICE

probe plugs directly onto this connector for chip-on-board emu-

lation. You must add this connector to your target board design

if you intend to use the ADSP-2106x EZ-ICE. T he length of

the traces between the connector and the AD14060/

T he BT MS, BT CK, BTRST and BT DI signals are provided so

that the test access port can also be used for board-level testing.

When the connector is not being used for emulation, place

jumpers between the Bxxx pins and the xxx pins as shown in

Figure 6. If you are not going to use the test access port for

board testing, tie BTRST to GND and tie or pull up BTCK to

V_DD. The TRST pin must be asserted after power-up (through

AD14060L’s JT AG pins should be as short as possible.

BTRST on the connector) or held low for proper operation of

the AD14060/AD14060L. None of the Bxxx pins (Pins 5, 7, 9,

11) are connected on the EZ-ICE probe.

1

3

5

2

4

6

EMU

GND

The JTAG signals are terminated on the EZ-ICE probe as follows:

KEY (NO PIN)

CLKIN (OPTIONAL)

TMS

Signal

Term ination

T MS

T CK

Driven through 22 Ω Resistor (16 µA–3.2 µA Driver)

Driven at 10 MHz through 22 Ω Resistor (16 µA–

3.2 µA Driver)

BTMS

7

9

8

TCK

BTCK

TRST

Driven by Open-Drain Driver* (Pulled Up by On-Chip

20 kΩ resistor)

10

12

BTRST

TRST

9

T DI

Driven by 16 µA–3.2 µA Driver

11

T DO

One T T L Load, No T ermination

BTDI

GND

TDI

CLKIN One T T L Load, No T ermination (Optional Signal)

EMU

4.7 kΩ Pull-Up Resistor, One TTL Load (Open-Drain

13

14

TDO

Output from ADSP-2106x)

*TRST is driven low until the EZ-ICE probe is turned on by the EZ-ICE

TOP VIEW

software (after the invocation command).

Figure 6. Target Board Connector for ADSP-2106x EZ-ICE

Em ulator (J um pers in Place)

Figure 7 shows JT AG scan path connections for the multi-

processor system.

Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.

T he emulator only uses CLKIN when directed to perform

JTAG DEVICE

(OPTIONAL)

ADSP-2106x

#n

SHARC_A

SHARC_B

SHARC_C

SHARC_D

TDI

TDO

TDI

TDO

TDI

TDO

TDI

TDO

TDI

TDO

TDI

TDO

EZ-ICE

JTAG

CONNECTOR

OTHER

JTAG

CONTROLLER

TCK

TMS

EMU

TRST

TDO

CLKIN

OPTIONAL

Figure 7. J TAG Scan Path Connections for the AD14060/AD14060L

REV. A

–12–

AD14060/AD14060L

operations such as starting, stopping and single-stepping mul-

tiple ADSP-2106xs in a synchronous manner. If you do not

need these operations to occur synchronously on the multiple

processors, simply tie Pin 4 of the EZ-ICE header to ground.

as possible on your board. If T CK, T MS and CLKIN are driv-

ing a large number of ADSP-2106xs (more than eight) in your

system, then treat them as a “clock tree” using multiple drivers

to minimize skew. (See Figure 8 JT AG Clock T ree and Clock

Distribution in the “High Frequency Design Considerations”

section of the ADSP-2106x User’s Manual).

If synchronous multiprocessor operations are needed and CLKIN

is connected, clock skew between the AD14060/AD14060L and

the CLKIN pin on the EZ-ICE header must be minimal. If the

skew is too large, synchronous operations may be off by one

cycle between processors. For synchronous multiprocessor

operation T CK, T MS, CLKIN and EMU should be treated as

critical signals in terms of skew, and should be laid out as short

If synchronous multiprocessor operations are not needed (i.e.,

CLKIN is not connected), just use appropriate parallel termina-

tion on T CK and T MS. T DI, T DO, EMU and TRST are not

critical signals in terms of skew.

TDI

TDO

TDI

TDO

TDI

TDO

5k⍀

*

TDI

TDO

TDI

TDO

TDI

TDO

TDI

5k⍀

*

EMU

TCK

TMS

TRST

TDO

SYSTEM

CLKIN

EMU

*

OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,

Figure 8. J TAG Clocktree for Multiple ADSP-2106x System s

REV. A

–13–

AD14060/AD14060L–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

B Grade

Min

K Grade

P ar am eter

Max

Min

Max

Units

V_DD

Supply Voltage (5 V)

Supply Voltage (3.3 V)

Case Operating T emperature

4.75

3.15

–40

5.25

3.6

+100

4.75

3.15

0

5.25

3.6

+85

V

°C

T _CASE

ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)

Case

Test

5 V

3.3 V

Min Typ Max

P ar am eter

Tem p Level Test Condition

Min Typ Max

Units

V_IH1

V_IH2

V_IL

V_OH

V_OL

I_IH

High Level Input Voltage¹

Full

I

@ V_DD= max

@ V_DD= min

2.0

2.2

V_DD+ 0.5 2.0

V_DD+ 0.5 2.2

0.8

2.4

0.4

10

V_DD+ 0.5

0.8

V

High Level Input Voltage²

Low Level Input Voltage^{1, 2}

High Level Output Voltage^{3, 4}

Low Level Output Voltage^{3, 4}

High Level Input Current^{5, 6, 7}

Low Level Input Current⁵

@ V_DD= min, I_OH= –2.0 mA⁴

@ V_DD= min, I_OL= 4.0 mA⁴

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= V_DDmax

@ V_DD= max, V_IN= 0 V

@ V_DD= max, V_IN= 1.5 V (5 V),

2 V (3.3 V)

4.1

0.4

10

150

600

10

350

1.5

V

µA

mA

I_IL

I_ILP

10

Low Level Input Current⁶

150

600

10

350

1.5

I_ILPX4

I_OZH

I_OZL

I_OZHP

I_OZLC

I_OZLA

Low Level Input Current⁷

T hree-State Leakage Current^{8, 9, 10, 14}

T hree-State Leakage Current^{8, 11}

T hree-State Leakage Current¹¹

T hree-State Leakage Current¹²

T hree-State Leakage Current¹³

350

4.2

150

600

350

4.2

150

600

µA

mA

µA

A

mA

pF

I_OZLAR

I_OZLS

T hree-State Leakage Current¹⁰

T hree-State Leakage Current⁹

Full

+25°C

I

IV

I

@ V_DD= max, V_IN= 0 V

t_CK= 25 ns, V_DD= max

V_DD= max

I_OZLSX4T hree-State Leakage Current¹⁴

I_DDIN

I_DDIDLESupply Current (Idle)¹⁶

C_IN

Input Capacitance^{17, 18}

Supply Current (Internal)¹⁵

1.4 3.4

800

1.0 2.2

760

V

15

EXP LANATIO N O F TEST LEVELS

Test Level

I

100% Production T ested¹⁹

.

II

100% Production T ested at +25°C, and Sample T ested at Specified T emperatures.

III

IV

V

Sample T ested Only.

Parameter is guaranteed by design and analysis, and characterization testing on discrete SHARCs.

Parameter is typical value only.

VI

All devices are 100% production tested at +25°C; sample tested at temperature extremes.

NOT ES

¹Applies to input and bidirectional pins: DAT A_47-0, ADDR_31-0, RD, WR, SW, ACK, SBTS, IRQy_2-0, FLAGy0, FLAG1, FLAGy2, HBG, CSy, DMAR1, DMAR2,

BR_6-1, RPBA, CPAy, T FS0, T FSy1, RFS0, RFSy1, LyxDAT _3-0, LyxCLK, LyxACK, EBOOT A, LBOOT A, EBOOT BCD, LBOOT BCD, BMSA, BMSBCD, T MS,

T DI, T CK, HBR, DR0, DRy1, T CLK0, T CLKy1, RCLK0, RCLKy1.

²Applies to input pins: CLKIN, RESET, TRST.

³Applies to output and bidirectional pins: DAT A_47-0, ADDR_31-0, MS_3-0RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, T IMEXPy, HBG,

REDY, DMAG1, DMAG2, BR_6-1, CPAy, DT O, DT y1, T CLK0, T CLKy1, RCLK0, RCLKy1, T FS0, T FSy1, RFS0, RFSy1 LyxDAT _3-0, LyxCLK, LyxACK,

BMSA, BMSBCD, T DO, EMU.

⁴See Output Drive Currents for typical drive current capabilities.

⁵Applies to input pins: SBTS, IRQy_2-0, HBR, CSy, DMAR1, DMAR2, RPBA, EBOOT A, LBOOT A, EBOOT BCD, LBOOT BCD, CLKIN, RESET, T CK.

⁶Applies to input pins with internal pull-ups: DR0, DRy1, T DI.

⁷Applies to bussed input pins with internal pull-ups: TRST, T MS.

⁸Applies to three-statable pins: DAT A_47-0, ADDR_31-0, MS_3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0, FLAG1, FLAGy2, REDY, HBG, DMAG1, DMAG2,

BMSA, BMSBCD, T DO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID _2-0= 001 and another ADSP-

2106x is not requesting bus mastership. HBG AND EMU are not tested for leakage current.)

⁹Applies to three-statable pins with internal pull-ups: DT y1, T CLKy1, RCLKy1.

¹⁰Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID _2-0= 001 and another

ADSP-2106x is not requesting bus mastership.)

¹¹Applies to three-statable pins with internal pull-downs: LyxDAT _3-0, LyxCLK, LyxACK.

¹²Applies to CPAy pin.

¹³Applies to ACK pin when keeper latch enabled.

¹⁴Applies to bused three-statable pins with internal pull-ups: DT 0, T CLK0, RCLK0.

¹⁵Applies to V_DDpins. Conditions of operation: each processor executing radix-2 FFT butterfly with instruction in cache, one data operand fetched from each internal

memory block, and one DMA transfer occurring from/to internal memory at t _CK= 25 ns.

¹⁶Applies to V_DDpins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.

¹⁷Applies to all signal pins.

¹⁸Guaranteed but not tested.

¹⁹Link and Serial Ports: All are 100% tested at die level prior to assembly. All are 100% ac tested at module level; Link-4 and Serial-0 are also dc tested at the module

level. See T iming Specifications.

Specifications subject to change without notice.

REV. A

–14–

AD14060/AD14060L

ABSO LUTE MAXIMUM RATINGS*

Supply Voltage (5 V) . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Supply Voltage (3.3 V) . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction T emperature Under Bias . . . . . . . . . . . . . . . . 130°C

Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C

*Stresses greater than those listed above may cause permanent damage to the

device. T hese are stress ratings only; functional operation of the device at these

or any other conditions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

ESD SENSITIVITY

T he AD14060/AD14060L modules are ESD (electrostatic discharge) sensitive devices. Electro-

static charges readily accumulate on the human body and equipment and can discharge without

detection. Permanent damage may occur to devices subjected to high energy electrostatic

discharges.

WARNING!

T he ADSP-21060 processors include proprietary ESD protection circuitry to dissipate high

energy discharges. Per method 3015 of MIL-ST D-883, the ADSP-21060 processors have been

classified as a Class 2 device.

ESD SENSITIVE DEVICE

Proper ESD precautions are recommended to avoid performance degradation or loss of function-

ality. Unused devices must be stored in conductive foam or shunts, and the foam should be

discharged to the destination socket before devices are removed.

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add parameters to derive longer times.

TIMING SPECIFICATIONS

GENERAL NO TES

T his data sheet represents production released specifications for

the AD14060 (5 V), and for the AD14060L (3.3 V). T he

ADSP-21060 die components are 100% tested, and the assembled

AD14060/AD14060L units are again extensively tested at-

speed, and across-temperature. Parametric limits were estab-

lished from the ADSP-21060 characterization followed by

further design/analysis of the AD14060/AD14060L package

characteristics. T he specifications shown are based on a CLKIN

frequency of 40 MHz (t_CK= 25 ns). T he DT derating allows

specifications at other CLKIN frequencies (within the min-max

range of the t_CKspecification; see “Clock Input” below). DT is the

difference between the actual CLKIN period and a CLKIN period

of 25 ns:

Switching Characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. T iming requirements guarantee that the processor

operates correctly with other devices.

DT = t_CK– 25 ns

(O/D) = Open Drain

(A/D) = Active Drain

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

REV. A

–15–

AD14060/AD14060L

40 MH z–5 V

Max

40 MH z–3.3 V

P aram eter

Min

Max

Units

Clock Input

Timing Requirements:

t_CK

CLKIN Period

25

7

5

100

3

25

8.75

5

100

3

ns

t_CKL

t_CKH

t_CKRF

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V–2.0 V)

t_CK

CLKIN

t_CKH

t_CKL

Figure 9. Clock Input

5 V

3.3 V

P aram eter

Reset

Min

Max

Min

Max

Units

Timing Requirements:

t_WRST

t_SRST

RESET Pulsewidth Low¹

4t_CK

14 + DT /2

ns

RESET Setup Before CLKIN High²14 + DT /2

t_CK

NOT ES

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is

low, assuming stable V_DDand CLKIN (not including start-up time of external clock oscillator).

²Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required

for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.

CLKIN

t_SRST

t_WRST

RESET

Figure 10. Reset

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Inter r upts

Timing Requirements:

t_SIR

t_HIR

t_IPW

IRQ2-0 Setup Before CLKIN High¹

18 + 3DT /4

2 + t_CK

18 + 3DT /4

2 + t_CK

ns

IRQ2-0 Hold Before CLKIN High¹

IRQ2-0 Pulsewidth²

11.5 + 3DT /4

NOT ES

¹Only required for IRQx recognition in the following cycle.

²Applies only if t_SIRand t_HIRrequirements are not met.

CLKIN

t_SIR

t_HIR

IRQ2-0

t_IPW

Figure 11. Interrupts

–16–

REV. A

AD14060/AD14060L

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Tim er

Switching Characteristic:

t_{DT EX}

CLKIN High to T IMEXP

16

ns

CLKIN

t_DTEX

TIMEXP

Figure 12. Tim er

5 V

3.3 V

P aram eter

Flags

Min

Max

Min

Max

Units

Timing Requirements:

t_SFI

t_HFI

t_DWRFI

t_HFIWR

FLAG2-0_INSetup Before CLKIN High¹

FLAG2-0_INHold After CLKIN High¹

FLAG2-0_INDelay After RD/WR Low¹

FLAG2-0_INHold After RD/WR Deasserted¹

8 + 5DT /16

0.5 – 5DT /16

8 + 5DT /16

0.5 – 5DT /16

ns

4.5 + 7DT /16

0.5

Switching Characteristics:

t_DFO

t_HFO

t_DFOE

t_DFOD

FLAG2-0_OUTDelay After CLKIN High

17

15

17

15

ns

FLAG2-0_OUTHold After CLKIN High

CLKIN High to FLAG2-0_OUTEnable

CLKIN High to FLAG2-0_OUTDisable

4

3

4

3

NOT E

¹Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.

CLKIN

t_DFOE

t_DFO

t_DFOD

t_HFO

FLAG2–0

OUT

FLAG OUTPUT

CLKIN

t_HFI

t_SFI

FLAG2–0

IN

t_HFIWR

t_DWRFI

RD, WR

FLAG INPUT

Figure 13. Flags

REV. A

–17–

AD14060/AD14060L

Mem or y Read—Bus Master

These switching characteristics also apply for bus master syn-

chronous read/write timing (see Synchronous Read/Write – Bus

Master below). If these timing requirements are met, the syn-

chronous read/write timing can be ignored (and vice versa).

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. T hese specifications apply when the AD14060/

AD14060L is the bus master accessing external memory space.

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Timing Requirements:

t_DAD

t_DRLD

t_HDA

t_HDRH

t_DAAK

t_DSAK

Address, Delay to Data Valid^{1, 4}

17.5 + DT + W

11.5 + 5DT/8 + W

17.5 + DT + W

11.5 + 5DT/8 + W ns

ns

RD Low to Data Valid¹

Data Hold from Address²

Data Hold from RD High²

ACK Delay from Address^{3, 4}

ACK Delay from RD Low³

1

2.5

1

2.5

ns

13.5 + 7DT/8 + W

7.5 + DT /2 + W

13.5 + 7DT/8 + W ns

7.5 + DT/2 + W

ns

Switching Characteristics:

t_DRHA

t_DARL

t_RW

Address Hold After RD High

–0.5 + H

1.5 + 3DT /8

12.5 + 5DT/8 + W

8 + 3DT /8 + HI

–0.5 + H

ns

Address to RD Low⁴

1.5 + 3DT /8

12.5 + 5DT/8 + W

8 + 3DT /8 + HI

–0.5 + DT /4

RD Pulsewidth

RD High to WR, RD, DMAGx Low

t_RWR

t_SADADCAddress Setup Before ADRCLK High⁴–0.5 + DT /4

W = (number of wait states specified in WAIT register) × t_CK.

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

H = t_CK(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).

NOT ES

¹Data Delay/Setup: User must meet t_DADor t_DRLDor synchronous spec t_{SSDAT I}

.

²Data Hold: User must meet t_HDAor t_HDRHor synchronous spec t_{HDAT I}. See System Hold T ime Calculation under T est Conditions for the calculation of hold times

given capacitive and dc loads.

³ACK Delay/Setup: User must meet t_DSAKor t_DAAKor synchronous specification t_SACKC

.

⁴For MSx, SW, BMS, the falling edge is referenced.

ADDRESS

MSx, SW

BMS

t_DRHA

t_DARL

t_RW

RD

t_HDA

t_HDRH

t_DRLD

t_DAD

DATA

t_DSAK

t_RWR

t_DAAK

ACK

WR, DMAG

t_SADADC

ADRCLK

(OUT)

Figure 14. Mem ory Read—Bus Master

REV. A

–18–

AD14060/AD14060L

Mem or y Wr ite—Bus Master

These switching characteristics also apply for bus master syn-

chronous read/write timing (see Synchronous Read/Write–Bus

Master). If these timing requirements are met, the synchronous

read/write timing can be ignored (and vice versa).

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) without reference to

CLKIN. T hese specifications apply when the AD14060/

AD14060L is the bus master accessing external memory space.

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Timing Requirements:

t_DAAK

t_DSAK

ACK Delay from Address, Selects^{1, 2}

13.5 + 7DT/8 + W

7.5 + DT /2 + W

13.5 + 7DT/8 + W ns

ACK Delay from WR Low¹

7.5 + DT /2 + W

ns

Switching Characteristics:

t_DAWH

t_DAWL

t_WW

t_DDWH

t_DWHA

Address, Selects to WR Deasserted²

16.5 + 15DT/16 + W

2.5 + 3DT /8

16.5 + 15DT/16 + W

2.5 + 3DT /8

ns

Address, Selects to WR Low²

WR Pulsewidth

12 + 9DT/16 + W

6.5 + DT /2 + W

–1 + DT/16 + H

0.5 + DT/16 + H

7.5 + 7DT/16 + H

4.5 + 3DT /8 + I

–1.5 + DT /16

12 + 9DT/16 + W

6.5 + DT /2 + W

–1 + DT/16 + H

0.5 + DT/16 + H

7.5 + 7DT/16 + H

4.5 + 3DT /8 + I

–1.5 + DT /16

Data Setup before WR High

Address Hold after WR Deasserted

t_{DAT RWH}Data Disable after WR Deasserted³

t_WWR

t_DDWR

t_WDE

t_SADADC

6.5 + DT/16 + H

WR High to WR, RD, DMAGx Low

Data Disable before WR or RD Low

WR Low to Data Enabled

Address, Selects to ADRCLK High²

–0.5 + DT /4

W = (number of wait states specified in WAIT register) × t_CK

.

H = t_CK(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).

I = t_CK(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).

NOT ES

¹ACK Delay/Setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SACKC

²For MSx, SW, BMS, the falling edge is referenced.

.

³See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.

ADDRESS

MSx , SW

BMS

t_DWHA

t_DAWH

t_WW

t_DAWL

WR

t_WWR

t_DDWR

t_DDWH

t_WDE

t_DATRWH

DATA

t_DSAK

t_DAAK

ACK

RD , DMAG

t_SADADC

ADRCLK

(OUT)

Figure 15. Mem ory Write—Bus Master

REV. A

–19–

AD14060/AD14060L

Synchr onous Read/Wr ite—Bus Master

When accessing a slave ADSP-2106x, these switching character-

istics must meet the slave’s timing requirements for synchronous

read/writes (see Synchronous Read/Write—Bus Slave). T he

slave ADSP-2106x must also meet these (bus master) timing

requirements for data and acknowledge setup and hold times.

Use these specifications for interfacing to external memory

systems that require CLKIN—relative timing or for accessing a

slave ADSP-2106x (in multiprocessor memory space). T hese

synchronous switching characteristics are also valid during asyn-

chronous memory reads and writes (see Memory Read—Bus

Master and Memory Write—Bus Master).

5 V

Max

3.3 V

Max

P aram eter

Min

Units

Timing Requirements:

t_{SSDAT I}

t_{HSDAT I}

t_DAAK

t_SACKC

t_HACKC

Data Setup Before CLKIN

Data Hold After CLKIN

3 + DT /8

4 – DT /8

3 + DT /8

4 – DT /8

ns

ACK Delay After Address, MSx, SW, BMS^{1, 2}

ACK Setup Before CLKIN²

ACK Hold After CLKIN

13.5 + 7 DT/8 + W

13.5 + 7 DT/8 + W ns

6.5 + DT /4

–0.5 – DT /4

6.5 + DT /4

–0.5 – DT /4

ns

Switching Characteristics:

t_DADRO

t_HADRO

t_DPGC

t_DRDO

t_DWRO

Address, MSx, BMS, SW Delay After CLKIN¹

8 – DT /8

ns

Address, MSx, BMS, SW Hold After CLKIN

PAGE Delay After CLKIN

RD High Delay After CLKIN

WR High Delay After CLKIN

RD/WR Low Delay After CLKIN

Data Delay After CLKIN

–1 – DT /8

9 + DT /8

–2 – DT /8

–1 – DT /8

9 + DT /8

–2 – DT /8

17 + DT /8

5 – DT /8

–3 – 3DT /16 5 – 3DT /16

17 + DT /8

5 – DT /8

–3 – 3DT /16 5 – 3DT /16

t_DRWL

8 + DT /4

13.5 + DT /4

20 + 5DT /16

8 – DT /8

8 + DT /4

13.5 + DT /4

20 + 5DT /16

8 – DT /8

t_{SDDAT O}

t_{DAT T R}

t_DADCCK

t_ADRCK

t_ADRCKH

t_ADRCKL

Data Disable After CLKIN ³

ADRCLK Delay After CLKIN

ADRCLK Period

ADRCLK Width High

ADRCLK Width Low

0 – DT /8

4 + DT /8

t_CK

(t_CK/2 – 2)

0 – DT /8

4 + DT /8

t_CK

(t_CK/2 – 2)

11 + DT /8

W = (number of Wait states specified in WAIT register) × t_CK

.

NOT ES

¹For MSx, SW, BMS, the falling edge is referenced.

²ACK Delay/Setup: User must meet t_DAAKor t_DSAKor synchronous specification t_SACKC

.

³See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.

REV. A

–20–

AD14060/AD14060L

CLKIN

t_ADRCK

t_ADRCKL

t_ADRCKH

t_DADCCK

ADRCLK

t_HADRO

t_DAAK

t_DADRO

ADDRESS

SW

t_DPGC

PAGE

t_HACKC

t_SACKC

ACK

(IN)

READ CYCLE

t_DRWL

t_DRDO

RD

t_HSDATI

t_SSDATI

DATA

(IN)

WRITE CYCLE

t_DWRO

t_DRWL

WR

t_DATTR

t_SDDATO

DATA

(OUT)

Figure 16. Synchronous Read/Write—Bus Master

REV. A

–21–

AD14060/AD14060L

Synchr onous Read/Wr ite —Bus Slave

T he bus master must meet these (bus slave) timing requirements.

Use these specifications for bus master accesses of a slave’s IOP

registers or internal memory (in multiprocessor memory space).

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Timing Requirements:

t_SADRI

t_HADRI

t_SRWLI

t_HRWLI

t_RWHPI

t_{SDAT WH}

t_{HDAT WH}

Address, SW Setup Before CLKIN

15.5 + DT /2

9.5 + 5DT /16

–3.5 – 5DT /16 8 + 7DT /16

3

15.5 + DT /2

9.5 + 5DT /16

–3.5 – 5DT /16 8 + 7DT /16

3

ns

Address, SW Hold Before CLKIN

RD/WR Low Setup Before CLKIN¹

RD/WR Low Hold After CLKIN

RD/WR Pulse High

Data Setup Before WR High

Data Hold After WR High

4.5 + DT /2

5.5

1.5

5.5

1.5

Switching Characteristics:

t_{SDDAT O}

t_{DAT T R}

t_DACKAD

t_{ACKT R}

Data Delay After CLKIN

20 + 5DT /16

8 – DT /8

10

20 + 5DT /16

8 – DT /8

10

ns

Data Disable After CLKIN²

ACK Delay After Address, SW³

ACK Disable After CLKIN³

0 – DT /8

–1 – DT /8

7 – DT /8

–1 – DT /8

7 – DT /8

NOT ES

¹t_SRWLI(min) = 9.5 + 5DT /16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled,

t_SRWLI(min) = 4 + DT /8.

²See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.

³t_DACKADis true only if the address and SW inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 18.5 + 3DT/4. If the address and SW inputs have

setup times greater than 19 + 3DT /4, then ACK is valid 15 + DT /4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK

regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t _{ACKT R}

.

CLKIN

t_SADRI

t_HADRI

ADDRESS

SW

t_DACKAD

t_ACKTR

ACK

READ ACCESS

t_SRWLI

t_HRWLI

t_RWHPI

RD

t_SDDATO

t_DATTR

DATA

(OUT)

WRITE ACCESS

t_RWHPI

t_SRWLI

t_HRWLI

WR

t_HDATWH

t_SDATWH

DATA

(IN)

Figure 17. Synchronous Read/Write —Bus Slave

REV. A

–22–

AD14060/AD14060L

Multipr ocessor Bus Request and H ost Bus Request

Use these specifications for passing of bus mastership between

multiprocessing ADSP-2106x’s (BRx) or a host processor

(HBR, HBG).

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Timing Requirements:

t_HBGRCSVHBG Low to RD/WR/CS Valid¹

19.5 + 5DT/4

13.5 + 3DT/4

5.5 + DT/2

19.5 + 5DT/4 ns

t_SHBRI

t_HHBRI

t_SHBGI

t_HHBGI

t_SBRI

HBR Setup Before CLKIN²

20 + 3DT/4

13 + DT/2

20 + 3DT/4

13 + DT/2

20 + 3DT/4

ns

13.5 + 3DT/4 ns

ns

HBR Hold Before CLKIN²

HBG Setup Before CLKIN

HBG Hold Before CLKIN High

BRx, CPA Setup Before CLKIN³

BRx, CPA Hold Before CLKIN High

RPBA Setup Before CLKIN

RPBA Hold Before CLKIN

5.5 + DT/2

ns

t_HBRI

5.5 + DT/2

t_SRPBAI

t_HRPBAI

11.5 + 3DT/4

11.5 + 3DT/4 ns

Switching Characteristics:

t_DHBGO

t_HHBGO

t_DBRO

HBG Delay After CLKIN

HBG Hold After CLKIN

BRx Delay After CLKIN

BRx Hold After CLKIN

CPA Low Delay After CLKIN

CPA Disable After CLKIN

8 – DT/8

ns

–2 – DT/8

t_HBRO

–2 – DT/8

t_DCPAO

t_TRCPA

t_DRDYCS

t_TRDYHG

t_ARDYTR

9 – DT/8

5.5 – DT/8

9.5

9 – DT/8

5.5 – DT/8

10.25

–2 – DT/8

REDY (O/D) or (A/D) Low from CS and HBR Low⁴

REDY (O/D) Disable or REDY (A/D) High from HBG⁴

REDY (A/D) Disable from CS or HBR High⁴

44 + 27DT/16

11

NOT ES

¹For first asynchronous access after HBR and CS asserted, ADDR_31–0must be a non-MMS value 1/2 t_CKbefore RD or WR goes low or by t_HBGRCSVafter HBG goes

low. T his is easily accomplished by driving an upper address signal high when HBG is asserted.

²Only required for recognition in the current cycle.

³CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.

⁴(O/D) = open drain, (A/D) = active drive.

REV. A

–23–

AD14060/AD14060L

CLKIN

t_SHBRI

t_HHBRI

HBR

t_DHBGO

t_HHBGO

HBG

(OUT)

t_DBRO

t_HBRO

BRx

(OUT)

t_DCPAO

t_TRCPA

CPA (OUT)

(O/D)

t_SHBGI

t_HHBGI

HBG (IN)

t_SBRI

t_HBRI

BRx (IN)

CPA (IN) (O/D)

HBR

CS

t_TRDYHG

t_DRDYCS

REDY (O/D)

REDY (A/D)

HBG (OUT)

t_ARDYTR

t_HBGRCSV

RD

WR

CS

t_SRPBAI

t_HRPBAI

RPBA

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

HBG WILL BE DELAYED BY n CLOCK CYCLES WHEN WAIT STATES OR BUS LOCK ARE IN EFFECT.

Figure 18. Multiprocessor Bus Request and Host Bus Request

REV. A

–24–

AD14060/AD14060L

Asynchr onous Read/Wr ite—H ost to AD 14060/AD 14060L

Use these specifications for asynchronous host processor accesses

of an AD14060/AD14060L, after the host has asserted CS and

HBR (low). After HBG is returned by the AD14060/

AD14060L, the host can drive the RD and WR pins to access

the AD14060/AD14060L’s internal memory or IOP registers.

HBR and HBG are assumed low for this timing.

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Read Cycle

Timing Requirements:

t_SADRDL

t_HADRDH

t_WRWH

t_DRDHRDY

Address Setup/CS Low Before RD Low¹

Address Hold/CS Hold Low After RD

RD/WR High Width

RD High Delay After REDY (O/D) Disable

RD High Delay After REDY (A/D) Disable

0.5

6

0.5

6

0.5

ns

Switching Characteristics:

t_SDATRDY

t_DRDYRDL

t_RDYPRD

Data Valid Before REDY Disable from Low

1.5

ns

REDY (O/D) or (A/D) Low Delay After RD Low

REDY (O/D) or (A/D) Low Pulsewidth for Read

Data Disable After RD High

11

9

11.5

9.5

45 + DT

1.5

45 + DT

1.5

t_HDARWH

Write Cycle

Timing Requirements:

t_SCSWRL

t_HCSWRH

t_SADWRH

t_HADWRH

t_WWRL

CS Low Setup Before WR Low

0.5

5.5

2.5

7

0.5

5.5

2.5

7

ns

CS Low Hold After WR High

Address Setup Before WR High

Address Hold After WR High

WR Low Width

t_WRWH

RD/WR High Width

6

t_DWRHRDY

t_SDATWH

t_HDATWH

WR High Delay After REDY (O/D) or (A/D) Disable

Data Setup Before WR High

Data Hold After WR High

0.5

5.5

1.5

0.5

5.5

1.5

Switching Characteristics:

t_DRDYWRL

t_RDYPWR

t_SRDYCK

REDY (O/D) or (A/D) Low Delay After WR/CS Low

REDY (O/D) or (A/D) Low Pulsewidth for Write

REDY (O/D) or (A/D) Disable to CLKIN

11

11.5

ns

15

1 + 7DT/16

9 + 7DT/16

0 + 7DT/16

8 + 7DT/16

NOT E

¹Not required if RD and address are valid t_HBGRCSVafter HBG goes low. For first access after HBR asserted, ADDR_31–0must be a non-MMS value 1/2 t_CLKbefore RD

or WR goes low or by t_HBGRCSVafter HBG goes low. T his is easily accomplished by driving an upper address signal high when HBG is asserted. For address bits to be

driven during asynchronous host accesses, see T able 8.2 of the ADSP-2106x SHARC User’s Manual.

CLKIN

t_SRDYCK

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 19a. Synchronous REDY Tim ing

REV. A

–25–

AD14060/AD14060L

READ CYCLE

ADDRESS/CS

t_HADRDH

t_SADRDL

t_WRWH

RD

t_HDARWH

DATA (OUT)

t_DRDHRDY

t_SDATRDY

t_RDYPRD

t_DRDYRDL

REDY (O/D)

REDY (A/D)

WRITE CYCLE

ADDRESS

t_HADWRH

t_SADWRH

t_HCSWRH

t_SCSWRL

CS

t_WWRL

t_WRWH

WR

t_HDATWH

t_SDATWH

DATA (IN)

t_DWRHRDY

t_RDYPWR

t_DRDYWRL

REDY (O/D)

REDY (A/D)

O/D = OPEN DRAIN, A/D = ACTIVE DRIVE

Figure 19b. Asynchronous Read/Write—Host to ADSP-2106x

REV. A

–26–

AD14060/AD14060L

Thr ee-State Tim ing—Bus Master , Bus Slave,

,

T hese specifications show how the memory interface is disabled

(stops driving) or enabled (resumes driving) relative to CLKIN

and the SBTS pin. T his timing is applicable to bus master tran-

sition cycles (BT C) and host transition cycles (HT C) as well as

the SBTS pin.

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Timing Requirements:

t_{ST SCK}

t_{HT SCK}

SBTS Setup Before CLKIN

SBTS Hold Before CLKIN

12 + DT /2

ns

5.5 + DT /2

Switching Characteristics:

t_MIENA

t_MIENS

Address/Select Enable After CLKIN

–1.5 – DT /8

–1.25 – DT /8

–1.5 – DT /8

ns

Strobes Enable After CLKIN¹

HBG Enable After CLKIN

t_MIENHG

t_{MIT RA}

t_{MIT RS}

Address/Select Disable After CLKIN

Strobes Disable After CLKIN¹

HBG Disable After CLKIN

1 – DT /4

2.5 – DT /4

3 – DT /4

1 – DT /4

2.5 – DT /4

3 – DT /4

t_{MIT RHG}

t_{DAT EN}

t_{DAT T R}

t_ACKEN

t_{ACKT R}

t_ADCEN

t_{ADCT R}

t_{MT RHBG}

t_MENHBG

Data Enable After CLKIN²

9 + 5DT /16

0 – DT /8

7.5 + DT /4

–1 – DT /8

–2 – DT /8

9 + 5DT /16

0 – DT /8

7.5 + DT /4

–1 – DT /8

–2 – DT /8

Data Disable After CLKIN²

8 – DT /8

7 – DT /8

9 – DT /4

8 – DT /8

7 – DT /8

9 – DT /4

ACK Enable After CLKIN²

ACK Disable After CLKIN²

ADRCLK Enable After CLKIN

ADRCLK Disable After CLKIN

Memory Interface Disable Before HBG Low³

Memory Interface Enable After HBG High³

–1 + DT /8

18.5 + DT

–1 + DT /8

18.5 + DT

NOT ES

¹Strobes = RD, WR, SW, PAGE, DMAG.

²In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.

³Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).

CLKIN

t_STSCK

t_HTSCK

SBTS

t_MITRA,t_MITRS,t_MITRHG

t_MIENA,t_MIENS,t_MIENHG

MEMORY

INTERFACE

t_DATTR

t_DATEN

DATA

t_ACKTR

t_ACKEN

ACK

ADRCLK

HBG

t_ADCEN

t_ADCTR

t_MTRHBG

t_MENHBG

MEMORY

INTERFACE

MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, HBG, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)

Figure 20. Three-State Tim ing

REV. A

–27–

AD14060/AD14060L

D MA H andshake

transfer is controlled by ADDR_31-0, RD, WR, MS_3-0, and ACK

(not DMAG). For Paced Master mode, the “Memory Read–Bus

Master”, “Memory Write–Bus Master”, and “Synchronous

T hese specifications describe the three DMA handshake modes.

In all three modes DMAR is used to initiate transfers. For hand-

shake mode, DMAG controls the latching or enabling of data

externally. For external handshake mode, the data transfer is

Read/Write–Bus Master” timing specifications for ADDR_31-0

,

RD, WR, MS_3-0, SW, PAGE, DAT A_47-0, and ACK also apply.

controlled by the ADDR_31-0, RD, WR, SW, PAGE, MS_3-0

,

ACK, and DMAG signals. For Paced Master mode, the data

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Timing Requirements:

t_SDRLC

t_SDRHC

t_WDR

t_{SDAT DGL}

t_{HDAT IDG}

t_{DAT DRH}

t_DMARLL

t_DMARH

DMARx Low Setup Before CLKIN ¹

5

6

5

6

ns

DMARx High Setup Before CLKIN ¹

DMARx Width Low (Nonsynchronous)

Data Setup After DMAGx Low²

Data Hold After DMAGx High

Data Valid After DMAGx High²

DMAGx Low Edge to Low Edge

DMAGx Width High

9.5 + 5DT /8

15.5 + 7DT /8

9.5 + 5DT /8

2.5

15.5 + 7DT /8 ns

23 + 7DT /8

6

23 + 7DT /8

6

ns

Switching Characteristics:

t_DDGL

t_WDGH

t_WDGL

t_HDGC

t_{VDAT DGH}

t_{DAT RDGH}

t_DGWRL

t_DGWRH

t_DGWRR

t_DGRDL

t_DRDGH

t_DGRDR

t_DGWR

DMAGx Low Delay After CLKIN

DMAGx High Width

DMAGx Low Width

9 + DT /4

16 + DT/4

7 – DT/8

9 + DT /4

6 + 3DT /8

12 + 5DT /8

–2 – DT /8

7.5 + 9DT /16

–0.5

16 + DT/4

7 – DT/8

ns

6 + 3DT /8

12 + 5DT /8

–2 – DT /8

7.5 + 9DT /16

–0.5

DMAGx High Delay After CLKIN

Data Valid Before DMAGx High³

Data Disable After DMAGx High⁴

WR Low Before DMAGx Low

DMAGx Low Before WR High

WR High Before DMAGx High

RD Low Before DMAGx Low

RD Low Before DMAGx High

RD High Before DMAGx High

DMAGx High to WR, RD, DMAGx Low

Address/Select Valid to DMAGx High

Address/Select Hold after DMAGx High

8

2.5

8

2.5

–0.5

9.5 + 5DT/8 + W

0.5 + DT /16

–0.5

10.5 + 9DT/16 + W

–0.5

4.5 + 3DT/8 + HI

16 + DT

–1

9.5 + 5DT/8 + W

0.5 + DT /16

–0.5

10.5 + 9DT/16 + W

–0.5

4.5 + 3DT/8 + HI

16 + DT

–1

3.5 + DT/16

2

3.5 + DT/16

2

3.5

t_DADGH

t_DDGHA

W = (number of wait states specified in WAIT register) × t_CK

.

HI = t_CK(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).

NOT ES

¹Only required for recognition in the current cycle.

²t_{SDAT DGL}is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the

data can be driven t_{DAT DRH}after DMARx is brought high.

³t_{VDAT DGH}is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t_{VDAT DGH}= 7.5 + 9DT /16 + (n × t_CK

where n equals the number of extra cycles that the access is prolonged.

)

⁴See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.

REV. A

–28–

AD14060/AD14060L

CLKIN

t_SDRLC

t_DMARLL

t_SDRHC

t_WDR

t_DMARH

DMARx

DMAGx

t_HDGC

t_DDGL

t_WDGL

t_WDGH

TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE

t_DATRDGH

t_VDATDGH

DATA (FROM

ADSP-2106x TO

EXTERNAL DRIVE)

t_DATDRH

t_HDATIDG

t_SDATDGL

DATA (FROM

EXTERNAL DRIVE

TO ADSP-2106x)

TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)

t_DGWRL

WR

t_DGWRH

t_DGWRR

(EXTERNAL DEVICE

TO EXTERNAL

MEMORY)

t_DGRDR

t_DGRDL

RD

(EXTERNAL

MEMORY TO

EXTERNAL DEVICE)

t_DRDGH

t_DADGH

t_DDGHA

ADDRESS

MS , SW

X

*

“MEMORY READ – BUS MASTER,” “MEMORY WRITE – BUS MASTER,” AND “SYNCHRONOUS READ/WRITE – BUS MASTER”

TIMING SPECIFICATIONS FOR ADDR

, RD, WR, SW, MS AND ACK ALSO APPLY HERE.

31–0

3-0

Figure 21. DMA Handshake Tim ing

REV. A

–29–

AD14060/AD14060L

Link P or ts: 1 × CLK Speed O per ation

P aram eter

5 V

3.3 V

Min

Max

Min

Max

Units

Receive

Timing Requirements:

t_SLDCL

t_HLDCL

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

Data Setup Before LCLK Low

Data Hold After LCLK Low

LCLK Period (1 × Operation)

LCLK Width Low

3.5

3

t_CK

6

3

t_CK

6

5

ns

LCLK Width High

5

Switching Characteristics:

t_DLAHC

t_DLALC

t_ENDLK

t_{T DLK}

LACK High Delay After CLKIN High

18 + DT /2

–3

5 + DT /2

29.5 + DT /2

13.5

18 + DT /2

–3

5 + DT /2

29.5 + DT /2

13.5

ns

LACK Low Delay After LCLK High¹

LACK Enable from CLKIN

LACK Disable from CLKIN

21 + DT /2

Tr ansm it

Timing Requirements:

t_SLACHLACK Setup Before LCLK High

t_HLACHLACK Hold After LCLK High

18

–7

20

–7

ns

Switching Characteristics:

t_DLCLK

LCLK Delay After CLKIN (1 × Operation)

16.5

3.5

17.5

3

ns

t_DLDCH

t_HLDCH

t_{LCLKT WL}

t_{LCLKT WH}

t_DLACLK

t_ENDLK

t_{T DLK}

Data Delay After LCLK High

Data Hold After LCLK High

LCLK Width Low

–3

(t_CK/2) – 2

(t_CK/2) + 8.5

5 + DT /2

(t_CK/2) + 2

(3 × t_CK/2) + 17.5 (t_CK/2) + 8

5 + DT /2

(t_CK/2) – 1

(t_CK/2) + 1.25

(t_CK/2) – 1.25 (t_CK/2) + 1

LCLK Width High

LCLK Low Delay After LACK High

LDAT , LCLK Enable After CLKIN

LDAT , LCLK Disable After CLKIN

(3 × t_CK/2) + 18 ns

ns

21 + DT /2

Link P or t Ser vice Request Inter r upts:

1 × and 2 × Speed O per ations

Timing Requirements:

t_SLCK

t_HLCK

LACK/LCLK Setup Before CLKIN Low²

10

2.5

10

2.5

ns

LACK/LCLK Hold After CLKIN Low²

NOT ES

¹LACK will go low with t_DLALCrelative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.

²Only required for interrupt recognition in the current cycle.

REV. A

–30–

AD14060/AD14060L

Link P or ts: 2 × CLK Speed O per ation

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

R

eceive

Timing Requirements:

t_SLDCL

t_HLDCL

t_LCLKIW

t_LCLKRWL

t_LCLKRWH

Data Setup Before LCLK Low

2.5

2.25

t_CK/2

5

ns

Data Hold After LCLK Low

LCLK Period (2 × Operation)

LCLK Width Low

2.25

t_CK/2

4.5

LCLK Width High

4.25

4

Switching Characteristics:

t_DLAHCLACK High Delay After CLKIN High

t_DLALC

LACK Low Delay After LCLK High¹

18 + DT /2

6

29.5 + DT /2

16.5

18 + DT /2

6

30.5 + DT /2

18.5

ns

Tr ansm it

Timing Requirements:

t_SLACHLACK Setup Before LCLK High

t_HLACHLACK Hold After LCLK High

19

–6.75

19

–6.5

ns

Switching Characteristics:

t_DLCLK

t_DLDCH

t_HLDCH

t_{LCLKT WL}

t_{LCLKT WH}

t_DLACLK

LCLK Delay After CLKIN

9

3

9

2.75

ns

Data Delay After LCLK High

Data Hold After LCLK High

LCLK Width Low

LCLK Width High

LCLK Low Delay After LACK High

–2

(t_CK/4) – 1

(t_CK/4) + 9

(t_CK/4) + 1

(3 × t_CL/4) + 17

(t_CK/4) – 0.75 (t_CK/4) + 1.5

(t_CK/4) – 1.5

(t_CK/4) + 9

(t_CK/4) + 1

(3 × t_CL/4) + 17

NOT E

¹LACK will go low with t_DLALCrelative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.

REV. A

–31–

AD14060/AD14060L

TRANSMIT

CLKIN

t_DLCLK

t_LCLKTWL

t_LCLKTWH

LAST NIBBLE

TRANSMITTED

FIRST NIBBLE

TRANSMITTED

LCLK INACTIVE

(HIGH)

LCLK 1x

OR

LCLK 2x

t_DLDCH

t_HLDCH

LDAT(3:0)

LACK (IN)

OUT

t_DLACLK

t_SLACH

t_HLACH

THE t_SLACHREQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.

RECEIVE

CLKIN

t_LCLKIW

t_LCLKRWH

t_LCLKRWL

LCLK 1x

OR

LCLK 2x

t_HLDCL

t_SLDCL

LDAT(3:0)

IN

t_DLALC

t_DLAHC

LACK (OUT)

LACK GOES LOW ONLY AFFTER THE SECOND NIBBLE IS RECEIVED.

LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION

CLKIN

t_ENDLK

t_TDLK

LCLK

LDAT(3:0)

LACK

LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.

LINK PORT INTERRUPT SETUP TIME

CLKIN

t_HLCK

t_SLCK

LCLK

LACK

Figure 22. Link Ports

REV. A

–32–

AD14060/AD14060L

Ser ial P or ts

P aram eter

5 V

3.3 V

Min

Max

Min

Max

Units

External Clock

Timing Requirements:

t_SFSE

TFS/RFS Setup Before TCLK/RCLK¹

4

4.5

2

4.5

9.5

t_CK

4

4.5

2

4.5

9

t_CK

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

TFS/RFS Hold After TCLK/RCLK^{1, 2}

Receive Data Setup Before RCLK¹

Receive Data Hold After RCLK¹

TCLK/RCLK Width

TCLK/RCLK Period

Internal Clock

Timing Requirements:

t_SFSI

TFS Setup Before TCLK¹; RFS Setup Before RCLK¹

9

1

4

3

9

1

4

3

ns

t_HFSI

t_SDRI

t_HDRI

TFS/RFS Hold After TCLK/RCLK^{1, 2}

Receive Data Setup Before RCLK¹

Receive Data Hold After RCLK¹

External or Internal Clock

Switching Characteristics:

t_DFSE

t_HFSE

RFS Delay After RCLK (Internally Generated RFS)³

14

ns

RFS Hold After RCLK (Internally Generated RFS)³

3

External Clock

Switching Characteristics:

t_DFSE

t_HFSE

t_DDTE

t_HDTE

TFS Delay After TCLK (Internally Generated TFS)³

14

17

14

17

ns

TFS Hold After TCLK (Internally Generated TFS)³

Transmit Data Delay After TCLK³

3

5

3

5

Transmit Data Hold After TCLK³

Internal Clock

Switching Characteristics:

t_DFSI

t_HFSI

t_DDTI

t_HDTI

t_SCLKIW

TFS Delay After TCLK (Internally Generated TFS)³

5

8

ns

TFS Hold After TCLK (Internally Generated TFS)³

Transmit Data Delay After TCLK³

Transmit Data Hold After TCLK³

TCLK/RCLK Width

–1.5

0

–1.5

0

8

(SCLK/2) – 2

(SCLK/2) + 2

(SCLK/2) – 2.5 (SCLK/2) + 2.5 ns

Enable and Three-State

Switching Characteristics:

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

t_DCLK

Data Enable from External TCLK³

3.5

0

4

0

ns

Data Disable from External TCLK³

Data Enable from Internal TCLK³

Data Disable from Internal TCLK³

TCLK/RCLK Delay from CLKIN

SPORT Disable After CLKIN

11.5

3

23 + 3DT/8

18

23 + 3DT/8

18

t_DPTR

External Late Fram e Sync

Switching Characteristics:

t_DDTLFSEData Delay from Late External TFS or

External RFS with MCE = 1, MFD = 0⁴

t_DDTENFSData Enable from late FS or MCE = 1, MFD = 0⁴

13

13.8

ns

3.0

3.5

T o determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame

sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.

NOT ES

¹Referenced to sample edge.

²RFS hold after RCK when MCE = 1, MFD = 0 is 0.5 ns minimum from drive edge. T FS hold after T CK for late external T FS is 0.5 ns minimum from drive edge.

³Referenced to drive edge.

⁴MCE = 1, T FS enable and T FS valid follow t_{DDT LFSE}and t_{DDT ENFS}

.

REV. A

–33–

AD14060/AD14060L

EXTERNAL RFS with MCE = 1, MFD = 0

DRIVE

SAMPLE

RCLK

RFS

t_HFSE/I

(SEE NOTE 2)

t_SFSE/I

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TFS

DRIVE

SAMPLE

TCLK

t_HFSE/I

(SEE NOTE 2)

t_SFSE/I

TFS

DT

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

2ND BIT

t_DDTLFSE

Figure 23. External Late Fram e Sync

REV. A

–34–

AD14060/AD14060L

DATA RECEIVE– INTERNAL CLOCK

DATA RECEIVE– EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKW

RCLK

t_DFSE

t_HFSE

t_DFSE

t_HFSE

t_SFSI

t_HFSI

t_SFSE

RFS

DR

RFS

DR

t_SDRE

t_HDRE

t_SDRI

t_HDRI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT– INTERNAL CLOCK

DATA TRANSMIT– EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKW

TCLK

t_DFSI

t_DFSE

t_HFSE

t_HFSI

t_SFSI

t_HFSI

t_HFSE

t_SFSE

TFS

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DT

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE

EDGE

DRIVE

EDGE

TCLK / RCLK

TCLK (EXT)

DT

t_DDTEN

t_DDTTE

DRIVE

EDGE

DRIVE

EDGE

TCLK (INT)

TCLK / RCLK

t_DDTIN

t_DDTTI

DT

CLKIN

t_HTFSCK

t_DPTR

t_STFSCK

SPORT ENABLE AND

THREE-STATE

LATENCY

TCLK, RCLK

SPORT DISABLE DELAY

FROM INSTRUCTION

TFS (EXT)

TFS, RFS, DT

IS TWO CYCLES

t_DCLK

NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH

EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR

MESH MULTIPROCESSING.

TCLK (INT)

RCLK (INT)

LOW TO HIGH ONLY

Figure 24. Serial Ports

REV. A

–35–

AD14060/AD14060L

JTAG Test Access P or t and Em ulation

5 V

3.3 V

P aram eter

Min

Max

Min

Max

Units

Timing Requirements:

t_{T CK}

T CK Period

t_CK

5

6

8

18.5

4t_CK

t_CK

5

6

8

19

4t_CK

ns

t_{ST AP}

t_{HT AP}

t_SSYS

t_HSYS

t_{T RST W}

T DI, T MS Setup Before T CK High

T DI, T MS Hold After T CK High

System Inputs Setup Before T CK Low¹

System Inputs Hold After T CK Low¹

TRST Pulsewidth

Switching Characteristics:

t_{DT DO}T DO Delay from T CK Low

t_DSYS

System Outputs Delay After T CK Low ²

13

20

13

20

ns

NOT ES

¹System Inputs = DAT A_47-0, ADDR_31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR_6-1, RPBA, IRQ_2-0, FLAG2-0, DR0, DR1, T CLK0,

T CLK1, RCLK0, RCLK1, T FS0, T FS1, RFS0, RFS1, LxDAT _3-0, LxCLK, LxACK, EBOOT , LBOOT , BMS, CLKIN, RESET.

²System Outputs = DAT A_47-0, ADDR_31-0, MS_3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR_6-1, CPA, FLAG_2-0, T IMEXP, DT 0,

DT 1, T CLK0, T CLK1, RCLK0, RCLK1, T FS0, T FS1, RFS0, RFS1, LxDAT _3-0, LxCLK, LxACK, BMS.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 25. IEEE 11499.1 J TAG Test Access Port

REV. A

–36–

AD14060/AD14060L

O UTP UT D RIVE CURRENTS

T he P_EXTequation is calculated for each class of pins that can

drive:

Figure 26 shows typical I-V characteristics for the output drivers

of the ADSP-2106x. T he curves represent the current drive

capability of the output drivers as a function of output voltage.

P in

# of

%

2

Type

P ins

Switching

؋

C

؋

f

؋

V_DD= P _EXT

120

100

Address

MS0

WR

Data

ADRCLK

15

1

32

1

50

0

–

50

–

× 55 pF

× 25 pF

× 15 pF

× 20 MHz × 25 V = 0.206 W

× 20 MHz × 25 V = 0.00 W

× 40 MHz × 25 V = 0.055 W

× 20 MHz × 25 V = 0.200 W

HIGH LEVEL DRIVE

80

(P DEVICE)

60

40 MHz

× 25 V = 0.015 W

40

20

P_EXT(5 V) = 0.476 W

P_EXT(3.3 V) = 0.207 W

0

–20

–40

–60

–80

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

LOW LEVEL DRIVE

P

_TOTAL= P_EXT+ (I_DDIN2× 5.0 V )

–100

(N DEVICE)

–120

–140

–160

Note that the conditions causing a worst-case P_EXTare different

from those causing a worst-case P_INT. Maximum P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Also note that it is not common for an application to

have 100% or even 50% of the outputs switching simultaneously.

0

1

2

3

4

5

SOURCE VOLTAGE – V

Figure 26. ADSP-2106x Typical Drive Currents (V_DD= 5 V)

TEST CO ND ITIO NS

O utput D isable Tim e

P O WER D ISSIP ATIO N

T otal power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved. Inter-

nal power dissipation is calculated in the following way:

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from

their output high or low voltage. T he time for the voltage on the

bus to decay by ∆V is dependent on the capacitive load, C_L, and

the load current, I_L. T his decay time can be approximated by

the following equation:

P_INT= I_DDIN× V_DD

T he external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

C_L∆V

t_DECAY

=

I_L

– the number of output pins that switch during each cycle (O)

– the maximum frequency at which they can switch (f)

– their load capacitance (C)

The output disable time, t_DIS, is the difference between t_MEASURED

and t_DECAYas shown in Figure 27. T he time t_MEASUREDis the

interval from when the reference signal switches to when the

output voltage decays ∆V from the measured output high or

output low voltage. t_DECAYis calculated with test loads C_Land

I_L, and with ∆V equal to 0.5 V.

– their voltage swing (V_DD

)

and is calculated by:

2

P_EXT= O × C × V_DD× f

T he load capacitance should include the processor’s package

capacitance (C_IN). T he switching frequency includes driving the

load high and then back low. Address and data pins can drive

high and low at a maximum rate of 1/(2t_CK). T he write strobe

can switch every cycle at a frequency of 1/t_CK. Select pins switch

at 1/(2t_CK), but selects can switch on each cycle.

O utput Enable Tim e

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start

driving. T he output enable time, t_ENA, is the interval from when

a reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram (Figure 27). If multiple

pins (such as the data bus) are enabled, the measurement value

is that of the first pin to start driving.

Example:

Estimate P_EXTwith the following assumptions:

–A system with one bank of external data memory RAM (32-bit)

–Four 128K × 8 RAM chips are used, each with a load of 10 pF

–External data memory writes occur every other cycle, a rate

–of 1/(4t_CK), with 50% of the pins switching

–The instruction cycle rate is 40 MH z (t_CK= 25 ns) and

–V_DD= 5.0 V.

Exam ple System H old Tim e Calculation

T o determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose

∆V to be the difference between the ADSP-2106x’s output

voltage and the input threshold for the device requiring the hold

time. A typical ∆V will be 0.4 V. C_Lis the total bus capacitance

(per data line), and I_Lis the total leakage or three-state current

REV. A

–37–

AD14060/AD14060L

16.0

14.0

12.0

10.0

8.0

(per data line). T he hold time will be t_DECAYplus the minimum

disable time (i.e., t_HDWDfor the write cycle).

14.7

REFERENCE

SIGNAL

RISE TIME

t_MEASURED

7.4

t_ENA

t_DIS

FALL TIME

6.0

V

OH (MEASURED)

V

OH (MEASURED)

V

– ∆V

+ ∆V

2.0V

1.0V

OH (MEASURED)

4.0

3.7

V

OL (MEASURED)

V

OL (MEASURED)

2.0

1.1

t_DECAY

0

20

40

60

80

100 120 140 160 180 200

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

LOAD CAPACITANCE – pF

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE

THIS VOLTAGE TO BE

Figure 30. Typical Output Rise Tim e (10%–90% V_DD

vs. Load Capacitance (V_DD= 5 V)

)

APPROXIMATELY 1.5V

Figure 27. Output Enable/Disable

3.5

3.0

I

OL

2.9

1.6

2.5

RISE TIME

2.0

TO

OUTPUT

+1.5V

1.5

50pF

FALL TIME

1.0

0.6

0.5

I

OH

0

20

40

60

80 100 120 140 160 180 200

Figure 28. Equivalent Device Loading for AC Measure-

m ents (Includes All Fixtures)

LOAD CAPACITANCE – pF

Figure 31. Typical Output Rise Tim e (0.8 V –2.0 V)

vs. Load Capacitance (V_DD= 5 V)

INPUT OR

OUTPUT

1.5V

Figure 29. Voltage Reference Levels for AC Measure-

m ents (Except Output Enable/Disable)

5

4

3

2

1

4.5

Capacitive Loading

Output delays and holds are based on standard capacitive loads:

50 pF on all pins (see Figure 28). T he delay and hold specifica-

tions given should be derated by a factor of 1.5 ns/50 pF for

loads other than the nominal value of 50 pF. Figures 30 and 31

show how output rise time varies with capacitance. Figure 32

graphically shows how output delays and holds vary with load

capacitance. (Note that this graph or derating does not apply to

output disable delays; see the previous section Output Disable

T ime under T est Conditions.) T he graphs of Figures 30, 31 and

32 may not be linear outside the ranges shown.

NOMINAL

–0.7

–1

25

50

75

100

125

150

175

200

LOAD CAPACITANCE – pF

Figure 32. Typical Output Delay or Hold vs. Load

Capacitance (at Maxim um Case Tem perature) (V_DD= 5 V)

REV. A

–38–

AD14060/AD14060L

18

16

14

12

10

8

AD 14060/AD 14060L ASSEMBLY

RECO MMEND ATIO NS

SO CKET INFO RMATIO N

Standard sockets and carriers are available for the AD14060/

AD14060L, if needed. Socket part number IC53-3084-262 and

carrier part number ICC-308-1 are available from Yamaichi

Electronics.

Y = 0.0796X + 1.17

RISE TIME

Tr im and For m

6

Y = 0.0467X + 0.55

T he AD14060/AD14060L will be shipped as shown on the final

page of the data sheet with untrimmed and unformed leads and

with the nonconductive tie bar in place. This avoids disturbance of

lead spacing and coplanarity prior to assembly. Optimally, the

leads should be trimmed, formed and solder-dipped just prior to

placement on the board.

4

FALL TIME

2

0

20

40

60

80 100 120 140 160 180 200

LOAD CAPACITANCE – pF

T rim/Form can be accomplished with a Universal T rim/Form,

Customer-Designed T rim/Form, or with the Analog Devices’

Developed T ooling described below.

Figure 33. Typical Output Rise Tim e (10%–90% V_DD) vs.

Load Capacitance (V_DD= 3.3 V)

9

8

7

A trim/form tool specific to the AD14060/AD14060L has been

developed and is available for use by all parties at:

T intronics Industries

2122-A Metro Circle

Huntsville, AL 35801

205-650-0220

Y = 0.0391X + 0.36

6

5

4

Contact Person: T om Rice

RISE TIME

Y = 0.0305X + 0.24

T he package outline and dimensions resulting from this tool are

shown below. (Alternatively, the package can also be trimmed/

formed for cavity-down placement.)

3

2

1

0

FALL TIME

0

20

40

60

80 100 120 140 160 180 200

0.170

(4.318)

LOAD CAPACITANCE – pF

2.110 (53.59)

2.210 ±0.010 (56.134 ±0.254)

Figure 34. Typical Output Rise Tim e (0.8 V –2.0 V) vs.

Load Capacitance (V_DD= 3.3 V)

5

4.5

4

3

2

1

Y = 0.0329X - 1.65

0.016 MIN

0° TO 8°

NOMINAL

0 TO 10 MILS

–0.7

–1

25

50

75

100

125

150

175

200

LOAD CAPACITANCE – pF

DETAIL "A"

Figure 35. Typical Output Delay or Hold vs. Load Capaci-

tance (at Maxim um Case Tem perature) (V_DD= 3.3 V)

REV. A

–39–

AD14060/AD14060L

P CB LAYO UT GUID ELINES

NOT E: T hese drawings are recommended PCB layout guide-

lines only, and they assume that the trim/form tooling described

above is used.

The drawing below assumes that the trim/form tooling described

above is used. T hese recommendations are provided for user

convenience and are recommendations only, based on stan-

dard practice. PCB pad footprint geometries and placement

are illustrated.

2.260 (57.404) 4 PLACES

2.060 (52.324) 4 PLACES

1.9000 (48.26) 4 PLACES

0.015

(0.381)

THIS IS A PC BOARD COMPONENT

FOOTPRINT, NOT THE PACKAGE

OUTLINE.

0.025

(0.635)

0.025 (0.635) MIN

REV. A

–40–

AD14060/AD14060L

Ther m al Char acter istics

Therm al Conductivity

T he AD14060/AD14060L is packaged in a 308-lead ceramic

quad flatpack (CQFP). T he package is optimized for thermal

conduction through the core (base of the package) down to the

mounting surface. T he AD14060/AD14060L is specified for a

case temperature (T_CASE). Design of the mounting surface and

attachment material should be such that T_CASEis not exceeded.

Therm al Conductivity

W/cm ؇C

Material

Ceramic

Kovar

T ungsten

T hermoplastic

Silicon

0.18

0.14

1.78

0.03

1.45

θ_JC= 0.36°C/W

Ther m al Cr oss-Section

T he data below, together with the detailed mechanical drawings

at the end of the data sheet, allows for constructing simple ther-

mal models for further analysis within targeted systems. T he top

layer of the package, where the die are mounted, is a metal V_DD

layer. T he approximate metal area coverage from the metal

planes and routing layers is estimated below.

Metal Coverage P er Layer

P ercent Metal

(1 Mil Thick)

Layer

V_DD

88

16

14

91

15

13

95

SIG2

SIG3

GND

SIG4

SIG5

BASE

KOVAR LID

0.015 MILS

KOVAR SEAL RING

HEIGHT = 50 MILS

SURFACE

SILICON DIE

19 MILS

CERAMIC LAYER 28 MILS

THERMOPLASTIC

THICKNESS 5 MILS

CERAMIC LAYER 6 MILS

V

DD

CERAMIC LAYER 10 MILS

CERAMIC LAYER 4 MILS

CERAMIC LAYER 10 MILS

SIG2

SIG3

GND

CERAMIC LAYER 10 MILS

CERAMIC LAYER 4 MILS

CERAMIC LAYER 10 MILS

CERAMIC LAYER 4 MILS

SIG4

SIG5

BASE

REV. A

–41–

AD14060/AD14060L

MECH ANICAL CH ARACTERISTICS

Lid D eflection Analysis

External P ressure Reduction

0.670

4X

D elta P ressure

D eflection

0.653

4X

12 psi

15 psi

10.0 mil

11.9 mil

0.302

2.050 SQ.

Mechanical Model

T he data below, together with the detailed mechanical drawings

at the end of the data sheet, allows for construction of simple

mechanical models for further analysis within targeted systems.

0.616

0.633

Mechanical P roperties

0.260

Material

Modulus of Elasticity

Ceramic

Kovar

T ungsten

T hermoplastic

Silicon

26 × 10³kg/mm²

14.1 × 10³kg/mm²

35 × 10³kg/mm²

279 kg/mm²

0.250

0.345

1.890

±

0.005

0.018

1.810

1.780

±

11 × 10³kg/mm²

0.012 REF

4X

0.040 ±0.002

308-LEAD CQ FP P IN CO NFIGURATIO N

308

232

231

1

AD14060/AD14060L

TOP VIEW

155

154

77

78

REV. A

–42–

AD14060/AD14060L

P IN CO NFIGURATIO NS

P in P in

No. Nam e

P in P in

No. Nam e

P in P in

No. Nam e

P in P in

No. Nam e

P in P in

No. Nam e

P in P in

No. Nam e

P in P in

No. Nam e

1

2

3

4

5

6

7

8

9

WR

RD

45 GND

89

90

91

92

93

94

95

96

97

98

99

ADDR13

133 IRQB0

134 IRQB1

135 IRQB2

136 GND

137 IRQC0

138 IRQC1

139 IRQC2

140 IRQD0

141 IRQD1

142 IRQD2

143 V_DD

177 LC4DAT 2 221 GND

178 LC4DAT 3 222 LA3ACK

265 GND

46 RFSD1

47 RCLKD1

48 DRD1

49 T FSD1

50 T CLKD1

51 DT D1

52 V_DD

ADDR12

ADDR11

GND

ADDR10

ADDR9

ADDR8

V_DD

ADDR7

ADDR6

ADDR5

266 DAT A24

267 DAT A25

268 DAT A26

269 DAT A27

270 V_DD

271 DAT A28

272 DAT A29

273 DAT A30

274 DAT A31

275 GND

276 DAT A32

277 DAT A33

278 DAT A34

279 DAT A35

280 V_DD

281 DAT A36

282 DAT A37

283 DAT A38

284 DAT A39

285 GND

286 DAT A40

287 DAT A41

288 CLKIN

289 GND

290 DAT A42

291 DAT A43

292 V_DD

293 DAT A44

294 DAT A45

295 DAT A46

296 DAT A47

297 GND

GND

CSA

CSB

CSC

CSD

GND

HBG

179 GND

180 LC3ACK

181 LC3CLK

223 LA3CLK

224 LA3DAT 0

225 LA3DAT 1

182 LC3DAT 0 226 LA3DAT 2

183 LC3DAT 1 227 LA3DAT 3

184 LC3DAT 2 228 V_DD

53 HBR

54 DMAR1

185 LC3DAT 3 229 LA1ACK

10 REDY

11 ADRCLK 55 DMAR2

12 V_DD

13 RFS0

14 RCLK0

15 DR0

16 T FS0

17 T CLK0

18 DT 0

186 V_DD

187 LC1ACK

188 LC1CLK

230 LA1CLK

231 LA1DAT 0

232 LA1DAT 1

56 SBTS

100 GND

144 EBOOT A

145 LBOOT A

146 EBOOT BCD 190 LC1DAT 1 234 LA1DAT 3

147 LBOOT BCD 191 LC1DAT 2 235 GND

148 GND

149 RESET

150 RPBA

57 BMSA

58 BMSBCD

59 SW

60 GND

61 MS0

62 MS1

63 MS2

64 MS3

65 V_DD

66 ADDR31

67 ADDR30

68 ADDR29

69 GND

70 ADDR28

71 ADDR27

72 ADDR26

73 V_DD

74 ADDR25

75 ADDR24

76 ADDR23

77 ADDR22

78 ADDR21

79 ADDR20

80 V_DD

81 ADDR19

82 ADDR18

83 ADDR17

84 GND

101 ADDR4

102 ADDR3

103 ADDR2

104 V_DD

105 ADDR1

106 ADDR0

107 FLAGA0

108 GND

109 FLAGA2

110 FLAGB0

111 FLAGB2

112 FLAGC0

113 FLAGC2

114 FLAGD0

115 FLAGD2

116 V_DD

117 FLAG1

118 EMU

119 T IMEXPA 163 LD3DAT 2

120 T IMEXPB

121 T IMEXPC

122 T IMEXPD 166 LD1ACK

123 GND

124 T DO

125 TRST

126 T DI

127 T MS

128 T CK

129 V_DD

130 IRQA0

131 IRQA1

132 IRQA2

189 LC1DAT 0 233 LA1DAT 2

192 LC1DAT 3 236 DAT A0

193 GND

194 LB4ACK

195 LB4CLK

237 DAT A1

238 DAT A2

239 DAT A3

19 GND

151 GND

20 CPAA

21 CPAB

22 CPAC

23 CPAD

24 V_DD

25 RFSA1

26 RCLKA1

27 DRA1

28 T FSA1

29 T CLKA1

30 DT A1

31 GND

32 RFSB1

33 RCLKB1

34 DRB1

35 T FSB1

36 T CLKB1

37 DT B1

38 V_DD

39 RFSC1

40 RCLKC1

41 DRC1

42 T FSC1

43 T CLKC1

44 DT C1

152 LD4ACK

153 LD4CLK

154 LD4DAT 0

155 LD4DAT 1

156 LD4DAT 2

157 LD4DAT 3

158 V_DD

159 LD3ACK

160 LD3CLK

161 LD3DAT 0

162 LD3DAT 1

196 LB4DAT 0 240 V_DD

197 LB4DAT 1 241 DAT A4

198 LB4DAT 2 242 DAT A5

199 LB4DAT 3 243 DAT A6

200 V_DD

201 LB3ACK

202 LB3CLK

244 DAT A7

245 GND

246 DAT A8

203 LB3DAT 0 247 DAT A9

204 LB3DAT 1 248 DAT A10

205 LB3DAT 2 249 DAT A11

206 LB3DAT 3 250 V_DD

207 GND

208 LB1ACK

209 LB1CLK

251 DAT A12

252 DAT A13

253 DAT A14

164 LD3DAT 3

165 GND

210 LB1DAT 0 254 DAT A15

211 LB1DAT 1 255 GND

212 LB1DAT 2 256 DAT A16

213 LB1DAT 3 257 DAT A17

298 BR1

299 BR2

300 BR3

301 BR4

302 BR5

303 BR6

304 PAGE

305 V_DD

306 DMAG1

307 DMAG2

308 ACK

167 LD1CLK

168 LD1DAT 0

169 LD1DAT 1

170 LD1DAT 2

171 LD1DAT 3

172 V_DD

173 LC4ACK

174 LC4CLK

175 LC4DAT 0

176 LC4DAT 1

214 V_DD

215 LA4ACK

216 LA4CLK

258 DAT A18

259 DAT A19

260 V_DD

85 ADDR16

86 ADDR15

87 ADDR14

88 V_DD

217 LA4DAT 0 261 DAT A20

218 LA4DAT 1 262 DAT A21

219 LA4DAT 2 263 DAT A22

220 LA4DAT 3 264 DAT A23

REV. A

–43–

AD14060/AD14060L

O RD ERING GUID E

SMD

P art Num ber

Case Tem perature Range

Instruction Rate

O perating Voltage

AD14060BF-4

AD14060LBF-4

5962-9750601HXC

5962-9750701HXC*

–40°C to +100°C

N/A

QML-H

40 MHz

5 V

3.3 V

5 V

3.3 V

*Part numbers marked with an * are shipping as x-grade (preproduction) material at the time of this printing. T hese parts are packaged in a 308-lead Ceramic Quad

Flatpack Package (CQFP). MIL-SMD parts, in the same package, are in development.

P ACKAGE D IMENSIO NS

D imensions shown in inches and (mm).

308-Lead Ceram ic Quad Flatpack (CQFP )

(QS-308)

3.050 (77.47) MAX

3.000 ؎0.010 (76.2 ؎0.254)

2.730 ؎0.015 (69.34 ؎0.381)

0.340 ؎0.010

(8.636 ؎0.254)

4x

2.050 ؎0.012 (52.07 ؎0.305)

0.015 (0.381) x 45°

3 PLACES

231

232

155

154

0.008 ؎0.002

(0.203 ؎0.051)

2.300 ؎0.030

(58.42 ؎0.762)

TOP VIEW

0.025 (0.635) TYP

308

78

1

77

0.040 (1.016) x 45°

0.035

(0.889)

MAX

0.005 +0.0015 –0.001

(0.127 +0.0381 –0.025)

1.890 ؎0.005

(48.006 ؎0.127)

0.160

0.092 ؎0.009

(2.337 ؎0.229)

(4.064)

MAX

REV. A

–44–


型号：	AD14060BF-4
厂家：	ADI
描述：	Quad-SHARC DSP Multiprocessor Family 四SHARC DSP多处理器家族微控制器和处理器外围集成电路数字信号处理器时钟
文件：	总44页 (文件大小：746K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD14060BF-4 [ADI]

相关型号：

AD14060L

AD14060LBF-4

AD14060L_15

AD14060_15

AD1408-7D

AD1408-8D

AD1408-9D

AD14160

AD14160BB-4

AD14160KB-4

AD14160L

AD14160LBB-4