AD14060L_15 [ADI]
DSP Multiprocessor Family;
| 型号： | AD14060L_15 |
| 厂家： | 
ADI |
| 描述： | DSP Multiprocessor Family |
| 文件： | 总48页 (文件大小：1371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad-SHARC®
DSP Multiprocessor Family
AD14060/AD14060L
PERFORMANCE FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADSP-21060 core processor ( × 4)
480 MFLOPS peak, 320 MFLOPS sustained
25 ns instruction rate, single-cycle
instruction execution—each of four processors
16 Mbit shared SRAM (internal to SHARCs)
4 gigawords addressable off-module memory
Twelve 40 Mbyte/s link ports (3 per SHARC)
LINK 0
LINK 2
LINK 5
TDO
LINK 0
LINK 2
LINK 5
TDI
CPA
SPORT 1
TDI
CPA
SPORT 1
SHARC_A
SHARC_B
(ID
= 1)
(ID
= 2)
2–0
2–0
Four 40 Mbit/s independent serial ports
(one from each SHARC)
One 40 Mbit/s common serial port
5 V and 3.3 V operation
32-bit single precision and 40-bit extended
precision IEEE floating point data formats, or
32-bit fixed point data format
SHARC BUS (ADDR
,
DATA
,
47–0
MS , RD, WR, PAGE, ADRCLK,
3-0
6–1 1.2 1.2
31–0
SW, ACK, SBTS, HBR, HBG, REDY, BR
, RPBA, DMAR , DMAG
)
IEEE JTAG Standard 1149.1 test access port and
on-chip emulation
PACKAGING FEATURES
308-lead ceramic quad flatpack (CQFP)
2.05" (52 mm) body size
Cavity up or down, configurable
Low profile, 0.160" height
Hermetic
SHARC_D
SHARC_C
CPA
SPORT 1
CPA
(ID
= 4)
(ID
= 3)
2–0
2–0
LINK 0
LINK 2
LINK 5
TDI
LINK 0
LINK 2
LINK 5
TDO
SPORT 1
TDO
25 Mil (0.65 mm) lead pitch
29 grams (typical)
AD14060/AD14060L
00667-001
Figure 1.
θJC = 0.36°C/W
GENERAL DESCRIPTION
32 address) is also brought off-module for interfacing with
expansion memory or other peripherals.
The AD14060/AD14060L Quad-SHARC is the first in a family
of high performance DSP multiprocessor modules. The core of
the multiprocessor is the ADSP-21060 DSP microcomputer. The
AD14060/AD14060L has the highest performance-to-density
and lowest cost-to-performance ratios of any in its class. It is
ideal for applications requiring higher levels of performance
and/or functionality per unit area.
The ADSP-21060 link ports are interconnected to provide direct
communication among the four SHARCs, as well as high speed
off-module access. Internally, each SHARC has a direct link port
connection. Externally, each SHARC has a total of 120 Mbytes/s
link port bandwidth.
The AD14060/AD14060L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve
480 peak MFLOPS with a single chip type in a single package.
The on-chip SRAM of the DSPs provides 16 Mbits of on-
module shared SRAM. The complete shared bus (48 data,
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and
optimized signal routing lengths and separation. The fully
tested and ready-to-insert multiprocessor also significantly
reduces board space.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD14060/AD14060L
TABLE OF CONTENTS
Specifications..................................................................................... 3
Link Port I/O............................................................................... 38
Serial Ports .................................................................................. 38
Program Booting........................................................................ 38
Host Processor Interface ........................................................... 39
Direct Memory Access (DMA) Controller............................. 39
Applications..................................................................................... 40
Development Tools .................................................................... 40
Quad-SHARC Development Board......................................... 40
Other Package Details................................................................ 40
Target Board Connector for Emulator Probe......................... 40
Output Drive Currents .............................................................. 42
Power Dissipation ...................................................................... 42
Test Conditions........................................................................... 43
Assembly Recommendations.................................................... 45
PCB Layout Guidelines.............................................................. 46
Mechanical Characteristics....................................................... 47
Additional Information ............................................................. 47
Outline Dimensions....................................................................... 48
Ordering Guide .......................................................................... 48
Electrical Characteristics (3.3 V, 5 V Supply)............................ 3
Explanation of Test Levels........................................................... 4
Timing Specifications....................................................................... 5
Memory Read—Bus Master........................................................ 8
Memory Write—Bus Master ....................................................... 9
Synchronous Read/Write—Bus Master................................... 10
Synchronous Read/Write—Bus Slave ...................................... 12
Multiprocessor Bus Request and Host Bus Request .............. 13
Asynchronous Read/Write—Host to AD14060/AD14060L. 15
HBR SBTS
..... 17
Three-State Timing—Bus Master, Bus Slave,
,
DMA Handshake........................................................................ 18
Absolute Maximum Ratings.......................................................... 27
ESD Caution................................................................................ 27
Pin Configuration and Function Descriptions........................... 28
Pin Function Descriptions ........................................................ 30
Detailed Description ...................................................................... 34
Architectural Features................................................................ 34
Shared Memory Multiprocessing ............................................. 34
Off-Module Memory and Peripherals Interface .................... 36
REVISION HISTORY
12/04—Rev. A to Rev. B
Format Updated..................................................................Universal
Changes to Specifications Section.................................................. 3
Changes to Development Tools Section...................................... 40
Changes to Target Board for Emulator Probe Section .............. 40
Changes to Figure 27...................................................................... 42
Updated Outline Dimensions....................................................... 48
Changes to Ordering Guide .......................................................... 48
10/97—Rev. 0 to Rev. A
4/97—Revision 0: Initial Version
Rev. B | Page 2 of 48
AD14060/AD14060L
SPECIFICATIONS
Table 1. Recommended Operating Conditions
B Grade
Max
K Grade
Parameter
Unit
V
Min
4.75
3.15
−40
Min
4.75
3.15
0
Max
5.25
3.6
VDD
Supply Voltage (5 V)
5.25
3.6
Supply Voltage (3.3 V)
Case Operating Temperature
V
TCASE
+100
+85
°C
ELECTRICAL CHARACTERISTICS (3.3 V, 5 V SUPPLY)
Table 2.
Test
5 V
3.3 V
Min Typ Max
VDD + 0.5 2.0 VDD + 0.5
Case
Temp
Parameter
Test Condition
@ VDD = max
@ VDD = max
@ VDD = min
Unit
V
Level
Min Typ Max
VIH1
VIH2
VIL
High Level Input Voltage1
Full
Full
Full
Full
Full
Full
Full
Full
Full
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2.0
2.2
High Level Input Voltage2
Low Level Input Voltage1, 2
High Level Output Voltage3, 4
Low Level Output Voltage3, 4
High Level Input Current5, 6, 7
Low Level Input Current5
Low Level Input Current6
Low Level Input Current7
VDD + 0.5 2.2
VDD + 0.5
0.8
V
0.8
2.4
0.4
10
V
4
VOH
VOL
IIH
@ VDD = min, IOH = −2.0 mA
4.1
V
4
@ VDD = min, IOL = 4.0 mA
0.4
10
V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max,
µA
µA
µA
µA
µA
µA
µA
mA
µA
IIL
10
10
IILP
150
600
10
150
600
10
IILPX4
IOZH
IOZL
IOZHP
IOZLC
IOZLA
Three-State Leakage Current8, 9, 10, 11 Full
Three-State Leakage Current8, 12
Three-State Leakage Current12
Three-State Leakage Current13
Three-State Leakage Current14
Full
Full
Full
Full
10
10
350
1.5
350
350
1.5
350
VIN = 1.5 V (5 V), 2 V (3.3 V)
Three-State Leakage Current10
Three-State Leakage Current9
Three-State Leakage Current11
Supply Current (Internal)15
Supply Current (Idle)16
IOZLAR
IOZLS
IOZLSX4
IDDIN
IDDIDLE
CIN
Full
Full
Full
Full
Full
25°C
I
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = 0 V
tCK = 25 ns, VDD = max
VDD = max
4.2
4.2
mA
µA
µA
A
I
150
600
2.92
800
150
600
2.2
I
IV
I
1.4
15
1.0
15
760
mA
pF
Input Capacitance17, 18
V
1 Applies to input and bidirectional pins: DATA47-0, ADDR31-0 RD WR SW
,
,
,
, ACK,
,
y2-0, FLAGy0, FLAG1, FLAGy2,
, CSy,
HBG
,
,
DMAR1 DMAR2 BR6-1, RPBA,
y, TFS0,
CPA
STBS IRQ
TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD,
,
, TMS, TDI, TCK,
, DR0, DRy1, TCLK0, TCLKy1, RCLK0,
HBR
BMSA BMSBCD
RCLKy1.
2 Applies to input pins: CLKIN,
,
.
RESET TRST
3 Applies to output and bidirectional pins: DATA47-0, ADDR31-0 MS3-0 RD WR
y, DTO, DTy1, TCLK0, TCLKy1, RCLK0, RCLKy1, TFS0, TFSy1, RFS0, RFSy1, LyxDAT3-0, LyxCLK, LyxACK,
,
,
,
, PAGE, ADRCLK,
, ACK, FLAGy0, FLAG1, FLAGy2, TIMEXPy,
SW
, REDY,
HBG
,
,
DMAG1 DMAG2
,
,
, TDO,
.
EMU
BR6-1 CPA
4 See the Output Drive Currents section for typical drive current capabilities.
5 Applies to input pins:
y2-0 HBR CSy, , RPBA, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, CLKIN,
BMSA BMSBCD
,
,
,
,
, TCK.
RESET
STBS IRQ DMAR1 DMAR2
6 Applies to input pins with internal pull-ups: DR0, DRy1, TDI.
7 Applies to bused input pins with internal pull-ups:
, TMS.
TRST
8 Applies to three-statable pins: DATA47-0, ADDR31-0 MS3-0 RD WR
. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-2106x is not requesting bus
,
,
,
, PAGE, ADRCLK,
, ACK, FLAGy0, FLAG1, FLAGy2, REDY,
SW
,
,
, , TDO,
,
HBG DMAG1 DMAG2 BMSA BMSBCD
EMU
mastership.
and
are not tested for leakage current.)
EMU
HBG
9 Applies to three-statable pins with internal pull-ups: DTy1, TCLKy1, RCLKy1.
10 Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-2106x is not requesting bus mastership.)
11 Applies to bused three-statable pins with internal pull-ups: DT0, TCLK0, RCLK0.
12 Applies to three-statable pins with internal pull-downs: LyxDAT3-0, LyxCLK, LyxACK.
13 Applies to
y pin.
CPA
14 Applies to ACK pin, when the keeper latch is enabled.
15 Applies to VDD pins. Conditions of operation: each processor is executing radix-2 FFT butterfly with instruction in cache, one data operand is fetched from each
internal memory block, and one DMA transfer is occurring from/to internal memory at tCK = 25 ns.
16 Applies to VDD pins. Idle denotes AD14060/AD14060L state during execution of IDLE instruction.
17 Applies to all signal pins.
18 Guaranteed, but not tested.
Rev. B | Page 3 of 48
AD14060/AD14060L
EXPLANATION OF TEST LEVELS
Test Level
I
100% production tested.1
II
100% production tested at 25°C, and sample tested at
specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and analysis, and
characterization testing on discrete SHARCs.
V
Parameter is typical value only.
VI
All devices are 100% production tested at 25°C, and
sample tested at temperature extremes.
1 Link and serial ports: All are 100% tested at die level prior to assembly. All are
100% ac tested at module level; Link 4 and Serial 0 are also dc tested at the
module level. See the Timing Specifications section.
Rev. B | Page 4 of 48
AD14060/AD14060L
TIMING SPECIFICATIONS
reflect statistical variations and worst cases. Consequently, one
cannot meaningfully add parameters to derive longer times.
This data sheet represents production-released specifications
for the AD14060 (5 V), and for the AD14060L (3.3 V). The
ADSP-21060 die components are 100% tested, and the
assembled AD14060/AD14060L units are again extensively
tested at speed and across temperature. Parametric limits were
established from the ADSP-21060 characterization followed by
further design and analysis of the AD14060/AD14060L package
characteristics.
Switching Characteristics specify how the processor changes its
signals. The user has no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics
specify what the processor does in a given circumstance. The
user can also use switching characteristics to ensure that any
timing requirement of a device connected to the processor
(such as memory) is satisfied.
The specifications are based on a CLKIN frequency of 40 MHz
(tCK = 25 ns). The DT derating allows specifications at other
CLKIN frequencies (within the minimum to maximum range
of the tCK specification; see Table 3). DT is the difference
between the actual CLKIN period and a CLKIN period of 25 ns:
Timing Requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
DT = tCK − 25 ns
(O/D) = Open Drain
(A/D) = Active Drive
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
Table 3. Clock Input
40 MHz (5 V)
Max
40 MHz (3.3 V)
Max
Parameter
Unit
Min
Min
Clock Input
Timing Requirements:
tCK
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
25
7
5
100
3
25
9.5
5
100
3
ns
ns
ns
ns
tCKL
tCKH
tCKRF
tCK
CLKIN
tCKH
tCKL
Figure 2. Clock Input
Rev. B | Page 5 of 48
AD14060/AD14060L
Table 4. Reset
5 V
3.3 V
Max
Parameter
Unit
Min
Max
Min
Reset
Timing Requirements:
tWRST
tSRST
RESET Pulse Width Low1
RESET Setup before CLKIN High2
4 tCK
4 tCK
ns
ns
14 + DT/2
tCK
14 + DT/2
tCK
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while
low, assuming stable VDD and CLKIN (not including start-up time of the external clock oscillator).
is
RESET
2 Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (that is, for a SIMD system). Not required for
multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
tSRST
tWRST
RESET
Figure 3. Reset
Table 5. Interrupts
5 V
Max
3.3 V
Max
Parameter
Min
Min
Unit
Interrupts
Timing Requirements:
tSIR
tHIR
tIPW
IRQ2-0 Setup before CLKIN High1
IRQ2-0 Hold before CLKIN High1
IRQ2-0 Pulse Width2
18 + 3 DT/4
2 + tCK
18 + 3 DT/4
2 + tCK
ns
11.5 + 3 DT/4
11.5 + 3 DT/4 ns
ns
1 Only required for
x recognition in the following cycle.
IRQ
2 Applies only if tSIR and tHIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ
2–0
tIPW
Figure 4. Interrupts
Rev. B | Page 6 of 48
AD14060/AD14060L
Table 6. Timer
5 V
Max
3.3 V
Parameter
Unit
Min
Min
Max
Timer
Switching Characteristic:
tDTEX
CLKIN High to TIMEXP
16
16
ns
CLKIN
tDTEX
tDTEX
TIMEXP
Figure 5. Timer
Table 7. Flags
5 V
3.3 V
Parameter
Unit
Min
Max
Min
Max
Flags
Timing Requirements:
tSFI
tHFI
tDWRFI
tHFIWR
FLAG2-0IN Setup before CLKIN High1
FLAG2-0IN Hold after CLKIN High1
FLAG2-0IN Delay after RD/WR Low1
FLAG2-0IN Hold after RD/WR De-asserted1
8 + 5 DT/16
0.5 − 5 DT/16
8 + 5 DT/16
0.5 − 5 DT/16
ns
ns
ns
ns
4.5 + 7 DT/16
4.5 + 7 DT/16
0.5
0.5
Switching Characteristics:
tDFO
tHFO
tDFOE
tDFOD
FLAG2-0OUT Delay after CLKIN High
17
15
17
15
ns
ns
ns
ns
FLAG2-0OUT Hold after CLKIN High
CLKIN High to FLAG2-0OUT Enable
CLKIN High to FLAG2-0OUT Disable
4
3
4
3
1 Flag inputs that meet these setup and hold times affect conditional instructions in the following instruction cycle.
CLKIN
tDFOE
tDFO
tDFO
tDFOD
tHFO
FLAG2–0
OUT
FLAG OUTPUT
CLKIN
tHFI
tSFI
FLAG2–0
IN
tDWRFI
tHFIWR
RD, WR
FLAG INPUT
Figure 6. Flags
Rev. B | Page 7 of 48
AD14060/AD14060L
MEMORY READ—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 8. Specifications
5 V
Max
3.3 V
Max
Parameter
Unit
Min
Min
Timing Requirements:
tDAD
tDRLD
tHDA
tHDRH
tDAAK
tDSAK
Address, Delay to Data Valid1, 2
17.5 + DT + W
11.5 + 5 DT/8 + W
17.5 + DT + W
11.5 + 5 DT/8 + W ns
ns
RD Low to Data Valid1
Data Hold from Address3
Data Hold from RD High3
ACK Delay from Address2, 4
ACK Delay from RD Low4
1
2.5
1
2.5
ns
ns
13.5 + 7 DT/8 + W
7.5 + DT/2 + W
13.5 + 7 DT/8 + W ns
7.5 + DT/2 + W
ns
Switching Characteristics:
tDRHA
tDARL
tRW
Address Hold after RD High
Address to RD Low2
−0.5 + H
−0.5 + H
ns
ns
ns
ns
ns
1.5 + 3 DT/8
12.5 + 5 DT/8 + W
8 + 3 DT/8 + HI
−0.5 + DT/4
1.5 + 3 DT/8
12.5 + 5 DT/8 + W
8 + 3 DT/8 + HI
−0.5 + DT/4
RD Pulse Width
tRWR
RD High to WR, RD, DMAGx Low
Address Setup before ADRCLK High2
tSADADC
W = number of wait states specified in WAIT register × tCK.
HI = tCK, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.
H = tCK, if an address hold cycle occurs as specified in WAIT register; otherwise, H = 0.
1 Data delay/setup: User must meet tDAD, tDRLD, or synchronous specification, tSSDATI
2 For x,
, the falling edge is referenced.
.
,
MS SW BMS
3 Data hold: User must meet tHDA, tHDRH, or synchronous specification, tHDATI. See the System Hold Time Calculation Example section for the calculation of hold times given
capacitive and dc loads.
4 ACK delay/setup: User must meet tDSAK, tDAAK, or synchronous specification, tSACKC
.
ADDRESS
MSx, SW
BMS
tDRHA
tDARL
tRW
RD
tHDA
tHDRH
tDRLD
tDAD
DATA
tDSAK
tDAAK
tRWR
ACK
WR, DMAG
tSADADC
ADRCLK
(OUT)
Figure 7. Memory Read—Bus Master
Rev. B | Page 8 of 48
AD14060/AD14060L
MEMORY WRITE—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 9. Specifications
5 V
3.3 V
Parameter
Unit
13.5 + 7 DT/8 + W ns
Min
Max
Min
Max
Timing Requirements:
tDAAK
tDSAK
Switching Characteristics:
ACK Delay from Address, Selects1, 2
ACK Delay from WR Low1
13.5 + 7 DT/8 + W
8 + DT/2 + W
8 + DT/2 + W
ns
tDAWH
Address, Selects to WR
De-asserted2
16.5 + 15 DT/16 + W
16.5 + 15 DT/16 + W
ns
tDAWL
tWW
tDDWH
tDWHA
tDATRWH Data Disable after WR De-asserted3 0.5 + DT/16 + H
Address, Selects to WR Low2
WR Pulse Width
2.5 + 3 DT/8
2.5 + 3 DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
12 + 9 DT/16 + W
6.5 + DT/2 + W
12 + 9 DT/16 + W
6.5 + DT/2 + W
0 + DT/16 + H
0.5 + DT/16 + H
8 + 7 DT/16 + H
4.5 + 3 DT/8 + 1
−1.5 + DT/16
Data Setup before WR High
Address Hold after WR De-asserted 0 + DT/16 + H
6.5 + DT/16 + H
6.5 + DT/16 + H
tWWR
tDDWR
tWDE
WR High to WR, RD, DMAGx Low
Data Disable before WR or RD Low
WR Low to Data Enabled
8 + 7 DT/16 + H
4.5 + 3 DT/8 + 1
−1.5 + DT/16
−0.5 + DT/4
tSADADC Address, Selects to ADRCLK High2
−0.5 + DT/4
W = number of wait states specified in WAIT register × tCK.
H = tCK, if an address hold cycle occurs, as specified in WAIT register; otherwise, H = 0.
I = tCK, if a bus idle cycle occurs, as specified in WAIT register; otherwise, I = 0.
1 ACK delay/setup: User must meet tDAAK, tDSAK, or synchronous specification, tSACKC
.
2 For x,
, the falling edge is referenced.
MS SW BMS
,
3 See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
ADDRESS
MSx, SW
BMS
tDAWH
tDWHA
tDAWL
tWW
WR
tWWR
tDDWR
tWDE
tDDWH
tDATRWH
DATA
tDSAK
tDAAK
ACK
RD, DMAG
tSADADC
ADRCLK
(OUT)
Figure 8. Memory Write—Bus Master
Rev. B | Page 9 of 48
AD14060/AD14060L
SYNCHRONOUS READ/WRITE—BUS MASTER
Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave
ADSP 2106x in multiprocessor memory space. These synchronous switching characteristics are also valid during asynchronous memory
reads and writes (see the Memory Read—Bus Master and Memory Write—Bus Master sections).
When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see the Synchronous Read/Write—Bus Slave section). The slave ADSP-2106x must also meet these bus master timing
requirements for data and acknowledge setup and hold times.
Table 10. Specifications
5 V
Max
3.3 V
Max
Parameter
Unit
Min
Min
Timing Requirements:
tSSDATI
tHSDATI
tDAAK
Data Setup before CLKIN
Data Hold after CLKIN
ACK Delay after Address, MSx, SW, BMS1, 2
ACK Setup before CLKIN2
ACK Hold after CLKIN
3 + DT/8
4 − DT/8
3 + DT/8
4 − DT/8
ns
ns
ns
ns
ns
13.5 + 7 DT/8 + W
13.5 + 7 DT/8 + W
tSACKC
tHACKC
6.5 + DT/4
−0.5 − DT/4
6.5 + DT/4
−0.5 − DT/4
Switching Characteristics:
tDADRO
tHADRO
tDPGC
Address, MSx, BMS, SW, Delay after CLKIN1
8 − DT/8
8 − DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address, MSx, BMS, SW, Hold after CLKIN
PAGE Delay after CLKIN
RD High Delay after CLKIN
WR High Delay after CLKIN
RD/WR Low Delay after CLKIN
Data Delay after CLKIN
Data Disable after CLKIN3
ADRCLK Delay after CLKIN
ADRCLK Period
−1 − DT/8
9 + DT/8
−2 − DT/8
−1 − DT/8
9 + DT/8
−2 − DT/8
17 + DT/8
+5 − DT/8
17 + DT/8
+5 − DT/8
tDRDO
tDWRO
tDRWL
−3 − 3 DT/16 +5 − 3 DT/16
−3 − 3 DT/16 +5 − 3 DT/16
8 + DT/4
13.5 + DT/4
20 + 5 DT/16
8 − DT/8
8 + DT/4
13.5 + DT/4
20.25 + 5 DT/16
8 – DT/8
tSDDATO
tDATTR
tDADCCK
tADRCK
tADRCKH
tADRCKL
0 − DT/8
4 + DT/8
tCK
(tCK/2 − 2)
(tCK/2 − 2)
0 − DT/8
4 + DT/8
tCK
(tCK/2 − 2)
(tCK/2 − 2)
11 + DT/8
11 + DT/8
ADRCLK Width High
ADRCLK Width Low
W = number of wait states specified in WAIT register × tCK.
1 For x,
, the falling edge is referenced.
MS SW BMS
,
2 ACK delay/setup: User must meet tDAAK, tDSAK, or synchronous specification, tSACKC
3 See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
.
Rev. B | Page 10 of 48
AD14060/AD14060L
CLKIN
tADRCK
tDADCCK
tADRCKH
tADRCKL
ADRCLK
tHADRO
tDADRO
tDAAK
ADDRESS
SW
tDPGC
PAGE
tHACKC
tSACKC
ACK
(IN)
READ CYCLE
tDRWL
tDRDO
RD
tSSDATI
tHSDATI
DATA
(IN)
WRITE CYCLE
WR
tDWRO
tDRWL
tSDDATO
tDATTR
DATA
(OUT)
Figure 9. Synchronous Read/Write—Bus Master
Rev. B | Page 11 of 48
AD14060/AD14060L
SYNCHRONOUS READ/WRITE—BUS SLAVE
Use these specifications for bus master access to a slave’s IOP registers or internal memory in multiprocessor memory space. The bus
master must meet these bus slave timing requirements.
Table 11. Specifications
5 V
Max
3.3 V
Max
Parameter
Unit
Min
Min
Timing Requirements:
tSADRI
Address, SW Setup before CLKIN
15.5 + DT/2
15.5 + DT/2
ns
ns
ns
ns
ns
ns
ns
tHADRI
tSRWLI
Address, SW Hold before CLKIN
RD/WR Low Setup before CLKIN1
RD/WR Low Hold after CLKIN
RD/WR Pulse High
4.5 + DT/2
4.5 + DT/2
9.5 + 5 DT/16
9.5 + 5 DT/16
tHRWLI
tRWHPI
tSDATWH
tHDATWH
−3.5 − 5 DT/16
+8 + 7 DT/16
−3.25 − 5 DT/16
+8 + 7 DT/16
3
3
Data Setup before WR High
Data Hold after WR High
5.5
1.5
5.5
1.5
Switching Characteristics:
tSDDATO Data Delay after CLKIN
tDATTR
tDACKAD
tACKTR
20 + 5 DT/16
8 − DT/8
10
20.25 + 5 DT/16
8 − DT/8
10
ns
ns
ns
ns
Data Disable after CLKIN2
ACK Delay after Address, SW3
ACK Disable after CLKIN3
0 − DT/8
0 − DT/8
−1 − DT/8
+7 − DT/8
−1 − DT/8
+7 − DT/8
1 tSRWLI (min) = 9.5 + 5 DT/16 when the multiprocessor memory space wait state (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min) =
4 + DT/8.
2 See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
3 tDACKAD is true only if the address and
inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 18.5 + 3 DT/4. If the address and
inputs have
SW
SW
setup times greater than 19 + 3 DT/4, then ACK is valid 15 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match responds with ACK regardless
of the state of MMSWS or strobes. A slave three-states ACK every cycle with tACKTR
.
CLKIN
tSADRI
tHADRI
ADDRESS
SW
tDACKAD
tACKTR
ACK
READ ACCESS
RD
tSRWLI
tHRWLI
tRWHPI
tDATTR
tSDDATO
DATA
(OUT)
WRITE ACCESS
WR
tSRWLI
tHRWLI
tRWHPI
tHDATWH
tSDATWH
DATA
(IN)
Figure 10. Synchronous Read/Write—Bus Slave
Rev. B | Page 12 of 48
AD14060/AD14060L
MULTIPROCESSOR BUS REQUEST AND HOST BUS REQUEST
BR
HBR HBG
, ).
Use these specifications for passing of the bus mastership among multiprocessing ADSP-2106xs ( x) or a host processor (
Table 12. Specifications
5 V
3.3 V
Max
Parameter
Unit
Min
Max
Min
Timing Requirements:
tHBGRCSV HBG Low to RD/WR/CS Valid1
19.5 + 5 DT/4
19.5 + 5 DT/4
13.5 + 3 DT/4
5.5 + DT/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSHBRI
tHHBRI
tSHBGI
tHHBGI
tSBRI
HBR Setup before CLKIN2
HBR Hold before CLKIN2
20 + 3 DT/4
13 + DT/2
13 + DT/2
21 + 3 DT/4
20 + 3 DT/4
13 + DT/2
13 + DT/2
21 + 3 DT/4
13.5 + 3 DT/4
5.5 + DT/2
HBG Setup before CLKIN
HBG Hold before CLKIN High
BRx, CPA Setup before CLKIN3
BRx, CPA Hold before CLKIN High
RPBA Setup before CLKIN
RPBA Hold before CLKIN
tHBRI
5.5 + DT/2
11.5 + 3 DT/4
8 − DT/8
5.5 + DT/2
11.5 + 3 DT/4
8 − DT/8
tSRPBAI
tHRPBAI
Switching Characteristics:
tDHBGO
tHHBGO
tDBRO
HBG Delay after CLKIN
ns
ns
ns
ns
ns
ns
ns
ns
ns
HBG Hold after CLKIN
−2 − DT/8
−2 − DT/8
–2 − DT/8
−2 − DT/8
−2 − DT/8
BRx Delay after CLKIN
8 − DT/8
8 − DT/8
tHBRO
BRx Hold after CLKIN
tDCPAO
tTRCPA
tDRDYCS
tTRDYHG
tARDYTR
CPA Low Delay after CLKIN
9 − DT/8
+5.5 − DT/8
9.5
9.5 − DT/8
+5.5 − DT/8
12
CPA Disable after CLKIN
−2 − DT/8
REDY (O/D) or (A/D) Low from CS and HBR Low4
REDY (O/D) Disable or REDY (A/D) High from HBG4
REDY (A/D) Disable from CS or HBR High4
40 + 27 DT/16
40 + 27 DT/16
11
11
1 For first asynchronous access after
and
asserted, ADDR31–0 must be a non-MMS value 1/2 tCK before
CS
or goes low, or by tHBGRCSV after HBG goes low. This is
RD WR
HBR
easily accomplished by driving an upper address signal high when
is asserted.
HBG
2 Required only for recognition in the current cycle.
3
assertion must meet the setup to CLKIN; de-assertion does not need to meet the setup to CLKIN.
CPA
4 (O/D) = open drain; (A/D) = active drive.
Rev. B | Page 13 of 48
AD14060/AD14060L
CLKIN
tSHBRI
tHHBRI
HBR
tDHBGO
tHHBGO
HBG
(OUT)
tDBRO
tHBRO
BRx
(OUT)
tDCPAO
tTRCPA
CPA (OUT)
(O/D)
tSHBGI
tHHBGI
HBG (IN)
tSBRI
tHBRI
BRx (IN)
CPA (IN) (O/D)
HBR
CS
tTRDYHG
tDRDYCS
REDY (O/D)
REDY (A/D)
tARDYTR
tHBGRCSV
HBG (OUT)
RD
WR
CS
tSRPBAI
tHRPBAI
RPBA
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
HBG IS DELAYED BY n CLOCK CYCLES WHEN WAIT STATES OR BUS LOCK ARE IN EFFECT.
Figure 11. Multiprocessor Bus Request and Host Bus Request
Rev. B | Page 14 of 48
AD14060/AD14060L
ASYNCHRONOUS READ/WRITE—HOST TO AD14060/AD14060L
CS
HBR
(low).
Use these specifications for asynchronous host processor access to an AD14060/AD14060L, after the host has asserted
and
HBG
RD
WR
and pins to access the AD14060/AD14060L’s internal
After
is returned by the AD14060/AD14060L, the host can drive the
HBR
HBG
are assumed low for this timing.
memory or IOP registers.
and
Table 13. Specifications
5 V
3.3 V
Parameter
Unit
Min
Max
Min
Max
Read Cycle
Timing Requirements:
tSADRDL
tHADRDH
tWRWH
Address Setup/CS Low before RD Low1
Address Hold/CS Hold Low after RD
RD/WR High Width
0.5
0.5
6
0.5
0.5
6
ns
ns
ns
ns
ns
tDRDHRDY
tDRDHRDY
RD High Delay after REDY (O/D) Disable
RD High Delay after REDY (A/D) Disable
0
0
0
0
Switching Characteristics:
tSDATRDY
tDRDYRDL
tRDYPRD
Data Valid before REDY Disable from Low
1.5
1.5
ns
ns
ns
ns
REDY (O/D) or (A/D) Low Delay after RD Low
REDY (O/D) or (A/D) Low Pulse Width for Read
Data Disable after RD High
11
9
13.5
9.5
45 + DT
1.5
45 + DT
1.5
tHDARWH
Write Cycle
Timing Requirements:
tSCSWRL
tHCSWRH
tSADWRH
tHADWRH
tWWRL
CS Low Setup before WR Low
0.5
0.5
5.5
2.5
7
0.5
0.5
5.5
2.5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Low Hold after WR High
Address Setup before WR High
Address Hold after WR High
WR Low Width
tWRWH
RD/WR High Width
6
6
tDWRHRDY
tSDATWH
tHDATWH
WR High Delay after REDY (O/D) or (A/D) Disable
Data Setup before WR High
Data Hold After WR High
0.5
5.5
1.5
0.5
5.5
1.5
Switching Characteristics:
tDRDYWRL
tRDYPWR
tSRDYCK
REDY (O/D) or (A/D) Low Delay after WR/CS Low
11
13.5
ns
ns
ns
REDY (O/D) or (A/D) Low Pulse Width for Write
REDY (O/D) or (A/D) Disable to CLKIN
15
15
0 + 7 DT/16
8 + 7 DT/16
0 + 7 DT/16
8 + 7 DT/16
1 Not required, if
and address are valid tHBGRCSV after
goes low. For first access after
is asserted, ADDR31–0 must be a non-MMS value 1/2 tCLK before
or
RD
HBG
HBR
RD WR
goes low or by tHBGRCSV after
goes low. This is easily accomplished by driving an upper address signal high when
is asserted. For address bits to be driven
HBG
HBG
during asynchronous host accesses, see the ADSP-2106x SHARC User’s Manual.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 12. Synchronous REDY Timing
Rev. B | Page 15 of 48
AD14060/AD14060L
READ CYCLE
ADDRESS/CS
tSADRDL
tHADRDH
tWRWH
RD
tHDARWH
DATA (OUT)
tDRDHRDY
tSDATRDY
tRDYPRD
tDRDYRDL
REDY (O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
tSADWRH
tHADWRH
tSCSWRL
tHCSWRH
CS
tWWRL
tWRWH
WR
tHDATWH
tSDATWH
DATA (IN)
tRDYPWR
tDWRHRDY
tDRDYWRL
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 13. Asynchronous Read/Write—Host to ADSP-2106x
Rev. B | Page 16 of 48
AD14060/AD14060L
THREE-STATE TIMING—BUS MASTER, BUS SLAVE, HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the
SBTS SBTS
pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the
pin.
Table 14. Specifications
5 V
3.3 V
Parameter
Unit
Min
Max
Min
Max
Timing Requirements:
tSTSCK
tHTSCK
Switching Characteristics:
tMIENA Address/Select Enable after CLKIN
tMIENS
tMIENHG
tMITRA
SBTS Setup before CLKIN
12.5 + DT/2
12.5 + DT/2
ns
ns
SBTS Hold before CLKIN
5.5 + DT/2
5.5 + DT/2
−1.5 − DT/8
−1.5 − DT/8
−1.5 − DT/8
−1.25 − DT/8
−1.5 − DT/8
−1.5 − DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Strobes Enable after CLKIN1
HBG Enable after CLKIN
Address/Select Disable after CLKIN
Strobes Disable after CLKIN1
HBG Disable after CLKIN
1 − DT/4
2.5 − DT/4
3 − DT/4
1.25 − DT/4
2.5 − DT/4
3 − DT/4
tMITRS
tMITRHG
tDATEN
tDATTR
tACKEN
tACKTR
tADCEN
tADCTR
tMTRHBG
tMENHBG
Data Enable after CLKIN2
9 + 5 DT/16
0 − DT/8
7.5 + DT/4
−1 − DT/8
−2 − DT/8
9 + 5 DT/16
0 − DT/8
7.5 + DT/4
−1 − DT/8
−2 − DT/8
Data Disable after CLKIN2
8 − DT/8
+7 − DT/8
9 − DT/4
8 − DT/8
+7 − DT/8
9 − DT/4
ACK Enable after CLKIN2
ACK Disable after CLKIN2
ADRCLK Enable after CLKIN
ADRCLK Disable after CLKIN
Memory Interface Disable before HBG Low3
Memory Interface Enable after HBG High3
−1 + DT/8
18.5 + DT
−1 + DT/8
18.5 + DT
1 Strobes =
,
,
, PAGE,
.
DMAG
RD WR SW
2 In addition to bus master transition cycles, these specifications also apply to bus master and bus slave synchronous read/write.
3 Memory interface = address,
,
,
x,
,
, PAGE,
x,
(in EPROM boot mode).
RD WR MS SW HBG
DMAG BMS
CLKIN
SBTS
tSTSCK
tHTSCK
tMIENA
,
tMIENS
,
tMIENHG
tMITRA, tMITRS, tMITRHG
MEMORY
INTERFACE
tDATEN
tDATTR
DATA
ACK
tACKEN
tACKTR
tADCEN
tADCTR
ADRCLK
HBG
tMENHBG
tMTRHBG
MEMORY
INTERFACE
MEMORY INTERFACE= ADDRESS, RD, WR, MSx, SW, HBG, PAGE,DMAGx. BMS (IN EPROM BOOT MODE)
Figure 14. Three-State Timing
Rev. B | Page 17 of 48
AD14060/AD14060L
DMA HANDSHAKE
DMAR
These specifications describe the three DMA handshake modes. In all three modes,
is used to initiate transfers. For handshake
DMAG
mode,
ADDR31-0
WR MS
controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the
RD WR SW MS DMAG RD
,
,
,
,
, PAGE,
DMAG
3-0, and ACK (not
3-0, ACK, and
signals. For paced master mode, the data transfer is controlled by ADDR31-0
,
,
). For paced master mode, the memory read—bus master, memory write—bus master, and synchronous
RD WR MS SW
read/write—bus master timing specifications for ADDR31-0
,
,
,
,
, PAGE, DATA47-0, and ACK also apply.
3-0
Table 15. Specifications
5 V
3.3 V
Parameter
Unit
Min
Max
Min
Max
Timing Requirements:
tSDRLC
DMARx Low Setup before CLKIN1
DMARx High Setup before CLKIN1
DMAR
Data Setup after DMAGx Low2
Data Hold after DMAGx High
Data Valid after DMAGx High2
DMAGx Low Edge to Low Edge
DMAGx Width High
5
5
6
5
5
6
ns
ns
ns
ns
ns
tSDRHC
tWDR
x Width Low (Nonsynchronous)
tSDATDGL
tHDATIDG
tDATDRH
tDMARLL
tDMARH
9 + 5 DT/8
9 + 5 DT/8
2
2
15.5 + 7 DT/8
15.5 + 7 DT/8 ns
23 + 7 DT/8
6
23 + 7 DT/8
6
ns
ns
Switching Characteristics:
tDDGL
DMAGx Low Delay after CLKIN
9 + DT/4
6 + 3 DT/8
12 + 5 DT/8
−2 − DT/8
7.5 + 9 DT/16
−1
16 + DT/4
+7 − DT/8
9 + DT/4
6 + 3 DT/8
12 + 5 DT/8
−2 − DT/8
7.5 + 9 DT/16
−1
16 + DT/4
+7 − DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWDGH
tWDGL
DMAGx High Width
DMAGx Low Width
tHDGC
DMAGx High Delay after CLKIN
Data Valid before DMAGx High3
Data Disable after DMAGx High4
WR Low before DMAGx Low
DMAGx Low before WR High
WR High before DMAGx High
RD Low before DMAGx Low
RD Low before DMAGx High
RD High before DMAGx High
DMAGx High to WR, RD, DMAGx Low
Address/Select Valid to DMAGx High
Address/Select Hold after DMAGx High
tVDATDGH
tDATRDGH
tDGWRL
tDGWRH
tDGWRR
tDGRDL
tDRDGH
tDGRDR
tDGWR
+7.5
+2.5
+7.5
+2.5
−0.5
−0.75
9.5 + 5 DT/8 + W
0.5 + DT/16
−0.25
9.5 + 5 DT/8 + W
0.5 + DT/16
0
3.5 + DT/16
+2.5
3.5 + DT/16
2.5
11 + 9 DT/16 + W
11 + 9 DT/16 + W
0
0
3.5
3.5
4.5 + 3 DT/8 + HI
16 + DT
4.5 + 3 DT/8 + HI
16 + DT
tDADGH
tDDGHA
−1.5
−1.5
W = number of wait states specified in WAIT register × tCK.
HI = tCK, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.
1 Required only for recognition in the current cycle.
2 tSDATDGL is the data setup requirement, if
x is not being used to hold off completion of a write. Otherwise, if
DMAR
x low holds off completion of the write, the data
DMAR
can be driven tDATDRH after
3 tVDATDGH is valid, if
x is brought high.
DMAR
x is not being used to hold off completion of a read. If
DMAR
x is used to prolong the read, then tVDATDGH = 7.5 + 9 DT/16 + (n × tCK), where n
DMAR
equals the number of extra cycles that the access is prolonged.
4 See the System Hold Time Calculation Example section for the calculation of hold times given capacitive and dc loads.
Rev. B | Page 18 of 48
AD14060/AD14060L
CLKIN
tSDRLC
tDMARLL
tSDRHC
tDMARH
tWDR
DMARx
DMAGx
tHDGC
tWDGL
tDDGL
tWDGH
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
tDATRDGH
tVDATDGH
DATA (FROM
ADSP-2106x TO
EXTERNAL DRIVE)
tDATDRH
tHDATIDG
tSDATDGL
DATA (FROM
EXTERNAL DRIVE
TO ADSP-2106x)
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY1 (EXTERNAL HANDSHAKE MODE)
tDGWRL
WR
tDGWRR
tDGWRH
(EXTERNAL DEVICE TO
EXTERNAL MEMORY)
tDGRDL
tDGRDR
RD
(EXTERNAL MEMORY
TO EXTERNAL DEVICE)
tDRDGH
tDADGH
tDDGHA
ADDRESS
MS , SW
X
1
MEMORY READ – BUS MASTER, MEMORY WRITE – BUS MASTER, AND SYNCHRONOUS READ/WRITE – BUS MASTER.
TIMING SPECIFICATIONS FOR ADDR
, RD, WR, SW, MS , AND ACK ALSO APPLY HERE.
31–0
3-0
Figure 15. DMA Handshake Timing
Rev. B | Page 19 of 48
AD14060/AD14060L
Table 16. 1× CLK Speed Operation
5 V
Max
3.3 V
Max
Parameter
Unit
Min
Min
Receive
Timing Requirements:
tSLDCL
tHLDCL
tLCLKIW
tLCLKRWL
tLCLKRWH
Data Setup before LCLK Low
Data Hold after LCLK Low
LCLK Period (1× Operation)
LCLK Width Low
3.5
3
tCK
6
3
3
tCK
6
5
ns
ns
ns
ns
ns
LCLK Width High
5
Switching Characteristics:
tDLAHC
tDLALC
tENDLK
tTDLK
LACK High Delay after CLKIN High
18 + DT/2
−3
5 + DT/2
29.5 + DT/2
+13.5
18 + DT/2
−3
5 + DT/2
30 + DT/2
+13.5
ns
ns
ns
ns
LACK Low Delay after LCLK High1
LACK Enable from CLKIN
LACK Disable from CLKIN
21 + DT/2
21 + DT/2
Transmit
Timing Requirements:
tSLACH LACK Setup before LCLK High
tHLACH LACK Hold after LCLK High
Switching Characteristics:
18
−7
20
−7
ns
ns
tDLCLK
LCLK Delay after CLKIN (1× Operation)
16.5
3.5
17.5
3
ns
ns
ns
ns
ns
ns
tDLDCH
tHLDCH
tLCLKTWL
tLCLKTWH
tDLACLK
Data Delay after LCLK High
Data Hold after LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay after LACK High
−3
−3
(tCK/2) − 2
(tCK/2) − 2
(tCK/2) + 8.5
(tCK/2) + 2
(tCK/2) + 2
(3 × tCK/2) + 17.5 (tCK/2) + 8
(tCK/2) − 1
(tCK/2) − 2.25
(tCK/2) + 2.25
(tCK/2) + 1
(3 × tCK/2) +
18.25
tENDLK
tTDLK
LDAT, LCLK Enable after CLKIN
LDAT, LCLK Disable after CLKIN
5 + DT/2
5 + DT/2
ns
ns
21 + DT/2
21 + DT/2
Link Port Service Request Interrupts:
1× and 2× Speed Operations
Timing Requirements:
tSLCK
tHLCK
LACK/LCLK Setup before CLKIN Low2
LACK/LCLK Hold after CLKIN Low2
10
2.5
10
2.5
ns
ns
1 LACK goes low with tDLALC relative to the rising edge of LCLK after the first nibble is received. LACK does not go low, if the receiver’s link buffer is not about to fill.
2 Required only for interrupt recognition in the current cycle.
Rev. B | Page 20 of 48
AD14060/AD14060L
Table 17. 2× CLK Speed Operation
5 V
3.3 V
Parameter
Unit
Min
Max
Min
Max
Receive
Timing Requirements:
tSLDCL
tHLDCL
tLCLKIW
tLCLKRWL
tLCLKRWH
Data Setup before LCLK Low
Data Hold after LCLK Low
LCLK Period (2× Operation)
LCLK Width Low
2.75
2.25
tCK/2
4.6
2.25
2.25
tCK/2
5.25
4.5
ns
ns
ns
ns
ns
LCLK Width High
4.25
Switching Characteristics:
tDLAHC
tDLALC
LACK High Delay after CLKIN High
LACK Low Delay after LCLK High1
18 + DT/2
6
31.5 + DT/2
17.8
18 + DT/2
6
30.5 + DT/2
19
ns
ns
Transmit
Timing Requirements:
tSLACH LACK Setup before LCLK High
tHLACH LACK Hold after LCLK High
Switching Characteristics:
20.25
−6.5
19
−6.5
ns
ns
tDLCLK
LCLK Delay after CLKIN
9
3.25
9
2.75
ns
ns
ns
ns
ns
ns
tDLDCH
tHLDCH
tLCLKTWL
tLCLKTWH
tDLACLK
Data Delay after LCLK High
Data Hold after LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay after LACK High
−2
−2
(tCK/4) − 1
(tCK/4) − 1.5
(tCK/4) + 9
(tCK/4) + 1.5
(tCK/4) + 1
(3 × tCL/4) + 17
(tCK/4) − 0.75
(tCK/4) − 1.5
(tCK/4) + 9
(tCK/4) + 1.5
(tCK/4) + 1
(3 × tCL/4) + 17
1 LACK goes low with tDLALC relative to the rising edge of LCLK after the first nibble is received. LACK does not go low, if the receiver’s link buffer is not about to fill.
Rev. B | Page 21 of 48
AD14060/AD14060L
TRANSMIT
CLKIN
tDLCLK
tLCLKTWH tLCLKTWL
LAST NIBBLE
TRANSMITTED
FIRST NIBBLE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LCLK 1x
OR
LCLK 2x
tDLDCH
tHLDCH
OUT
LDAT(3:0)
LACK (IN)
tSLACH
tHLACH
tDLACLK
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
RECEIVE
CLKIN
tLCLKIW
tLCLKRWH
tLCLKRWL
LCLK 1x
OR
LCLK 2x
tHLDCL
tSLDCL
IN
LDAT(3:0)
tDLAHC
tDLALC
LACK (OUT)
LACK GOES LOW ONLY AFTER THE SECOND NIBBLE IS RECEIVED.
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
CLKIN
tENDLK
tTDLK
LCLK
LDAT(3:0)
LACK
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
LINK PORT INTERRUPT SETUP TIME
CLKIN
tHLCK
tSLCK
LCLK
LACK
Figure 16. Link Ports
Rev. B | Page 22 of 48
AD14060/AD14060L
Table 18. Serial Ports
5 V
Max
3.3 V
Parameter
Unit
Min
Min
Max
External Clock
Timing Requirements:
tSFSE
TFS/RFS Setup before TCLK/RCLK1
4
4.5
2
4.5
9.5
tCK
4
4.5
2
4.5
9.5
tCK
ns
ns
ns
ns
ns
ns
tHFSE
tSDRE
tHDRE
tSCLKW
tSCLK
TFS/RFS Hold after TCLK/RCLK1, 2
Receive Data Setup before RCLK1
Receive Data Hold after RCLK1
TCLK/RCLK Width
TCLK/RCLK Period
Internal Clock
Timing Requirements:
tSFSI
tHFSI
tSDRI
tHDRI
TFS Setup before TCLK1; RFS Setup before RCLK1
9.5
1
4.5
3
9.5
1
4.5
3
ns
ns
ns
ns
TFS/RFS Hold after TCLK/RCLK1, 2
Receive Data Setup before RCLK1
Receive Data Hold after RCLK1
External or Internal Clock
Switching Characteristics:
tDFSE
tHFSE
RFS Delay after RCLK (Internally Generated RFS)3
RFS Hold after RCLK (Internally Generated RFS)3
14.5
14.5
ns
ns
2.5
2.5
External Clock
Switching Characteristics:
tDFSE
tHFSE
tDDTE
tHDTE
TFS Delay after TCLK (Internally Generated TFS)3
14.5
17.5
14.5
17.5
ns
ns
ns
ns
TFS Hold after TCLK (Internally Generated TFS)3
Transmit Data Delay after TCLK3
3
5
3
5
Transmit Data Hold after TCLK3
Internal Clock
Switching Characteristics:
tDFSI
tHFSI
tDDTI
tHDTI
tSCLKIW
TFS Delay after TCLK (Internally Generated TFS)3
5
5
ns
ns
ns
ns
ns
TFS Hold after TCLK (Internally Generated TFS)3
Transmit Data Delay after TCLK3
Transmit Data Hold after TCLK3
TCLK/RCLK Width
−1.5
−1.5
7.5
7.5
−0.5
(SCLK/2) − 2
−0.5
(SCLK/2) − 2.5
(SCLK/2) + 2
(SCLK/2) + 2.5
Enable and Three-State
Switching Characteristics:
tDDTEN
tDDTTE
tDDTIN
tDDTTI
tDCLK
Data Enable from External TCLK3
3.5
4
ns
ns
ns
ns
ns
ns
Data Disable from External TCLK3
Data Enable from Internal TCLK3
Data Disable from Internal TCLK3
TCLK/RCLK Delay from CLKIN
SPORT Disable after CLKIN
12
12
−0.5
−0.5
3
3
23.5 + 3 DT/8
18.5
23.5 + 3 DT/8
18.5
tDPTR
Gated SCLK with External TFS (Mesh Multiprocessing)
Timing Requirements:
tSTFSCK
tHTFSCK
TFS Setup before CLKIN
TFS Hold after CLKIN
5.5
5.5
ns
ns
(TCK/2) + 0.5
(TCK/2) + 0.5
Rev. B | Page 23 of 48
AD14060/AD14060L
5 V
Max
3.3 V
Max
Parameter
Unit
Min
Min
External Late Frame Sync
Switching Characteristics:
tDDTLFSE
Data Delay from Late External TFS or External RFS
14.1
14.3
ns
ns
with MCE = 1, MFD = 04
tDDTENFS
Data Enable from Late FS or MCE = 1, MFD = 04
3.0
3.5
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame
sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
1 Referenced to sample edge.
2 RFS hold after RCK when MCE = 1, MFD = 0 is 0.5 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0.5 ns minimum from drive edge.
3 Referenced to drive edge.
4 MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS
.
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
DRIVE
SAMPLE
RCLK
RFS
1
tSFSE/I
tHFSE/I
tDDTE/I
tDDTENFS
tHDTE/I
DT
FIRST BIT
SECOND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE SAMPLE
DRIVE
TCLK
TFS
1
tSFSE/I
tHFSE/I
tDDTE/I
tDDTENFS
tHDTE/I
DT
FIRST BIT
SECOND BIT
tDDTLFSE
1
RFS HOLD AFTER RCK WHEN MCE = 1, MFD = 0 IS 0.5ns MINIMUM FROM DRIVE EDGE.
TFS HOLD AFTER TCK FOR LATE EXTERNAL TFS IS 0.5ns MINIMUM FROM DRIVE EDGE.
Figure 17. External Late Frame Sync
Rev. B | Page 24 of 48
AD14060/AD14060L
DATA RECEIVE– INTERNAL CLOCK
DATA RECEIVE– EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHFSE
tDFSE
tHFSE
tSFSI
tHFSI
tSFSE
tHFSE
RFS
DR
RFS
DR
tSDRI
tHDRI
tSDRE
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tDFSI
tHFSI
tDFSE
tHFSE
tSFSI
tHFSI
tSFSE
tHFSE
TFS
DT
TFS
DT
tDDTI
tHDTI
tDDTE
tHDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK/RCLK
TCLK (EXT)
tDDTEN
tDDTTE
DT
DRIVE
EDGE
DRIVE
EDGE
TCLK (INT)
TCLK/RCLK
tDDTIN
tDDTTI
DT
CLKIN
CLKIN
tDPTR
tSTFSCK
tHTFSCK
TCLK, RCLK
SPORT ENABLE AND
THREE-STATE LATENCY
IS TWO CYCLES
SPORT DISABLE DELAY
FROM INSTRUCTION
TFS (EXT)
TFS, RFS, DT
tDCLK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O
FOR MESH MULTIPROCESSING.
TCLK (INT)
RCLK (INT)
LOW TO HIGH ONLY
Figure 18. Serial Ports
Rev. B | Page 25 of 48
AD14060/AD14060L
Table 19. JTAG Test Access Port and Emulation
5 V
Max
3.3 V
Max
Parameter
Unit
Min
Min
Timing Requirements:
tTCK
TCK Period
tCK
5
6
7
18.5
4 tCK
tCK
ns
ns
ns
ns
ns
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup before TCK High
TDI, TMS Hold after TCK High
System Inputs Setup before TCK Low1
System Inputs Hold after TCK Low1
TRST Pulse Width
6
8
19
4 tCK
Switching Characteristics:
tDTDO TDO Delay from TCK Low
tDSYS
System Outputs Delay after TCK Low2
13.5
20
13.5
20
ns
ns
1 System Inputs = DATA47-0, ADDR31-0 RD WR
TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT,
,
,
, ACK,
,
,
,
,
,
,
,
SBTS SW HBR HBG CS DMAR1 DMAR2 BR6-1, RPBA, IRQ2-0, FLAG2-0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0,
, CLKIN,
.
,
BMS
RESET
SW HBG
2 System Outputs = DATA47-0, ADDR31-0 MS3-0 RD WR
,
,
,
, ACK, PAGE, ADRCLK,
, REDY,
, , , , FLAG2-0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0,
DMAG1 DMAG2 BR6-1 CPA
RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK,
.
BMS
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 19. IEEE 11499.1 JTAG Test Access Port
Rev. B | Page 26 of 48
AD14060/AD14060L
ABSOLUTE MAXIMUM RATINGS
Table 20.
Stresses greater than those listed above may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Parameters
Ratings
Supply Voltage (5 V)
Supply Voltage (3.3 V)
Input Voltage
Output Voltage Swing
Load Capacitance
Junction Temperature under Bias
Storage Temperature Range
Lead
−0.3 V to +7 V
−0.3 V to +4.6 V
−0.5 V to VDD + 0.5 V
−0.5 V to VDD + 0.5 V
200 pF
130°C
−65°C to +150°C
280°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 27 of 48
AD14060/AD14060L
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
308
1
232
231
AD14060/AD14060L
TOP VIEW
155
154
77
78
Figure 20. 308-Lead CQFP Pin Configuration
Rev. B | Page 28 of 48
AD14060/AD14060L
Table 21. Pin Numbers and Mnemonics
Pin
No.
Pin
Pin
Pin
Pin
Pin
Pin
Mnemonic No.
Mnemonic No.
Mnemonic No.
Mnemonic No.
Mnemonic No.
Mnemonic No.
Mnemonic
GND
1
WR
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
8
GND
89
ADDR13
ADDR12
ADDR11
GND
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
IRQ
IRQ
IRQ
177
178
179
180
181
182
183
184
185
186
187
188
189
LC4DAT2
LC4DAT3
GND
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
GND
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
B0
B1
B2
2
RD
RFSD1
RCLKD1
DRD1
TFSD1
TCLKD1
DTD1
VDD
90
LA3ACK
LA3CLK
LA3DAT0
LA3DAT1
LA3DAT2
LA3DAT3
VDD
DATA24
DATA25
DATA26
DATA27
VDD
3
GND
91
4
CSA
92
GND
LC3ACK
LC3CLK
LC3DAT0
LC3DAT1
LC3DAT2
LC3DAT3
VDD
5
CSB
93
ADDR10
ADDR9
ADDR8
VDD
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
VDD
C0
C1
C2
D0
D1
D2
6
CSC
94
7
CSD
95
DATA28
DATA29
DATA30
DATA31
GND
8
GND
96
9
HBG
HBR
97
ADDR7
ADDR6
ADDR5
GND
LA1ACK
LA1CLK
LA1DAT0
LA1DAT1
LA1DAT2
LA1DAT3
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
REDY
ADRCLK
VDD
DMAR
DMAR
SBTS
98
1
2
99
LC1ACK
LC1CLK
LC1DAT0
LC1DAT1
LC1DAT2
LC1DAT3
GND
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
EBOOTA
LBOOTA
DATA32
DATA33
DATA34
DATA35
VDD
RFS0
BMSA
ADDR4
ADDR3
ADDR2
VDD
RCLK0
DR0
BMSBCD
SW
EBOOTBCD 190
LBOOTBCD 191
TFS0
GND
GND
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
DATA0
DATA1
DATA2
DATA3
VDD
TCLK0
DT0
MS
MS
MS
MS
ADDR1
ADDR0
FLAGA0
GND
RESET
DATA36
DATA37
DATA38
DATA39
GND
0
1
2
3
RPBA
LB4ACK
LB4CLK
LB4DAT0
LB4DAT1
LB4DAT2
LB4DAT3
VDD
GND
GND
CPAA
CPAB
CPAC
CPAD
VDD
LD4ACK
LD4CLK
LD4DAT0
LD4DAT1
LD4DAT2
LD4DAT3
VDD
VDD
FLAGA2
FLAGB0
FLAGB2
FLAGC0
FLAGC2
FLAGD0
FLAGD2
VDD
DATA4
DATA5
DATA6
DATA7
GND
ADDR31
ADDR30
ADDR29
GND
DATA40
DATA41
CLKIN
RFSA1
RCLKA1
DRA1
TFSA1
TCLKA1
DTA1
GND
LB3ACK
LB3CLK
LB3DAT0
LB3DAT1
LB3DAT2
LB3DAT3
GND
GND
ADDR28
ADDR27
ADDR26
VDD
DATA8
DATA9
DATA10
DATA11
VDD
DATA42
DATA43
VDD
LD3ACK
LD3CLK
LD3DAT0
LD3DAT1
LD3DAT2
LD3DAT3
GND
FLAG1
EMU
DATA44
DATA45
DATA46
DATA47
GND
ADDR25
ADDR24
ADDR23
ADDR22
ADDR21
ADDR20
VDD
TIMEXPA
TIMEXPB
TIMEXPC
TIMEXPD
GND
DATA12
DATA13
DATA14
DATA15
GND
RFSB1
RCLKB1
DRB1
TFSB1
TCLKB1
DTB1
VDD
LB1ACK
LB1CLK
LB1DAT0
LB1DAT1
LB1DAT2
LB1DAT3
VDD
LD1ACK
LD1CLK
LD1DAT0
LD1DAT1
LD1DAT2
LD1DAT3
VDD
BR
BR
BR
BR
BR
BR
1
2
3
4
5
6
TDO
DATA16
DATA17
DATA18
DATA19
VDD
ADDR19
ADDR18
ADDR17
GND
TRST
TDI
RFSC1
RCLKC1
DRC1
TFSC1
TCLKC1
DTC1
TMS
LA4ACK
LA4CLK
LA4DAT0
LA4DAT1
LA4DAT2
LA4DAT3
TCK
PAGE
VDD
ADDR16
ADDR15
ADDR14
VDD
VDD
LC4ACK
LC4CLK
LC4DAT0
LC4DAT1
DATA20
DATA21
DATA22
DATA23
IRQ
IRQ
IRQ
DMAG
DMAG
ACK
A0
A1
A2
1
2
88
Rev. B | Page 29 of 48
AD14060/AD14060L
PIN FUNCTION DESCRIPTIONS
AD14060/AD14060L pin function descriptions are listed in
Table 22. Inputs identified as synchronous (S) must meet timing
requirements with respect to CLKIN (or with respect to TCK
for TMS, TDI). Inputs identified as asynchronous (A) can be
Unused inputs should be tied or pulled to VDD or GND, except
SW
internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,
TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS, and TDI)—
these pins can be left floating. These pins have a logic-level hold
circuit that prevents the input from floating internally.
for ADDR31-0, DATA47-0, FLAG2-0
,
, and inputs that have
TRST
asserted asynchronously to CLKIN (or to TCK for
).
Table 22. Pin Function Descriptions
Pin
Type1 Function
ADDR31-0
I/O/T
I/O/T
O/T
External Bus Address (common to all SHARCs). The AD14060/AD14060L outputs addresses for external memory
and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes on the
internal memory or IOP registers of slave ADSP-2106xs. The AD14060/AD14060L inputs addresses when a host
processor or multiprocessing bus master is reading or writing the internal memory or IOP registers of internal
ADSP-21060s.
External Bus Data (common to all SHARCs). The AD14060/AD14060L inputs and outputs data and instructions on
these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is transferred over Bits 47–16 of
the bus. 40-bit extended-precision floating-point data is transferred over Bits 47–48 of the bus. 16-bit short word
data is transferred over Bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over Bits 23–16. Pull-up
resistors on unused DATA pins are not necessary.
Memory Select Lines (common to all SHARCs). These lines are asserted (low) as chip selects for the corresponding
banks of external memory. Memory bank size must be defined in the individual ADSP-21060’s system control
registers (SYSCON). The MS3-0 lines are decoded memory address lines that change at the same time as the other
address lines. When no external memory access is occurring, the MS3-0 lines are inactive. They are active, however,
when a conditional memory access instruction is executed, whether or not the condition is true. MS0 can be used
with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system, the MS3-0 lines
are output by the bus master.
DATA47-0
MS3-0
RD
I/O/T
I/O/T
O/T
Memory Read Strobe (common to all SHARCs). This pin is asserted (low) when the AD14060/AD14060L reads from
external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices
(including other ADSP-2106xs) must assert RD to read from the AD14060/AD14060L’s internal memory. In a
multiprocessing system, RD is output by the bus master and is input by all other ADSP-2106xs.
WR
Memory Write Strobe (common to all SHARCs). This pin is asserted (low) when the AD14060/AD14060L writes to
external devices or when the internal memory of internal ADSP-2106xs is being accessed. External devices
(including other ADSP-2106xs) must assert WR to write to the AD14060/ AD14060L’s internal memory. In a
multiprocessing system, WR is output by the bus master and is input by all other ADSP-2106xs.
PAGE
DRAM Page Boundary. The AD14060/AD16060L asserts this pin to signal that an external DRAM page boundary has
been crossed. DRAM page size must be defined in the individual ADSP-21060’s memory control register (WAIT).
DRAM can be implemented only in external memory Bank 0. The PAGE signal can be activated only for Bank 0
accesses. In a multiprocessing system, PAGE is output by the bus master.
ADRCLK
SW
O/T
I/O/T
Clock Output Reference (common to all SHARCs). In a multiprocessing system, ADRCLK is output by the bus master.
Synchronous Write Select (common to all SHARCs). This signal is used to interface the AD14060/AD14060L to
synchronous memory devices (including other ADSP-2106xs). The AD14060/AD14060L asserts SW (low) to provide
an early indication of an impending write cycle, which can be aborted, if WR is not later asserted (for example, in a
conditional write instruction). In a multiprocessing system, SW is output by the bus master and is input by all other
ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW is asserted at the same time
as the address output. A host processor using synchronous writes must assert this pin when writing to the
AD14060/AD14060L.
ACK
I/O/S
Memory Acknowledge (common to all SHARCs). External devices can de-assert ACK (low) to add wait states to an
external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off comple-
tion of an external memory access. The AD14060/AD14060L de-asserts ACK, as an output, to add wait states to a
synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-2106x de-asserts the bus
master’s ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.
Rev. B | Page 30 of 48
AD14060/AD14060L
Pin
Type1 Function
SBTS
I/S
I/A
I/O
Suspend Bus Three-State (common to all SHARCs). External devices can assert SBTS (low) to place the external bus
address, data, selects, and strobes in a high impedance state for the following cycle. If the AD14060/AD14060L
attempts to access external memory while SBTS is asserted, the processor halts and the memory access does not
complete until SBTS is de-asserted. SBTS should be used only to recover from host processor/AD14060/AD14060L
deadlock, or used with a DRAM controller.
Host Bus Request (common to all SHARCs). Must be asserted by a host processor to request control of the
AD14060/AD14060L’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus
master relinquishes the bus and asserts HBG. To relinquish the bus, the ADSP-2106x places the address, data, select,
and strobe lines in a high impedance state. HBR has priority over all ADSP-2106x bus requests (BR6-1) in a
multiprocessing system.
HBR
HBG
Host Bus Grant (common to all SHARCs). Acknowledges an HBR bus request, indicating that the host processor can
take control of the external bus. HBG is asserted (held low) by the AD14060/AD14060L until HBR is released. In a
multiprocessing system, HBG is output by the ADSP-2106x bus master and is monitored by all others.
CSA
CSB
CSC
CSD
I/A
I/A
I/A
I/A
O
Chip Select. Asserted by host processor to select SHARC_A.
Chip Select. Asserted by host processor to select SHARC_B.
Chip Select. Asserted by host processor to select SHARC_C.
Chip Select. Asserted by host processor to select SHARC_D.
REDY
(O/D)
Host Bus Acknowledge (common to all SHARCs). The AD14060/AD14060L de-asserts REDY (low) to add wait states
to an asynchronous access of its internal memory or IOP registers by a host. Open-drain output (O/D) by default;
can be programmed in ADREDY bit of SYSCON register of individual ADSP-21060s to be active drive (A/D). REDY is
output only if the CS and HBR inputs are asserted.
BR6-1
I/O/S
I/S
Multiprocessing Bus Requests (common to all SHARCs). Used by multiprocessing ADSP-2106xs to arbitrate for bus
mastership. An ADSP-2106x drives only its own BRx line (corresponding to the value of its ID2-0 inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused BRx pins should be
pulled high; BR4-1 must not be pulled high or low, because they are outputs.
RPBA
Rotating Priority Bus Arbitration Select (common to all SHARCs). When RPBA is high, rotating priority for multi-
processor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system
configuration selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed
during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
CPAy (O/D) I/O
Core Priority Access (y = SHARC_A, B, C, D). Asserting its CPA pin allows the core processor of an ADSP-2106x bus
slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open-drain output that
is connected to all ADSP-2106xs in the system, if this function is required. The CPA pin of each internal ADSP-21060
is brought out individually. The CPA pin has an internal 5 kΩ pull-up resistor. If core access priority is not required in
a system, the CPA pin should be left unconnected.
DT0
DR0
O/T
I
Data Transmit (common Serial Ports 0 to all SHARCs, TDM). The DT pin has a 50 kΩ internal pull-up resistor.
Data Receive (common Serial Ports 0 to all SHARCs, TDM). The DR pin has a 50 kΩ internal pull-up resistor.
Transmit Clock (common Serial Ports 0 to all SHARCs, TDM). The TCLK pin has a 50 kΩ internal pull-up resistor.
Receive Clock (common Serial Ports 0 to all SHARCs, TDM). The RCLK pin has a 50 kΩ internal pull-up resistor.
Transmit Frame Sync (common Serial Ports 0 to all SHARCs, TDM).
Receive Frame Sync (common Serial Ports 0 to all SHARCs, TDM).
Data Transmit (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The DT pin has a 50 kΩ
internal pull-up resistor.
TCLK0
RCLK0
TFS0
RFS0
DTy1
I/O
I/O
I/O
I/O
O/T
DRy1
I
Data Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The DR pin has a 50 kΩ
internal pull-up resistor.
TCLKy1
RCLKy1
I/O
I/O
Transmit Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The TCLK pin has a 50 kΩ
internal pull-up resistor.
Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). The RCLK pin has a 50 kΩ
internal pull-up resistor.
TFSy1
RFSy1
FLAGy0
I/O
I/O
I/O/A
Transmit Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
Receive Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
Flag Pins (FLAG0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). Each pin is configured via control bits
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
Rev. B | Page 31 of 48
AD14060/AD14060L
Pin
Type1 Function
FLAG1
I/O/A
I/O/A
I/A
Flag Pins (FLAG1 common to all SHARCs). This pin is configured via control bits internal to individual ADSP-21060s
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
Flag Pins (FLAG2 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). Each pin is configured via control bits
as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals.
Interrupt Request Lines (individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D). Can be either edge-
triggered or level-sensitive.
FLAGy2
IRQy2-0
DMAR1
DMAR2
DMAG1
DMAG2
LyxCLK
I/A
DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
I/A
DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)2. Each LyxCLK pin has a 50 kΩ internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-20160.
O/T
O/T
I/O
LyxDAT3-0 I/O
Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)2. Each LyxDAT pin has a 50 kΩ internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-21060.
LyxACK
I/O
I
Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 3, 4)2. Each LyxACK pin has a 50 kΩ internal pull-
down resistor that is enabled or disabled by the LPDRD bit of the LCOM register of the ADSP-21060.
EPROM Boot Select (SHARC_A). When EBOOTA is high, SHARC_A is configured for booting from an 8-bit EPROM.
When EBOOTA is low, the LBOOTA and BMSA inputs determine booting mode for SHARC_A. See the following
table. This signal is a system configuration selection that should be hardwired.
EBOOTA
LBOOTA
BMSA
I
Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is low, SHARC_A is
configured for host processor booting or no booting. See the following table. This signal is a system configuration
selection that should be hardwired.
I/O/T3 Boot Memory Select. When this pin is an output, it is used as chip select for boot EPROM devices (when EBOOTA =
1, LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master. As an input, when low, this pin
indicates that no booting is to occur and that SHARC_A is to begin executing instructions from external memory.
See the following table. This input is a system configuration selection that should be hardwired.
EBOOTBCD
I
EPROM Boot Select (common to SHARC_B, SHARC_C, SHARC_D). When EBOOTBCD is high, SHARC_B, C, and D are
configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the LBOOTBCD and BMSBCD inputs
determine booting mode for SHARC_B, C, and D. See the following table. This signal is a system configuration
selection that should be hardwired.
LBOOTBCD
BMSBCD
I
LINK Boot (common to SHARC_B, SHARC_C, SHARC_D). When LBOOTBCD is high, SHARC_B, C, and D are configured
for link port booting. When LBOOTBCD is low, SHARC_B, C, and D are configured for host processor booting or no
booting. See the following table. This signal is a system configuration selection that should be hardwired.
I/O/T3 Boot Memory Select. When this pin is an output, it is used as chip select for boot EPROM devices (when EBOOTBCD
= 1, LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. As an input, when low, this pin
indicates that no booting is to occur and that SHARC_B, C, and D are to begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
EBOOT LBOOT BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
EPROM (connect BMS to EPROM chip select).
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
Host processor.
Link port.
No booting. Processor executes from external memory.
Reserved.
Reserved.
TIMEXPy
CLKIN
O
I
Timer Expired (individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D). Asserted for four cycles when
the timer is enabled and TCOUNT decrements to 0.
Clock In (common to all SHARCs). External clock input to the AD14060/AD14060L. The instruction cycle rate is equal
to CLKIN. CLKIN cannot be halted, changed, or operated below the minimum specified frequency.
RESET
I/A
Module Reset (common to all SHARCs). Resets the AD14060/AD14060L to a known state. This input must be
asserted (low) at power-up.
TCK
I
Test Clock (JTAG) (common to all SHARCs). Provides an asynchronous clock for JTAG boundary scan.
TMS
I/S
Test Mode Select (JTAG) (common to all SHARCs). Used to control the test state machine. TMS has a 20 kΩ internal
pull-up resistor.
Rev. B | Page 32 of 48
AD14060/AD14060L
Pin
Type1 Function
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A. TDI has a 20 kΩ
internal pull-up resistor.
TDO
TRST
O
I/A
Test Data Output (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.
Test Reset (JTAG) (common to all SHARCs). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the AD14060/AD14060L. TRST has a 20 kΩ internal pull-up resistor.
EMU (O/D)
O
Emulation Status (common to all SHARCs). Must be connected to the ADSP-2106x EZ-ICE target board connector
only.
VDD
GND
P
G
Power Supply. Nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices (26 pins).
Power Supply Return (28 pins).
FLAG3 is connected internally, common to SHARC_A, B, C, and D.
ID pins are hardwired internally as shown in Figure 1.
1 I = input; P = power supply; (A/D) = active drive; O = output; S = synchronous; (O/D) = open drain; G = ground; A = asynchronous; T = three-state, when
is
SBTS
asserted, or when the AD14060/AD14060L is a bus slave.
2 Link Ports 0, 2, and 5 are connected internally, as described in the Link Port I/O section.
3 Three-statable only in EPROM boot mode (when
is an output).
BMS
Rev. B | Page 33 of 48
AD14060/AD14060L
DETAILED DESCRIPTION
ARCHITECTURAL FEATURES
SHARED MEMORY MULTIPROCESSING
ADSP-21060 Core
The AD14060/AD14060L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs
are connected to maximize the performance of this cluster-of-
four architecture, and still allow for off-module expansion. The
AD14060/AD14060L in itself is a complete shared memory
multiprocessing system, as shown in Figure 22. The unified
address space of the SHARCs allows direct interprocessor
accesses of each SHARCs’ internal memory. In other words,
each SHARC can directly access the internal memory and IOP
registers of each of the other SHARCs by simply reading or
writing to the appropriate address in multiprocessor memory
space (see Figure 23)—this is called a direct read or direct write.
The AD14060/AD14060L is based on the powerful
ADSP-21060 (SHARC) DSP chip. The ADSP-21060 SHARC
combines a high performance floating-point DSP core with
integrated, on-chip system features, including a 4-Mbit SRAM
memory, host processor interface, DMA controller, serial ports,
and both link port and parallel bus connectivity for glueless
DSP multiprocessing (see Figure 21). It is fabricated in a high
speed, low power CMOS process, and has a 25 ns instruction
cycle time. The arithmetic/logic unit (ALU), multiplier, and
shifter all perform single-cycle instructions, and the three units
are arranged in parallel, maximizing computational throughput.
The SHARC features an enhanced Harvard architecture, in
which the data memory (DM) bus transfers data and the
program memory (PM) bus transfers both instructions and
data. An on-chip instruction cache selectively caches only those
instructions whose fetches conflict with the PM bus data
accesses. This combines with the separate program and data
memory buses to enable 3-bus operation for fetching an
instruction and two operands, all in a single cycle. The SHARC
also contains a general-purpose data register file, which is a
10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates
a variety of parallel operations for concise programming. For
example, the ADSP-21060 can conditionally execute a multiply,
an add, a subtract, and a branch, all in a single instruction.
Bus arbitration is accomplished with the on-SHARC arbitration
logic. Each SHARC has a unique ID, and drives the bus-request
(BR) line corresponding to its ID, while monitoring all others.
BR
BR
1 to 4 are used within the AD14060/AD14060L, while
BR
BR BR
5 and 6 can be used for expansion. All bus requests (
1
BR
to 6) are included in the module I/O. Two different priority
schemes, fixed and rotating, are available to resolve competing
bus requests. The RPBA pin selects which scheme is used. When
RPBA is high, rotating priority bus arbitration is selected; when
RPBA is low, fixed priority is selected.
Bus mastership is passed from one SHARC to another during a
bus transition cycle. A bus transition cycle occurs only when the
current bus master de-asserts its BR line and one of the slave
SHARCs asserts its BR line. The bus master can, therefore,
retain bus mastership by keeping its BR line asserted. When the
bus master de-asserts its BR line and no other BR line is
asserted, then the master does not lose any bus cycles. When
more than one SHARC asserts its BR line, the SHARC with the
highest priority request becomes bus master on the following
cycle. Each SHARC observes all the BR lines, and, therefore,
tracks when a bus transition cycle has occurred, and which
processor has become the new bus master. Master processor
changeover incurs only one cycle of overhead. Table 23 shows
an example of a bus transition sequence.
The SHARCs contain 4 Mbits of on-chip SRAM each, organized
as two blocks of 2 Mbits, which can be configured for different
combinations of code and data storage. The memory can be
configured as a maximum of 128k words of 32-bit data, 256k
words of 16-bit data, 80k words of 48-bit instructions (or 40-bit
data), or combinations of different word sizes up to 4 Mbits. A
16-bit floating-point storage format is supported, which
effectively doubles the amount of data that can be stored on-
chip. Conversion between the 32-bit floating-point and 16-bit
floating-point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
access by the core processor and I/O processor or DMA
controller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from the I/O, all
in a single cycle.
Table 23. Rotating Priority Arbitration Example
Hardware Processor IDs
Cycle
ID1
ID2
ID3
ID4
ID5
ID6
Priority
1
M
1
2 BR
3
4
5
Initial priority
assignments
2
3
4
5
4
5 BR
5 BR
M
M-BR
1
1
2
4
2
2
3
5
3
4
M
1
3
5 BR
1 BR
4 BR
M
2
3
Final priority
assignments
1–5 = Assigned priority.
M = Bus mastership (in that cycle).
BR = Requesting bus mastership with x.
BR
Rev. B | Page 34 of 48
AD14060/AD14060L
CORE PROCESSOR
DUAL-PORTED SRAM
INSTRUCTION
CACHE
TWO INDEPENDENT
DUAL-PORTED BLOCKS
JTAG
TIMER
7
32 x 48-BIT
TEST AND
EMULATION
PROCESSOR PORT
ADDR DATA
I/O PORT
DATA ADDR
ADDR
DATA
DATA
ADDR
DAG1
8 x 4 x 32 8 x 4 x 24
DAG2
PROGRAM
SEQUENCER
EXTERNAL
PORT
IOD
48
IOA
17
24
32
PM ADDRESS BUS
32
ADDR BUS
MUX
DM ADDRESS BUS
MULTIPROCESSOR
INTERFACE
PM DATA BUS
DM DATA BUS
48
BUS
CONNECT
(PX)
48
DATA BUS
MUX
40/32
HOST PORT
DATA
REGISTER
FILE
4
6
DMA
CONTROLLER
IOP
REGISTERS
(MEMORY MAPPED)
BARREL
SHIFTER
16 x 40-BIT
MULTIPLIER
ALU
SERIAL PORTS
(2)
6
CONTROL,
STATUS, AND
DATA BUFFERS
36
LINK PORTS
(6)
I/O PROCESSOR
Figure 21. ADSP-21060 Processor Block Diagram (Core of AD10460)
SYSTEM EXPANSION
SHARC_A
LINKS 1, 3, AND 4; LINKS 1, 3, AND 4;
IRQ IRQ
SHARC_B
1× CLOCK
CLKIN
RESET
RPBA
CPA
ADDR
DATA
31–0
;
;
2–0
47–0
RD
2–0
FLAGS 2 AND 0;
TIMEXP,
FLAGS 2 AND 0;
TIMEXP,
WR
SPORT1
SPORT1
ACK
MS
3-0
BOOTSELECT A
PAGE
BOOTSELECT BCD
SBTS
SW
AD14060/AD14060L
DMAR1, 2
DMAG1, 2
SPORT0
FLAG1
(QUAD PROCESSOR CLUSTER)
ADRCLK
CS
SHARC_D
LINKS 1, 3, AND 4; LINKS 1, 3, AND 4;
SHARC_C
HBR
HBG
IRQ
;
IRQ ;
2–0
2–0
REDY
FLAGS 2 AND 0;
FLAGS 2 AND 0;
TIMEXP,
SPORT1
TIMEXP,
SPORT1
JTAG
BR
1–6
Figure 22. Complete Shared Memory Multiprocessing System
Rev. B | Page 35 of 48
AD14060/AD14060L
0x0040 0000
0x0000 0000
0x0002 0000
0x0004 0000
0x0008 0000
IOP REGISTERS
INTERNAL
MEMORY SPACE
(INDIVIDUAL
BANK 0
MS
0
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
DRAM
(OPTIONAL)
SHARCs)
INTERNAL MEMORY SPACE
OF SHARC_A
BANK 1
BANK 2
MS
MS
MS
1
2
3
ID = 001
0x0010 0000
0x0018 0000
0x0020 0000
0x0028 0000
0x0030 0000
0x0038 0000
0x003F FFFF
INTERNAL MEMORY SPACE
OF SHARC_B
ID = 010
INTERNAL
TO AD14060
INTERNAL MEMORY SPACE
OF SHARC_C
ID = 011
EXTERNAL
MEMORY
SPACE
INTERNAL MEMORY SPACE
OF SHARC_D
MULTIPROCESSOR
MEMORY SPACE
ID = 100
BANK 3
INTERNAL MEMORY SPACE
OF ADSP-2106x
ID = 101
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD
OF SYSCON
INTERNAL MEMORY SPACE
OF ADSP-2106x
ID = 110
EXTERNAL
TO AD14060
REGISTER
BROADCAST WRITE
TO ALL
NONBANKED
ADSP-2106xs
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
0xFFFF FFFF
Figure 23. AD14060/AD14060L Memory Map
Bus locking is possible, allowing indivisible read-modify-write
sequences for semaphores. In either the fixed or rotating
priority scheme, it is also possible to limit the number of cycles
that the master can use to control the bus. The AD14060/
AD14060L provides the option of using the core priority access
(CPA) mode of the SHARC. Using the CPA signal allows
external bus accesses by the core processor of a slave SHARC to
take priority over ongoing DMA transfers. Also, each SHARC
can broadcast write to all other SHARCs simultaneously,
allowing the implementation of reflective semaphores.
OFF-MODULE MEMORY AND PERIPHERALS
INTERFACE
The AD14060/AD14060L’s external port provides the interface
to off-module memory and peripherals (see Figure 24). This
port consists of the complete external port bus of the SHARC,
bused in common among the four SHARCs.
The 4-gigaword off-module address space is included in the
ADSP-14060’s unified address space. Addressing of external
memory devices is facilitated by each SHARC internally
decoding the high-order address lines to generate memory-
bank select signals. Separate control lines are also generated for
simplified addressing of page-mode DRAM. The AD14060/
AD14060L also supports programmable memory wait states
and external memory acknowledge controls to allow interfacing
to DRAM and peripherals with variable access, hold, and
disable time requirements.
The bus master can communicate with slave SHARCs by
writing messages to their internal IOP registers. The MSRG0 to
MSRG7 registers are general-purpose registers that can be used
for convenient message passing, semaphores, and resource
sharing among the SHARCs. For message passing, the master
communicates with a slave by writing and/or reading any of the
eight message registers on the slave. For vector interrupts, the
master can issue a vector interrupt to a slave by writing the
address of an interrupt service routine to the slave’s VIRPT
register. This causes an immediate high priority interrupt on the
slave, which, when serviced, causes it to branch to the specified
service routine.
Rev. B | Page 36 of 48
AD14060/AD14060L
AD14060/
AD14060L
1x
CLOCK
ADDR
DATA
ADDR
31–0
CLKIN
DATA
47–0
GLOBAL
MEMORY
AND
RESET
RESET
RD
OE
PERIPHERALS
(OPTIONAL)
WR
WE
ACK
CS
RPBA
ACK
MS
3–0
BMS
PAGE
SBTS
CS
BOOT
EPROM
(OPTIONAL)
ADDR
DATA
CONTROL
SW
ADRCLK
CS
HBR
HOST
HBG
PROCESSOR
INTERFACE
(OPTIONAL)
REDY
ADDR
DATA
SERIALS
LINKS
CPA
5
5
5
BR
2–6
DISCRETES
BR
1
ADSP-2106x #5
(OPTIONAL)
CLKIN
ADDR
DATA
31–0
47–0
RESET
RPBA
3
101
ID
2–0
CONTROL
CPA
1–4, 6
BR
BR
5
ADSP-2106x #6
(OPTIONAL)
CLKIN
RESET
RPBA
ADDR
DATA
31–0
47–0
3
110
ID
2–0
CONTROL
CPA
BR
1–5
BR
6
Figure 24. Optional System Interconnections
Rev. B | Page 37 of 48
AD14060/AD14060L
LINK PORT I/O
SERIAL PORTS
Each individual SHARC features six 4-bit link ports that
facilitate SHARC-to-SHARC communication and external I/O
interfacing. Each link port can be configured for either 1× or 2×
operation, allowing each to transfer either four or eight bits
per cycle.
The SHARC serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices.
Each SHARC has two serial ports. The AD14060/AD14060L
provides direct access to Serial Port 1 of each SHARC. Serial
Port 0 is bused in common to each SHARC, and brought off-
module.
The link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.
The serial ports can operate at the full clock rate of the module,
providing each with a maximum data rate of 40 Mbit/s.
Independent transmit and receive functions provide more
flexible communications. Serial port data can be automatically
transferred to and from on-SHARC memory via DMA, and
each of the serial ports offers time-division-multiplexed (TDM)
multichannel mode.
The AD14060/AD14060L optimizes the link port connections
internally, and brings a total of 12 of the link ports off-module
for user-defined system connections. Internally, each SHARC
has a connection to the other three SHARCs with a dedicated
link port interface. Thus, each SHARC can directly interface
with its nearest and next-nearest neighbor. The remaining three
link ports from each SHARC are brought out independently
from each SHARC. A maximum of 480 MBytes/s link port
bandwidth is then available off of the AD14060/AD14060L.
The link port connections are shown in Figure 25.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits
to 32 bits. They offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
PROGRAM BOOTING
1
3
4
1
3
4
5
2
5
2
The AD14060/AD14060L supports automatic downloading of
programs following power-up or a software reset. The SHARC
offers the following options for program booting:
SHARC_A
SHARC_B
0
0
0
0
•
•
•
•
From an 8-bit EPROM
From a host processor
Through the link ports
No boot
1
3
4
1
3
4
2
5
2
5
SHARC_D
SHARC_C
In no-boot mode, the SHARC starts executing instructions
from Address 0x0040 0004 in external memory. The boot mode
BMS
is selected by the state of the following signals:
and LBOOT.
, EBOOT,
Figure 25. Link Port Connections
Link Port 4, the boot-link port, is brought off independently
from each SHARC. Individual booting is then allowed, or
chained link-port booting is possible, as described in the
Multiprocessor Link-Port Booting section.
On the AD14060/AD14060L, SHARC_A’s boot mode is sepa-
rately controlled, while SHARC_B, C, and D are controlled as a
group. With this flexibility, the AD14060/AD14060L can be
configured to boot using any of the following methods.
Link port data is packed into 32-bit or 48-bit words, and can be
directly read by the SHARC core processor or DMA transferred
to on-SHARC memory.
Multiprocessor Host Booting
To boot multiple ADSP-21060 processors from a host, each
BMS
ADSP-21060 must have its EBOOT, LBOOT, and
configured for host booting: EBOOT = 0, LBOOT = 0, and
BMS
pins
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
= 1. After system power-up, each ADSP-21060 is in the
BR
idle state and the x bus request lines are de-asserted. The
HBR
host must assert the
input and boot each ADSP-21060 by
asserting its CS pin and downloading instructions.
Rev. B | Page 38 of 48
AD14060/AD14060L
Multiprocessor EPROM Booting
HOST PROCESSOR INTERFACE
The following methods boot the multiprocessor system from an
EPROM:
The AD14060/AD14060L’s host interface allows easy connec-
tion to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. Asynchronous transfers
at speeds of up to the full clock rate of the module are sup-
ported. The host interface is accessed through the AD14060/
AD14060L external port and is memory-mapped into the
unified address space. Four channels of DMA are available for
the host interface; code and data transfers are accomplished
with low software overhead.
•
SHARC_A is booted, which then boots the others.
The EBOOT pin on the SHARC_A must be set high for
EPROM booting. All other ADSP-21060s should be
configured for host booting (EBOOT = 0, LBOOT = 0, and
BMS
= 1), which leaves them in the idle state at startup and
allows SHARC_A to become bus master and boot itself.
BMS
Only the
pin of SHARC_A is connected to the chip
The host processor requests the AD14060/AD14060L’s external
select of the EPROM. When SHARC_A has finished
booting, it can boot the remaining ADSP-21060s by writing
to their external port DMA Buffer 0 (EPB0) via multiproc-
essor memory space.
HBR
HBG
bus with the host bus request (
), host bus grant (
), and
ready (REDY) signals. The host can directly read and write the
internal memory of the SHARCs, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
•
All ADSP-21060s boot in turn from a single EPROM.
DIRECT MEMORY ACCESS (DMA) CONTROLLER
BMS
The
signals from each ADSP-21060 can be wire-OR’ed
The SHARCs’ on-chip DMA control logic allows zero-overhead
data transfers without processor intervention. The DMA
controller operates independently and invisibly to each
SHARC’s processor core, allowing DMA operations to occur
while the core is simultaneously executing its program
instructions.
together to drive the chip select pin of the EPROM. Each
ADSP-21060 can boot in turn, according to its priority.
When the last one has finished booting, it must inform the
others (which can be in the idle state) that program
execution can begin.
Multiprocessor Link-Port Booting
DMA transfers can occur between SHARC internal memory
and either external memory, external peripherals, or a host
processor. DMA transfers can also occur between the SHARC’s
internal memory and its serial ports or link ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32- or
48-bit words is performed during DMA transfers.
Booting can also be accomplished from a single source through
the link ports. Link Buffer 4 must always be used for booting. To
simultaneously boot all the ADSP-21060s, a parallel common
connection is available through Link Port 4 on each of the
processors. Or, using the daisy-chain connection that exists
between the processors’ link ports, each ADSP-21060 can boot
the next one in turn. In this case, the link assignment register
(LAR) must be programmed to configure the internal link ports
with Link Buffer 4.
Ten channels of DMA are available on the SHARCs: two via the
link ports, four via the serial ports, and four via the processor’s
external port (for either host processor, other SHARCs,
memory, or I/O transfers). Four additional link port DMA
channels are shared with Serial Port 1 and the external port.
Programs can be downloaded to the SHARCs using DMA
transfers. Asynchronous off-module peripherals can control two
Multiprocessor Booting from External Memory
If external memory contains a program after reset, then
SHARC_A should be set up for no-boot mode. It begins execut-
ing from Address 0x0040 0004 in external memory. When
booting has completed, the other ADSP-21060s can be booted
by SHARC_A, if they are set up for host booting; or they can
begin executing out of external memory, if they are set up for
no-boot mode. Multiprocessor bus arbitration allows this
booting to occur in an orderly manner.
DMAR
DMA channels using DMA request/grant lines (
DMAG
1-2,
1-2). Other DMA features include interrupt generation
upon completion of DMA transfers and DMA chaining for
automatic linked DMA transfers.
Rev. B | Page 39 of 48
AD14060/AD14060L
APPLICATIONS
The HP USB-based emulator supports the background
telemetry channel (BTC), a nonintrusive method for exchang-
ing data between the host and target application without
affecting the target system's real-time characteristics. Nonintru-
sive in-circuit emulation is assured by the use of the processor’s
JTAG interface. The emulator does not affect target system
loading or timing.
DEVELOPMENT TOOLS
The AD14060/AD14060L is supported with a complete set of
software and hardware development tools, including an
in-circuit emulator and development software.
Analog Devices, Inc. (ADI) uses VisualDSP++®, which is an
easy-to-use integrated software development and debugging
environment (IDDE) that efficiently manages projects from
start to finish from within a single interface.
Further details and ordering information are available on the
analog.com Web site.
The ADSP-21262 EZ-KIT LITE™ provides developers with a
cost-effective method for initial evaluation of the ADSP-2106x
SHARC processor architecture for applications via a USB-based
PC-hosted tool set. With this EZ-KIT LITE, users can learn
about ADI’s ADSP-2106x hardware and software development
and can quickly prototype applications.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family.
Hardware tools include SHARC PC plug-in cards, multi-
processor SHARC VME boards, and daughter card modules
with multiple SHARCs and additional memory. These modules
are based on the SHARCPAC module specification. Third-party
software tools include an Ada compiler, DSP libraries, operating
systems, and block diagram design tools.
The EZ-KIT LITE includes an ADSP-2106x processor desktop
evaluation board, along with an evaluation suite of the
VisualDSP++ development and debugging environment with
the C/C++ compiler, assembler, and linker. VisualDSP++
development and debugging software, along with the USB-
based debugger interface, enables users to perform standard
debugging functions (such as read and write memory, read and
write registers, load and execute executables, set and clear
breakpoints, and single-step assembly, C, and C++ source
code).
QUAD-SHARC DEVELOPMENT BOARD
The BlackTip-MCM, AD14060 development board with
software is available from Bittware Research Systems, Inc. This
board has one AD14060 BITSI interface, and PROM and SRAM
expansion options on an ISA card. It is supported by Bittware’s
SHARC software development package. To contact Bittware,
call 1-800-848-0436.
The ADI cost-effective universal serial bus (USB)-based
emulator and high performance (HP) universal serial bus
(USB)-based emulator each provide an easy, portable, non-
intrusive, target-based debugging solution for ADI JTAG
processors and DSPs. These powerful USB-based emulators
perform a wide range of emulation functions, including single-
step and full speed execution with predefined breakpoints, and
viewing and altering of register and memory contents. With the
ability to automatically detect and support multiple I/O
voltages, the USB and HP USB emulators enable users to
communicate with all the ADI JTAG processors and DSPs
using either a full speed USB 1.1 or high speed USB 2.0 port on
the host PC. Applications and data can be easily and rapidly
tested and transferred between the emulators and the separately
available VisualDSP++ development and debugging environ-
ment (sold separately).
OTHER PACKAGE DETAILS
The AD14060/AD14060L contains 16 on-module 0.018 µF
bypass capacitors. It is recommended that, in the target system,
at least four additional capacitors of 0.018 µF value be placed
around the module, one near each of the four corners.
The top surface (lid) of the AD14060/AD14060L is electrically
connected to GND on the industrial and military grade parts.
TARGET BOARD CONNECTOR FOR EMULATOR
PROBE
The ADSP-2106x emulator uses the IEEE 1149.1 JTAG test
access port of the ADSP-2106x to monitor and control the
target board processor during emulation. The emulator probe
requires that the AD14060/AD14060L’s CLKIN (optional), TMS,
TRST
EMU
TCK,
, TDI, TDO,
, and GND signals be made
The plug-and-play architecture of the USB allows the host
operating system to automatically detect and configure the
emulators. The USB can be connected to and disconnected
from the host without opening the PC or turning off the power
to the PC. A 3-meter cable is included to connect the emulators
to the host PC, providing abundant accessibility to hard-to-
reach targets.
accessible on the target system via a 14-pin connector (pin strip
header) similar to Figure 26. The emulator probe plugs directly
into this connector for chip-on-board emulation. You must add
this connector to your target board design, if you intend to use
the ADSP-2106x emulator. The length of the traces between the
connector and the AD14060/AD14060L’s JTAG pins should be
as short as possible.
Rev. B | Page 40 of 48
AD14060/AD14060L
Table 24. JTAG Signals
Signal Termination
1
2
GND
KEY (NO PIN)
BTMS
EMU
TMS
TCK
Driven through 22 Ω resistor (16 µA to 3.2 µA driver).
Driven at 10 MHz through 22 Ω resistor (16 µA to 3.2 µA
driver).
3
5
4
6
CLKIN (OPTIONAL)
Driven by open-drain driver1 (pulled up by on-chip
20 kΩ resistor).
TMS
TCK
TRST
TDI
TRST
7
9
8
BTCK
TDI
TDO
Driven by 16 µA to 3.2 µA driver.
One TTL load, no termination.
10
12
BTRST
9
CLKIN One TTL load, no termination (optional signal).
11
EMU
4.7 kΩ pull-up resistor, one TTL load (open-drain
output from ADSP-2106x).
BTDI
______________________________________
13
14
1
is driven low until the emulator probe is turned on by the emulator
TRST
GND
TDO
software (after the invocation command).
TOP VIEW
Connecting CLKIN to Pin 4 of the emulator header is optional.
The emulator uses CLKIN only when directed to perform
operations such as starting, stopping, and single-stepping
multiple ADSP-2106xs in a synchronous manner. If these
operations do not need to occur synchronously on the multiple
processors, tie Pin 4 of the emulator header to ground.
Figure 26. Target Board Connector for ADSP-2106x Emulator
(Jumpers in Place)
The 14-pin, 2-row pin-strip header is keyed at the Pin 3 loca-
tion; Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 inch × 0.1 inch. Pin strip headers are available
from vendors such as 3M, McKenzie, and Samtec.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the AD14060/
AD14060L and the CLKIN pin on the emulator header must be
minimal. If the skew is too large, synchronous operations might
be off by one cycle between processors. For synchronous multi-
BTRST
The BTMS, BTCK,
, and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the other pins, as shown in
Figure 26. If you are not going to use the test access port for
EMU
processor operation, TCK, TMS, CLKIN, and
should be
treated as critical signals in terms of skew, and should be laid
out as short as possible on the board.
BTRST
board testing, tie
to GND and tie or pull up BTCK to
pin must be asserted after power-up (through
on the connector) or held low for proper operation of
If TCK, TMS, and CLKIN are driving a large number of
ADSP-2106x’s (more than eight) in the system, treat them as a
clock tree using multiple drivers to minimize skew. (See the
ADSP-2106x User’s Manual for details).
TRST
VDD. The
BTRST
the AD14060/AD14060L. None of the Bxxx pins (Pins 5, 7, 9,
11) are connected on the emulator probe.
If synchronous multiprocessor operations are not needed
(CLKIN is not connected), use appropriate parallel termination
The JTAG signals are terminated on the emulator probe as
listed in Table 24.
EMU
TRST
on TCK and TMS. Note that TDI, TDO,
not critical signals in terms of skew.
, and
are
Figure 27 shows JTAG scan path connections for the
multiprocessor system.
Rev. B | Page 41 of 48
AD14060/AD14060L
SHARC_A
SHARC_B
SHARC_C
SHARC_D
JTAG DEVICE
(OPTIONAL)
ADSP-2106x
#n
TDI
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
EMULATOR
JTAG
CONNECTOR
OTHER JTAG
CONTROLLER
TCK
TMS
EMU
TRST
TDO
CLKIN
OPTIONAL
Figure 27. JTAG Scan Path Connections for the AD14060/AD14060L
TDI TDO
TDI TDO
TDI TDO
5kΩ
1
TDI TDO
TDI TDO
TDI TDO
5kΩ
TDI
EMU
1
TCK
TMS
TRST
TDO
SYSTEM
CLKIN
CLKIN
EMU
1
OPEN-DRAIN DRIVER OR EQUIVALENT, THAT IS:
Figure 28. JTAG Clock Tree for Multiple ADSP-2106x Systems
OUTPUT DRIVE CURRENTS
POWER DISSIPATION
Figure 29 shows typical I-V characteristics for the output
drivers of the ADSP-2106x. The curves represent the current
drive capability of the output drivers as a function of output
voltage.
Total power dissipation has two components, one due to
internal circuitry and one due to the switching of external
output drivers. Internal power dissipation is dependent on the
instruction execution sequence and the data operands involved.
Internal power dissipation is calculated as follows:
120
100
PINT = IDDIN × VDD
HIGH LEVEL DRIVE
80
(P DEVICE)
60
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on the
following:
40
20
0
–20
–40
–60
–80
•
•
•
•
Number of output pins that switch during each cycle (O)
Maximum frequency at which they can switch (f)
Load capacitance (C)
LOW LEVEL DRIVE
–100
(N DEVICE)
–120
–140
–160
Voltage swing (VDD
)
0
1
2
3
4
5
SOURCE VOLTAGE (V)
and is calculated by
EXT = O × C × VDD2 × f
Figure 29. ADSP-2106x Typical Drive Currents (VDD = 5 V)
P
Rev. B | Page 42 of 48
AD14060/AD14060L
The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2 tCK). The write strobe
can switch every cycle at a frequency of 1/tCK. Select pins switch
at 1/(2 tCK), but selects can switch on each cycle.
The output disable time, tDIS, is the difference between tMEASURED
and tDECAY, as shown in Figure 30. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays ΔV from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and IL,
and with ΔV equal to 0.5 V.
Example
Output Enable Time
Estimate PEXT with the following assumptions: a system with
one bank of external data memory RAM (32-bit);
four 128k × 8 RAM chips are used, each with a load of 10 pF;
external data memory writes occur every other cycle; a rate of
1/(4 tCK) with 50% of the pins switching; and an instruction
cycle rate is 40 MHz (tCK = 25 ns) and VDD = 5.0 V.
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time, tENA, is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the output enable/disable diagram (Figure 30). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
The PEXT equation is calculated for each class of pins that can
drive, as shown in Table 25.A typical power consumption can
now be calculated for these conditions by adding a typical
internal power dissipation:
System Hold Time Calculation Example
To determine the data output hold time in a particular system,
first calculate tDECAY using the previous equation. Choose ΔV to
be the difference between the ADSP-2106x’s output voltage and
the input threshold for the device requiring the hold time. A
typical ΔV is 0.4 V. CL is the total bus capacitance per data line,
and IL is the total leakage or three-state current per data line.
The hold time is tDECAY plus the minimum disable time (tHDWD
for the write cycle).
P
TOTAL = PEXT + (IDDIN2 × 5.0 V)
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all 1s to
all 0s. It is uncommon for an application to have 100% or even
50% of the outputs switching simultaneously.
TEST CONDITIONS
Output Disable Time
REFERENCE
SIGNAL
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by ΔV is dependent on the capacitive load, CL, and
the load current, IL. This decay time can be approximated by the
following equation:
tMEASURED
tDIS
tENA
V
OH (MEASURED)
V
V
OH (MEASURED)
OL (MEASURED)
V
V
– ∆V
+ ∆V
2.0V
1.0V
OH (MEASURED)
OL (MEASURED)
V
OL (MEASURED)
tDECAY
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
CL ∆ V
tDECAY
=
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
IL
APPROXIMATELY 1.5V
Figure 30. Output Enable/Disable
Table 25. PEXT Calculations
2
Pin Type
Address
MSO
Number of Pins
% Switching
× C
× f
× VDD
= PEXT
15
1
50
0
× 55 pF
× 55 pF
× 55 pF
× 25 pF
× 15 pF
× 20 MHz
× 20 MHz
× 40 MHz
× 20 MHz
× 40 MHz
× 25 V
× 25 V
× 25 V
× 25 V
× 25 V
= 0.206 W
= 0.00 W
= 0.055 W
= 0.200 W
= 0.015 W
WR
1
–
Data
ADRCLK
32
1
50
–
PEXT (5 V) = 0.476 W.
PEXT (3.3 V) = 0.207 W.
Rev. B | Page 43 of 48
AD14060/AD14060L
3.5
3.0
2.5
2.0
1.5
1.0
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 31). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figure 33 and
Figure 34 show how output rise time varies with capacitance.
Figure 35 graphically shows how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the Output Disable Time
section.) The graphs in Figure 33, Figure 34, and Figure 35
might not be linear outside the ranges shown.
2.9
1.6
RISE TIME
FALL TIME
0.6
0.5
0
I
OL
0
20
40
60
80
100 120 140 160 180 200
LOAD CAPACITANCE (pF)
Figure 34. Typical Output Rise Time (0.8 V to 2.0 V)
vs. Load Capacitance (VDD = 5 V)
TO OUTPUT
PIN
1.5V
5.0
4.0
50pF
4.5
I
OH
3.0
Figure 31. Equivalent Device Loading for AC Measurement
(Includes All Fixtures)
2.0
1.0
INPUT OR
OUTPUT
1.5V
1.5V
NOMINAL
Figure 32. Voltage Reference Levels for AC Measurements
(except Output Enable/Disable)
–0.7
–1.0
25
50
75
100
125
150
175
200
LOAD CAPACITANCE (pF)
16.0
Figure 35. Typical Output Delay or Hold vs. Load Capacitance
at Maximum Case Temperature (VDD = 5 V)
14.7
14.0
12.0
10.0
8.0
18
16
14
RISE TIME
Y = 0.0796X + 1.17
12
7.4
FALL TIME
6.0
10
RISE TIME
8
4.0
3.7
Y = 0.0467X + 0.55
6
2.0
1.1
4
2
0
FALL TIME
0
0
20
40
60
80
100 120 140 160 180 200
LOAD CAPACITANCE (pF)
Figure 33. Typical Output Rise Time (10% to 90% VDD
vs. Load Capacitance (VDD = 5 V)
)
0
20
40
60
80
100 120 140 160 180 200
LOAD CAPACITANCE (pF)
Figure 36. Typical Output Rise Time (10% to 90% VDD
vs. Load Capacitance (VDD = 3.3 V)
)
Rev. B | Page 44 of 48
AD14060/AD14060L
9
8
7
6
5
4
3
2
1
0
Trim/form can be accomplished with a universal trim/form,
a customer-designed trim/form, or with the Analog Devices
developed tooling described as follows.
A trim/form tool specific to the AD14060/AD14060L has been
developed and is available for use by all parties at
Y = 0.0391X + 0.36
Tintronics Industries
2122-A Metro Circle
Huntsville, AL 35801
256-650-0220
Y = 0.0305X + 0.24
RISE TIME
FALL TIME
Contact Person: Tom Rice
0
20
40
60
80
100 120 140 160 180 200
The package outline and dimensions resulting from this tool are
shown in Figure 39. (Alternatively, the package can be
trimmed/formed for cavity-down placement.)
LOAD CAPACITANCE (pF)
Figure 37. Typical Output Rise Time (0.8 V to 2.0 V)
vs. Load Capacitance (VDD = 3.3 V)
5.0
4.5
0.170
(4.318)
4.0
3.0
2.110 (53.59)
Y = 0.0329X – 1.65
2.210 ± 0.010 (56.134 ± 0.254)
2.0
1.0
0.016 MIN
NOMINAL
–0.7
–1.0
25
50
75
100
125
150
175
200
LOAD CAPACITANCE (pF)
Figure 38. Typical Output Delay or Hold vs. Load Capacitance
at Maximum Case Temperature (VDD = 3.3 V)
0° TO 8°
0 TO 10 MILS
DETAIL A
ASSEMBLY RECOMMENDATIONS
Socket Information
Standard sockets and carriers are available for the
AD14060/AD14060L, if needed. Socket part number
IC53-3084-262 and carrier part number ICC-308-1 are
available from Yamaichi Electronics.
Figure 39. Package and Lead Profile
Dimensions shown in inches and (millimeters)
Trim and Form
The AD14060/AD14060L is shipped as shown in Figure 43 with
untrimmed and unformed leads and with the nonconductive tie
bar in place. This avoids disturbance of lead spacing and
coplanarity prior to assembly. Optimally, the leads should be
trimmed, formed, and solder-dipped just prior to placement on
the board.
Rev. B | Page 45 of 48
AD14060/AD14060L
Thermal Characteristics
PCB LAYOUT GUIDELINES
The AD14060/AD14060L is packaged in a 308-lead ceramic
quad flatpack (CQFP). The package is optimized for thermal
conduction through the core (base of the package) down to the
mounting surface. The AD14060/AD14060L is specified for a
case temperature (TCASE). Design of the mounting surface and
attachment material should be such that TCASE is not exceeded.
The drawing in Figure 40 assumes that the trim/form tooling
described previously is used. These recommendations are
provided for user convenience and are PCB layout guidelines
only, based on standard practice. PCB pad footprint geometries
and placement are illustrated.
2.260 (57.404) 4 PLACES
2.060 (52.324) 4 PLACES
1.9000 (48.26) 4 PLACES
θJC = 0.36°C/W
Thermal Cross-Section
The following data, together with the detailed mechanical
drawings in Figure 43, allows the designer to construct simple
thermal models for further analysis within targeted systems.
The top layer of the package, where the die are mounted, is a
metal VDD layer. The approximate metal area coverage from the
metal planes and routing layers is estimated in Table 27. The
layers are shown in Figure 41.
0.015
(0.381)
THIS IS A PC BOARD COMPONENT FOOTPRINT,
NOT THE PACKAGE OUTLINE.
0.025
(0.635)
Table 26. Thermal Conductivity
Material
Thermal Conductivity (W/cm°C)
Ceramic
Kovar™
Tungsten
Thermoplastic
Silicon
0.18
0.14
1.78
0.03
1.45
0.025 (0.635) MIN
0.025 (0.635) MIN
Table 27. Metal Coverage per Layer
Layer
% Metal (1 Mil Thick)
Figure 40. PC Board Component Footprint
Dimensions shown in inches and (millimeters)
VDD
88
16
14
91
15
13
95
SIG2
SIG3
GND
SIG4
SIG5
BASE
KOVAR LID
0.015 MILS
KOVAR SEAL RING
HEIGHT = 50 MILS
SURFACE
SILICON DIE
19 MILS
THERMOPLASTIC
THICKNESS 5 MILS
CERAMIC LAYER 28 MILS
CERAMIC LAYER 6 MILS
CERAMIC LAYER 6 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
CERAMIC LAYER 10 MILS
V
DD
SIG2
SIG3
GND
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
CERAMIC LAYER 10 MILS
CERAMIC LAYER 4 MILS
SIG4
SIG5
BASE
Figure 41. Co-Fired Packaged Profile
Rev. B | Page 46 of 48
AD14060/AD14060L
MECHANICAL CHARACTERISTICS
Lid Deflection Analysis
Table 28. External Pressure Reduction
Deflection
Δ Pressure
12 psi
15 psi
10.0 mil
11.9 mil
0.670
4X
0.653
4X
Mechanical Model
0.302
2.050 SQ.
The following data, together with the detailed mechanical
drawings in Figure 43, allows the designer to construct simple
mechanical models for further analysis within targeted systems.
0.616
0.633
Table 29. Mechanical Properties
Material
Ceramic
Kovar
Tungsten
Thermoplastic
Silicon
Modulas of Elasticity
26 × 103 kg/mm2
14.1 × 103 kg/mm2
35 × 103 kg/mm2
279 kg/mm2
0.260
0.250
0.345
1.890 ± 0.005
1.810 ± 0.005
1.780 ± 0.018
11 × 103 kg/mm2
ADDITIONAL INFORMATION
0.040 ± 0.002
0.012 REF
4X
This data sheet provides a general overview of the AD14060/
AD14060L architecture and functionality. For detailed
information on the ADSP-2106x SHARC and the ADSP-21000
Family core architecture and instruction set, refer to the
ADSP-2106x SHARC User’s Manual.
Figure 42. Internal Package Dimensions
Dimensions shown in inches
Rev. B | Page 47 of 48
AD14060/AD14060L
OUTLINE DIMENSIONS
3.050 (77.47) MAX
3.01 (76.46)
3.00 (76.20)
2.99 (75.95)
2.745 (69.72)
2.730 (69.34)
2.715 (68.96)
2.062 (52.38)
2.050 (52.07)
2.038 (51.77)
0.350 (8.89)
0.340 (8.64)
0.330 (8.38)
4×
0.015 (0.381) × 45°
3 PLACES
231
232
155
154
0.010 (0.254)
0.008 (0.203)
0.006 (0.152)
2.330 (59.18)
2.300 (58.42)
2.270 (57.66)
TOP VIEW
0.025 (0.635)
BSC
308
78
1
77
0.040 (1.016) × 45°
0.007 (0.165)
0.005 (0.127)
0.004 (0.102)
1.895 (48.13)
1.890 (48.01)
1.885 (47.88)
0.101 (2.566)
0.092 (2.337)
0.083 (2.108)
0.035 (0.889)
MAX
0.160 (4.064)
MAX
Figure 43. 308-Lead Ceramic Quad Flatpack (CQFP)
(QS-308)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Temperature
Range
Instruction Operating
Package
Option
Model
SMD
N/A
N/A
Rate
Voltage
Package Description
AD14060BF-4
AD14060LBF-4
−40°C to +100°C
−40°C to +100°C
40 MHz
40 MHz
5 V
3.3 V
308-Lead Ceramic Quad Flatpack (CQFP)
308-Lead Ceramic Quad Flatpack (CQFP)
QS-308
QS-308
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00667–0–12/04(B)
Rev. B | Page 48 of 48
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