AD1853JRSZ [ADI]
Stereo, 24-Bit, 192 kHz, Multibit DAC; 立体声， 24位， 192千赫，多位?? DAC
| 型号： | AD1853JRSZ |
| 厂家： | 
ADI |
| 描述： | Stereo, 24-Bit, 192 kHz, Multibit DAC |
| 文件： | 总16页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Stereo, 24-Bit, 192 kHz, Multibit ꢀꢁ DAC
AD1853
FEATURES
APPLICATIONS
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 192 kHz Sample Rate
Hi End: DVD, CD, Home Theater Systems, Automotive
Audio Systems, Sampling Musical Keyboards, Digital
Mixing Consoles, Digital Audio Effects Processors
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz
Multibit Sigma-Delta Modulator with “Perfect Differential
Linearity Restoration” for Reduced Idle Tones and
Noise Floor
Data Directed Scrambling DAC—Least Sensitive to Jitter
Differential Output for Optimum Performance
120 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Mono)
117 dB Signal to Noise (Not Muted) at 48 kHz
(A-Weighted Stereo)
119 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Mono)
PRODUCT OVERVIEW
The AD1853 is a complete high performance single-chip stereo
digital audio playback system. It is comprised of a high per-
formance digital interpolation filter, a multibit sigma-delta
modulator, and a continuous-time current-out analog DAC
section. Other features include an on-chip clickless stereo at-
tenuator and mute capability, programmed through an SPI-
compatible serial control port. The AD1853 is fully compatible
with all known DVD formats and supports 48 kHz, 96 kHz and
192 kHz sample rates with up to 24 bits word lengths. It also
provides the “Redbook” standard 50 µs/15 µs digital de-emphasis
filters at sample rates of 32 kHz, 44.1 kHz and 48 kHz.
116 dB Dynamic Range (Not Muted) at 48 kHz Sample
Rate (A-Weighted Stereo)
–107 dB THD+N (Mono Application Circuit, See Figure 30)
–104 dB THD+N (Stereo)
115 dB Stopband Attenuation (96 kHz)
On-Chip Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Interpolation Factor, Volume, Mute, De-Emphasis, Reset
Digital De-Emphasis Processing for 32, 44.1 and 48 kHz
Sample Rates
The AD1853 has a very flexible serial data input port that
allows for glueless interconnection to a variety of ADCs, DSP
chips, AES/EBU receivers and sample rate converters. The
AD1853 can be configured in left-justified, I2S, right-justified,
or DSP serial port compatible modes. The AD1853 accepts
serial audio data in MSB first, twos complement format.
The AD1853 operates from a single +5 V power supply. It is
fabricated on a single monolithic integrated circuit and is housed in
a 28-lead SSOP package for operation over the temperature
range 0°C to +70°C.
Clock Auto-Divide Circuit Supports Five Master-Clock
Frequencies
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
28-Lead SSOP Plastic Package
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
SUPPLY
CLOCK
IN
CONTROL DATA
INPUT
INT2ꢂ INT4ꢂ
VOLUME
MUTE
2
3
VOLTAGE
REFERENCE
AUTO-CLOCK
DIVIDE CIRCUIT
SERIAL CONTROL
INTERFACE
AD1853
8 ꢂ F
INTERPOLATOR
MULTIBIT SIGMA-
DIGITAL
ATTEN/
MUTE
S
IDAC
DELTA MODULATOR
DATA INPUT
SERIAL
ANALOG
OUTPUTS
DATA
INTERFACE
2
SERIAL
MODE
MULTIBIT SIGMA-
DELTA MODULATOR
8 ꢂ F
ATTEN/
MUTE
S
IDAC
INTERPOLATOR
2
ANALOG
2
MUTE
DE-EMPHASIS
ZERO
FLAG
RESET
SUPPLY
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD1853–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD
Ambient Temperature
Input Clock
)
+5.0 V
+25°C
24.576 MHz (512 × FS Mode)
996.094 kHz
–0.5 dB Full Scale
48 kHz
Input Signal
Input Sample Rate
Measurement Bandwidth
Word Width
20 Hz to 20 kHz
20 Bits
Input Voltage HI
Input Voltage LO
3.5 V
0.8 V
ANALOG PERFORMANCE (See Figures)
Min
Typ
Max
Units
Resolution
24
Bits
Signal-to-Noise Ratio (20 Hz to 20 kHz)
No Filter (Stereo)
114
117
117
120
dB
dB
dB
dB
No Filter (Mono—See Figure 30)
With A-Weighted Filter (Stereo)
With A-Weighted Filter (Mono—See Figure 30)
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter (Stereo)
No Filter (Mono—See Figure 30)
With A-Weighted Filter (Stereo)
With A-Weighted Filter (Mono—See Figure 30)
Total Harmonic Distortion + Noise (Stereo)
107.5
110
113
116
116
119
–104
0.00063
–107
0.00045
dB
dB
dB
dB
dB
%
–94
Total Harmonic Distortion + Noise (Mono—See Figure 30)
Analog Outputs
dB
%
Differential Output Range ( Full Scale w/1 mA into IREF
Output Capacitance at Each Output Pin
Out-of-Band Energy (0.5 × FS to 75 kHz)
CMOUT
)
3.0
mA p-p
pF
dB
30
–90
2.75
V
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Mute Attenuation
3.0
0.01
25
–125
0.1
%
dB
ppm/°C
dB
Degrees
dB
dB
–0.15
+0.15
0.1
–100
De-Emphasis Gain Error
NOTES
Single-ended current output range: 1 mA
0.75 mA.
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
DIGITAL I/O (+25ꢃC–AVDD, DVDD = +5.0 V ꢄ 10%)
Min
Typ
Max
Units
Input Voltage HI (VIH)
Input Voltage LO (VIL)
Input Leakage (IIH @ VIH = 3.5 V)
Input Leakage (IIL @ VIL = 0.8 V)
Input Capacitance
Output Voltage HI (VOH
Output Voltage LO (VOL
2.4
V
V
µA
µA
pF
V
0.8
10
10
20
)
)
DVDD–0.5 DVDD–0.4
0.2
0.5
V
Specifications subject to change without notice.
–2–
REV. A
AD1853
POWER
Min
Typ
Max
Units
Supplies
Voltage, Analog and Digital
Analog Current
Digital Current
4.5
5
12
28
5.5
15
33
V
mA
mA
Dissipation
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
200
60
140
mW
mW
mW
–77
–72
dB
dB
Specifications subject to change without notice.
TEMPERATURE RANGE
Min
Typ
Max
Units
Specifications Guaranteed
Functionality Guaranteed
Storage
25
°C
°C
°C
0
–55
70
125
Specifications subject to change without notice.
DIGITAL FILTER CHARACTERISTICS
Sample Rate (kHz)
Passband (kHz)
Stopband (kHz)
Stopband Attenuation (dB)
Passband Ripple (dB)
44.1
48
96
DC–20
24.1–328.7
26.23–358.28
56.9–327.65
117–327.65
110
110
115
95
0.0002
0.0002
0.0005
+0/–0.04 (DC–21.8 kHz)
+0/–0.5 (DC–65.4 kHz)
+0/–1.5 (DC–87.2 kHz)
DC–21.8
DC–39.95
DC–87.2
192
Specifications subject to change without notice.
GROUP DELAY
Chip Mode
Group Delay Calculation
FS
Group Delay
Units
INT8x Mode
INT4x Mode
INT2x Mode
5553/(128 × FS)
5601/(64 × FS)
5659/(32 × FS)
48 kHz
96 kHz
192 kHz
903.8
911.6
921
µs
µs
µs
Specifications subject to change without notice.
DIGITAL TIMING (Guaranteed Over 0ꢃC to +70ꢃC, AVDD = DVDD = +5.0 V ꢄ 10%)
Min
Units
tDMP
tDML
tDMH
tDBH
tDBL
tDBP
tDLS
tDLH
tDDS
tDDH
tPDRP
MCLK Period (With FMCLK = 256 × FLRCLK)*
MCLK LO Pulsewidth (All Modes)
MCLK HI Pulsewidth (All Modes)
BCLK HI Pulsewidth
BCLK LO Pulsewidth
BCLK Period
LRCLK Setup
LRCLK Hold (DSP Serial Port Mode Only)
SDATA Setup
SDATA Hold
PD/RST LO Pulsewidth
54
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.4 × tDMP
0.4 × tDMP
20
20
140
20
5
5
10
5
*Higher MCLK frequencies are allowable when using the on-chip Master Clock Auto-Divide feature.
Specifications subject to change without notice.
REV. A
–3–
AD1853
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Min
Max
Units
DVDD to DGND
AVDD to AGND
Digital Inputs
Analog Outputs
AGND to DGND
Reference Voltage
Soldering
–0.3
–0.3
DGND – 0.3
AGND – 0.3
–0.3
6
6
V
V
V
V
V
1
2
DGND
MCLK
28 DVDD
27
26
25
24
23
SDATA
BCLK
DVDD + 0.3
AVDD + 0.3
0.3
(AVDD + 0.3)/2
+300
CLATCH
CCLK
3
4
L/RCLK
CDATA
INT4ꢂ
INT2ꢂ
ZEROR
DEEMP
IREF
5
RST
6
MUTE
AD1853
TOP VIEW
(Not to Scale)
°C
sec
7
22 ZEROL
10
8
21
IDPM0
9
20 IDPM1
19 FILTB
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
10
11
12
13
14
18
17
16
15
AGND
OUTL+
OUTL–
FILTR
AVDD
OUTR+
OUTR–
FCR
PACKAGE CHARACTERISTICS
Min
Typ
Max
Units
θ
θ
JA (Thermal Resistance
[Junction-to-Ambient])
JC (Thermal Resistance
[Junction-to-Case])
109
39
°C/W
°C/W
ORDERING GUIDE
Model
Temperature
Package Description
Package Options
AD1853JRS
AD1853JRSRL
0°C to +70°C
0°C to +70°C
28-Lead Shrink Small Outline
28-Lead Shrink Small Outline
RS-28
RS-28 on 13" Reels
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1853 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD1853
PIN FUNCTION DESCRIPTIONS
Pin
Input/Output
Pin Name
Description
Digital Ground.
1
2
I
I
DGND
MCLK
Master Clock Input. Connect to an external clock source. See Table II for allowable
frequencies.
3
4
I
I
CLATCH
CCLK
Latch input for control data. This input is rising-edge sensitive.
Control clock input for control data. Control input data must be valid on the rising edge
of CCLK. CCLK may be continuous or gated.
5
6
7
8
9
I
CDATA
INT4×
Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying
control information and channel-specific attenuation.
Assert HI to select interpolation ratio of 4×, for use with double-speed inputs (88 kHz or
96 kHz). Assert LO to select 8× interpolation ratio.
Assert HI to select interpolation ratio of 2×, for quad-speed inputs (176 kHz or 192 kHz).
Assert LO to select 8× interpolation ratio.
Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to
impose a 50 µs/15 µs response characteristic on the output audio spectrum at an assumed
44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via
SPI control register.
I
I
INT2×
O
I
ZEROR
DEEMP
10
11
12
13
14
I
I
O
O
O
IREF
Connection point for external bias resistor. Voltage held at VREF
Analog Ground.
Left Channel Positive line level analog output.
Left Channel Negative line level analog output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-
.
AGND
OUTL+
OUTL–
FILTR
ence with parallel 10 µF and 0.1 µF capacitors to the AGND (Pin 11).
15
16
17
18
19
20
21
22
I
FCR
Filter cap return pin for cap connected to FILTB (Pin 19).
Right Channel Negative line level analog output.
Right Channel Positive line level analog output.
Analog Power Supply. Connect to analog +5 V supply.
Filter Capacitor connection, connect 10 µF capacitor to FCR (Pin 15).
Input serial data port mode control one. With IDPM0, defines one of four serial modes.
Input serial data port mode control zero. With IDPM1, defines one of four serial modes.
Left Channel Zero Flag output. This pin goes HI when Left Channel has no signal input
for more than 1024 LR Clock Cycles.
O
O
I
O
I
OUTR–
OUTR+
AVDD
FILTB
IDPM1
IDPM0
ZEROL
I
O
23
24
I
I
MUTE
RST
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is
reset on the rising edge of this signal. The serial control port registers are reset to the
default values. Connect HI for normal operation.
25
26
27
I
I
I
L/RCLK
BCLK
SDATA
Left/Right clock input for input data. Must run continuously.
Bit clock input for input data.
Serial input, MSB first, containing two channels of 16/18/20/24 bit twos-complement
data.
28
I
DVDD
Digital Power Supply Connect to digital +5 V supply.
REV. A
–5–
AD1853
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB–1
LSB+1
LSB+2
MSB
MSB–2
LSB
Figure 1. Right-Justified Mode
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB
Figure 2. I2S-Justified Mode
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
MSB
MSB–1 MSB–2
LSB+2 LSB+1
LSB
MSB
MSB–1
Figure 3. Left-Justified Mode
L/RCLK
INPUT
RIGHT CHANNEL
LEFT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB MSB–1
LSB+2 LSB+1
LSB
MSB MSB–1
LSB+2 LSB+1
LSB
MSB MSB–1
Figure 4. Left-Justified DSP Mode
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB
MSB–1 MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1 MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1
Figure 5. 32 × FS Packed Mode
–6–
REV. A
AD1853
Figure 1 shows the right-justified mode. LRCLK is HI for the
left channel, LO for the right channel. Data is valid on the rising
edge of BCLK.
OPERATING FEATURES
Serial Data Input Port
The AD1853’s flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by using either the external mode pins (IDPM0 Pin 21 and
IDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPI
control register. To control the serial mode using the external
mode pins, the SPI mode select bits should be set to zero
(default at power-up). To control the serial mode using the SPI
mode select bits, the external mode control pins should be
grounded.
In normal operation, there are 64-bit clocks per frame (or 32
per half-frame). When the SPI word length control bits (Bits 8
and 9 in the control register) are set to 24 bits (0:0), the serial
port will begin to accept data starting at the 8th bit clock pulse
after the L/RCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12th bit
clock position. In 16-bit mode, data is accepted starting at the
16th-bit clock position. These delays are independent of the
number of bit clocks per frame, and therefore other data formats
are possible using the delay values described above. For detailed
timing, see Figure 6.
Figure 2 shows the I2S mode. L/RCLK is LO for the left chan-
nel, and HI for the right channel. Data is valid on the rising
edge of BCLK. The MSB is left-justified to an L/RCLK transi-
tion but with a single BCLK period delay. The I2S mode can be
used to accept any number of bits up to 24.
In all modes except for the right-justified mode, the serial port
will accept an arbitrary number of bits up to a limit of 24 (extra
bits will not cause an error, but they will be truncated inter-
nally). In the right-justified mode, control register Bits 8 and 9
are used to set the word length to 16, 20, or 24 bits. The default
on power-up is 24-bit mode. When the SPI Control Port is not
being used, the SPI pins (3, 4 and 5) should be tied LO.
Serial Data Input Mode
The AD1853 uses two multiplexed input pins to control the
mode configuration of the input data port mode.
Figure 3 shows the left-justified mode. L/RCLK is HI for the
left channel, and LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left-justified to an L/RCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits.
Table I. Serial Data Input Modes
Figure 4 shows the DSP serial port mode. L/RCLK must pulse
HI for at least one bit clock period before the MSB of the left
channel is valid, and L/RCLK must pulse HI again for at least
one bit clock period before the MSB of the right channel is
valid. Data is valid on the falling edge of BCLK. The DSP serial
port mode can be used with any word length up to 24 bits.
IDPM1
(Pin 20)
IDPM0
(Pin 21)
Serial Data Input Format
0
0
1
1
0
1
0
1
Right Justified (24 Bits) Default
I2S-Compatible
Left Justified
DSP
tDBH
tDBP
BCLK
tDBL
tDLS
L/RCLK
tDDS
MSB
SDATA
LEFT-JUSTIFIED
MSB-1
MODE
tDDH
tDDS
MSB
tDDH
SDATA
2
I S-JUSTIFIED
MODE
tDDS
LSB
tDDH
tDDS
MSB
tDDH
SDATA
RIGHT-JUSTIFIED
MODE
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 6. Serial Data Port Timing
REV. A
–7–
AD1853
Table II.
Nominal Input
Sample Rate
Internal Sigma-Delta
Clock Rate
Chip Mode
Allowable Master Clock Frequencies
INT8× Mode
INT4× Mode
INT2× Mode
256 × FS, 384 × FS, 512 × FS, 768 × FS, 1024 × FS
128 × FS, 192 × FS, 256 × FS, 384 × FS, 512 × FS
64 × FS, 96 × FS, 128 × FS, 192 × FS, 256 × FS
48 kHz
96 kHz
192 kHz
128 × FS
64 × FS
32 × FS
In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse, and that
synchronism is maintained from that point forward.
CLATCH is used internally to latch the parallel data from the
serial-to-parallel converter. This rising edge should be aligned
with the falling edge of the last CCLK pulse in the 16-bit frame.
The CCLK can run continuously between transactions.
Note that the AD1853 is capable of a 32 × FS BCLK frequency
“packed mode” where the MSB is left-justified to an L/RCLK
transition, and the LSB is right-justified to the opposite L/RCLK
transition. L/RCLK is HI for the left channel, and LO for the
right channel. Data is valid on the rising edge of BCLK. Packed
mode can be used when the AD1853 is programmed in right-
justified or left-justified mode. Packed mode is shown is Figure 5.
The serial control data is 16-bit MSB first, and is unsigned. Bits
0 and 1 are used to select 1 of 3 registers (control, volume left,
and volume right). The remaining 14 bits (bits 15:2) are used to
carry the data for the selected register. If a volume register is
selected, then the upper 14 bits are used to multiply the digital
input signal by the control word, which is interpreted as an
unsigned number (for example, 11111111111111 is 0 dB, and
01111111111111 is –6 dB, etc.). The default volume control
words on power-up are all 1s (0 dB). The control register only
uses bits 11:2 to carry data; the upper bits (15:12) should al-
ways be written with zeroes, as several test modes are decoded
from these upper bits. The control register defaults on power-up
to 8× interpolation mode, 24-bit right-justified serial mode,
unmuted, and no de-emphasis filter. The intent with these reset
defaults is to enable AD1853 applications without requiring the
use of the serial control port. For those users that do not use the
serial control port, it is still possible to mute the AD1853 output
by using the MUTE pin (Pin 23) signal.
Master Clock Auto-Divide Feature
The AD1853 has a circuit that autodetects the relationship
between master clock and the incoming serial data, and inter-
nally sets the correct divide ratio to run the interpolator and
modulator. The allowable frequencies for each mode are shown
above.
Serial Control Port
The AD1853 serial control port is SPI-compatible. SPI (Serial
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
input mode, soft reset, soft de-emphasis, channel specific at-
tenuation and mute (both channels at once). The SPI port is a
3-wire interface with serial data (CDATA), serial bit clock
(CCLK), and data latch (CLATCH). The data is clocked
into an internal shift register on the rising edge of CCLK.
The serial data should change on the falling edge of CCLK and
be stable on the rising edge of CCLK. The rising edge of
Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the LRCLK after CLATCH
write pulse as shown in Figure 6.
tCHD
CDATA
CCLK
D15
D14
D0
tCCH
tCLH
tCSU
tCCL
tCLL
CLATCH
Figure 7. Serial Control Port Timing
–8–
REV. A
AD1853
Table III. Digital Timing
Min
Units
tCCH
tCCL
tCSU
tCHD
tCLL
tCLH
CCLK HI Pulsewidth
CCLK LOW Pulsewidth
CDATA Setup Time
CDATA Hold Time
CLATCH LOW Pulsewidth
CLATCH HI Pulsewidth
40
40
10
10
10
10
ns
ns
ns
ns
ns
ns
SPI REGISTER DEFINITIONS
VOLUME LEFT and VOLUME RIGHT Registers
The SPI port allows flexible control of many chip parameters.
It is organized around three registers; a LEFT-CHANNEL
VOLUME register, a RIGHT-CHANNEL VOLUME register
and a CONTROL register. Each WRITE operation to the
AD1853 SPI control port requires 16 bits of serial data in
MSB-first format. The bottom two bits are used to select one
of three registers, and the top 14 bits are then written to that
register. This allows a write to one of the three registers in a
single 16-bit transaction.
A write operation to the left or right volume registers will acti-
vate the “auto-ramp” clickless volume control feature of the
AD1853. This feature works as follows. The upper 10 bits of
the volume control word will be incremented or decremented by
1 at a rate equal to the input sample rate. The bottom 4 bits are
not fed into the auto-ramp circuit and thus take effect immedi-
ately. This arrangement gives a worst-case ramp time of about
1024/FS for step changes of more than 60 dB, which has been
determined by listening tests to be optimal in terms of pre-
venting the perception of a “click” sound on large volume
changes. See Figure 8 for a graphical description of how the
volume changes as a function of time.
The SPI CCLK signal is used to clock in the data. The incom-
ing data should change on the falling edge of this signal. At the
end of the 16 CCLK periods, the CLATCH signal should rise
to latch the data internally into the AD1853.
The 14-bit volume control word is used to multiply the signal,
and therefore the control characteristic is linear, not dB. A con-
stant dB/step characteristic can be obtained by using a lookup
table in the microprocessor that is writing to the SPI port.
Register Addresses
The lowest two bits of the 16-bit input word are decoded as
follows to set the register into which the upper 14 bits will be
written.
Bit 1
Bit 0
Register
0
VOLUME REQUEST REGISTER
0
1
0
0
0
1
Volume Left
Volume Right
Control Register
–60
0
ACTUAL VOLUME REGISTER
–60
TIME
20ms
Figure 8. Smooth Volume Control
REV. A
–9–
AD1853
Control Register
The following table shows the functions of the control register. The control register is addressed by having a “01” in the bottom 2 bits
of the 16-bit SPI word. The top 14 bits are then used for the control register.
Bit 11
Bit 10
Bit 9:8
Bit 7
Bit 6
Bit 5:4
Bit 3:2
INT2× Mode
INT4× Mode
Number of
Soft Reset.
Default = 0
Soft Mute OR’d Serial Mode OR’d
De-Emphasis Filter
Select.
0:0 No Filter
0:1 44.1 kHz Filter
1:0 32 kHz Filter
1:1 48 kHz Filter
Default = 0.0
OR’d with Pin. OR’d with Pin. Bits in Right-
with Pin.
Default = 0
with Mode Pins.
IDPMI:IDPM0
0:0 Right-Justified
0:1 I2S
Default = 0
Default = 0
Justified Serial
Mode.
0:0 = 24
0:1 = 20
1:0 = 16
1:0 Left-Justified
1:1 DSP Mode
Default = 0:0
Default = 0:0
Mute
De-Emphasis
The AD1853 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Bit 6) HI. The AD1853
has been designed to minimize pops and clicks when muting
and unmuting the device by automatically “ramping” the gain
up or down. When the device is unmuted, the volume returns to
the value set in the volume register.
The AD1853 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
“Redbook” 50 µs/15 µs emphasis response curve. Three curves
are available; one each for 32 kHz, 44.1 kHz and 48 kHz sam-
pling rates. The external “DEEMP” pin (Pin 9) turns on the
44.1 kHz de-emphasis filter. The other filters may be selected
by writing to control Bits 2 and 3 in the control register. If the
SPI port is used to control the de-emphasis filter, the external
DEEMP pin should be tied LO.
Analog Attenuation
The AD1853 also offers the choice of using IREF (Pin 10) to
attenuate by up to 50 dB in the analog domain. This feature can
be used as an analog volume control. It is also a convenient
place to add a compressor/limiter gain control signal.
Control Signals
The IDPM0 and IDPM1 control inputs are normally con-
nected HI or LO to establish the operating state of the AD1853.
They can be changed dynamically (and asynchronously to
LRCLK and the master clock), but it is possible that a click
or pop sound may result during the transition from one serial
mode to another. If possible, the AD1853 should be placed in
mute before such a change is made.
Output Drive, Buffering and Loading
The AD1853 analog output stage is able to drive a 1 kΩ (in
series with 2 nF) load. The analog outputs are usually ac
coupled with a 10 µF capacitor.
Figures 9–14 show the calculated frequency response of the
digital interpolation filters. Figures 15–27 show the performance
of the AD1853 as measured by an Audio Precision System 2
Cascade. For the wideband plots, the noise floor shown in the
plots is higher than the actual noise floor of the AD1853. This is
caused by the higher noise floor of the “High Bandwidth” ADC
used in the Audio Precision measurement system. The two-tone
test shown in Figure 18 is per the SMPTE standard for measur-
ing Intermodulation Distortion.
0.001
0.0008
0.0006
0.0004
0.0002
0
0
–20
–40
–60
–80
–0.0002
–0.0004
–0.0006
–0.0008
–0.001
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
20
0
50
100
150
200
250
300
350
FREQUENCY – kHz
FREQUENCY – kHz
Figure 9. Passband Response 8× Mode, 48 kHz Sample
Rate
Figure 10. Complete Response, 8× Mode, 48 kHz
Sample Rate
–10–
REV. A
Typical Performance Characteristics–
AD1853
0.5
0.4
0
–20
–40
0.3
0.2
–60
–80
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–100
–120
–140
–160
–10
5
10
15
20
25
30
35
40
0
50
100
150
200
250
300
FREQUENCY – kHz
FREQUENCY – kHz
Figure 11. 44 kHz Passband Response 4× Mode, 96 kHz
Sample Rate
Figure 14. Complete Response, 4× Mode, 96 kHz
Sample Rate
2.0
1.5
0
–20
1.0
0.5
0
–40
–60
–80
–0.5
–100
–120
–140
–160
–1.0
–1.5
–2.0
0
10
20
30
40
50
60
70
80
0
50
100
150
200
250
FREQUENCY – kHz
FREQUENCY – kHz
Figure 15. Complete Response, 2× Mode, 192 kHz
Sample Rate
Figure 12. 88 kHz Passband Response 2× Mode, 192 kHz
Sample Rate
0
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–100
–110
–120
–80
–90
–100
–110
–120
–100
–80
–60
–40
–20
0
10
100
1k
10k
dBFS
FREQUENCY – Hz
Figure 16. THD + N Ratio vs. Amplitude Input 1 kHz,
SR 48 kHz, 24-Bit
Figure 13. THD vs. Frequency Input @ –3 dBFS, SR 48 kHz
REV. A
–11–
AD1853
2
–90
–100
–110
–120
–130
–140
0
–2
–4
–6
–8
–10
–150
–160
–12
10
100
1k
10k
0
2
4
6
8
10
12
14
16
18
20 22
FREQUENCY – Hz
FREQUENCY – kHz
Figure 17. Normal De-Emphasis Frequency Response
Input @ –10 dBFS, SR 48 kHz
Figure 20. Noise Floor for Zero Input, SR 48 kHz,
SNR –117 dBFS A-Weighted
–10
–30
0
–10
–20
–30
–40
–50
–60
–70
–80
–50
–70
–90
–90
–100
–110
–120
–130
–140
–150
–110
–130
–150
0
2
4
6
8
10
12
14
16
18
20 22
0
2
4
6
8
10
12
14
16
18
20 22
FREQUENCY – kHz
FREQUENCY – kHz
Figure 18. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS
Figure 21. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz,
SR 48 kHz, THD+N 104 dBFS
0
–50
–60
–20
–70
–80
–40
–60
–80
–90
–100
–110
–120
–130
–100
–120
–140
–140
–150
–160
–140
–120
–100
–80
–60
–40
–20
0
0
2
4
6
8
10
12
14
16
18
20 22
dBFS
FREQUENCY – kHz
Figure 19. Linearity vs. Amplitude Input 200 Hz,
SR 48 kHz, 24-Bit Word
Figure 22. Dynamic Range for 1 kHz @ –60 dBFS,
116 dB, Triangular Dithered Input
–12–
REV. A
AD1853
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–100
–110
–120
–130
–140
–150
–160
–100
10
100
1k
10k
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
FREQUENCY – kHz
FREQUENCY – Hz
Figure 23. Power Supply Rejection vs. Frequency
AVDD 5 V dc + 100 mV p-p ac
Figure 26. Wideband Plot, 25 kHz Input, 2× Interpolation,
SR 192 kHz
0
0
–10
–20
–10
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–80
–70
–90
–80
–100
–110
–120
–130
–140
–150
–160
–90
–100
–110
–120
–130
–140
20
40
60
80
100
120
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
FREQUENCY – kHz
FREQUENCY – kHz
Figure 24. Wideband Plot, 15 kHz Input, 8× Interpolation,
SR 48 kHz
Figure 27. Wideband Plot, 75 kHz Input, 2× Interpolation,
SR 192 kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
20
40
60
80
100
120
FREQUENCY – kHz
Figure 25. Wideband Plot, 37 kHz Input, 4× Interpolation,
SR 96 kHz
REV. A
–13–
AD1853
STEREO MODE OUTPUT FILTER
DVDD
HDR2
1
EXT SDATA
EXT L/RCLK
EXT SCLK
EXT MCLK
HDR3 F
1
2
N
44/48
96
192
NO
0
1
0
1
0
0
1
1
DVDD
DVDD
R18
10kꢅ
R17
10kꢅ
R24
R25
R26
R27
9
8
DVDD
100ꢅ
100ꢅ
100ꢅ
100ꢅ
IDPM0
IDPM1
S2B
S2C
EXT I/F
IN
2
3
R12
10kꢅ
R13
10kꢅ
C35
47pF
R14
10kꢅ
C36
47pF
R15
10kꢅ
C34
47pF
SAMPLE RATE
MODE
R5
R6
10kꢅ 10kꢅ
C37
47pF
DVDD
HDR3
C11
100nF
DVDD
DVDD
1
0
U4
R11
SPDIF/EXT
I/F
U2 DATA SOURCE
1
2
3
4
5
S2A
S2B
S2C
S2D
S2E
PALCE22V10-J
10kꢅ
FB2
SPDIF/EXT
2
600Z
I S SERIAL
EXT MCLK
EXT SCLK
SELECT
C6
C5
10
1
CLK/I0
DATA MODE
S2A
100nF
100nF
DEEMPH OFF
MUTE OFF
I1
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
EXT L/RCLK
EXT SDATA
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
VD+
VA+
DVDD
AVDD
SDATA
FSYNC
SCK
SIGNAL
SOURCE
S1
F
S
J1
64F
C9
100nF
C8
100nF
S
1
C1
SPNIF
IN
10nF
256F
S
MCK
RXP
0
R1
75ꢅ
U2
CS8414-CS
C2
10nF
DVDD AVDD
U5
M0
M1
M2
RXN
AD1853JRS
ROUT+
ROUT–
LOUT+
LOUT–
OUTR+
OUTR–
OUTL+
OUTL–
FILTR
INT4ꢂ
INT2ꢂ
SDATA
L/RCLK
BCLK
M3
C
R23
DVDD
VERF
DS4
274ꢅ
500mVp-p
U
R19
CBL
VERF
ERF
DVDD
10kꢅ
MCLK
IDPM0
IDPM1
DEEMP
MUTE
VREF
Q1
2N2222
FB1
600Z
MCLK
C4
100nF
R2
3.40kꢅ
C0/E0
Ca/E1
V
REF
+2.7V
U3A
74HC00D
CLATCH
Cb/E2
Cc/F0
CLATCH
CCLK
1
PREEMPH
IREF
CCLK
CDATA
ZR
3
DVDD
OUT
FILT
2
FILTB
Cd/F1
CDATA
ZEROR
ZEROL
RST
+
–
C26
10ꢆF
TOSLINK
IN
R4
1kꢅ
U1
DVDD
Ce/F2
TORX173
ZL
C56
SEL
R3
750ꢅ
100nF
RST
SHLD DGND
CSI2/FCK
AGND DGND
FCR
C24
47nF
DGND AGND
R28
2.67kꢅ
AGND
DVDD
DGND
DGND
SET Ib = 1mA
FB3
600Z
DVDD
C10
R10
R16
100nF
10kꢅ
U3D
74HC00D
10kꢅ
DEEMPH
DS1
ZERO
LEFT
R20
274ꢅ
ZL 12
MUTE
ON
11
OFF
DEEMPH
7
13
S2D
4
OFF
DS2
ZERO
RIGHT
ON
HDR1 DVDD
6
5
U3C
74HC00D
9
S2E
1
MUTE
R21
274ꢅ
ZR
CDATA
CCLK
8
10
EXT ꢆC
CLATCH
MCLK
I/F
NOTE:
DVDD
U3B
74HC00D
4
DVDD
= DGND
= AGND
R7
10kꢅ
R8
R9
DS3
R22
274ꢅ
C12
100nF
10kꢅ 10kꢅ
DEEMPH
6
5
#98107-02-3 REV. 1.1
Figure 28. Digital Receiver, MUX and AD1853 DAC
–14–
REV. A
AD1853
R48
4.12kꢅ
OUTPUT BUFFERS AND LP FILTERS
–AV
C46
330pF, NP0
SS
C23
100nF
C38
R34
220pF
NP0
2.74kꢅ
R33
R29
ROUT+
2.74kꢅ
2.94kꢅ
C52*
U6A
+AV
NP
C43
680pF
NP0
OP275
C21
100nF
C57
220pF
NP0
R41
604ꢅ
J2
1
RIGHT
OUT
U8B
OP275
0
C50
2.2nF
NP0
C42
680pF
NP0
R43
49.9kꢅ
CC
R30
2.94kꢅ
R35
2.74kꢅ
OP275
ROUT–
C53*
NP
U6B
C39
220pF
NP0
R36
2.74kꢅ
C47
330pF, NP0
R52
402ꢅ
V
+2.7V
REF
R49
4.12kꢅ
R50
4.12kꢅ
+
–
C7
C25
10ꢆF
GAUSSIAN FILTER RESPONSE
–3dB CORNER FREQUENCY: 75kHz
100nF
–AV
EE
C48
330pF, NP0
R53
402ꢅ
C22
100nF
C40
220pF
NP0
R38
2.74kꢅ
R37
R31
2.94kꢅ
LOUT+
–AV
SS
2.74kꢅ
C54*
U7A
+AV
C18
NP
100nF
C45
680pF
NP0
OP275
C58
220pF
NP0
C20
R42
J3
100nF
604ꢅ
1
LEFT
OUT
U8A
0
OP275
C19
C51
2.2nF
NP0
C44
680pF
NP0
R44
49.9kꢅ
CC
R32
2.94kꢅ
R39
2.74kꢅ
OP275
LOUT–
100nF
C55*
NP
U7B
+AV
C49
330pF, NP0
CC
C41
R40
2.74kꢅ
220pF
NP0
*NOT POPULATED
R51
4.12kꢅ
RESET GENERATOR
VOLTAGE REGULATORS AND SUPPLY FILTERING
J6
DVDD
+AV
+15V dc
CC
+
–
U11
ADP3303-5.0
C32
10ꢆF
C17
100nF
FB4
600Z
V
CC
IN
IN
OUT
OUT
+5V REG
AVDD
U10
ADM707AR
CR2
1SMB15AT3
R47
332ꢅ
C16
100nF
ERR NR
SD GND
RESET
RESET
PFO
PFI
C15
100nF
+
–
C31
RST
DS5
POWER
C3
10nF
10ꢆF
+
C30
10ꢆF
J7
0V
MR
–
AGND
GND
S3
RESET
AGND
+
–
C33
10ꢆF
J8
–AV
SS
–15V dc
U9
LM317
FB5
600Z
CR3
1N4001
J4
+9V dc
+5V REG
TO
V
V
DVDD
IN
OUT
+15V dc
R45
GND
NOTE:
+
–
243ꢅ
C27
10ꢆF
C14
100nF
CR1
= DGND
= AGND
+
–
C29
10ꢆF
1SMB15AT3
C13
100nF
+
–
R46
715ꢅ
C28
10ꢆF
J5
0V
DGND
DGND
Figure 29. DAC Output LP Filter, Power and Reset
REV. A
–15–
AD1853
I/V CONVERTERS AND LP FILTER
R9*
2.87kꢅ
GAUSSIAN FILTER RESPONSE
–3dB CORNER FREQUENCY: 75kHz
C6
68pF, NP0
R11
100ꢅ
C1
220pF
NP0
R4
2.74kꢅ
PIN 12
LOUT+
R3
2.74kꢅ
R1
2.94kꢅ
U2
PIN 13
LOUT–
C4
AD797
680pF
R7
604ꢅ
J1
NP0
1
OUT
6Vrms
U1
AD797
C3
680pF
NP0
0
C5
2.2nF
NP0
R8
49.9kꢅ
R5
2.74kꢅ
R2
2.94kꢅ
U3
PIN 17
C2
220pF
NP0
R6
2.74kꢅ
ROUT+
AD797
PIN 16
ROUT–
C7
R12
100ꢅ
68pF, NP0
V
REF
R10*
2.87kꢅ
NOTES:
+2.78V
C15
1. R9, R10 MUST BE LOW NOISE TYPES.
METAL FILM IS RECOMMENDED.
+
–
C8
100nF
10ꢆF
TANT
2. RIGHT CHANNEL DIGITAL DATA MUST BE INVERTED.
J2
+16.5V dc
+AV
–AV
CC
C16
+
–
C10
C12
C14
10ꢆF
100nF
100nF
100nF
J3
J4
NOTE:
TANT
0V
AGND
= AGND
C17
10ꢆF
TANT
+
–
C9
100nF
C11
100nF
C13
100nF
–16.5V dc
SS
Figure 30. Mono Application Circuit
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package (SSOP)
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.21)
1
0.07 (1.79)
0.066 (1.67)
0.078 (1.98)
0.068 (1.73)
PIN 1
0.03 (0.762)
0.022 (0.558)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
–16–
REV. A
相关型号：
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