AD1865N-J [ADI]
Complete Dual 18-Bit 16 x Fs Audio DAC; 完整的双通道18位， 16× Fs的音频DAC
| 型号： | AD1865N-J |
| 厂家： | 
ADI |
| 描述： | Complete Dual 18-Bit 16 x Fs Audio DAC |
| 文件： | 总12页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete Dual 18-Bit
a
16
؋
FS Audio DAC AD1865*
FUNCTIONAL BLOCK DIAGRAM
(DIP Package)
FEATURES
Dual Serial Input, Voltage Output DACs
No External Components Required
110 dB SNR
0.003% THD+N
Operates at 16
؋
Oversampling per Channel ؎5 Volt Operation
–VS
1
2
3
4
5
6
7
8
9
24
23
22
21
+VS
AD1865
TRIM
TRIM
REFERENCE
REFERENCE
MSB
IOUT
MSB
IOUT
Cophased Outputs
AGND
20 AGND
19 SJ
116 dB Channel Separation
Pin Compatible with AD1864
DIP or SOIC Packaging
SJ
RF
RF
18
17
APPLICATIONS
Multichannel Audio Applications
Compact Disc Players
Multivoice Keyboard Instruments
DAT Players and Recorders
Digital Mixing Consoles
Multimedia Workstations
VOUT
VOUT
+VL
16 NC
15 DL
DR 10
LR 11
18-BIT
LATCH
18-BIT
D/A
18-BIT
D/A
18-BIT
LATCH
14
13
LL
CLK
12
DGND
NC = NO CONNECT
PRODUCT DESCRIPTION
A versatile digital interface allows the AD1865 to be directly
connected to standard digital filter chips. This interface employs
five signals: Data Left (DL), Data Right (DR), Latch Left (LL),
Latch Right (LR) and Clock (CLK). DL and DR are the serial
input pins for the left and right DAC input registers. Input data
bits are clocked into the input register on the rising edge of
CLK. A low-going latch edge updates the respective DAC out-
put. For systems using only a single latch signal, LL and LR
may be connected together. For systems using only one DATA
signal, DR and DL may be connected together.
The AD1865 is a complete, dual 18-bit DAC offering excellent
THD+N and SNR while requiring no external components. Two
complete signal channels are included. This results in cophased
voltage or current output signals and eliminates the need for
output demultiplexing circuitry. The monolithic AD1865 chip
includes CMOS logic elements, bipolar and MOS linear ele-
ments and laser-trimmed thin-film resistor elements, all fabri-
cated on Analog Devices’ ABCMOS process.
The DACs on the AD1865 chip employ a partially segmented
architecture. The first four MSBs of each DAC are segmented
into 15 elements. The 14 LSBs are produced using standard R-2R
techniques. Segment and R-2R resistors are laser trimmed to pro-
vide extremely low total harmonic distortion. This architecture
minimizes errors at major code transitions resulting in low out-
put glitch and eliminating the need for an external deglitcher.
When used in the current output mode, the AD1865 provides
two ±1 mA output signals.
The AD1865 operates with ±5 V power supplies. The digital
supply, VL, can be separated from the analog supplies, VS and
–VS, for reduced digital feedthrough. Separate analog and digital
ground pins are also provided. The AD1865 typically dissipates
only 225 mW, with a maximum power dissipation of 260 mW.
The AD1865 is packaged in both a 24-pin plastic DIP and a
28-pin SOIC package. Operation is guaranteed over the temper-
ature range of –25°C to +70°C and over the voltage supply
range of ±4.75 V to ±5.25 V.
Each channel is equipped with a high performance output am-
plifier. These amplifiers achieve fast settling and high slew rate,
producing ±3 V signals at load currents up to 8 mA. Each out-
put amplifier is short-circuit protected and can withstand indefi-
nite short circuits to ground.
PRODUCT HIGHLIGHTS
11. The AD1865 is a complete dual 18-bit audio DAC.
12. 110 dB signal-to-noise ratio for low noise operation.
13. THD+N is typically 0.003%.
14. Interchannel gain and midscale matching.
15. Output voltages and currents are cophased.
16. Low glitch for improved sound quality.
17. Both channels are 100% tested at 16 × FS.
18. Low Power—only 225 mW typ, 260 mW max.
19. Five-wire interface for individual DAC control.
10. 24-pin DIP or 28-pin SOIC packages available.
The AD1865 was designed to balance two sets of opposing re-
quirements, channel separation and DAC matching. High chan-
nel separation is the result of careful layout. At the same time,
both channels of the AD1865 have been designed to ensure
matched gain and linearity as well as tracking over time and
temperature. This assures optimum performance when used in
stereo and multi-DAC per channel applications.
*Protected by U.S. Patents Nos.: RE 30,586; 3,961,326; 4,141,004;
4,349,811; 4,855,618; 4,857,862.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
(TA = +25؇C, +VL = +VS = +5 V and –VS = –5 V, FS = 705.6 kHz, no MSB adjustment
AD1865–SPECIFICATIONS or deglitcher)
Parameter
Min
Typ
Max
Unit
RESOLUTION
18
Bits
DIGITAL INPUTS VIH
VIL
2.0
+VL
0.8
V
V
IIH, VIH = +VL
IIL, VIL = 0.4 V
Clock Input Frequency
1.0
–10
µA
µA
MHz
13.5
ACCURACY
Gain Error
Interchannel Gain Matching
Midscale Error
0.2
0.3
4
1.0
0.8
% of FSR
% of FSR
mV
Interchannel Midscale Matching
Gain Linearity (0 dB to –90 dB)
5
<2
mV
dB
DRIFT (0°C to +70°C)
Gain Drift
Midscale Drift
±25
±4
ppm of FSR/°C
ppm of FSR/°C
TOTAL HARMONIC DISTORTION + NOISE*
0 dB, 990.5 Hz
AD1865N, R
0.004
0.003
0.010
0.010
1.0
0.006
0.004
0.040
0.020
4.0
%
%
%
%
%
%
AD1865N-J, R-J
20 dB, 990.5 Hz AD1865N, R
AD1865N-J, R-J
–60 dB, 990.5 Hz AD1865N, R
AD1865N-J, R-J
1.0
2.0
CHANNEL SEPARATION*
0 dB, 990.5 Hz
110
107
116
110
dB
dB
SIGNAL-TO-NOISE RATIO* (20 Hz to 30 kHz)
D-RANGE* (With A-Weight Filter)
–60 dB, 990.5 Hz AD1865N, R
AD1865N-J, R-J
88
94
100
100
dB
dB
OUTPUT
Voltage Output Configuration
Output Range (±1%)
Output Impedance
؎2.94
±8
±3.0
0.1
؎3.06
V
Ω
mA
Load Current
Short Circuit Duration
Current Output Configuration
Bipolar Output Range (±30%)
Output Impedance (±30%)
Indefinite to Common
±1
1.7
mA
kΩ
POWER SUPPLY
+VL and +VS
–VS
+I, +VL and +VS = +5 V
–I, –VS = –5 V
4.75
–5.25
5.0
–5.0
22
5.25
–4.75
26
V
V
mA
mA
–23
–26
POWER DISSIPATION, +VL = +VS = +5 V, –VS = –5 V
225
260
mW
TEMPERATURE RANGE
Specification
Operation
0
–25
–60
+25
+70
+70
+100
°C
°C
°C
Storage
WARMUP TIME
1
min
Specifications shown in boldface are tested on production units at final test without optional MSB adjustment.
*Tested in accordance with EIAJ Test Standard CP-307 with 18-bit data.
Specifications subject to change without notice.
–2–
REV. 0
AD1865
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –6.0 V to 0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 to VL
Short Circuit Protection . . . . . . . . Indefinite Short to Ground
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1865 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PINOUT
(24-Pin DIP Package)
ORDERING GUIDE
Temperature
Range
Package
THD+N @ FS Option*
+VS
–VS
Model
24
1
2
3
4
5
TRIM
23 TRIM
22 MSB
AD1865N
AD1865N-J
AD1865R
AD1865R-J
–25°C to +70°C
–25°C to +70°C
–25°C to +70°C
–25°C to +70°C
0.006%
0.004%
0.006%
0.004%
N-24A
N-24A
R-28
MSB
IOUT
RIGHT
CHANNEL
LEFT
CHANNEL
IOUT
21
R-28
AGND
AGND
20
*N = Plastic DIP, R = Small Outline IC Package.
AD1865
6
7
19 SJ
SJ
RF
TOP VIEW
PIN DESIGNATIONS
DIP SOIC
RF
18
17
16
(Not to Scale)
VOUT
+VL
DR
VOUT
NC
8
11 22
12 23
13 24
–VS
Negative Analog Supply
9
TRIM Right Channel Trim Network Connection
10
15 DL
MSB
IOUT
Right Channel Trim Potentiometer
Wiper Connection
Right Channel Output Current
LR 11
LL
14
14 26
15 28
16 11
17 12
18 13
19 14
10 15
11 16
12 17
13 18
14 19
15 10
12
CLK
13 DGND
AGND Analog Common Pin
SJ
Right Channel Amplifier Summing Junction
NC = NO CONNECT
RF
Right Channel Feedback Resistor
Right Channel Output Voltage
Positive Digital Supply
Right Channel Data Input Pin
Right Channel Latch Pin
Clock Input Pin
VOUT
+VL
DR
LR
(28-Pin SOIC Package)
SJ
1
2
28 AGND
27 NC
CLK
R
F
DGND Digital Common Pin
V
I
26
OUT
3
OUT
LL
DL
Left Channel Latch Pin
Left Channel Data Input Pin
No Internal Connection*
+V
4
25 NC
L
16 11, 16, 18 NC
25, 27
DR
24 MSB
5
LR
6
23 TRIM
–V
17 12
18 13
19 14
20 15
21 17
22 19
VOUT
Left Channel Output Voltage
AD1865
CLK
7
22
21
20
19
18
17
16
15
S
RF
SJ
Left Channel Feedback Resistor
Left Channel Amplifier Summing Junction
TOP VIEW
(Not to Scale)
+V
DGND
LL
8
S
AGND Analog Common Pin
9
TRIM
MSB
NC
IOUT
Left Channel Output Current
DL
NC
10
11
12
13
MSB
Left Channel Trim Potentiometer
Wiper Connection
V
I
23 20
24 21
TRIM Left Channel Trim Network Connection
+VS Positive Analog Supply
OUT
OUT
R
F
NC
AGND
*Pin 16 has no internal connection; –VL from AD1864 DIP socket can be safely
applied.
SJ 14
NC = NO CONNECT
REV. 0
–3–
AD1865
TOTAL HARMONIC DISTORTION + NOISE
INTERCHANNEL MIDSCALE MATCHING
Total harmonic distortion plus noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the am-
plitudes of the harmonics and noise to the value of the funda-
mental input frequency. It is usually expressed in percent.
The midscale matching specification indicates how closely the
amplitudes of the output signals of the two channels match
when the twos complement input code representing half scale is
loaded into the input register of both channels. It is expressed in
mV and is measured with half-scale output signals.
THD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
ing on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small (–20 dB, –60 dB) signal amplitudes. THD+N measure-
ments for the AD1865 are made using the first 19 harmonics
and noise out to 30 kHz.
FUNCTIONAL DESCRIPTION
The AD1865 is a complete, monolithic, dual 18-bit audio DAC.
No external components are required for operation. As shown in
the block diagram, each chip contains two voltage references,
two output amplifiers, two 18-bit serial input registers and two
18-bit DACs.
The voltage reference section provides a reference voltage for
each DAC circuit. These voltages are produced by low-noise
bandgap circuits. Buffer amplifiers are also included. This com-
bination of elements produces reference voltages that are unaf-
fected by changes in temperature and age.
SIGNAL-TO-NOISE RATIO
The signal-to-noise ratio is defined as the ratio of the amplitude
of the output when a full-scale code is entered to the amplitude
of the output when a midscale code is entered. It is measured
using a standard A-Weight filter. SNR for the AD1865 is mea-
sured for noise components out to 30 kHz.
The output amplifiers use both MOS and bipolar devices and
incorporate an all NPN output stage. This design technique
produces higher slew rate and lower distortion than previous
techniques. Frequency response is also improved. When com-
bined with the appropriate on-chip feedback resistor, the output
op amps convert the output current to output voltages.
CHANNEL SEPARATION
Channel separation is defined as the ratio of the amplitude of a
full-scale signal appearing on one channel to the amplitude of
that same signal which couples onto the adjacent channel. It is
usually expressed in dB. For the AD1865 channel separation is
measured in accordance with EIAJ Standard CP-307, Section
5.5.
The 18-bit D/A converters use a combination of segmented de-
coder and R-2R architecture to achieve consistent linearity and
differential linearity. The resistors which form the ladder struc-
ture are fabricated with silicon chromium thin film. Laser trim-
ming of these resistors further reduces linearity errors resulting
in low output distortion.
D-RANGE DISTORTION
D-Range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
–60 dB below full scale is reproduced. D-Range is tested with a
1 kHz input sine wave. This is measured with a standard A-Weight
filter as specified by EIAJ Standard CP-307.
The input registers are fabricated with CMOS logic gates.
These gates allow the achievement of fast switching speeds and
low power consumption, contributing to the low glitch and low
power dissipation of the AD1865.
–VS
GAIN ERROR
1
2
3
4
5
6
7
8
9
24
23
22
21
+VS
AD1865
The gain error specification indicates how closely the output of
a given channel matches the ideal output for given input data. It
is expressed in % of FSR and is measured with a full-scale out-
put signal.
TRIM
TRIM
REFERENCE
REFERENCE
MSB
IOUT
MSB
IOUT
AGND
20 AGND
19 SJ
INTERCHANNEL GAIN MATCHING
SJ
RF
The gain matching specification indicates how closely the ampli-
tudes of the output signals match when producing identical in-
put data. It is expressed in % of FSR (Full-Scale Range = 6 V
for the AD1865) and is measured with full-scale output signals.
RF
18
17
VOUT
VOUT
+VL
16 NC
15 DL
DR 10
LR 11
18-BIT
LATCH
18-BIT
D/A
18-BIT
D/A
18-BIT
LATCH
MIDSCALE ERROR
14
13
LL
Midscale error is the deviation of the actual analog output of a
given channel from the ideal output (0 V) when the twos
complement input code representing half scale is loaded into the
input register of the DAC. It is expressed in mV and is mea-
sured with half-scale output signals.
CLK
12
DGND
NC = NO CONNECT
AD1865 Block Diagram (DIP Package)
–4–
REV. 0
Typical Performance Data–AD1865
100
120
110
0dB
90
80
100
90
80
70
12
16
4
8
0
16
12
0
4
8
FREQUENCY – kHz
FREQUENCY – kHz
Figure 1. THD+N (dB) vs. Frequency (kHz)
Figure 2. Channel Separation (dB) vs. Frequency (kHz)
10
1
–60dB
.1
.01
–20dB
0dB
.001
–10
0
20 30
40
50
C
60
70
80
–30 –20
10
90
TEMPERATURE –
°
Figure 3. THD+N (%) vs. Temperature (°C)
10
8
100
90
80
6
4
2
0
70
60
–2
–4
–6
–8
50
40
–10
1500
2500
3000
0
500
1000
2000
–90
–100
–80
–70
–60 –50
–40 –30 –20 –10
0
LOAD RESISTANCE –
Ω
INPUT AMPLITUDE – dB
Figure 4. THD+N (dB) vs. Load Resistance (Ω)
Figure 5. Gain Linearity (dB) vs. Input Amplitude (dB)
REV. 0
–5–
AD1865–Analog Circuit Consideration
GROUNDING RECOMMENDATIONS
As with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be incor-
porated into the design of an audio system.
The AD1865 has three ground pins, two labeled AGND and
one labeled DGND. AGND, the analog ground pins, are the
“high quality” ground references for the device. To minimize
distortion and reduce crosstalk between channels, the analog
ground pins should be connected together only at the analog
common point in the system. As shown in Figure 6, the AGND
pins should not be connected at the chip.
DISTORTION PERFORMANCE AND TESTING
The THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. The THD+N specification, therefore,
provides a direct method to classify and choose an audio DAC
for a desired level of performance. Figure 1 illustrates the typ-
ical THD+N performance of the AD1865 versus frequency. A
load impedance of at least 1.5 kΩ is recommended for best
THD+Nperformance.
AD1865
S
–ANALOG
SUPPLY
ANALOG
SUPPLY
–V
+V
1
2
24
23
22
21
20
19
18
17
16
15
14
13
S
TRIM
MSB
TRIM
MSB
3
I
I
4
OUT
OUT
5
AGND AGND
Analog Devices tests and grades all AD1865s on the basis of
THD+Nperformance.Duringthedistortiontest,ahigh-speed
digital pattern generator transmits digital data to each channel
of the device under test. Eighteen-bit data is transmitted at
705.6 kHz (16 × FS). The test waveform is a 990.5 Hz sine wave
with 0 dB, –20 dB and –60 dB amplitudes. A 4096 point FFT
calculates total harmonic distortion + noise, signal-to-noise ratio,
D-Range and channel separation. No deglitchers or MSB trims
are used in the testing of the AD1865.
6
SJ
SJ
R
F
R
F
7
V
8
V
V
V
OUT
OUT
OUT
OUT
DIGITAL
SUPPLY
9
+V
L
NC
DR
10
11
12
DL
LL
LR
CLK
DGND
DIGITAL
COMMON
NC = NO CONNECT
OPTIONAL MSB ADJUSTMENT
Figure 6. Recommended Circuit Schematic
Use of optional adjust circuitry allows residual distortion error
to be eliminated. This distortion is especially important when
low amplitude signals are being reproduced. The MSB adjust
circuitry is shown in Figure 7. The trim potentiometer should
be adjusted to produce the lowest distortion using an input sig-
nal with a –60 dB amplitude.
The digital ground pin returns ground current from the digital
logic portions of the AD1865 circuitry. This pin should be con-
nected to the digital common pin in the system. Other digital
logic chips should also be referred to that point. The analog and
digital grounds should be connected together at one point in the
system, preferably at the power supply.
AD1865
–V
+V
1
2
3
4
5
6
7
8
9
24
POWER SUPPLIES AND DECOUPLING
S
S
200kΩ 100kΩ
470kΩ 100kΩ
470kΩ
200kΩ
TRIM 23
MSB 22
The AD1865 has three power supply input pins. ±VS provides
the supply voltages which operate the analog portions of the
DAC including the voltage references, output amplifiers and
control amplifiers. The ±VS supplies are designed to operate
from ±5 V supplies. Each supply should be decoupled to analog
common using a 0.1 µF capacitor in parallel with a 10 µF
capacitor. Good engineering practice suggests that the bypass
capacitors be placed as close as possible to the package pins.
This minimizes the parasitic inductive effects of printed circuit
board traces.
TRIM
MSB
I
I
21
OUT
OUT
AGND AGND 20
SJ
SJ 19
R
F
R
18
F
V
V
OUT
17
OUT
+V
NC
DL
LL
16
15
14
13
L
10 DR
11 LR
12
CLK
DGND
The +VL supply operates the digital portions of the chip includ-
ing the input shift registers and the input latching circuitry.
This supply should be bypassed to digital common using a
0.1 µF capacitor in parallel with a 10 µF capacitor. +VL oper-
ates with a +5 V supply. In order to assure proper operation of
the AD1865, –VS must be the most negative power supply volt-
age at all times.
NC = NO CONNECT
Figure 7. Optional THD+N Adjust Circuitry
Though separate positive power supply pins are provided for
the analog and digital portions of the AD1865, it is also possible
to use the AD1865 in systems featuring a single +5 V power
supply. In this case, both the +VS and +VL input pins should be
connected to the single +5 V power supply. This feature allows
reduction of the cost and complexity of the system power
supply.
–6–
REV. 0
Digital Circuit Considerations–AD1865
CURRENT OUTPUT MODE
VOLTAGE OUTPUT MODES
One or both channels of the AD1865 can be operated in current
output mode. IOUT can be used to directly drive an external
current-to-voltage (I-V) converter. The internal feedback resis-
tor, RF, can still be used in the feedback path of the external I-V
converter, thus assuring that RF tracks the DAC over time and
temperature.
As shown on the block diagram, each channel of the AD1865 is
complete with an I-V converter and a feedback resistor. These
can be connected externally to provide direct voltage output
from one or both AD1865 channels. Figure 6 shows these con-
nections. IOUT is connected to the Summing Junction, SJ. VOUT
is connected to the feedback resistor, RF. This implementation
results in the lowest possible component count and achieves the
specifications shown on the Specifications page while operating
at 16 × FS.
Of course, the AD1865 can also be used in voltage output mode
in order to utilize the onboard I-V converter.
CLK
L
S
B
M
DL
DR
LL
S
B
L
S
B
M
S
B
LR
Figure 8. AD1865 Control Signals
INPUT DATA
TIMING
Data is transmitted to the AD1865 in a bit stream composed of
18-bit words with a serial, twos complement, MSB first format.
Data Left (DL) and Data Right (DR) are the serial inputs for
the left and right DACs, respectively. Similarly, Latch Left (LL)
and Latch Right (LR) update the left and right DACs. The fall-
ing edge of LL and LR cause the last 18 bits which were clocked
into the Serial Registers to be shifted into the DACs, thereby
updating the DAC outputs. Left and Right channels share the
Clock (CLK) signal. Data is clocked into the input registers on
the rising edge of CLK.
Figure 9 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. The input pins of the AD1865 are both TTL and 5 V
CMOS compatible.
The minimum clock rate of the AD1865 is at least 13.5 MHz.
This clock rate allows data transfer rates of 2×, 4×, 8× and
16 × FS (where FS equals 44.1 kHz).
Figure 8 illustrates the general signal requirements for data
transfer for the AD1865.
>74.1ns
>30ns
>30ns
CLK
>15ns
>40ns >40ns
>40ns
LL/LR
DL/DR
>15ns
>15ns
INTERNAL DAC INPUT REGISTER
UPDATED WITH 18 MOST RECENT BITS
>30ns
MSB
1st BIT
LSB
NEXT
WORD
2nd BIT
18th BIT
BITS CLOCKED
TO SHIFT REGISTER
Figure 9. AD1865 Timing Diagram
–7–
REV. 0
AD1865
–5V ANALOG SUPPLY
+5V ANALOG SUPPLY
AD1865
SM5813AP/
24
23
–V
1
2
28
27
1
2
3
+V
S
APT
S
TRIM
MSB
TRIM
MSB 22
I
3
BCKO
LEFT
CHANNEL
OUTPUT
26
25
C1
C2
I
OUT
21
4
OUT
4
5
WCKO
DOL
20
19
AGND
SJ
5
6
AGND
SJ
24
23
RIGHT
6
7
8
9
CHANNEL
OUTPUT
1
2
3
+V
S
DOR
8
R
F
18
17
22
21
7
8
V
R
F
7
6
5
DD
V
V
OUT
VS
S1
OUT
VS
S2
16
15
14
13
9
NC
4
DG
20
19
18
–V
S
+V
L
10
11
12
10
11
12
NE5532
DR
LR
DL
LL
CLK
DGND
17
16
15
OW18
OW20
13
14
+5V DIGITAL
SUPPLY
Figure 10. Complete 8 × FS 18-Bit CD Player
18-BIT CD PLAYER DESIGN
An NE5532 dual op amp is used to provide the output antialias
filters required for adequate image rejection. One 2-pole filter
section is provided for each channel. An additional pole is cre-
ated from the combination of the internal feedback resistors
(RF) and the external capacitors C1 and C2. For example, the
nominal 3 kΩ RF with a 360 pF capacitor for C1 and C2 will
place a pole at approximately 147 kHz, effectively eliminating
all high frequency noise components.
Figure 10 illustrates an 18-bit CD player design incorporating
an AD1865 D/A converter, an NE5532 dual op amp and the
SM5813 digital filter chip manufactured by NPC. In this de-
sign, the SM5813 filter transmits left and right digital data to
both channels of the AD1865. The left and right latch signals,
LL and LR, are both provided by the word clock signal
(WCKO) of the digital filter. The digital filter supplies data at
an 8 × FS oversample rate to each channel.
Low distortion, superior channel separation, low power con-
sumption and a low parts count are all realized by this simple
design.
The digital data is converted to analog output voltages by the
output amplifiers on the AD1865. Note that no external compo-
nents are required by the AD1865. Also, no deglitching cir-
cuitry is required.
–8–
REV. 0
AD1865
MULTICHANNEL DIGITAL KEYBOARD DESIGN
In this application, the advantages of choosing the AD1865 are
clear. Its flexible digital interface allows the clock and data to be
shared among all DACs. This reduces PC board area require-
ments and also simplifies the actual layout of the board. The low
power requirements of the AD1865 (approximately 225 mW) is
an advantage in a multiple DAC system where any power advan-
tage is multiplied by the number of DACs used. The AD1865
requires no external components, simplifying the design, reduc-
ing the total number of components required and enhancing
reliability.
Figure 11 illustrates how to cascade AD1865’s to add multiple
voices to an electronic musical instrument. In this example, the
data and clock signals are shared between all six DACs. As the
data representing an output for a specific voice is loaded, the ap-
propriate DAC is updated. For example, after the 18-bits repre-
senting the next output value for Voice 4 is clocked out on the
data line, then “Voice 4 Load” is pulled low. This produces a
new output for Voice 4. Furthermore, all voices can be returned
to the same output by pulling all six load signals low.
VOICE 1
OUTPUT
VOICE 2
OUTPUT
VOICE 3
OUTPUT
VOICE 4
OUTPUT
VOICE 5
OUTPUT
VOICE 6
OUTPUT
+5V ANALOG
SUPPLY
–5V ANALOG
SUPPLY
AD1865
S
AD1865
S
AD1865
S
–V
+V
S
24
23
22
1
2
3
4
5
6
–V
–V
+V
+V
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
24
1
2
3
4
5
6
S
S
TRIM
MSB
TRIM
TRIM
TRIM
MSB
TRIM
TRIM 23
MSB
22
MSB
MSB
MSB
I
I
I
I
I
I
OUT
OUT
21
20
21
20
19
18
17
16
15
14
13
OUT
OUT
OUT
OUT
AGND
SJ
AGND
SJ
AGND
SJ
AGND
SJ
AGND
SJ
AGND
SJ
ANALOG
COMMON
19
18
17
16
15
14
13
R
F
7
8
R
F
R
F
7
8
R
F
7
8
R
F
R
F
V
V
V
V
OUT
V
OUT
V
OUT
OUT
OUT
OUT
9
NC
DL
9
+V
L
NC
DL
9
NC
DL
+V
L
+V
L
10
10
DR
10
DR
DR
LR
11
12
LL
LR
11
12
VOICE 6 LOAD
LR
LL
11
LL
VOICE 1 LOAD
DGND
CLK
CLK
DGND
12 CLK
DGND
VOICE 5 LOAD
VOICE 4 LOAD
VOICE 2 LOAD
VOICE 3 LOAD
DATA
CLOCK
DIGITAL COMMON
+5V DIGITAL SUPPLY
Figure 11. Cascaded AD1865s in a Multichannel Keyboard Instrument
REV. 0
–9–
AD1865
ADDITIONAL APPLICATIONS
–5V ANALOG
SUPPLY
+5V ANALOG
SUPPLY
Figures 12 through 14 show connection diagrams for the AD1865
and standard digital filter chips from Yamaha, NPC and Sony.
Each figure is an example of cophase operation operating at 8 ×
FS for each channel. The 2-pole Rauch low-pass filters shown in
Figure 10 can be used with all of the applications shown in this
data sheet.
AD1865
24
1
2
+V
–V
S
S
RIGHT
CHANNEL
OUTPUT
23
22
21
20
19
18
17
16
TRIM
TRIM
LPF
LPF
3
4
MSB
MSB
I
I
OUT
OUT
5
AGND
SJ
AGND
YM3434
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
6
SHL
SHR
SJ
LEFT
CHANNEL
OUTPUT
R
F
7
R
F
16/18
ST
V
V
8
OUT
OUT
9
NC
+V
L
V
V
DD2
DD1
SS
10
11
12
DL 15
DR
LR
BCO
WCO
DRO
DLO
14
13
LL
DGND
CLK
V
TEST 40
TEST 39
TEST 38
1
2
GND
+5V ANALOG
SUPPLY
–5V ANALOG
SUPPLY
TEST
+5V DIGITAL SUPPLY
3
4
37
TEST
Figure 12. AD1865 with Yamaha YM3434 Digital Filter
AD1865
+V 24
1
2
3
4
5
6
7
8
9
5
36
–V
S
S
CXD1244S
RIGHT
CHANNEL
OUTPUT
23
22
21
20
19
18
17
TRIM
MSB
6
35
34
33
32
31
30
29
28
TRIM
LPF
LPF
7
MSB
I
I
8
OUT
BCKO
OUT
16.9344
MHz
9
AGND AGND
DATAL
GND
XIN
SJ
SJ
10
11
12
13
14
15
16
V
DD
LEFT
CHANNEL
OUTPUT
R
V
R
V
GND
F
DD
F
V
DATAR
OUT
OUT
+V
NC 16
DL 15
LL 14
L
10 DR
LE/WS 27
11
12
26
25
24
23
22
21
LR
OUT 16/18
CLK
DGND 13
17 LFS
DPOL
18
19
20
SONY/12S
TEST
–5V ANALOG
SUPPLY
+5V ANALOG
SUPPLY
TEST TEST
AD1865
–VS
24
23
+V
1
2
3
4
5
6
7
8
9
+5V DIGITAL SUPPLY
S
RIGHT
TRIM
MSB
TRIM
MSB
LPF
CHANNEL
OUTPUT
Figure 13. AD1865 with Sony CXD1244s Digital Filter
22
21
20
19
18
17
16
I
I
OUT
OUT
AGND AGND
SM5818
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SJ
SJ
R
DD
LEFT
LPF
CHANNEL
OUTPUT
R
BCKO
WDCO
OMOD2
DOR
F
F
OUT
NC
V
V
OUT
+V
L
DL 15
14
10 DR
11
12
LL
DGND 13
DOL
LR
CLK
V
OMOD1
SS
+5V DIGITAL SUPPLY
Figure 14. AD1865 with NPC SM5818AP Digital Filter
–10–
REV. 0
AD1865
OTHER DIGITAL AUDIO COMPONENTS AVAILABLE
FROM ANALOG DEVICES
AD1856 16-BIT AUDIO DAC
Complete, No External Components Required
0.0025% THD
Low Cost
16-Pin DIP or SOIC Package
Standard Pinout
16-BIT
LATCH
16-BIT
DAC
1
2
–V
16 +V
S
S
DGND
+V
15 TRIM
SERIAL
INPUT
REGISTER
3
14 MSB ADJ
L
I
13 I
OUT
NC
4
5
OUT
CLK
12 AGND
11 SJ
REF
CONTROL
LOGIC
6
7
8
LE
10
9
R
DATA
F
AD1856
–V
V
OUT
L
=
NC NO CONNECT
AD1860 18-BIT AUDIO DAC
Complete, No External Components Required
0.0025% THD+N
108 dB Signal-to-Noise Ratio
16-Pin DIP or SOIC Package
Standard Pinout
18-BIT
LATCH
18-BIT
DAC
1
–V
16 +V
S
S
2
3
DGND
+V
15 TRIM
SERIAL
INPUT
REGISTER
14 MSB ADJ
L
I
13 I
OUT
NC
4
5
OUT
CLK
12 AGND
11 SJ
REF
CONTROL
LOGIC
6
7
8
LE
10
9
R
DATA
F
AD1860
–V
V
OUT
L
=
NC NO CONNECT
AD1862 20-BIT AUDIO DAC
119 dB Signal-to-Noise Ratio
0.0016% THD+N
1
2
–V
–V
VOLTAGE
REFERENCE
16 +V
S
S
15
NR
S
2
102 dB D-Range Performance
±1 dB Gain Linearity
16-Pin DIP Package
3
TRIM
14 ADJ
13
4
5
NR
+V
L
1
CLK
12 AGND
INPUT
&
DIGITAL
OFFSET
20-BIT
DAC
11
10
I
OUT
6
7
8
LE
R
DATA
F
–V
L
9
DGND
AD1862
AD1868
AD1868 +5 V SINGLE SUPPLY DUAL 18-BIT
AUDIO DAC
No External Components Required
0.004% THD+N
92 dB D-Range Performance
±3 dB Gain Linearity
16-Pin DIP or SOIC Package
18-BIT
DAC
V
V
L
V
L
1
16
15
BIAS
2
3
V
LL
DL
S
18-BIT
SERIAL
REGISTER
L
14
OUT
V
CLK
DR
13 NRL
4
5
REF
AGND
18-BIT
SERIAL
12
REGISTER
V
REF
11 NRR
LR
6
7
8
10
9
DGND
V
R
18-BIT
DAC
OUT
V
R
V
BIAS
S
REV. 0
–11–
AD1865
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Plastic DIP
(N-24A) Package
24
13
0.580 (14.73)
0.485 (12.32)
PIN 1
1
12
1.290 (32.70)
1.150 (29.30)
0.625 (15.87)
0.600 (15.24)
0.060 (1.52)
0.195 (4.95)
0.125 (3.18)
0.015 (0.38)
0.250 (6.35)
SEATING
PLANE
0.015 (0.381)
0.008 (0.204)
0.200 (5.05)
0.125 (3.18)
0.150
(3.81)
0.100 (2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.030 (0.77)
28-Pin SOIC
(R-28) Package
0.708 (18.02)
0.696 (17.67)
28
15
0.299 (7.6)
0.291 (7.39)
0.414 (10.52)
0.398 (10.10)
14
1
0.003 (0.76)
0.02 (0.51)
0.096 (2.44)
0.089 (2.26)
6°
0°
0.019 (0.49)
0.014 (0.35)
0.050 (1.27) BSC
0.042 (0.32)
0.009 (0.23)
0.01 (0.254)
0.006 (0.15)
0.013 (0.32)
0.009 (0.23)
–12–
REV. 0
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