AD1886 [ADI]

AC’97 SoundMAX Codec; AC'97的SoundMAX编解码器
AD1886
型号: AD1886
厂家: ADI    ADI
描述:

AC’97 SoundMAX Codec
AC'97的SoundMAX编解码器

解码器 编解码器
文件: 总28页 (文件大小:276K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
®
a
AC’97 SoundMAX Codec  
AD1886A  
Stereo Line Level Outputs  
AC’97 2.1 FEATURES  
Mono Output for Speakerphone or Internal Speaker  
Power Management Support  
48-Terminal LQFP Package  
Variable Sample Rate Audio  
Multiple Codec Configuration Options  
External Audio Power-Down Control  
AC’97 FEATURES  
ENHANCED FEATURES  
AC’97 2.2 Compliant  
Greater than 90 dB Dynamic Range  
Stereo Headphone Amplifier  
Multibit -Converter Architecture for Improved S/N  
Ratio Greater than 90 dB  
16-Bit Stereo Full-Duplex Codec  
Four Analog Line-Level Stereo Inputs for:  
LINE-IN, CD, VIDEO, and AUX  
Two Analog Line-Level Mono Inputs for Speakerphone  
and PC BEEP  
Mono MIC Input w/Built-In 20 dB Preamp, Switchable  
from Two External Sources  
20-Bit SPDIF Output w/32 kHz, 44.1 kHz, and 48 kHz  
Symbol Rates  
Full Duplex Variable Sample Rates from 7040 Hz to  
48 kHz with 1 Hz Resolution  
Jack Sense Pins Provide Automatic Output Switching  
Software-Enabled VREFOUT Output for Microphones and  
External Power Amp  
Split Power Supplies (3.3 V Digital/5 V Analog)  
Mobile Low-Power Mixer Mode  
Extended 6-Bit Master Volume Control  
Extended 6-Bit Headphone Volume Control  
Digital Audio Mixer Mode  
High-Quality CD Input with Ground Sense  
Phat™ Stereo 3D Stereo Enhancement  
FUNCTIONAL BLOCK DIAGRAM  
SPDIF  
JS  
ID1  
ID0  
VREF  
V
REFOUT  
AD1886A  
SPDIF  
OUT  
CHIP SELECT  
JACK SENSE  
MIC1  
MIC2  
0dB/  
20dB  
LINE  
AUX  
CD  
16-BIT  
-A/D  
CONVERTER  
PGA  
PGA  
16-BIT  
-A/D  
CONVERTER  
RESET  
VIDEO  
PHONE_IN  
SYNC  
SAMPLE  
RATE  
GENERATORS  
MONO_OUT  
MV  
BIT_CLK  
G
A
M
G
G
A
M
G
A
M
G
A
M
G
A
M
A
M
HP_OUT_L  
MV  
SDATA_OUT  
G
16-BIT  
-D/A  
CONVERTER  
PHAT  
STEREO  
A
LINE_OUT_L  
MV  
M
SDATA_IN  
G
A
M
16-BIT  
-D/A  
CONVERTER  
PHAT  
STEREO  
LINE_OUT_R  
MV  
MV  
A
M
G = GAIN  
HP_OUT_R  
PC_BEEP  
A = ATTENUATE  
M = MUTE  
OSCILLATOR  
XTAL_OUT  
XTAL_IN  
SoundMAX is a registered trademark and Phat is a trademark of Analog Devices, Inc.  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2001  
AD1886A–SPECIFICATIONS  
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED  
Temperature  
Digital Supply (VDD  
25°C  
3.3 V  
DAC Test Conditions  
)
Calibrated  
Analog Supply (VCC  
Sample Rate (fS)  
Input Signal  
Analog Output Pass Band  
VIH  
VIL  
)
5.0 V  
–3 dB Attenuation Relative to Full Scale  
Input 0 dB  
10 kOutput Load (LINE_OUT)  
32 Output Load (HP_OUT)  
48 kHz  
1008 Hz  
20 Hz to 20 kHz  
2.0 V  
0.8 V  
4.0 V  
ADC Test Conditions  
Calibrated  
V
IH (CS0, CS1, CHAIN_IN)  
VIL  
1.0 V  
0 dB Gain  
Input –3.0 dB Relative to Full Scale  
ANALOG INPUT  
Parameter  
Min  
Typ  
Max  
Unit  
Input Voltage (RMS Values Assume Sine Wave Input)  
LINE_IN, AUX, CD, VIDEO, PHONE_IN, PC_BEEP  
1
V rms  
V p-p  
V rms  
V p-p  
V rms  
V p-p  
kΩ  
2.83  
0.1  
0.283  
1
2.83  
20  
MIC1 or MIC2 with +20 dB Gain (M20 = 1)  
MIC1 or MIC2 with 0 dB Gain (M20 = 0)  
Input Impedance*  
Input Capacitance*  
5
7.5  
pF  
MASTER VOLUME  
Parameter  
Min  
Typ  
Max  
Unit  
Step Size (0 dB to –94.5 dB); LINE_OUT_L, LINE_OUT_R  
Output Attenuation Range Span*  
Step Size (0 dB to –46.5 dB); MONO_OUT  
Output Attenuation Range Span*  
Step Size (+6 dB to –88.5 dB); HP_OUT_R, HP_OUT_L  
Output Attenuation Range Span*  
Mute Attenuation of 0 dB Fundamental*  
1.5  
–94.5  
1.5  
–46.5  
1.5  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
–94.5  
80  
PROGRAMMABLE GAIN AMPLIFIER—ADC  
Parameter  
Min  
Min  
Typ  
Max  
Unit  
Step Size (0 dB to 22.5 dB)  
PGA Gain Range Span  
1.5  
22.5  
dB  
dB  
ANALOG MIXER—INPUT GAIN / AMPLIFIERS / ATTENUATORS  
Parameter  
Typ  
Max  
Unit  
Signal-to-Noise Ratio (SNR)  
CD to LINE_OUT  
Other to LINE_OUT  
90  
90  
dB  
dB  
Step Size (+12 dB to –34.5 dB): (All Steps Tested)  
MIC, LINE_IN, AUX, CD, VIDEO, PHONE_IN, DAC  
Input Gain/Attenuation Range:  
MIC, LINE, AUX, CD, VIDEO, PHONE_IN, DAC  
Step Size (0 dB to –45 dB): (All Steps Tested)  
PC_BEEP  
1.5  
dB  
dB  
–46.5  
3.0  
–45  
dB  
dB  
Input Gain/Attenuation Range: PC_BEEP  
*Guaranteed but not tested.  
–2–  
REV. 0  
AD1886A  
DIGITAL DECIMATION AND INTERPOLATION FILTERS*  
Parameter  
Min  
Typ  
Max  
Unit  
Pass Band  
Pass-Band Ripple  
Transition Band  
Stop Band  
Stop-Band Rejection  
Group Delay  
0
0.4 × fS  
0.09  
0.6 × fS  
Hz  
dB  
Hz  
Hz  
dB  
sec  
µs  
0.4 × fS  
0.6 × fS  
–74  
12/fS  
0.0  
Group Delay Variation over Pass Band  
ANALOG-TO-DIGITAL CONVERTERS  
Parameter  
Min  
Typ  
Max  
Unit  
Resolution  
Total Harmonic Distortion (THD)  
Dynamic Range (–60 dB input THD + N Referenced to Full Scale, A-Weighted)  
Signal-to-Intermodulation Distortion* (CCIF Method)  
ADC Crosstalk*  
16  
–84  
87  
85  
Bits  
dB  
dB  
dB  
84  
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)  
LINE_IN to Other  
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)  
Interchannel Gain Mismatch (Difference of Gain Errors)  
ADC Offset Error  
–100  
–90  
–90  
–85  
10  
0.5  
5
dB  
dB  
%
dB  
mV  
DIGITAL-TO-ANALOG CONVERTERS  
Parameter  
Min  
Typ  
Max  
Unit  
Resolution  
16  
Bits  
dB  
dB  
dB  
dB  
%
Total Harmonic Distortion (THD) LINE_OUT  
Total Harmonic Distortion (THD) HP_OUT  
–85  
–75  
90  
–100  
10  
Dynamic Range (–60 dB Input THD + N Referenced to Full Scale, A-Weighted)  
Signal-to-Intermodulation Distortion* (CCIF Method)  
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)  
Interchannel Gain Mismatch (Difference of Gain Errors)  
DAC Crosstalk* (Input L, Zero R, Measure R_OUT; Input R, Zero L,  
Measure L_OUT)  
85  
0.7  
–80  
dB  
dB  
Total Audible Out-of-Band Energy (Measured from 0.6 × fS to 20 kHz)*  
–40  
dB  
ANALOG OUTPUT  
Parameter  
Min  
Typ  
Max  
Unit  
Full-Scale Output Voltage; LINE_OUT  
1
2.83  
V rms  
V p-p  
Output Impedance*  
800  
External Load Impedance*  
Output Capacitance*  
External Load Capacitance  
Full-Scale Output Voltage; HP_OUT (0 dB Gain)  
Output Capacitance*  
External Load Impedance*  
VREF  
10  
kΩ  
15  
1
pF  
pF  
V rms  
pF  
V
V
mA  
100  
100  
2.45  
5
32  
2.05  
2.25  
2.25  
VREF_OUT  
V
REF _OUT Current Drive  
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)  
5
mV  
*Guaranteed but not tested.  
–3–  
REV. 0  
AD1886A–SPECIFICATIONS  
STATIC DIGITAL SPECIFICATIONS  
Parameter  
Min  
Typ  
Max  
Unit  
High-Level Input Voltage (VIH): Digital Inputs  
Low-Level Input Voltage (VIL)  
High-Level Output Voltage (VOH), IOH = 2 mA  
Low-Level Output Voltage (VOL), IOL = 2 mA  
Input Leakage Current  
0.65 × DVDD  
V
V
V
V
µA  
µA  
0.35 × DVDD  
0.9 × DVDD  
0.1 × DVDD  
+10  
+10  
–10  
–10  
Output Leakage Current  
POWER SUPPLY  
Parameter  
Min  
Typ  
Max  
Unit  
Power Supply Range—Analog (AVDD  
Power Supply Range—Digital (DVDD  
Power Dissipation—5 V/3.3 V  
)
)
4.75  
3.0  
5.0  
3.3  
306  
48  
20  
40  
5.25  
3.6  
V
V
mW  
mA  
mA  
dB  
Analog Supply Current—5 V (AVDD  
)
Digital Supply Current—3.3 V (DVDD  
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*  
)
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)  
CLOCK SPECIFICATIONS*  
Parameter  
Min  
Typ  
Max  
Unit  
Input Clock Frequency  
Recommended Clock Duty Cycle  
24.576  
50  
MHz  
%
40  
60  
POWER-DOWN STATES  
Parameter  
Set Bits  
DVDD Typ  
AVDD Typ  
Unit  
ADC  
DAC  
PR0  
PR1  
17.5  
17.0  
4.1  
4.1  
20  
17.6  
17  
4.1  
4.1  
0
41.6  
38.3  
31.9  
22.4  
17.5  
11.2  
8.4  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
ADC + DAC  
ADC + DAC + Mixer (Analog CD On)  
Mixer  
ADC + Mixer  
DAC + Mixer  
ADC + DAC + Mixer  
Analog CD Only (AC-Link On)  
Analog CD Only (AC-Link Off)  
Standby  
PR1, PR0  
LPMIX, PR1, PR0  
PR2  
PR2, PR0  
PR2, PR1  
PR2, PR1, PR0  
LPMIX, PR5, PR1, PR0  
LPMIX, PR1, PR0, PR4, PR5  
PR5, PR4, PR3, PR2, PR1, PR0  
PR6  
2.2  
22.4  
22.4  
0
0
20  
Headphone Standby  
38.8  
*Guaranteed but not tested.  
Specifications subject to change without notice.  
–4–  
REV. 0  
AD1886A  
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
RESET Active Low Pulsewidth  
RESET Inactive to BIT_CLK Startup Delay  
SYNC Active High Pulsewidth  
SYNC Low Pulsewidth  
SYNC Inactive to BIT_CLK Startup Delay  
BIT_CLK Frequency  
BIT_CLK Period  
BIT_CLK Output Jitter*  
BIT_CLK High Pulsewidth  
BIT_CLK Low Pulsewidth  
SYNC Frequency  
tRST_LOW  
tRST2CLK  
tSYNC_HIGH  
tSYNC_LOW  
tSYNC2CLK  
1.0  
µs  
162.8  
ns  
ms  
µs  
1.3  
19.5  
162.8  
ns  
MHz  
ns  
ps  
ns  
ns  
kHz  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
12.288  
81.4  
tCLK_PERIOD  
750  
48.84  
48.84  
tCLK_HIGH  
tCLK_LOW  
32.56  
32.56  
42  
38  
48.0  
20.8  
2.5  
SYNC Period  
tSYNC_PERIOD  
tSETUP  
tHOLD  
Setup to Falling Edge of BIT_CLK  
Hold from Falling Edge of BIT_CLK  
BIT_CLK Rise Time  
BIT_CLK Fall Time  
SYNC Rise Time  
SYNC Fall Time  
SDATA_IN Rise Time  
SDATA_IN Fall Time  
SDATA_OUT Rise Time  
5
5
2
2
2
2
2
2
2
2
0
15  
tRISECLK  
tFALLCLK  
tRISESYNC  
tFALLSYNC  
tRISEDIN  
tFALLDIN  
tRISEDOUT  
tFALLDOUT  
tS2_PDOWN  
tSETUP2RST  
tOFF  
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
SDATA_OUT Fall Time  
End of Slot 2 to BIT_CLK, SDATA_IN Low  
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)  
Rising Edge of RESET to HI-Z Delay  
Propagation Delay  
RESET Rise Time  
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid  
1.0  
ns  
ns  
ns  
ns  
ns  
25  
15  
50  
15  
*Guaranteed but not tested.  
Specifications subject to change without notice.  
REV. 0  
–5–  
AD1886A  
tRST_LOW  
tRST2CLK  
BIT_CLK  
SYNC  
RESET  
tRISECLK  
tFALLCLK  
tFALLSYNC  
tFALLDIN  
BIT_CLK  
tRISESYNC  
Figure 1. Cold Reset  
SDATA_IN  
tRISEDIN  
tRST2CLK  
tSYNC_HIGH  
SYNC  
SDATA_OUT  
BIT_CLK  
tRISEDOUT  
tFALLDOUT  
Figure 5. Signal Rise and Fall Time  
Figure 2. Warm Reset  
tCLK_LOW  
SLOT 1  
SLOT 2  
BIT_CLK  
SYNC  
tCLK_HIGH  
tCLK_PERIOD  
BIT_CLK  
tSYNC_LOW  
WRITE  
TO 0x26  
DATA  
PR4  
DON’T  
CARE  
SYNC  
SDATA_OUT  
SDATA_IN  
tS2_PDOWN  
tSYNC_HIGH  
tSYNC_PERIOD  
NOTE: BIT_CLK NOTTO SCALE  
Figure 6. AC Link Low Power Mode Timing  
Figure 3. Clock Timing  
tSETUP  
RESET  
BIT_CLK  
SYNC  
SDATA_OUT  
tSETUP2RST  
SDATA_OUT  
SDATA_IN, BIT_CLK  
HI-Z  
tHOLD  
tOFF  
Figure 7. ATE Test Mode  
Figure 4. Data Setup and Hold  
–6–  
REV. 0  
AD1886A  
ABSOLUTE MAXIMUM RATINGS*  
ORDERING GUIDE  
Temperature Package  
Parameter  
Min Max  
Unit  
Package  
Option*  
Model  
Range  
Description  
Power Supplies  
Digital (DVDD  
)
–0.3 +3.6  
–0.3 +6.0  
V
V
mA  
AD1886AJST 0°C to 70°C  
48-Lead LQFP  
ST-48  
Analog (AVCC  
)
*ST = Thin Quad Flatpack.  
Input Current (Except Supply Pins)  
10.0  
Analog Input Voltage (Signal Pins) –0.3 AVDD + 0.3  
Digital Input Voltage (Signal Pins) –0.3 DVDD + 0.3  
V
V
°C  
°C  
ENVIRONMENTAL CONDITIONS  
Ambient Temperature Rating  
Ambient Temperature (Operating)  
Storage Temperature  
0
70  
–65 +150  
TAMB = TCASE – (PD × θCA  
CASE = Case Temperature in °C  
PD = Power Dissipation in W  
)
*Stresses greater than those listed under Absolute Maximum Ratings may cause  
permanent damage to the device. This is a stress rating only; functional operation  
of the device at these or any other conditions above those indicated in the  
operational section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
T
θ
θ
θ
CA = Thermal Resistance (Case-to-Ambient)  
JA = Thermal Resistance (Junction-to-Ambient)  
JC = Thermal Resistance (Junction-to-Case)  
Package  
JA  
JC  
CA  
LQFP  
76.2°C/W  
17°C/W  
59.2°C/W  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection. Although  
the AD1886A features proprietary ESD protection circuitry, permanent damage may occur on  
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are  
recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
REV. 0  
–7–  
AD1886A  
PIN CONFIGURATION  
48 47 46 45 44 43 42 41 40 39 38 37  
1
2
DV  
DD1  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
LINE_OUT_R  
LINE_OUT_L  
CX3D  
PIN 1  
IDENTIFIER  
XTL_IN  
3
XTL_OUT  
4
DV  
RX3D  
SS1  
5
SDATA_OUT  
BIT_CLK  
FILT_L  
AD1886A  
6
FILT_R  
TOP VIEW  
7
DV  
AFILT2  
SS2  
(Not to Scale)  
8
SDATA_IN  
AFILT1  
9
DV  
V
DD2  
REFOUT  
10  
11  
12  
SYNC  
V
REF  
RESET  
PC_BEEP  
AV  
AV  
SS1  
DD1  
13 14 15 16 17 18 19 20 21 22 23 24  
NC = NO CONNECT  
PIN FUNCTION DESCRIPTIONS  
Description  
Digital I/O  
Pin Name  
LQFP  
I/O  
XTL_IN  
2
3
5
6
I
O
I
O/I  
O
I
Crystal (or Clock) Input, 24.576 MHz.  
Crystal Output  
AC-Link Serial Data Output, AD1886A Input Stream.  
AC-Link Bit Clock. 12.288 MHz Serial Data Clock. Daisy-Chain Output Clock.  
AC-Link Serial Data Input. AD1886A Output Stream.  
AC-Link Frame Sync  
XTL_OUT  
SDATA_OUT  
BIT_CLK  
SDATA_IN  
SYNC  
RESET  
SPDIF  
8
10  
11  
48  
I
O
AC-Link Reset. AD1886A Master H/W Reset.  
SPDIF Output  
CHIP SELECTS  
Pin Name  
LQFP  
Type  
Description  
ID0  
ID1  
45  
46  
I
I
Chip Select Input 0 (Active Low)  
Chip Select Input 1 (Active Low)  
JACK SENSE/GENERAL-PURPOSE DIGITAL OUTPUT  
The JS pin can be used to sense the presence of an audio plug in the output jacks and automatically mute the MONO and/or  
LINE_OUT audio outputs. Alternatively, the JS can be programmed as a general-purpose digital output pin.  
Pin Name  
LQFP  
Type  
Description  
JS  
47  
I/O  
JACK SENSE Input, or GPIO.  
–8–  
REV. 0  
AD1886A  
Analog I/O  
These signals connect the AD1886A component to analog sources and sinks, including microphones and speakers.  
Pin Name  
LQFP  
I/O  
Description  
PC_BEEP  
PHONE  
AUX_L  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
35  
36  
37  
39  
41  
I
I
I
I
I
I
I
I
I
I
I
I
PC Beep. PC Speaker beep passthrough.  
Phone. From telephony subsystem speakerphone or handset.  
Auxiliary Input Left Channel  
Auxiliary Input Right Channel  
Video Audio Left Channel  
Video Audio Right Channel  
CD Audio Left Channel  
CD Audio Analog Ground Reference for CD Input  
CD Audio Right Channel  
Microphone 1. Desktop microphone input.  
Microphone 2. Second microphone input.  
Line In, Left Channel.  
Line In, Right Channel.  
Line Out, Left Channel.  
Line Out, Right Channel.  
Monaural Output to Telephony Subsystem Speakerphone  
Headphones Out, Left Channel.  
Headphones Out, Right Channel.  
AUX_R  
VIDEO_L  
VIDEO_R  
CD_L  
CD_GND_REF  
CD_ R  
MIC1  
MIC2  
LINE_IN_L  
LINE_IN_R  
LINE_OUT_L  
LINE_OUT_R  
MONO_OUT  
HP_OUT_L  
HP_OUT_R  
I
O
O
O
O
O
Filter/Reference  
These signals are connected to resistors, capacitors, or specific voltages.  
Pin Name  
LQFP  
I/O  
Description  
VREF  
27  
28  
29  
30  
31  
32  
33  
34  
O
O
O
O
O
O
O
I
Voltage Reference Filter  
VREFOUT  
AFILT1  
AFLIT2  
FILT_R  
FILT_L  
RX3D  
Voltage Reference Output 5 mA Drive. (Intended for Mic Bias.)  
Antialiasing Filter Capacitor—ADC Right Channel.  
Antialiasing Filter Capacitor—ADC Left Channel.  
AC-Coupling Filter Capacitor—ADC Right Channel.  
AC-Coupling Filter Capacitor—ADC Left Channel.  
3D Phat Stereo Enhancement—Resistor.  
CX3D  
3D Phat Stereo Enhancement—Capacitor.  
Power and Ground Signals  
Pin Name  
DVDD  
DVSS1  
DVSS  
DVDD2  
AVDD1  
LQFP  
Type  
Description  
1
1
4
7
9
25  
26  
38  
40  
43  
44  
I
I
I
I
I
I
I
I
I
I
Digital VDD 3.3 V  
Digital GND  
Digital GND  
Digital VDD 3.3 V  
Analog VDD 5.0 V  
Analog GND  
Analog VDD 5.0 V  
Analog GND  
2
AVSS  
1
AVDD2  
AVSS2  
AVDD  
AVSS  
3
3
Analog VDD 5.0 V  
Analog GND  
No Connects  
Pin Name  
LQFP  
Type  
Description  
NC  
42  
No Connect  
REV. 0  
–9–  
AD1886A  
JS  
SPDIF  
SPDIF  
AD1886A  
0x3A  
0x2A  
0x28  
0x72  
JACK SENSE  
0x72  
0
MIC1  
MIC2  
0dB/20dB  
M20 0x0E  
MS  
LS/RS (0)  
LS (4)  
1
S 0x20  
LINE_IN  
AUX  
RS (4)  
GM 0x1C  
LIV  
IM  
RS (3)  
16-BIT  
-A/D  
LS (3)  
S
E
L
E
C
T
O
R
LS (1)  
RS (1)  
CD  
LS (2)  
RS (2)  
VIDEO  
PHONE_IN  
GM 0x1C  
RIV  
IM  
LS/RS (7)  
16-BIT  
A/D  
-
LS (5)  
LS/RS (6)  
RESET  
RS (5)  
S 0x1A  
SYNC  
GA 0x0C  
PHV  
GA 0x0E GA 0x10 GA 0x12 GA 0x16 GA 0x14  
MCV  
LLV  
RLA  
LCV  
RCV  
LAV  
RAV  
LVV  
RVV  
BIT_CLK  
M
0x0C  
M
0x0E  
M
0x10  
M
0x12  
M
0x16  
M
0x14  
PHM  
SDATA_OUT  
SDATA_IN  
MCM  
LM  
CM  
AM  
VM  
0x04  
HPM  
0x04  
LHV  
HP_OUT_L  
GAM 0x18  
LOV  
OM  
16-BIT  
D/A  
M
0x02  
A
0x02  
-
3D 0x22  
POP3D  
LINE_OUT_L  
MONO_OUT  
LINE_OUT_R  
MM  
LMV  
MIX  
M
0x06  
A
0x06  
0
1
D
A
M
3D 0x20  
SWITCH  
MMM  
MMV  
S 0x20  
A
0x02  
M
0x02  
3D 0x22  
POP3D  
GAM 0x18  
16-BIT  
D/A  
MM  
RMV  
ROV  
OM  
-
0x04  
HPM  
0x04  
RHV  
HP_OUT_R  
PC_BEEP  
M 0x0A  
PCM  
A 0x0A  
PCV  
OSCILLATORS  
XTL_OUT  
XTL_IN  
Figure 8. Block Diagram Register Map  
–10–  
REV. 0  
AD1886A  
Indexed Control Registers  
Reg  
Num  
Name  
D15  
X
D14  
SE4  
X
D13  
D12  
D11  
D10  
D9  
D8  
D7  
ID7  
X
D6  
ID6  
X
D5  
D4  
D3  
D2  
D1  
D0  
Default  
00h  
02h  
04h  
06h  
08h  
0Ah  
0Ch  
0Eh  
10h  
12h  
14h  
16h  
18h  
1Ah  
1Ch  
20h  
22h  
26h  
28h  
2Ah  
Reset  
SE3  
SE2  
SE1  
SE0  
ID9  
ID8  
ID5  
ID4  
ID3  
ID2  
ID1  
ID0  
0410h  
Master Volume  
Headphones Volume  
MM  
HPM  
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0  
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h  
RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h  
MMV4 MMV3 MMV2 MMV1 MMV0 8000h  
X
LHV5  
X
LHV4  
X
LHV3  
X
LHV2 LHV1 LHV0  
X
X
Master Volume Mono MMM  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reserved  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PC Beep Volume  
Phone-In Volume  
Mic Volume  
PCM  
PHM  
MCM  
LM  
CVM  
VM  
AM  
OM  
X
X
X
X
X
X
X
PCV3  
PHV4  
PCV2  
PHV3  
PCV1 PCV0  
8000h  
X
X
X
X
X
X
PHV2 PHV1 PHV0 8008h  
X
X
X
X
X
M20  
X
MCV4 MCV3 MCV2 MCV1 MCV0 8008h  
Line-In Volume  
CD Volume  
X
X
LLV4  
LCV4  
LVV4  
LAV4  
LOV4  
X
LLV3  
LCV3  
LVV3  
LAV3  
LOV3  
X
LLV2 LLV1 LLV0  
LCV2 LCV1 LCV0  
LVV2 LVV1 LVV0  
LAV2 LAV1 LAV0  
LOV2 LOV1 LOV0  
X
RLV4  
RCV4  
RVV4  
RAV4  
ROV4  
X
RLV3  
RLV2 RLV1 RLV0 8808h  
X
X
X
X
RCV3 RCV2 RCV1 RCV0 8808h  
Video Volume  
Aux Volume  
X
X
X
X
RVV3  
RAV3  
RVV2 RVV1 RVV0 8808h  
RAV2 RAV1 RAV0 8808h  
X
X
X
X
PCM Out Vol  
Record Select  
Record Gain  
X
X
X
X
ROV3 ROV2 ROV1 ROV0 8808h  
X
X
LS2  
LS1  
LS0  
X
X
X
RS2  
RS1  
RS0  
0000h  
IM  
X
X
X
LIM3  
X
LIM2 LIM1 LIM0  
X
X
X
RIM3  
X
RIM2 RIM1 RIM0 8000h  
General-Purpose  
3D Control  
POP  
X
X
3D  
X
X
X
MIX  
X
MS  
X
LPBK  
X
X
X
X
X
X
0000h  
0000h  
000Xh  
0005h  
0000h  
BB80h  
X
X
X
X
X
X
DP3  
REF  
X
DP2  
ANL  
SPDF  
SPDIF  
SR2  
DP1  
DP0  
Power-Down Ctrl/Stat  
Ext’d Audio ID  
Ext’d Audio Stat/Ctrl  
X
X
PR5  
X
PR4  
X
PR3  
X
PR2  
X
PR1  
X
PR0  
X
X
X
X
DAC ADC  
ID1  
X
ID0  
X
X
X
X
X
VRA  
VRA  
SR0  
X
X
X
SPCV  
SR10  
X
X
X
X
SPSA1 SPSA0  
X
X
2Ch/  
(7Ah)*  
PCM DAC Rate (SR1) SR15  
SR14  
SR13  
SR12  
SR11  
SR9  
SR8  
SR7  
SR6  
SR5  
SR5  
CC1  
SR4  
SR4  
CC0  
SR3  
SR1  
32h/  
(78h)*  
PCM ADC Rate (SR0) SR15  
SR14  
X
SR13  
SR12  
SR11  
SR10  
CC6  
SR9  
SR8  
SR7  
SR6  
SR3  
SR2  
SR1  
SR0  
BB80h  
3Ah  
72h  
74h  
76h  
SPDIF Control  
V
SPSR1 SPSR0  
SPRZ JSPD  
L
CC5  
CC4  
CC3  
X
CC2  
JSC  
X
PRE  
VWI  
X
COPY AUD PRO  
0000h  
0000h  
7000h  
Jack Sense/SPDIF  
Serial Configuration  
Misc Control Bits  
SPMIX JSOD  
X
JSOE JSLM JSD  
JSMM JSM  
JS1  
JS0  
X
JSI  
X
SLOT16 REGM2 REGM1 REGM0 DRQEN  
X
X
X
X
X
X
X
X
X
DACZ  
LPMIX  
X
DAM  
DMS  
DLSR  
ALSR MOD SRX1 SRX8  
X
DRSR  
X
ARSR 0404h  
EN  
0D7  
D7  
7Ch  
Vendor ID1  
Vendor ID2  
F7  
T7  
F6  
T6  
F5  
T5  
F4  
T4  
F3  
T3  
F2  
T2  
F1  
T1  
F0  
T0  
S7  
S6  
S5  
S4  
S3  
S2  
S1  
S0  
4144h  
7Eh  
REV7 REV6 REV5 REV4  
REV3  
REV2 REV1 REV0 5363h  
NOTES  
All registers not shown and bits containing an X are assumed to be reserved.  
Odd register addresses are aliased to the next lower even address.  
Reserved registers should not be written.  
Zeros should be written to reserved bits.  
*Indicates Aliased register for AD1819, AD1819A backward compatibility  
REV. 0  
–11–  
AD1886A  
Reset (Index 00h)  
Reg  
Name  
Num  
D15 D14 D13 D12 D11 D10 D9  
SE4 SE3 SE2 SE1 SE0 ID9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Default  
0410h  
00h  
Reset  
X
ID8  
ID7  
ID6  
ID5  
ID4  
ID3  
ID2  
ID1  
ID0  
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except 74h,  
which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo  
Enhancement.  
ID[9:0]  
Identify Capability. The ID decodes the capabilities of AD1886A based on the following:  
Bit = 1  
Function  
AD1886A*  
ID0  
ID1  
ID2  
ID3  
ID4  
ID5  
ID6  
ID7  
ID8  
ID9  
Dedicated Mic PCM in Channel  
Modem Line Codec support  
Bass and Treble Control  
Simulated Stereo (Mono to Stereo)  
Headphone Out Support  
Loudness (Bass Boost) Support  
18-Bit DAC Resolution  
20-Bit DAC Resolution  
18-Bit ADC Resolution  
20-Bit ADC Resolution  
0
0
0
0
1
0
0
0
0
0
*The AD1886A contains none of the optional features identified by these bits.  
SE[4:0]  
Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.  
Master Volume Registers (Index 02h)  
Reg  
Num Name  
D15  
MM  
D14  
X
D13  
D12  
D11  
D10  
D9  
D8  
D7  
X
D6  
X
D5  
D4  
D3  
D2  
D1  
D0  
Default  
Master  
02h  
Volume  
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0  
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h  
RMV[5:0]  
LMV[5:0]  
MM  
Right Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from  
0 dB to a maximum attenuation of –94.5 dB.  
Left Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from  
0 dB to a maximum attenuation of –94.5 dB.  
Master Volume Mute. When this bit is set to “1,” the channel is muted.  
MM  
xMV5 . . . xMV0  
Function  
0
0
0
1
00 0000  
01 1111  
11 1111  
xx xxxx  
0 dB Attenuation  
–46.5 dB Attenuation  
–94.5 dB Attenuation  
dB Attenuation  
–12–  
REV. 0  
AD1886A  
Headphones Volume Registers (Index 04h)  
Reg  
Num Name  
D15 D14 D13 D12 D11 D10 D9  
D8  
D7 D6 D5  
D4  
D3  
D2  
D1  
D0  
Default  
04h  
Headphone Volume HPM X  
LHV5 LHV4 LHV3 LHV2 LHV1 LHV0  
X
X
RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h  
RHV[5:0]  
Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output  
from +6 dB to a maximum attenuation of –88.5 dB.  
LHV[5:0]  
HPM  
Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output  
from +6 dB to a maximum attenuation of –88.5 dB.  
Headphones Volume Mute. When this bit is set to “1,” the channel is muted.  
HPM  
xHV5 . . . xHV0  
Function  
0
0
0
1
00 0000  
01 1111  
11 1111  
xx xxxx  
6 dB Gain  
–40.5 dB Attenuation  
–88.5 dB Attenuation  
dB Attenuation  
Master Volume Mono (Index 06h)  
Reg  
Num Name  
Master Volume  
Mono  
D15  
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5  
D4  
D3  
D2  
D1  
D0  
Default  
06h  
MMM X  
X
X
X
X
X
X
X
X
MMV5 MMV4 MMV3 MMV2 MMV1 MMV0 8000h  
MMV[5:0]  
Mono Master Volume Control. The least significant bit represents 1.5 dB. This register controls the output from  
0 dB to a maximum attenuation of –94.5 dB.  
MMM  
Mono Master Volume Mute. When this bit is set to “1,” the channel is muted.  
PC Beep Register (Index 0Ah)  
Reg  
Num Name  
D15  
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D0 Default  
D3  
D2  
D1  
0Ah PC_BEEP Volume PCM  
X
X
X
X
X
X
X
X
X
X
PCV3 PCV2 PCV1 PCV0 X 8000h  
PCV[3:0]  
PCM  
PC Beep Volume Control. The least significant bit represents 3 dB attenuation. This register controls the output  
from 0 dB to a maximum attenuation of –45 dB. The PC Beep is routed to Left and Right Line outputs even when  
AD1886A is in a RESET State. This is so Power-On Self-Test (POST) codes can be heard by the user in case of a  
hardware problem with the PC.  
PC Beep Mute. When this bit is set to “1,” the channel is muted.  
PCM  
PCV3 . . . PCV0  
Function  
0
0
1
0000  
1111  
xxxx  
0 dB Attenuation  
45 dB Attenuation  
dB Attenuation  
REV. 0  
–13–  
AD1886A  
Phone Volume (Index 0Ch)  
Reg  
Name  
D15  
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4  
D3  
D2  
D1  
D0  
Default  
Num  
0Ch  
Phone Volume PHM  
X
X
X
X
X
X
X
X
X
X
PHV4 PHV3 PHV2 PHV1 PHV0 8008h  
PHV[4:0]  
PHM  
Phone Volume. Allows setting the Phone Volume Attenuator in 32 steps. The LSB represents 1.5 dB, and the  
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Phone Mute. When this bit is set to “1,” the channel is muted.  
Mic Volume (Index 0Eh)  
Reg  
Name  
D15  
D14 D13 D12 D11 D10 D9 D8 D7 D6  
M20  
D5 D4  
D3  
D2  
D1  
D0  
Default  
Num  
MIC  
Volume  
0Eh  
MCM  
X
X
X
X
X
X
X
X
X MCV4 MCV3 MCV2 MCV1 MCV0 8008h  
MCV[4:0]  
M20  
Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the  
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Microphone 20 dB Gain Block  
0 = Disabled; Gain = 0 dB  
1 = Enabled; Gain = 20 dB  
MCM  
Mic Mute. When this bit is set to “1,” the channel is muted.  
Line In Volume (Index 10h)  
Reg  
Name  
D15 D14 D13 D12  
D11  
D10  
D9  
D8  
D7 D6 D5 D4  
D3  
D2  
D1  
D0  
Default  
Num  
10h  
Line In Volume LM  
X
X
LLV4 LLV3 LLV2 LLV1 LLV0  
X
X
X
RLV4 RLV3 RLV2 RLV1 RLV0 8808h  
RLV[4:0]  
LLV[4:0]  
LM  
Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB,  
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Left Line In Volume. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5dB,  
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Line In Mute. When this bit is set to “1,” the channel is muted.  
CD Volume (Index 12h)  
Reg  
Name  
D15 D14 D13 D12  
D11  
D10  
D9  
D8  
D7  
X
D6  
X
D5  
X
D4  
D3  
D2  
D1  
D0  
Default  
Num  
12h  
CD Volume CVM  
X
X
LCV4 LCV3 LCV2 LCV1 LCV0  
RCV4 RCV3 RCV2 RCV1 RCV0 8808h  
RCV[4:0]  
LCV[4:0]  
CVM  
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and  
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the  
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
CD Volume Mute. When this bit is set to “1,” the channel is muted.  
–14–  
REV. 0  
AD1886A  
Video Volume (Index 14h)  
Reg  
Name  
D15 D14 D13 D12  
D11  
D10  
D9  
D8  
D7  
X
D6  
X
D5  
X
D4  
D3  
D2  
D1  
D0  
Default  
Num  
14h  
Video Volume VM  
X
X
LVV4 LVV3 LVV2 LVV1 LVV0  
RVV4 RVV3 RVV2 RVV1 RVV0 8808h  
RVV[4:0]  
LVV[4:0]  
VM  
Right Video Volume. Allows setting the Video right channel attenuator in 32 steps. The LSB represents 1.5dB,  
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Left Video Volume. Allows setting the Video left channel attenuator in 32 steps. The LSB represents 1.5 dB, and  
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Video Mute. When this bit is set to “1,” the channel is muted.  
AUX Volume (Index 16h)  
Reg  
Name  
D15 D14 D13 D12  
D11  
D10  
D9  
D8  
D7  
X
D6  
X
D5  
X
D4  
D3  
D2  
D1  
D0  
Default  
Num  
16h  
Aux Volume AM  
X
X
LAV4 LAV3 LAV2 LAV1 LAV0  
RAV4 RAV3 RAV2 RAV1 RAV0 8808h  
RAV[4:0]  
LAV[4:0]  
AM  
Right Aux Volume. Allows setting the Aux right channel attenuator in 32 steps. The LSB represents 1.5 dB, and  
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Left Aux Volume. Allows setting the Aux left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the  
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Aux Mute. When this bit is set to “1,” the channel is muted.  
PCM Out Volume (Index 18h)  
Reg  
Name  
D15 D14 D13 D12  
D11  
D10  
D9  
D8  
D7  
X
D6  
X
D5  
X
D4  
D3  
D2  
D1  
D0  
Default  
Num  
PCM Out  
Volume  
18h  
OM  
X
X
LOV4 LOV3 LOV2 LOV1 LOV0  
ROV4 ROV3 ROV2 ROV1 ROV0 8808h  
ROV[4:0]  
LOV[4:0]  
OM  
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5dB,  
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB,  
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.  
PCM Out Volume Mute. When this bit is set to “1,” the channel is muted.  
Volume Table (Index 0Ch to 18h)  
Mute  
x4 . . . x0  
Function  
0
0
0
1
00000  
01000  
11111  
xxxxx  
+12 dB Gain  
0 dB Gain  
–34.5 dB Gain  
dB Gain  
REV. 0  
–15–  
AD1886A  
Record Select Control Register (Index 1Ah)  
Reg  
Name  
D15 D14 D13 D12  
D11  
X
D10  
LS2  
D9  
D8  
D7  
X
D6  
X
D5  
X
D4  
X
D3  
X
D2  
D1  
D0  
Default  
0000h  
Num  
1Ah Record Select  
X
X
X
X
LS1  
LS0  
RS2  
RS1  
RS0  
RS[2:0]  
LS[2:0]  
Right Record Select  
Left Record Select  
Used to select the record source independently for right and left. See table for legend.  
The default value is 0000h, which corresponds to Mic in.  
RS2 . . . RS0  
Right Record Source  
0
1
2
3
4
5
6
7
MIC  
CD_R  
VIDEO_R  
AUX_R  
LINE_IN_R  
Stereo Mix (R)  
Mono Mix  
PHONE_IN  
LS2 . . . LS0  
Left Record Source  
0
1
2
3
4
5
6
7
MIC  
CD_L  
VIDEO_L  
AUX_L  
LINE_IN_L  
Stereo Mix (L)  
Mono Mix  
PHONE_IN  
Record Gain (Index 1Ch)  
Reg  
Num  
1Ch Record Gain IM  
Name  
D15 D14 D13 D12  
D11  
D10  
D9  
D8  
D7  
X
D6  
X
D5  
X
D4  
X
D3  
D2  
D1  
D0  
Default  
X
X
X
LIM3 LIM2 LIM1 LIM0  
RIM3 RIM2 RIM1 RIM0 8000h  
RIM[3:0]  
LIM[3:0]  
IM  
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB.  
Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to +22.5 dB.  
Input Mute  
0 = Unmuted  
1 = Muted or –dB Gain  
IM  
xIM3 . . . xIM0 Function  
0
0
1
1111  
0000  
xxxxx  
+22.5 dB Gain  
0 dB Gain  
dB Gain  
–16–  
REV. 0  
AD1886A  
General-Purpose Register (Index 20h)  
Reg  
Num Name  
D15 D14 D13 D12 D11 D10 D9  
D8  
D7  
D6  
X
D5  
X
D4  
X
D3  
X
D2  
X
D1  
D0  
X
Default  
20h General-Purpose POP  
X
3D  
X
X
X
MIX MS  
LPBK  
X
X
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function default  
value is 0000h, which is all off.  
LPBK  
MS  
Loopback Control. ADC/DAC digital loopback mode.  
Mic Select  
0 = Mic1  
1 = Mic2  
MIX  
3D  
Mono Output Select  
0 = Mix  
1 = Mic  
3D Phat Stereo Enhancement  
0 = Phat Stereo is off.  
1 = Phat Stereo is on.  
POP  
PCM Output Path and Mute. The POP bit controls the optional PCM out 3D bypass path (the pre and post 3D  
PCM out paths are mutually exclusive).  
0 = pre 3D  
1 = post 3D  
3D Control Register (Index 22h)  
Reg  
Name  
D15 D14 D13 D12 D11 D10 D9  
D8  
X
D7  
X
D6  
X
D5  
X
D4  
X
D3  
D2  
D1  
D0  
Default  
Num  
22h  
3D Control  
X
X
X
X
X
X
X
DP3 DP2 DP1 DP0 0000h  
DP[3:0]  
Depth Control. Sets 3D “Depth” Phat Stereo enhancement according to table below.  
DP3 . . . DP0  
Depth  
0
0%  
1
14  
15  
6.67%  
93.33%  
100%  
REV. 0  
–17–  
AD1886A  
Subsection Ready Register (Index 26h)  
Reg  
Name  
D15  
X
D14 D13 D12 D11 D10 D9  
D8  
D7 D6 D5 D4 D3  
D2  
D1  
D0  
Default  
Num  
26h  
Power-Down Cntrl/Stat  
PR6 PR5 PR4 PR3 PR2 PR1 PR0  
X
X
X
X
REF ANL DAC ADC NA  
Note: The ready bits are read only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the  
AD1886A subsections. If the bit is a one, that subsection is “ready.” Ready is defined as the subsection able to perform in its  
nominal state.  
ADC  
DAC  
ANL  
ADC section ready to transmit data.  
DAC section ready to accept data.  
Analog gainuators, attenuators, and mixers ready.  
Voltage References, VREF and VREFOUT up to nominal level.  
REF  
PR[6:0]  
AD1886A Power-Down Modes. The first three bits are to be used individually rather than in combination with  
each other. The last bit, PR3, can be used in combination with PR2 or by itself. The mixer and reference cannot  
be powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up  
until the reference is up.  
PR0—Power-Down ADC  
PR1—Power-Down DAC  
PR2—Power-Down Analog Mixer  
PR3—Power-Down VREF and VREFOUT  
PR4—Power-Down AC-Link  
PR5—Power-Down Internal Clock  
PR6—Power-Down Headphone  
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can be  
either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are both set.  
In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in  
the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or disable PR5.  
Power-Down State  
PR6  
PR5  
PR4  
PR3  
PR2  
PR1  
PR0  
ADC Power-Down  
DAC Power-Down  
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
ADC and DAC Power-Down  
Mixer Power-Down  
ADC + Mixer Power-Down  
DAC + Mixer Power-Down  
ADC + DAC + Mixer Power-Down  
Standby  
Extended Audio ID Register (Index 28h)  
Reg  
Num  
Name  
D15 D14 D13 D12 D11 D10 D9  
D8  
X
D7  
D6  
X
D5  
D4  
X
D3  
X
D2  
D1  
X
D0  
Default  
28h  
Extended Audio ID  
ID1 ID0  
X
X
X
X
X
X
X
SPDF  
VRA 0001h  
Note: The Extended Audio ID is a read only register.  
VRA  
Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio.  
“1” indicates SPDIF support, “0” indicates no SPDIF support.  
ID1, ID0 is a 2-bit field which indicates the codec configuration.  
SPDF  
ID[1:0]  
–18–  
REV. 0  
AD1886A  
Extended Audio Status and Control Register (Index 2Ah)  
Reg  
Name  
D15 D14 D13 D12 D11 D10  
D9 D8 D7 D6 D5  
D4  
D3  
X
D2  
D1 D0  
Default  
Num  
2Ah Ext'd Audio Stat/Ctrl  
X
X
X
X
X
SPCV  
X
X
X
X
SPSA1 SPSA0  
SPDIF X VRA 0000h  
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended  
audio features.  
VRA  
Variable Rate Audio. VRA = 1 enables Variable Rate Audio mode (sample rate control registers and SLOTREQ  
signaling.  
SPDIF  
SPSA[1,0]  
SPDIF transmitter subsystem enable/disable bit:  
“1” indicates SPDIF is enabled, “0” indicates SPDIF is disabled.  
SPDIF Slot Assignment:  
SPSA[1, 0] = 00 SPDIF uses AC-LINK slots 3 and 4.  
SPSA[1, 0] = 01 SPDIF uses AC-LINK slots 7 and 8.  
SPSA[1, 0] = 10 SPDIF uses AC-LINK slots 6 and 9.  
SPSA[1, 0] = 11 Reserved.  
SPCV  
SPDIF Configuration Valid: (Read Only)  
“1” indicates current SPDIF configuration (SPA, SPR, DAC-Rate) is supported.  
“0” indicates current SPDIF configuration (SPA, SPR, DAC-Rate) is not supported.  
PCM DAC Rate Register (Index 2Ch)  
Reg  
Name  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Default  
Num  
2Ch/(7Ah) PCM DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h  
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA, both sample  
rates are reset to 48 kHz.  
SR[15:0]  
Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in  
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the  
codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back  
when read; otherwise, the closest rate supported is returned.  
PCM ADC Rate Register (Index 32h)  
Reg  
Name  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Default  
Num  
32h/(78h) PCM ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h  
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both  
sample rates are reset to 48 kHz.  
SR[15:0]  
Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in  
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the  
codec to saturate. For all rates, if the value written to the register is supported, that value will be echoed back  
when read; otherwise, the closest rate supported is returned.  
REV. 0  
–19–  
AD1886A  
SPDIF Control Register (Index 3Ah)  
Reg  
Name  
D15 D14 D13  
D12  
D11 D10 D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Default  
Num  
3Ah SPDIF Control  
V
X
SPSR1 SPSR0 L  
CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY AUD PRO 0000h  
Note: Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or  
subframe in the V case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF  
bit in register 2Ah is “0”). This ensures that control and status information startup correctly at the beginning of SPDIF transmission.  
PRO  
Professional: “1” indicates Professional use of channel status, “0” Consumer.  
Non-Audio: “1” indicates data is non PCM format, “0” data is PCM.  
AUD  
COPY  
PRE  
Copyright: “1” indicates copyright is not asserted, “0” copyright is asserted.  
Preemphasis: “1” indicates filter preemphasis is 50/15 µs, “0” preemphasis is none.  
Category Code: Programmed according to IEC standards, or as appropriate.  
Generation Level: Programmed according to IEC standards, or as appropriate.  
CC[6-0]  
L
SPSR[1,0]  
SPDIF Transmit Sample Rate:  
SPSR[1:0] = “00” Transmit Sample Rate = 44.1 kHz.  
SPSR[1:0] = “01” Reserved.  
SPSR[1:0] = “10” Transmit Sample Rate = 48 kHz.  
SPSR[1:0] = “11” Transmit Sample Rate = 32 kHz.  
V
Validity: This bit affects the “Validity flag,” bit <28> transmitted in each subframe and enables the SPDIF trans-  
mitter to maintain connection during error or mute conditions.  
V = 1 Each SPDIF subframe (L + R) has bit <28> set to “1.” This tags both samples as valid.  
V = 0 Each SPDIF subframe (L + R) has bit <28> set to “0” for valid data and “1” for invalid data (error condition).  
Jack Sense/SPDIF Register (Index 72h)  
Reg  
Num  
Name  
D15  
D14  
D13  
D12  
D11 D10  
D9  
D8  
D7 D6  
D5  
D4  
D3  
D2 D1 D0 Default  
JS1 0000h  
72h  
Jack Sense/SPDIF SPMIX JS0D SPRZ JSPD  
X
JSOE JSLM JSD  
X
JSC JSMM JSM VW1  
X
X
Note: All register bits are read/write except for JSI, JS and VWI, which are read only.  
JSI  
Indicates that Jack Sense pin has generated an interrupt. Must be enabled by JSM bit and remains set until soft-  
ware clears JSC bit.  
VWI  
JSM  
Indicates Voice Wake Interrupt occurred.  
Jack Sense Mode:  
1 = Interrupt Mode (Software intervention required).  
0 = Jack Sense Mode ( Hardware asserted Mono/Line Muting).  
JSMM  
JSC  
Jack Sense Mono Mute:  
Setting this bit enables Jack Sense to mute the Mono output.  
Jack Sense Clear:  
Setting this bit clears the Jack Sense interrupt (only needed when JSM = 1).  
JSD  
Jack Sense Disabled:  
Setting this bit disables Jack Sense functionality.  
JSLM  
JSOE  
JSPD  
JSOD  
SPRZ  
SPMIX  
Jack Sense Line Mute:  
Setting this bit enables Jack Sense to mute the LINE_OUT output.  
Jack Sense Output Enable:  
Setting this bit allows the JS pin to operate as GPIO (output mode only).  
Jack Sense Pull-up Disable:  
Setting this bit disables the internal Jack Sense pull-up.  
Jack Sense Output Data:  
Data on this bit is transferred to the JS pin if JSOE = 1 (otherwise no effect).  
1 = SPDIF Return to Zero on under run.  
0 = SPDIF Repeat last sample on under run.  
1 = SPDIF Transmits output of ADC.  
0 = SPDIF Transmits AC-Link Time Slot Data.  
–20–  
REV. 0  
AD1886A  
Serial Configuration (Index 74h)  
Reg  
Name  
D15  
D14  
D13  
D12  
D11 D10 D9  
DHWR  
D8 D7 D6 D5 D4 D3 D2 D1 D0 Default  
Num  
Serial  
Configuration 16  
SLOT  
74h  
REGM2 REGM1 REGM0  
X
X
X
X
X
X
X
X
X
X
X
X
Note: This register is not reset when the reset register (Register 00h) is written.  
DHWR  
REGM0  
REGM1  
REGM2  
SLOT16  
Disable Hardware Reset  
Master Codec Register Mask  
Slave 1 Codec Register Mask  
Slave 2 Codec Register Mask  
Enable 16-bit slots.  
If your system uses only a single AD1886A, you can ignore the register mask bits.  
SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.  
Miscellaneous Control Bits (Index 76h)  
Reg  
Name  
D15 D14  
D13 D12  
D11 D10  
D9 D8  
D7  
D6  
D5  
D4 D3 D2  
D1 D0  
Default  
Num  
DAC LPMI  
MOD SRX10 SRX8  
ALSR EN D7 D7  
76h  
Misc Control Bits  
Z
X
X
DAM DMS DLSR  
X
X
X
DRSR  
X
ARSR 0000h  
ARSR  
ADC Right Sample Generator Select  
0 = SR0 Selected (32h)  
1 = SR1 Selected (2Ch)  
DRSR  
DAC Right Sample Generator Select  
0 = SR0 Selected (32h)  
1 = SR1 Selected (2Ch)  
SRX8D7  
SRX10D7  
MODEN  
ALSR  
Multiply SR1 rate by 8/7  
Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set.  
Modem filter enable (left channel only). Change only when DACs are powered down.  
ADC Left Sample Generator Select  
0 = SR0 Selected (32h)  
1 = SR1 Selected (2Ch)  
DLSR  
DMS  
DAC Left Sample Generator Select  
0 = SR0 Selected (32h)  
1 = SR1 Selected (2Ch)  
Digital Mono Select  
0 = Mixer  
1 = Left DAC + Right DAC  
DAM  
Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output.  
Low-Power Mixer  
LPMIX  
DACZ  
Zero-fill (vs. repeat) if DAC is starved for data.  
REV. 0  
–21–  
AD1886A  
Sample Rate 0 (Index 78h)  
Reg  
Num  
Name  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Default  
(32h)/78h Sample Rate 0 SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80h  
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both  
sample rates are reset to 48 kHz.  
SR0[15:0]  
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)  
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.  
Sample Rate 1 (Index 7Ah)  
Reg  
Num  
Name  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Default  
(2Ch)/7Ah Sample Rate 1 SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h  
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both  
sample rates are reset to 48 kHz.  
SR1[15:0]  
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in  
1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.  
Vendor ID1 Register (Index 7Ch)  
Reg  
Name  
D15 D14 D13 D12 D11 D10 D9  
D8  
F0  
D7  
S7  
D6  
S6  
D5  
S5  
D4  
S4  
D3  
S3  
D2  
S2  
D1  
S1  
D0  
S0  
Default  
4144h  
Num  
7Ch Vendor ID1  
F7  
F6  
F5  
F4  
F3  
F2  
F1  
S[7:0]  
F[7:0]  
This register is ASCII encoded to ‘A.’  
This register is ASCII encoded to ‘D.’  
Vendor ID2 Register (Index 7Eh)  
Reg  
Name  
D15 D14 D13 D12 D11 D10 D9 D8 D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Default  
Num  
7Eh  
Vendor ID2 T7  
T6  
T5  
T4  
T3  
T2  
T1  
T0  
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5363h  
T[7:0]  
This register is ASCII encoded to ‘S.’  
–22–  
REV. 0  
AD1886A  
AVDD  
NOTE  
IF NOT USED, GROUND  
JACK SENSE PIN.  
(PIN 47)  
+
0.1F  
10F  
NCNC  
NC  
DVDD  
U1  
10F  
0.1F  
0.1F  
22pF  
22pF  
1
2
3
4
5
6
36  
24.576MHz  
DV  
LINE_OUT_R  
LINE_OUT_L  
CX3D  
DD1  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
XTL_IN  
0.1F  
XTL_OUT  
47nF  
1F  
DV  
RX3D  
SS1  
+
SDATA_OUT  
BIT_CLK  
FILT_L  
FILT_R  
AD1886A  
270pF NPO  
7
8
1F  
DV  
AFILT2  
AFILT1  
SS2  
+
SDATA_IN  
9
DV  
270pF NPO  
V
DD2  
REFOUT  
10  
11  
12  
SYNC  
RESET  
PC_BEEP  
V
REF  
SDATA_OUT  
AV  
SS1  
+
AV  
DD1  
SDATA_IN  
SYNC  
0.1F  
10F  
0.1F  
RESET  
47⍀  
AVDD  
BIT_CLK  
47pF  
NC = NO CONNECT  
FB  
600Z  
NOTE  
ALL UNUSED ANALOG INPUTS (LINE_IN_L/R,VIDEO_L/R,  
MIC1, MIC2, PC_BEEP, PHONE_IN, AND CD_L/R/GND)  
MUST BE LEFT UNCONNECTED.  
Figure 9. Recommended Power Connections, Decoupling and Support Components  
SPDIF TRANSMITTER OUTPUT CONNECTION  
The codec SPDIF output is located on Pin 48. This pin has a weak internal pull-up that allows detection of SPDIF connector  
hardware at power-up and automatically enables or disables the SPDIF transmitter. This feature allows system manufacturers to  
populate or depopulate SPDIF connector hardware according to their requirements.  
When the output pin is simply left open (NC) or strapped high by a pull-up resistor, the internal sense circuitry disables the  
SPDIF transmitter. This condition prevents the SPDIF enable bit on Register 2Ah from being enabled.  
When the output pin is strapped low by a pull-down resistor (10 kor less), the SPDIF transmitter is enabled and the SPDIF  
enable bit on Register 2Ah can be asserted.  
The following circuits (Figure 10 and Figure 11) describe two ways to provide an SPDIF connection to the codec.  
SPDIF OUT  
(CODEC PIN 48)  
U1  
R2  
5
NC  
NC  
10k  
4
3
2
1
INPUT  
VCC  
J1  
R2  
240  
RCA JACK  
5V  
(LOGIC)  
T1  
1
2
1
4
5
8
SPDIF OUT  
(CODEC PIN 48)  
R1  
8.2k⍀  
U1A  
R2  
110⍀  
R3  
LED  
10k⍀  
C1  
0.1F  
3.3V BUFFER  
(CAPABLE OF  
12mA DRIVE)  
1:1  
6
GND  
TOTX173  
TOSLINK  
NC = NO CONNECT  
Figure 11. SPDIF Output Connection Using Electrical Link  
Figure 10. SPDIF Output Connection Using Optical Link  
REV. 0  
–23–  
AD1886A  
The first option consists of an optical link using a TOSLINK fiber-optic transmitting module. A typical offering is the  
TOSHIBA TOTX173 module for PCB mounted applications. This module can drive fiber optic cables up to 10 meters long, de-  
pending on the cable hardware used. This solution offers compatibility with state of the art audio systems and provides excellent  
common-mode rejection and noise immunity. R1 sets the current level for the internal LED and R2 allows the SPDIF transmitter to  
be enabled at power-up. Note that the TOSLINK module requires VCC = 5 V (PC logic supply).  
The second method uses an electrical connection matching the requirements of the IEC958 “Digital Audio Interface” for consumer  
products. This method uses a 75 coax cable as the connecting medium, with RCA type connectors at both ends. The transmission  
distance is at least 10 to 15 meters depending on the hardware used. The nominal electrical levels are 0.5 V p-p with a required bandwidth  
of 7 MHz. The 1:1 ratio transformer is used for galvanic isolation and for improved common-mode noise rejection. R1 and R2 provide  
the proper signal amplitude and impedance matching. R3 allows the SPDIF transmitter to be enabled at power-up.  
JACK SENSE OPERATION  
The AD1886A features a Jack Sense pin (JS) that can be used with the HP_OUT or LINE_OUT jacks to automatically mute the  
other audio outputs. When the Jack Sense pin is connected to one of the output jacks, the AD1886A can sense whether an audio  
plug has been inserted into the jack and automatically mute the LINE_OUT or MONO_OUT or both outputs.  
The JS pin should normally be connected to the HP_OUT jack to automatically mute the MONO_OUT and LINE_OUT audio  
signals, alternatively the JS pin can be connected to the LINE_OUT jack to automatically mute the MONO_OUT signal. The action  
of the JS pin can be programmed by setting the JSLM and JSMM bits in the Jack Sense Register (72h). The following table summa-  
rizes the Jack Sense operation:  
Table I. Jack Sense Operation Table  
JSLM Bit  
(Reg 72h, D9 Bit)  
JSMM Bit  
(Reg 72h, D5 Bit)  
JS State = HIGH  
(PLUG INSERTED)  
JS State = LOW  
(PLUG REMOVED)  
1
1
0
0
1
0
1
0
LINE_OUT = ON  
MONO_OUT = ON  
LINE_OUT = ON  
MONO_OUT = MUTE  
LINE_OUT = MUTE  
MONO_OUT = ON  
LINE_OUT = MUTE  
MONO_OUT = MUTE  
LINE_OUT = ON  
MONO_OUT = ON  
LINE_OUT = ON  
MONO_OUT = ON  
LINE_OUT = ON  
MONO_OUT = ON  
LINE_OUT = ON  
MONO_OUT = ON  
The Jack Sense functionality is enabled by default on codec power-up (JSD bit = 0), however the JSLM and JSMM bits are set to  
zero, therefore the muting action is not enabled for both outputs. The JSLM and JSMM bits have to be configured by the software  
or INF configuration file for the desired muting action.  
The Jack Sense pin is active high and contains an active internal pull-up. If the Jack Sense input is not going to be used, it should be  
pulled down to digital ground using 10 kresistors.  
–24–  
REV. 0  
AD1886A  
CONNECTING THE JACK SENSE TO THE OUTPUT JACKS  
Headphone Jack  
The diagram on Figure 12 shows the preferred method to connect the Jack Sense line to the HP_OUT jack. This scheme requires a  
stereo jack with a normally closed and isolated single switch. The switch holds the Jack Sense line low (grounded) until an audio plug  
is inserted, causing the switch to open and the Jack Sense line to go high due to the codec internal pull-up.  
The R2 and R3 resistors keep the electrolytic output caps properly polarized while the HP_OUT jack is not used.  
NOTE: LOCATE R1 CLOSETO CODEC.  
R1  
2k  
JACK SENSE LINE  
TO CODEC JS (PIN 47)  
C2  
220F  
OPTIONAL EMC  
COMPONENTS  
ISOLATED  
NC SWITCH  
FROM CODEC HP_OUT_R (PIN 41)  
FROM CODEC HP_OUT_L (PIN 39)  
5
4
3
+
R2  
10k⍀  
L1 600Z  
C3  
220F  
2
1
+
L2 600Z  
C4  
R3  
10k⍀  
C1  
470pF  
HEADPHONE OUT  
470pF  
Figure 12. Jack Sense Connection to HP_OUT Jack, Using Isolated Switch  
Alternatively, when an audio output jack containing an isolated switch is not available, the circuit shown in Figure 13 can be used.  
While the audio plug is out, this circuit keeps the Jack Sense line state low, by the pull-down effect of R2 (with no audio present) or  
by tracking the lower peaks of the HP_OUT audio signal. Once an audio plug is inserted and the jack switch opens, the Jack Sense  
line switches to a high state due to the codec internal pull-up, which quickly charges C1 to DVDD  
.
The R2 and R3 resistors also keep the electrolytic output caps properly polarized while the HP_OUT jack is not used.  
NOTE: LOCATE R1 AND C1 CLOSETO CODEC.  
JACK SENSE  
R1  
2k  
D1  
TO CODEC JS (PIN 47)  
C1  
MMBD914  
2F  
CERAMIC  
OPTIONAL EMC  
COMPONENTS  
C2  
220F  
L1 600Z  
L2 600Z  
FROM CODEC HP_OUT_R (PIN 41)  
FROM CODEC HP_OUT_L (PIN 39)  
+
J1  
R2  
10k⍀  
C4  
470pF  
1
2
3
4
5
C3  
220F  
+
R3  
10k⍀  
C5  
470pF  
HEADPHONE OUT  
Figure 13. Jack Sense Connection to HP_OUT Jack, Using Nonisolated Switch  
LINE OUT JACK  
Although not shown, if a LINE_OUT jack is used and the Jack Sense functionality is desired with this jack, the LINE_OUT jack  
should be wired in a similar configuration as shown above for the HP_OUT jack (preferably Figure 12). We recommend that in this  
case the output coupling caps (C2, C3) be set to 2.2 µF. All other values should be kept the same.  
REV. 0  
–25–  
AD1886A  
APPLICATION CIRCUITS  
CD-ROM CONNECTIONS  
Typical CD-ROM drives generate 2 V rms output and require a voltage divider for compatibility with the Codec input (1 V rms range).  
The recommended circuit is a group of divide-by-two voltage dividers as shown on Figure 14.  
The CD_GND_REF pin is used to cancel differential ground noise from the CD-ROM. For optimal noise cancellation, this section  
of the divider should have approximately half the impedance of the Right and Left channel section dividers.  
VOLTAGE DIVIDER  
AC-COUPLING  
C1  
0.33F  
R1  
4.7k⍀  
TO CODEC CD_L INPUT  
+
R2  
4.7k⍀  
1
2
3
4
C2  
0.33F  
R3  
2.7k⍀  
HEADER FOR  
CD ROM AUDIO  
(LGGR)  
TO CODEC CD_GND_REF INPUT  
TO CODEC CD_R INPUT  
+
R4  
2.7k⍀  
C3  
0.33F  
R5  
4.7k⍀  
+
R6  
4.7k⍀  
Figure 14. Typical CD-ROM Audio Connections  
LINE_IN, AUX, AND VIDEO INPUT CONNECTIONS  
Most audio sources also generate 2 V rms audio level and require a –6 dB input voltage divider to be compatible with the Codec  
inputs. Figure 15 shows the recommended application circuit. For applications requiring EMC compliance, the EMC components  
should be configured and selected to provide adequate RF immunity and emissions control.  
EMC  
COMPONENTS  
VOLTAGE DIVIDER  
AC-COUPLING  
C3  
R1  
4.7k⍀  
LINE/AUX/VIDEO INPUT  
0.33F  
L2 600Z  
C1  
J1  
TO CODEC RIGHT CHANNEL INPUT  
TO CODEC LEFT CHANNEL INPUT  
+
1
R2  
4.7k⍀  
2
3
4
5
470pF  
C4  
0.33F  
R3  
4.7k⍀  
L1 600Z  
+
R4  
C2  
470pF  
4.7k⍀  
Figure 15. LINE_IN, AUX and VIDEO Input Connections  
MICROPHONE CONNECTIONS  
The AD1886A contains an internal microphone preamp with 20 dB gain; in most cases a direct microphone connection as shown in  
Figure 16 is adequate. If the microphone level is too low, an external preamp can be added as shown in Figure 17. In either case the  
microphone bias can be derived from the codec’s internal reference (VREFOUT) using a 2.2 kresistor. For the preamp circuit, the  
V
REFOUT signal can also provide the midpoint bias for the amplifier.  
To meet the PC99 1.0A requirements, the MIC signal should be placed on the microphone jack tip and the bias on the ring. This  
configuration supports electret microphones with three conductor plugs as well as dynamic microphones with two conductor plugs  
(ring and sleeve shorted together).  
Additional filtering may be required to limit the microphone response to the audio band of interest.  
–26–  
REV. 0  
AD1886A  
EMC  
COMPONENTS  
L1 600Z  
J1  
1
2
3
4
5
AC-COUPLING  
C2  
C3  
0.22F  
470pF  
L2 600Z  
C1  
TO CODEC MIC1 OR MIC2 INPUT  
470pF  
MIC BIAS  
MIC INPUT  
R1  
2.2k⍀  
FROM CODEC V  
REFOUT  
Figure 16. Recommended Microphone Input Connections  
PREAMP  
EMC  
COMPONENTS  
R3  
100k  
L1 600Z  
J1  
1
2
3
4
5
AC-COUPLING  
AVDD  
C2  
AC-COUPLING  
C3  
0.22F  
470pF  
R2  
10k⍀  
C4  
0.22F  
L2 600Z  
C1  
470pF  
U1  
TO CODEC MIC1 OR MIC2 INPUT  
AD8531  
MIC INPUT  
MIC BIAS  
R1  
2.2k⍀  
FROM CODEC V  
REFOUT  
Figure 17. Microphone with Additional External Preamp (20 dB Gain)  
LINE OUTPUT CONNECTIONS  
The AD1886A Codec provides stereo LINE_OUT signals at a standard 1 V rms level. These signals must be ac-coupled before they  
can be connected to an external load. After the ac-coupling, a minimal resistive load is recommended to keep the capacitors properly  
biased and reduce clicks and pops when plugging stereo equipment into the output jack. The capacitor values should be selected to  
provide a desired frequency response, taking into account the nominal impedance of the external load. To meet the PC99 specifica-  
tion for PCs, testing must be performed with a 10 kload, therefore a minimum of 1 µF value is recommended to achieve less than  
–3 dB roll-off at 20 Hz.  
STEREO LINE_OUT JACK  
J1  
C3  
1F  
L2 600Z  
L1 600Z  
FROM CODEC LINE_OUT_R  
FROM CODEC LINE_OUT_L  
C1  
470pF  
C2  
470pF  
R1  
47k⍀  
R2  
47k⍀  
C4  
1F  
Figure 18. Recommended LINE_OUT Connections  
PC BEEP INPUT CONNECTIONS  
The recommended PC BEEP input circuit is shown below. Under most cases the PC_BEEP signal should be attenuated, filtered and  
then ac-coupled into the Codec.  
C2  
0.1F  
R1  
10k⍀  
PC_BEEP (FROM ICH)  
TO CODEC PC_BEEP INPUT  
R2  
1k⍀  
C1  
0.1F  
Figure 19. Recommended PC_BEEP Connections  
REV. 0  
–27–  
AD1886A  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
48-Lead Thin Plastic Quad Flatpack (LQFP)  
(ST-48)  
0.063 (1.60)  
MAX  
0.354 (9.00) BSC SQ  
0.030 (0.75)  
0.018 (0.45)  
37  
48  
36  
1
0.276  
(7.00)  
BSC  
SQ  
TOPVIEW  
(PINS DOWN)  
COPLANARITY  
0.003 (0.08)  
12  
25  
0؇  
MIN  
13  
24  
0.011 (0.27)  
0.006 (0.17)  
0.019 (0.5)  
BSC  
0.008 (0.2)  
0.004 (0.09)  
0.057 (1.45)  
0.053 (1.35)  
7؇  
0؇  
0.006 (0.15)  
0.002 (0.05)  
SEATING  
PLANE  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS  
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE  
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN  
–28–  
REV. 0  

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