AD1887JSTZ-REEL [ADI]
IC SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC, TQFP-48, Consumer IC:Other;
| 型号： | AD1887JSTZ-REEL |
| 厂家： | 
ADI |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PQFP48, PLASTIC, TQFP-48, Consumer IC:Other 商用集成电路 |
| 文件： | 总16页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
a
AC’97 SoundMAX Codec
AD1887
AC’97 2.1 FEATURES
ENHANCED FEATURES
Variable Sample Rate Audio
Full Duplex Variable Sample Rates from 7040 Hz to
48 kHz with 1 Hz Resolution
Software-Enabled VREFOUT Output for Microphones and
External Power Amp
Split Power Supplies (3.3 V Digital/5 V Analog)
Mobile Low-Power Mixer Mode
Extended 6-Bit Headphone Volume Control
Digital Audio Mixer Mode
AC’97 FEATURES
AC’97 2.2 Compliant
Greater than 90 dB Dynamic Range
Integrated Stereo Headphone Amplifier
Multibit ⌺-⌬ Converter Architecture for Improved S/N
Ratio Greater than 90 dB
16-Bit Stereo Full-Duplex Codec
Two Analog Line-Level Stereo Inputs for:
LINE-IN and CD
Mono MIC Input with Built-In Programmable Preamp
High-Quality CD Input with Ground Sense
Power Management Support
48-Terminal TQFP Package
FUNCTIONAL BLOCK DIAGRAM
ID0
ID1
AD1887
V
REF
V
CHIP SELECT
REFOUT
MIC
PREAMP
MIC
LINE_IN
CD
16-BIT
⌺-⌬ A/D
CONVERTER
PGA
PGA
16-BIT
⌺-⌬ A/D
RESET
CONVERTER
SYNC
SAMPLE
RATE
AC
LINK
BIT_CLK
SDATA_OUT
SDATA_IN
GA
M
GA
M
GA
M
GA
M
GA
M
GENERATORS
16-BIT
⌺-⌬ A/D
CONVERTER
M
M
GA
GA
M
GA
HP
HP_OUT_L
HP_OUT_R
16-BIT
⌺-⌬ A/D
CONVERTER
M
GA
HP
M
M
OSCILLATOR
G = GAIN
A = ATTENUATE
M = MUTE
XTL_OUT
XTL_IN
SoundMAX is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD1887–SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature
Digital Supply (VDD
25°C
3.3 V
DAC Test Conditions
)
Calibrated
Analog Supply (VCC
Sample Rate ( S
Input Signal
Analog Output Pass Band
VIH
)
5.0 V
–3 dB Attenuation Relative to Full Scale
Input 0 dB
32 Ω Output Load (HP_OUT)
f
)
48 kHz
1008 Hz
20 Hz to 20 kHz
2.0 V
ADC Test Conditions
Calibrated
VIL
0.8 V
VIH (CS0, CS1)
VIL
4.0 V
1.0 V
0 dB Gain
Input –3.0 dB Relative to Full Scale
ANALOG INPUT
Parameter
Min
Typ
Max
Unit
Input Voltage (RMS Values Assume Sine Wave Input)
LINE_IN, CD
1
V rms
V p-p
V rms
V p-p
V rms
V p-p
kΩ
2.83
0.1
0.283
1
2.83
20
MIC with 20 dB Gain
MIC with 0 dB Gain
Input Impedance
*
Input Capacitance
*
5
7.5
pF
HEADPHONE OUT VOLUME
Parameter
Min
Typ
Max
Unit
Step Size (+6 dB to –88.5 dB); HP_OUT_R, HP_OUT_L
1.5
–94.5
dB
dB
dB
Output Attenuation Range Span
*
Mute Attenuation of 0 dB Fundamental
*
80
PROGRAMMABLE GAIN AMPLIFIER—ADC
Parameter
Min
Min
Typ
Max
Max
Unit
Step Size (0 dB to 22.5 dB)
PGA Gain Range Span
1.5
22.5
dB
dB
ANALOG MIXER—INPUT GAIN/AMPLIFIERS/ATTENUATORS
Parameter
Typ
Unit
Signal-to-Noise Ratio (SNR)
CD to HP_OUT
Other to HP_OUT
90
90
dB
dB
Step Size (+12 dB to –34.5 dB): (All Steps Tested)
MIC, LINE_IN, CD, DAC
Input Gain/Attenuation Range:
MIC, LINE_IN, CD, DAC
1.5
dB
dB
–46.5
DIGITAL DECIMATION AND INTERPOLATION FILTERS*
Parameter
Min
Typ
Max
Unit
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Rejection
Group Delay
0
0.4 × fS
0.09
0.6 × fS
∞
Hz
dB
Hz
Hz
dB
sec
µs
0.4 × fS
0.6 × fS
–74
12/fS
0.0
Group Delay Variation over Pass Band
*Guaranteed but not tested.
–2–
REV. 0
AD1887
ANALOG-TO-DIGITAL CONVERTERS
Parameter
Min
Typ
Max
Unit
Resolution
Total Harmonic Distortion (THD)
Dynamic Range (–60 dB Input THD + N Referenced to Full Scale, A-Weighted)
Signal-to-Intermodulation Distortion
16
–84
87
Bits
dB
dB
dB
84
*
(CCIF Method)
85
ADC Crosstalk
*
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
LINE_IN to Other
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
ADC Offset Error
–100
–90
–90
–85
10
0.5
5
dB
dB
%
dB
mV
DIGITAL-TO-ANALOG CONVERTERS
Parameter
Min
Typ
Max
Unit
Resolution
16
–75
90
–100
10
Bits
dB
dB
dB
%
dB
dB
Total Harmonic Distortion (THD) HP_OUT
Dynamic Range (–60 dB Input THD + N Referenced to Full Scale, A-Weighted)
Signal-to-Intermodulation Distortion
Gain Error (Full-Scale Span Relative to Nominal Input Voltage)
Interchannel Gain Mismatch (Difference of Gain Errors)
DAC Crosstalk
85
*
(CCIF Method)
0.7
–80
*
(Input L, Zero R, Measure R_OUT; Input R, Zero L,
Measure L_OUT)
Total Audible Out-of-Band Energy (Measured from 0.6 × fS to 20 kHz)
*
–40
dB
ANALOG OUTPUT
Parameter
Min
Typ
Max
Unit
Full-Scale Output Voltage; HP_OUT
1
2.83
V rms
V p-p
Ω
Output Impedance
External Load Impedance
Output Capacitance
*
800
*
32
Ω
*
15
pF
External Load Capacitance
VREF
VREF_OUT
100
2.45
pF
V
V
2.05
2.25
2.25
VREF_OUT Current Drive
Mute Click (Muted Output Minus Unmuted Midscale DAC Output)
5
mA
mV
5
STATIC DIGITAL SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
High-Level Input Voltage (VIH): Digital Inputs
Low-Level Input Voltage (VIL)
High-Level Output Voltage (VOH), IOH = 2 mA
Low-Level Output Voltage (VOL), IOL = 2 mA
Input Leakage Current
0.65 × DVDD
V
V
V
V
µA
µA
0.35 × DVDD
0.9 × DVDD
0.1 × DVDD
+10
+10
–10
–10
Output Leakage Current
POWER SUPPLY
Parameter
Min
Typ
Max
Unit
Power Supply Range—Analog (AVDD
Power Supply Range—Digital (DVDD
Power Dissipation—5 V/3.3 V
)
)
4.75
3.15
5.25
3.45
V
V
mW
mA
mA
dB
253
36
22
Analog Supply Current—5 V (AVDD
Digital Supply Current—3.3 V (DVDD
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)
)
)
*
40
(At Both Analog and Digital Supply Pins, Both ADCs and DACs)
*Guaranteed but not tested.
REV. 0
–3–
AD1887–SPECIFICATIONS
CLOCK SPECIFICATIONS*
Parameter
Min
Typ
Max
Unit
Input Clock Frequency
Recommended Clock Duty Cycle
24.576
50
MHz
%
40
60
POWER-DOWN STATES
Parameter
Set Bits
DVDD Typ
AVDD Typ
Unit
ADC
DAC
PR0
PR1
15.82
15.08
3.79
30.0
26.3
19.9
18.1
17.4
11.1
8.3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ADC + DAC
ADC + DAC + Mixer (Analog CD On)
Mixer
ADC + Mixer
DAC + Mixer
ADC + DAC + Mixer
Analog CD Only (AC-Link On)
Analog CD Only (AC-Link Off)
Standby
PR1, PR0
LPMIX, PR1, PR0
PR2
PR2, PR0
PR2, PR1
PR2, PR1, PR0
LPMIX, PR5, PR1, PR0
LPMIX, PR1, PR0, PR4, PR5
PR5, PR4, PR3, PR2, PR1, PR0
PR6
3.85
17.65
15.70
15.07
3.80
3.85
0.06
2.1
18.1
18.1
0
0.06
17.66
Headphone Standby
26.1
*Guaranteed but not tested.
Specifications subject to change without notice.
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
Typ
Max
Unit
RESET Active Low Pulsewidth
RESET Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter*
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
tRST_LOW
tRST2CLK
tSYNC_HIGH
tSYNC_LOW
tSYNC2CLK
1.0
µs
162.8
ns
µs
1.3
19.5
µs
162.8
ns
MHz
ns
ps
ns
ns
kHz
µs
12.288
81.4
tCLK_PERIOD
750
48.84
48.84
tCLK_HIGH
tCLK_LOW
32.56
32.56
42
38
48.0
20.8
2.5
SYNC Period
tSYNC_PERIOD
tSETUP
tHOLD
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
5
5
2
2
2
2
2
2
2
2
0
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
tRISECLK
tFALLCLK
tRISESYNC
tFALLSYNC
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
tS2_PDOWN
tSETUP2RST
tOFF
4
4
4
4
4
4
4
4
6
6
6
6
6
6
6
6
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT)
Rising Edge of RESET to HI-Z Delay
Propagation Delay
RESET Rise Time
Output Valid Delay from Rising Edge of BIT_CLK to SDI Valid
1.0
25
15
50
15
*Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.
–4–
REV. 0
AD1887
BIT_CLK
SYNC
tRST_LOW
tRST2CLK
tRISECLK
tFALLCLK
tFALLSYNC
tFALLDIN
RESET
BIT_CLK
tRISESYNC
Figure 1. Cold Reset
SDATA_IN
tRISEDIN
tRST2CLK
tSYNC_HIGH
SYNC
SDATA_OUT
BIT_CLK
tRISEDOUT
tFALLDOUT
Figure 2. Warm Reset
Figure 5. Signal Rise and Fall Time
tCLK_LOW
SLOT 1
SLOT 2
SYNC
BIT_CLK
tCLK_HIGH
BIT_CLK
tCLK_PERIOD
WRITE
DATA
PR4
DON’T
CARE
TO 0x26
tSYNC_LOW
SDATA_OUT
SDATA_IN
SYNC
tS2_PDOWN
tSYNC_HIGH
tSYNC_PERIOD
NOTE: BIT_CLK NOTTO SCALE
Figure 6. AC Link Low Power Mode Timing
Figure 3. Clock Timing
tSETUP
RESET
BIT_CLK
SYNC
SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK
HI-Z
SDATA_OUT
tOFF
tHOLD
Figure 7. ATE Test Mode
Figure 4. Data Setup and Hold
REV. 0
–5–
AD1887
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
Temperature Package
Package
Option
Parameter
Min Max
Unit
Model
Range
Description
Power Supplies
Digital (DVDD
Analog (AVCC
AD1887JST 0°C to 70°C
Thin-Quad Flatpack ST-48
)
)
–0.3 +3.6
–0.3 +6.0
V
V
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins) –0.3 AVDD + 0.3
Digital Input Voltage (Signal Pins) –0.3 DVDD + 0.3
Ambient Temperature (Operating)
Storage Temperature
10.0
mA
V
V
°C
°C
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating
TAMB = TCASE – (PD × θCA
)
0
70
TCASE = Case Temperature in °C
–65 +150
PD = Power Dissipation in W
*Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
θ
θ
θ
CA = Thermal Resistance (Case-to-Ambient)
JA = Thermal Resistance (Junction-to-Ambient)
JC = Thermal Resistance (Junction-to-Case)
Package
JA
JC
CA
TQFP
76.2°C/W
17°C/W
59.2°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1887 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
DV
DD1
36
35
34
33
32
31
30
29
28
27
26
25
NC
PIN 1
IDENTIFIER
XTL_IN
NC
3
XTL_OUT
NC
4
DV
SS1
NC
5
SDATA_OUT
BIT_CLK
FILT_L
FILT_R
AFILT2
AFILT1
AD1887
TOP VIEW
(Not to Scale)
6
7
DV
SS2
8
SDATA_IN
DV
9
V
DD2
REFOUT
10
11
12
SYNC
RESET
NC
V
REF
AV
AV
SS1
DD1
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
–6–
REV. 0
AD1887
PIN FUNCTION DESCRIPTIONS
Description
Digital I/O
Pin Name
TQFP
I/O
XTL_IN
2
3
5
6
8
10
11
I
O
I
O/I
O
I
Crystal (or Clock) Input, 24.576 MHz
Crystal Output
AC-Link Serial Data Output, AD1887 Input Stream
AC-Link Bit Clock 12288 MHz Serial Data Clock Daisy Chain Output Clock
AC-Link Serial Data Input AD1887 Output Stream
AC-Link Frame Sync
XTL_OUT
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET
I
AC-Link Reset AD1887 Master H/W Reset
Chip Selects
Pin Name
TQFP
Type
Description
ID0
ID1
45
46
I
I
Chip Select Input 0 (Active Low)
Chip Select Input 1 (Active Low)
Analog I/O
These signals connect the AD1887 component to analog sources and sinks, including microphones and speakers
Pin Name
TQFP
I/O
Description
CD_L
CD_GND_REF
CD_ R
MIC
LINE_IN_L
LINE_IN_R
HP_OUT_L
HP_OUT_R
18
19
20
21
23
24
39
41
I
I
I
I
I
I
O
O
CD Audio Left Channel
CD Audio Analog Ground Reference for Differential CD Input
CD Audio Right Channel
Microphone Input
Line in Left Channel
Line in Right Channel
Headphones Out Left Channel
Headphones Out Right Channel
Filter/Reference
These signals are connected to resistors, capacitors, or specific voltages
Pin Name
TQFP
I/O
Description
VREF
27
28
29
30
31
32
O
O
O
O
O
O
Voltage Reference Filter
VREFOUT
AFILT1
AFLIT2
FILT_R
FILT_L
Voltage Reference Output 5 mA Drive (Intended for Mic Bias)
Antialiasing Filter Capacitor—ADC Right Channel
Antialiasing Filter Capacitor—ADC Left Channel
AC-Coupling Filter Capacitor—ADC Right Channel
AC-Coupling Filter Capacitor—ADC Left Channel
Power and Ground Signals
Pin Name
TQFP
Type
Description
DVDD
DVSS1
DVSS2
DVDD
AVDD1
AVSS1
1
1
4
7
9
25
26
38
40
43
44
I
I
I
I
I
I
I
I
I
I
Digital VDD 33 V
Digital GND
Digital GND
Digital VDD 33 V
Analog VDD 50 V
Analog GND
Analog VDD 50 V
Analog GND
2
AVDD
2
AVSS2
AVDD3
AVSS3
Analog VDD 50 V
Analog GND
REV. 0
–7–
AD1887
No Connects
Pin Name
TQFP
Type
Description
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
12
13
14
15
16
17
22
33
34
35
36
37
42
47
48
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
Indexed Control Registers
Reg
Num
00h
04h
08h
00Eh
10h
12h
18h
1Ah
1Ch
20h
26h
28h
2Ah
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
ID7
X
D6
ID6
X
D5
D4
D3
D2
D1
D0
Default
Reset
X
SE4
X
SE3
SE2
SE1
SE0
ID9
ID8
ID5
ID4
ID3
ID2
ID1
ID0
0010h
Headphones Volume
Reserved
HPM
X
LHV5 LHV4 LHV3 LHV2 LHV1 LHV0
RHV5 RHV4
RHV3 RHV2 RHV1 RHV0 8000h
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Mic Volume
MCM
LM
CVM
OM
X
X
X
X
X
M30
X
X
MCV4 MCV3 MCV2 MCV1 MCV0 8008h
Line-In Volume
CD Volume
X
X
LLV4
LCV4
LOV4
X
LLV3 LLV2 LLV1 LLV0
LCV3 LCV2 LCV1 LCV0
LOV3 LOV2 LOV1 LOV0
X
X
RLV4
RCV4
ROV4
X
RLV3
RLV2 RLV1 RLV0 8808h
X
X
X
X
X
RCV3 RCV2 RCV1 RCV0 8808h
ROV3 ROV2 ROV1 ROV0 8808h
PCM Out Vol
X
X
X
X
X
Record Select
X
X
X
LS2
LS1
LS0
X
X
X
X
RS2
RS1
RS0
0000h
Record Gain
IM
X
X
X
LIM3 LIM2 LIM1 LIM0
X
X
X
X
RIM3
X
RIM2 RIM1 RIM0 8000h
General-Purpose
Power-Down Ctrl/Stat
Ext’d Audio ID
Ext’d Audio Stat/Ctrl
X
X
X
X
X
X
X
X
LPBK
X
X
X
X
X
X
X
0000h
000Xh
0005h
0000h
BB80h
X
X
PR5
X
PR4
X
PR3
X
PR2
X
PR1
X
PR0
X
X
X
X
REF
X
ANL
X
DAC ADC
ID1
X
ID0
X
X
X
X
X
X
VRA
VRA
SR0
X
X
X
X
X
X
X
X
X
X
X
X
X
2Ch/
PCM DAC Rate (SR1) SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
(7Ah)*
32h/
(78h)*
PCM ADC Rate (SR0) SR15
SR14
SR13
SR12
SR11
SR10
X
SR9
X
SR8
X
SR7
X
SR6
X
SR5
X
SR4
X
SR3
X
SR2
X
SR1
X
SR0
X
BB80h
7000h
74h
Serial Configuration
Misc Control Bits
SLOT16 REGM2 REGM1 REGM0 X
76h
DACZ
LPMIX
X
DAM
DMS DLSR
X
ALSR
MOD SRX10 SRX8
X
X
DRSR
X
ARSR 0404h
EN
D7
D7
7Ch
Vendor ID1
Vendor ID2
F7
T7
F6
T6
F5
T5
F4
T4
F3
T3
F2
T2
F1
T1
F0
T0
S7
S6
S5
S4
S3
S2
S1
S0
4144h
7Eh
REV7 REV6 REV5 REV4
REV3
REV2 REV1 REV0 5362h
NOTES
All registers not shown and bits containing an X are assumed to be reserved.
Odd register addresses are aliased to the next lower even address.
Reserved registers should not be written.
Zeros should be written to reserved bits.
*Indicates Aliased register for AD1819, AD1819A backward compatibility.
–8–
REV. 0
AD1887
Reset (Index 00h)
Reg
Name
Num
D15 D14 D13 D12 D11 D10 D9
SE4 SE3 SE2 SE1 SE0 ID9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0010h
00h
Reset
X
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Note: Writing any value to this register performs a register reset, which causes all registers to revert to their default values (except
74h, which forces the serial configuration). Reading this register returns the ID code of the part and a code for the type of 3D Stereo
Enhancement.
ID[9:0]
Identify Capability. The ID decodes the capabilities of AD1887 based on the following:
Bit = 1
Function
AD1887*
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9
Dedicated Mic PCM in Channel
Modem Line Codec Support
Bass and Treble Control
Simulated Stereo (Mono to Stereo)
Headphone Out Support
Loudness (Bass Boost) Support
18-Bit DAC Resolution
20-Bit DAC Resolution
18-Bit ADC Resolution
20-Bit ADC Resolution
0
0
0
0
1
0
0
0
0
0
*The AD1887 contains none of the optional features identified by these bits.
SE[4:0]
Stereo Enhancement. The 3D stereo enhancement identifies the Analog Devices 3D stereo enhancement.
Headphones Volume Registers (Index 04h)
Reg
Name
D15
D14 D13
D12
D11
D10
D9
D8
D7 D6 D5
D4
D3
D2
D1
D0
Default
Num
04h
Headphones
Volume
HPM
X
LHV5 LHV4 LHV3 LHV2 LHV1 LHV0
X
X
RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h
RHV[5:0]
LHV[5:0]
HPM
Right Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from +6 dB to a maximum attenuation of –88.5 dB.
Left Headphone Volume Control. The least significant bit represents 1.5 dB. This register controls the output
from +6 dB to a maximum attenuation of –88.5 dB.
Headphones Volume Mute. When this bit is set to “1,” the channel is muted.
HPM
xHV5 . . . xHV0
Function
0
0
0
1
00 0000
01 1111
11 1111
xx xxxx
6 dB Gain
–40.5 dB Attenuation
–88.5 dB Attenuation
–∞ dB Attenuation
REV. 0
–9–
AD1887
Mic Volume (Index 0Eh)
Reg
Name
D15
D14 D13 D12 D11 D10 D9
D8
X
D7
X
D6
D5
X
D4
D3
D2
D1
D0
Default
Num
0Eh
MIC
Volume
MCM
X
X
X
X
X
X
M30
MCV4 MCV3 MCV2 MCV1 MCV0 8008h
MCV[4:0]
Mic Volume Gain. Allows setting the Mic Volume attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
M30
Mic Boost Gain: Amplifies the Mic input. 0 = 0 dB, 1 = 30 dB
Mic Mute. When this bit is set to “1,” the channel is muted.
MCM
Line In Volume (Index 10h)
Reg
Name
D15 D14 D13 D12
D11
D10
D9
D8
D7 D6 D5 D4
D3
D2
D1
D0
Default
Num
10h
Line In
Volume
LM
X
X
LLV4 LLV3 LLV2 LLV1 LLV0
X
X
X
RLV4 RLV3 RLV2 RLV1 RLV0 8808h
RLV[4:0]
LLV[4:0]
LM
Right Line In Volume. Allows setting the Line In right channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
Line In Volume Left. Allows setting the Line In left channel attenuator in 32 steps. The LSB represents 1.5dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
Line In Mute. When this bit is set to “1,” the channel is muted.
CD Volume (Index 12h)
Reg
Name
D15
D14 D13 D12
D11
D10
D9
D8
D7 D6 D5 D4
D3
D2
D1
D0
Default
Num
12h
CD
Volume
CVM
X
X
LCV4 LCV3 LCV2 LCV1 LCV0
X
X
X
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0]
LCV[4:0]
CVM
Right CD Volume. Allows setting the CD right channel attenuator in 32 steps. The LSB represents 1.5 dB, and
the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
Left CD Volume. Allows setting the CD left channel attenuator in 32 steps. The LSB represents 1.5 dB, and the
range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
CD Volume Mute. When this bit is set to “1,” the channel is muted.
–10–
REV. 0
AD1887
PCM Out Volume (Index 18h)
Reg
Name
D15 D14 D13 D12
D11
D10
D9
D8
D7
X
D6
X
D5
X
D4
D3
D2
D1
D0
Default
Num
PCM Out
Volume
18h
OM
X
X
LOV4 LOV3 LOV2 LOV1 LOV0
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
ROV[4:0]
LOV[4:0]
OM
Right PCM Out Volume. Allows setting the PCM right channel attenuator in 32 steps. The LSB represents 1.5dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
Left PCM Out Volume. Allows setting the PCM left channel attenuator in 32 steps. The LSB represents 1.5 dB,
and the range is +12 dB to –34.5 dB. The default value is 0 dB, mute enabled.
PCM Out Volume Mute. When this bit is set to “1,” the channel is muted.
Volume Table (Index 0Ch to 18h)
Mute
x4 . . . x0
Function
0
0
0
1
00000
01000
11111
xxxxx
+12 dB Gain
0 dB Gain
–34.5 dB Gain
–∞ dB Gain
Record Select Control Register (Index 1Ah)
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
X
D6
X
D5
X
D4
X
D3
X
D2
D1
D0
Default
0000h
Num
1Ah
Record Select
X
X
X
X
X
LS2
LS1
LS0
RS2 RS1
RS0
RS[2:0]
LS[2:0]
Right Record Select
Left Record Select
Used to select the record source independently for right and left. See table for legend.
The default value is 0000h, which corresponds to Mic in.
LS2 . . . LS0
Left Record Source
RS2 . . . RS0
Right Record Source
0
1
4
5
6
MIC
CD_L
LINE_IN_L
Stereo Mix (L)
Mono Mix
0
1
4
5
6
MIC
CD_L
LINE_IN_R
Stereo Mix (R)
Mono Mix
Record Gain (Index 1Ch)
Reg
Name
D15 D14 D13 D12 D11
D10
D9
D8
D7
X
D6
X
D5
X
D4
X
D3
D2
D1
D0
Default
Num
1Ch
Record Gain IM
X
X
X
LIM3 LIM2 LIM1 LIM0
RIM3 RIM2 RIM1 RIM0 8000h
RIM[3:0]
LIM[3:0]
IM
Right Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to 22.5 dB.
Left Input Mixer Gain Control. Each LSB represents 1.5 dB, 0000 = 0 dB and the range is 0 dB to 22.5 dB.
Input Mute
0 = Unmuted
1 = Muted or –∞ dB Gain
IM
xIM3 . . . xIM0 Function
0
0
1
1111
0000
xxxxx
22.5 dB Gain
0 dB Gain
–∞ dB Gain
REV. 0
–11–
AD1887
General Purpose Register (Index 20h)
Reg
Name
D15 D14 D13 D12 D11 D10 D9
D8
X
D7
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
Default
0000h
Num
20h
General Purpose
X
X
X
X
X
X
X
LPBK
Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function default
value is 0000h, which is all off.
LPBK
Loopback Control. ADC/DAC digital loopback mode.
Subsection Ready Register (Index 26h)
Reg
Name
D15 D14 D13 D12 D11 D10 D9
D8
D7
X
D6
X
D5
X
D4
X
D3
D2
D1
D0
Default
Num
26h
Power-Down Cntrl/Stat
X
PR6 PR5 PR4 PR3 PR2 PR1 PR0
REF ANL DAC ADC NA
Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the
AD1887 subsections. If the bit is a one, that subsection is “ready.” Ready is defined as the subsection able to perform in its nomi-
nal state.
ADC
DAC
ANL
ADC section ready to transmit data.
DAC section ready to accept data.
Analog gainuators, attenuators, and mixers ready.
Voltage References, VREF and VREFOUT up to nominal level.
REF
PR[5:0]
AD1887 Power-Down Modes. The first three bits are to be used individually rather than in combination with each
other. The last bit, PR3, can be used in combination with PR2 or by itself. The mixer and reference cannot be
powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until
the reference is up.
PR0 – Powered-Down ADC
PR1 – Powered-Down DAC
PR2 – Powered-Down Analog Mixer
PR3 – Powered-Down VREF and VREFOUT
PR4 – Powered-Down AC-Link
PR5 – Powered-Down Internal Clock
PR6 – Powered-Down Headphone
PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can
be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are
both set.
In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in
the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect or disable PR5.
Power-Down State
PR6
PR5
PR4
PR3
PR2
PR1
PR0
ADC Power-Down
DACs Power-Down
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
ADC and DAC Power-Down
Mixer Power-Down
ADC + Mixer Power-Down
DAC + Mixer Power-Down
ADC + DAC + Mixer Power-Down
Standby
–12–
REV. 0
AD1887
Extended Audio ID Register (Index 28h)
Reg
Name
D15 D14 D13 D12 D11 D10 D9
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
Default
Num
28h
Extended Audio ID
ID1 ID0
X
X
X
X
X
VRA 0001h
Note: The Extended Audio ID is a read only register.
VRA
Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio.
ID1, ID0 is a 2-bit field which indicates the codec configuration: Primary is 00; Secondary is 01, 10, or 11.
ID[1:0]
Extended Audio Status and Control Register (Index 2Ah)
Reg
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Default
Num
2Ah
Ext'd Audio Stat/Ctrl
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VRA 0000h
Note: The Extended Audio Status and Control Register is a read/write register that provides status and control of the extended audio
features.
VRA
Variable Rate Audio. VRA = 1 indicates support for Variable Rate Audio mode (sample rate control registers and
SLOTREQ signaling).
PCM DAC Rate Register (Index 2Ch)
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
Num
2Ch/(7Ah) PCM DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the
codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when
read, otherwise the closest rate supported is returned.
PCM ADC Rate Register (Index 32h)
Reg
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
Num
32h/(78h) PCM ADC Rate
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
Note: 32h is an alias for 78h. The VRA bit in register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR[15:0]
Writing to this register allows programming of the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h) in
1 Hz increments. Programming a value outside of the range 7040 Hz (1b80h) to 48000 Hz (bb80h) causes the
codec to saturate. For all rates, if the value written to the register is supported that value will be echoed back when
read, otherwise the closest rate supported is returned.
REV. 0
–13–
AD1887
Serial Configuration (Index 74h)
Reg
Name
D15
D14
D13
D12
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
Num
74h
Serial
Configuration
SLOT 16 REGM2 REGM1 REGM0
X
X
X
X
X
X
X
X
X
X
X
X
7000h
Note: This register is not reset when the reset register (Register 00h) is written.
DHWR
REGM0
REGM1
REGM2
SLOT16
Disable Hardware Reset.
Master Codec Register Mask.
Slave 1 Codec Register Mask.
Slave 2 Codec Register Mask.
Enable 16-bit slots.
If your system uses only a single AD1887, you can ignore the register mask bits.
SLOT16 makes all AC Link slots 16 bits in length, formatted into 16 slots.
Miscellaneous Control Bits (Index 76h)
Reg
Name
D15
D14
D13 D12
D11
D10
D9 D8
D7
D6
D5
D4 D3 D2
DRSR
D1 D0
Default
Num
76h
Misc
Control
Bits
DACZ LPMIX
X
DAM DMS DLSR
X
ALSR MOD SRX10 SRX8
EN D7 D7
X
X
X
ARSR 0404h
ARSR
ADC Right Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
DRSR
DAC Right Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
SRX8D7
SRX10D7
MODEN
Multiply SR1 rate by 8/7.
Multiply SR1 rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set.
Modem filter enable (left channel only). Change only when DACs are powered down.
ALSR
DLSR
DMS
ADC Left Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
DAC Left Sample Generator Select
0 = SR0 Selected (32h)
1 = SR1 Selected (2Ch)
Digital Mono Select
0 = Mixer
1 = Left DAC + Right DAC
DAM
Digital Audio Mode. DAC Outputs bypass analog mixer and sent directly to the codec output.
Low-Power Mixer
LPMIX
DACZ
Zero-fill (vs. repeat) if DAC is starved for data.
–14–
REV. 0
AD1887
Sample Rate 0 (Index 78h)
Reg
Name D15
Num
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
Sample
Rate 0
(32h)/78h
SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80h
Note: 32h is an alias for 78h. The VRA bit in Register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR0[15:0]
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Sample Rate 1 (Index 7Ah)
Reg
Num
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
Sample
Rate 1
(2Ch)/7Ah
SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: 2Ch is an alias for 7Ah. The VRA bit in Register 2Ah must be set for the alias to work; if a zero is written to VRA then both
sample rates are reset to 48 kHz.
SR1[15:0]
Writing to this register allows the user to program the sampling frequency from 7 kHz (1B58h) to 48 kHz (BB80h)
in 1 Hertz increments. Programming a value greater than 48 kHz or less than 7 kHz may cause unpredictable results.
Vendor ID Registers (Index 7Ch–7Eh)
Reg
Name
D15 D14 D13 D12 D11 D10 D9
D8
F0
D7
S7
D6
S6
D5
S5
D4
S4
D3
S3
D2
S2
D1
S1
D0
S0
Default
4144h
Num
7Ch
Vendor ID1 F7
F6
F5
F4
F3
F2
F1
S[7:0]
F[7:0]
This register is ASCII encoded to ‘A.’
This register is ASCII encoded to ‘D.’
Reg
Num
Name
D15 D14 D13 D12 D11 D10 D9 D8 D7
D6
D5
D4
D3
D2
D1
D0
Default
7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5362h
T[7:0]
This register is ASCII encoded to ‘S.’
REV. 0
–15–
AD1887
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Thin Plastic Quad Flatpack (LQFP)
(ST-48)
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
12
25
0؇
MIN
13
24
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
0.057 (1.45)
0.053 (1.35)
7؇
0؇
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
–16–
REV. 0
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