AD1986_技术文档

AC ’97 SoundMAX CODEC

AD1986

FEATURES

ENHANCED FEATURES

AC `97 2.3 COMPLIANT FEATURES

6 DAC channels for 5.1 surround

S/PDIF output

Integrated headphone amplifiers

Variable rate audio

Integrated parametric equalizer

Stereo microphone with up to 30 dB gain boost

Integrated PLL for system clocking

Variable sample rate: 7 kHz to 96 kHz

7 kHz to 48 kHz in 1 Hz increments

Double rate audio (F_s= 96 kHz)

Greater than 90 dB dynamic range

20-bit resolution on all DACs

20-bit resolution on all ADCs

Line-level mono phone input

High quality CD input

Selectable MIC input w/preamp

AUX and line-in stereo inputs

External amplifier power down (EAPD)

Power management modes

Jack sensing and device identification

48-pin LQFP package

96 kHz for double rate audio

Jack sense with auto topology switching

Jack presence detection on up to 8 jacks

Three software-controlled VREF_OUT signals

Software-enabled outputs for jack sharing

Auto-down mix and channel spreading

Microphone-to-mono output

Stereo microphone pass-through to mixer

Built-in microphone/center/LFE/line-in sharing

Built-in SURROUND/LINE_IN sharing

Center/LFE line swapping

Microphone swapping

Reduced support component count

General purpose digital output pin (GPO)

Separate LINE_OUT and HP_OUT pins

Headphone drivers on LINE_OUT and HP_OUT pins

Independent headphone/LINE_OUT operation

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD1986

TABLE OF CONTENTS

Functional Block Diagram .............................................................. 4

Surround DAC PCM Rate (Register 0x2E) ............................ 30

C/LFE DAC PCM Rate (Register 0x30) .................................. 30

ADC PCM Rate (Register 0x32) .............................................. 30

C/LFE DAC Volume (Register 0x36)....................................... 31

Surround DAC Volume (Register 0x38) ................................. 31

SPDIF Control (Register 0x3A)................................................ 32

EQ Control Register (Register 0x60)....................................... 33

EQ Data Register (Register 0x62) ............................................ 34

Misc Control Bits 2 (Register 0x70)......................................... 34

Jack Sense (Register 0x72)......................................................... 35

Serial Configuration (Register 0x74)....................................... 37

Misc Control Bits 1 (Register 0x76)......................................... 39

Advanced Jack Sense (Register 0x78)...................................... 40

Misc Control Bits 3 (Register 0x7A)........................................ 41

Vendor ID Registers (Register 0x7C to 0x7E)........................ 42

CODEC Class/Revision Register (Register 0x60).................. 42

Specifications..................................................................................... 5

AC ’97 Timing Parameters.......................................................... 9

Absolute Maximum Ratings.......................................................... 12

Environmental Conditions........................................................ 12

ESD Caution................................................................................ 12

Pin Configuration And Function Description ........................... 13

AC ’97 Registers.............................................................................. 15

Register Details ............................................................................... 17

Reset (Register 0x00).................................................................. 17

Master Volume (Register 0x02)................................................ 17

Headphone Volume (Register 0x04)........................................ 18

Mono Volume (Register 0x06).................................................. 18

PC Beep (Register 0x0A)........................................................... 19

Phone Volume (Register 0x0C) ................................................ 19

Microphone Volume (Register 0x0E)...................................... 20

Line In Volume (Register 0x10)................................................ 21

CD Volume (Register 0x12)...................................................... 21

AUX Volume (Register 0x16) ................................................... 22

Front DAC Volume (Register 0x18)......................................... 22

ADC Select (Register 0x1A)...................................................... 23

ADC Volume (Register 0x1C) .................................................. 24

General-Purpose (Register 0x20)............................................. 25

Audio Int and Paging (Register 0x24) ..................................... 25

Power-Down Ctrl/Stat (Register 0x26).................................... 26

Ext’d Audio ID (Register 0x28)................................................. 27

Ext’d Audio Stat/Ctrl (Register 0x2A)...................................... 28

Front DAC PCM Rate (Register 0x2C) ................................... 29

PCI Subsystem Vendor ID Register (Register 0x62, Page 01)

....................................................................................................... 43

PCI Subsystem Device ID Register (Register 0x64, Page 01)43

Function Select Register (Register 0x66, Page 01)................. 43

Information and I/O Register (Register 0x68, Page 01)........ 44

Sense Register (Register 0x6A, Page 01) ................................. 46

Jack Presence Detection................................................................. 48

Audio Jack Styles (NC/NO) ...................................................... 48

Microphone Selection/Mixing...................................................... 49

Outline Dimensions....................................................................... 50

Ordering Guide .......................................................................... 50

REVISION HISTORY

10/04—Initial Version: Revision 0

Rev. 0 | Page 2 of 52

AD1986

NOTES

•

Advanced Jack Presence Detection: Using two CODEC

REDUCED SUPPORT COMPONENTS

pins, eight resistors and isolated switch jacks, the AD1986

can detect jack insertion on eight separate jacks. Previous

CODECs would have required 8 CODEC pins and

16 resistors.

Internal Microphone/Line In/C/LFE Sharing: On systems

that share the microphone with the C/LFE jack there are

no external components required. The micro-phone

selector can select the LINE_IN pins in those cases where

the microphone and line input devices are swapped.

Internal Line In/Microphone/Surround Sharing: On

systems that share the line in with the surround jack there

are no external components required.

The AD1986’s many improvements reduce external support

components for particular applications.

•

Multiple Microphone Sourcing: The MIC_1/2, LINE_IN

and C/LFE pins may all be selected as sources for

microphone input (boost amplifier).

•

Multiple VREF_OUT Pins: Each microphone-capable pin

group (MIC_1/2, LINE_IN and C/LFE) has separate,

software controllable VREF_OUT pins, reducing the need

for external biasing components.

•

Internal Microphone Mixing: Any combination of the

MIC_1/2, LINE_IN and C/LFE pins may be summed to

produce the microphone input. This removes the need for

external mixing components in those applications that

externally mixed microphone sources.

Dual Headphone Amplifiers: The AD1986 can drive

headphones out of the HP_OUT or LINE_OUT pins.

Rev. 0 | Page 3 of 52

AD1986

FUNCTIONAL BLOCK DIAGRAM

SPDIF_OUT

SPDIF TX

AC97CK

PLL

MIC_1

AD1986

MICROPHONE

SELECTOR/

MIXING AND

GAIN BLOCK

MIC_2

CODEC CORE

PHONE_IN

CD_L

RESET

SYNC

CD

CD_GND

CD_R

DIFF AMP

20-BIT

Σ-∆ ADC

G

M

ADC

SLOT

LOGIC

AUX_L

AUX_R

LINE_IN_L

20-BIT

Σ-∆ ADC

BITCLK

LINE

IN

SELECT

LINE_IN_R

SDATA_OUT

DAC

SLOT

LOGIC

PCBEEP_IN

SDATA_IN

MZ

LFE_OUT

CENTER_OUT

MONO_OUT

A

24-BIT

GA

M

Σ-∆ DAC

AC '97

24-BIT

Σ-∆ DAC

CONTROL

GA

REGISTERS

GA

M

GA

M

GA

M

GA

M

GA

M

A

GA

M

GA

M

GA

M

GA

M

A

M

JACK_SENSE_A

JACK_SENSE_B

PC BEEP

SURR_OUT_L

SURR_OUT_R

MZ

A

GENERATOR

24-BIT

EQ

GA

M

Σ-∆ DAC

24-BIT

EQ

Σ-∆ DAC

A

LINE_OUT_L

HP

M

EAPD

GPO

GPIO

EAPD

24-BIT

Σ-∆ DAC

Σ

M

GA

Σ

Z

G

M

LINE_OUT_R

HP_OUT_L

HP

VREF_OUT

(MIC1/2)

24-BIT

Σ-∆ DAC

Σ

M

VREF_OUT

(C/LFE)

A

VOLTAGE

REFERENCE

G = GAIN

A = ATTENUATION

M = MUTE

VREF_OUT

(LINE_IN)

M

HP_OUT_R

Z = HI-Z

VREF_FILT

Figure 1.

Rev. 0 | Page 4 of 52

AD1986

SPECIFICATIONS

Test conditions, unless otherwise noted.

Table 1.

Parameter

Typ

Unit

°C

Temperature

25

Digital Supply (DV_DD)

3.3 ±±0ꢀ

V

Analog Supply (AV_DD)

5.0 ±±0ꢀ

V

Sample Rate (F_S)

Input Signal

48

±,008

kHz

Hz

Analog Output Pass Band

20 Hz–20 kHz

V_IH

V_IL

V_IH

V_IL

2.0

0.8

2.4

0.6

V

DAC Test Conditions

Calibrated

ADC Test Conditions

Calibrated

Output −3 dB Relative to Full Scale

10 kΩ Output Load: Line (Surround), Mono, Center, and LFE

32 Ω Output Load: Headphone

0 dB PGA Gain

Input −3.0 dB Relative to Full Scale

Table 2. Analog Input

Input Voltage

Min

Typ

±

2.83

0.032

0.089

0.±

0.283

0.3±6

0.894

20

Max

Unit

VRMS^±

V p-p

VRMS

V p-p

VRMS

V p-p

VRMS

V p-p

kΩ

MIC_±/2, LINE_IN, CD, AUX, PHONE_IN (No Preamp)

C/LFE and SURROUND (When Used as Inputs)

MIC_±/2, LINE_IN, C/LFE With 30 dB Preamp

MIC_±/2, LINE_IN, C/LFE With 20 dB Preamp

MIC_±/2, LINE_IN, C/LFE With ±0 dB Preamp

Input Impedance²

2

Input Capacitance

5

7.5

pF

^±RMS values assume sine wave input.

²Guaranteed by design, not production tested.

Table 3. Master Volume

Parameter

Min

Typ

−±.5

−6.5

Max

Unit

dB

Step Size (LINE_OUT, HP Out, Mono Out, SURROUND, CENTER, LFE)

Output Attenuation Range (0 dB to –46.5 dB)

2

Mute Attenuation of 0 dB Fundamental

−80

dB

Table 4. Programmable Gain Amplifier—ADC

Parameter

Min

Typ

±.5

Max

Unit

dB

Step Size

PGA Gain Range Span (0 dB to 22.5 dB)

22.5

dB

Rev. 0 | Page 5 of 52

AD1986

Table 5. Analog Mixer—Input Gain/Amplifiers/Attenuators

Parameter

Min

Typ

Max

Unit

Signal-to-Noise Ratio (SNR)

CD to LINE_OUT

LINE, AUX, PHONE to LINE_OUT^±

MIC_± or MIC_2 to LINE_OUT^±

Step Size: All Mixer Inputs (Except PC Beep)

Step Size: PC Beep

Input Gain/Attenuation Range: All Mixer Inputs (+±2 dB to −34.5 dB)

90

88

80

−±.5

−3.0

−46.5

dB

^±Guaranteed by design, not production tested.

Table 6. Digital Decimation and Interpolation Filters¹

Parameter

Min

Typ

Max

Unit

Pass Band

0

0.4 × F_SHz

±0.09 dB

0.6 × F_SHz

Pass Band Ripple

Transition Band

Stop Band

Stop Band Rejection

Group Delay

0.4 × F_S

0.6 × F_S

−74

∞

Hz

dB

S

±6/F_S

0

Group Delay Variation Over Pass Band

µs

Table 7. Analog-to-Digital Converters

Parameter

Resolution

Min

Typ

Max

Unit

Bits

dB

ꢀ

dB

mV

20

Total Harmonic Distortion (THD)

−95

−85

−80

−±00

±±0

Dynamic Range (−60 dB Input, THD + N referenced to Full Scale, A-Weighted)

Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)

LINE_IN to Other Inputs

Gain Error (Full-Scale Span Relative to Nominal Input Voltage)

Interchannel Gain Mismatch (Difference of Gain Errors)

ADC Offset Error

−80

±0.5

±5

Rev. 0 | Page 6 of 52

AD1986

Table 8. Digital-to-Analog Converters

Parameter

Min

Typ

24

−92

−75

9±

Max

Unit

Bits

dB

ꢀ

dB

Resolution

Total Harmonic Distortion (LINE_OUT Drive)

Total Harmonic Distortion HP_OUT

Dynamic Range (−60 dB Input, THD + N referenced to Full Scale, A-Weighted)

Gain Error (Full-Scale Span Relative to Nominal Input Voltage)

Interchannel Gain Mismatch (Difference of Gain Errors)

DAC Crosstalk^±(Input L, Zero R, Read R_OUT; Input R, Zero L, Read L_OUT)

±±0

±0.7

−80

^±Guaranteed by design, not production tested.

Table 9. Analog Output

Parameter

Min

Typ

±

2.83

300

Max

Unit

VRMS

V p-p

Ω

kΩ

pF

FULL-SCALE OUTPUT VOLTAGE: SURROUND, CENTER/LFE, MONO_OUT

Output Impedance^±

External Load Impedance^±

±0

Output Capacitance^±

±5

External Load Capacitance

±,000

±

pF

FULL-SCALE OUTPUT VOLTAGE: HP_OUT, LINE_OUT

±

2.83

VRMS

V p-p

Ω

Output Impedance^±

External Load Impedance^±

Output Capacitance^±

32

Ω

pF

±5

External Load Capacitance^±

±,000

2.450

VREF_FILT, A_VDD= 5.0 V

A_VDD= 3.3 V

2.050

2.250

±.±25

2.250

3.700

2.250

0.0

V

VREF_OUT(MIC, C/LFE, LIN) (xVREF [2:0] = 00±)

(xVREF [2:0] = ±00, A_VDD= 5.0 V)

(xVREF [2:0] = ±00, A_VDD= 3.3 V)

(xVREF [2:0] = 0±0)

V

Current Drive

5

mA

mV

Mute Click (Muted Output, Unmuted Midscale DAC Output)

±5

Table 10. Static Digital Specifications—AC ’97

Parameter

Min

Typ

Max

Unit

V

High Level Input Voltage (V_IH), Digital Inputs

Low Level Input Voltage (V_IL)

0.65 × DV_DD

0.35 × DV_DD

High Level Output Voltage (V_OH), I_OH= 2 mA

Low Level Output Voltage (V_OL), I_OL= 2 mA

Input Leakage Current

Output Leakage Current

Input/Output Pin Capacitance

0.90 × DV_DD

V

µA

pF

0.±0 × DV_DD

−±0

±0

7.5

Rev. 0 | Page 7 of 52

AD1986

Table 11. Power Supply (Quiescent State)

Parameter

Min

4.5

2.97

Typ

Max

5.5

3.63

Unit

V

mW

mA

dB

Power Supply Range—Analog (AV_DD) ±±0ꢀ

Power Supply Range—Digital (DV_DD) ±±0ꢀ

Power Dissipation—Analog (AV_DD)/Digital (DV_DD)

Analog Supply Current—Analog (AV_DD)

Digital Supply Current—Digital (DV_DD)

Power Supply Rejection (±00 mV p–p Signal @ ± kHz)

365/±7±.6

73

52

40

Table 12. Power-Down States—AC ’97 (Quiescent State)

Parameter

Set Bits

DV_DDTyp

AV_DDTyp

Unit

mA

ADC

FRONT DAC

PR0

PR±

PRI

PRJ

53.0

53.7

62.0

53.5

62.0

27.0

36.6

27.6

±2.6

2.4

45.7

47.7

53.2

47.±

52.8

±4.5

53.2

45.7

33.0

±4.5

0.05

53.2

CENTER DAC

SURROUND DAC

LFE DAC

ADC + ALL DACs

Mixer

PRK

PR±, PR0, PRI, PRJ, PRK

PR2

PR2, PR0

PR2, PR±, PRI, PRJ, PRK

PR2, PR±, PR0, PRI, PRJ, PRK

PR5, PR4, PR3, PR2, PR±(IJK), PR0

PR6

ADC + Mixer

ALL DACs + Mixer

ADC + ALL DACs + Mixer

Standby

Headphone Standby

LINE_OUT HP Standby

0.0

55.0

62.0

LOHPEN = 0

Table 13. Clock Specifications—AC ’97¹

Parameter

Min

Typ

Max

Unit

Input Clock Frequency (Reference Clock Mode)

±4.3±8±8

48.000

MHz

Recommended Clock Duty Cycle

40

50

60

ꢀ

^±Refer to AC ’97, Revision 2.3 specifications for details of clock detection at startup. AD±986 CODEC clock source detection must follow AC ’97, Revision 2.3 guidelines.

Rev. 0 | Page 8 of 52

AD1986

AC ’97 TIMING PARAMETERS

Guaranteed over operating temperature range. Refer to the AC ’97 specifications (Revision 2.3, Release 1.0) for further information. The

specification can be downloaded from http://developer.intel.com/ial.scalableplatforms/audio.

t_RST2CLK

t_{RST_LOW}

RESET

BIT_CLK

Figure 2. Cold Reset Timing (CODEC is Supplying the BIT_CLK Signal)

Table 14.

Symbol

t_{RST_LOW}

t_RST2CLK

Parameter

Min

±.0

±62.8

Typ

Max

Unit

µS

nS

Recommended During Active (Low) RESET Signal

RESET Inactive (High) to BIT_CLK Active

400,000

t_{SYNC_HIGH}

t_SYNC2CLK

SYNC

BIT_CLK

Figure 3. Warm Reset Timing

Table 15.

Symbol

t_{SYNC_HIGH}

t_SYNC2CLK

Parameter

Min

Typ

±.3

Max

Unit

Sync Active (High) Pulse Width

Sync Inactive to BITCLK Startup Delay

µS

nS

±62.8

RESET

SDATA_OUT

SYNC

t_SETUP2RST

BIT_CLK, EAPD,

SPDIF_OUT,

SDATA_IN,

Hi-Z

DIGITAL I/O

t_OFF

Figure 4. ATE Test Mode

Table 16.

Symbol

t_SETUP2RST

t_OFF

Parameter

Min

Typ

Max

Unit

Setup to RESET Inactive (SYNC, SDATA_OUT)

Rising Edge of RESET to Hi-Z Delay

±5

nS

25

Rev. 0 | Page 9 of 52

AD1986

t_{CLK_LOW}

BIT_CLK

t_{CLK_HIGH}

t_{CLK_PERIOD}

t_{SYNC_LOW}

SYNC

t_{SYNC_HIGH}

t_{SYNC_PERIOD}

Figure 5. Bit Clock and Sync Timing

Table 17.

Symbol

t_{SYNC_HIGH}

t_{CLK_LOW}

Parameter

Min

40.5

39.7

Typ

Max

4±.7

40.6

Units

nS

BITCLK High Pulse Width

BITCLK Low Pulse Width

BITCLK Period

t_{CLK_PERIOD}

8±.4

nS

BIT_CLK Frequency

BIT_CLK Frequency Accuracy

BIT_CLK Jitter^{±, 2}

Sync Active (High) Pulse Width

Sync Inactive (Low) Pulse Width

Sync Period

±2.288

MHz

ppm

ps

µS

±±.0

750

±.3

±9.5

20.8

48.0

t_{SYNC_HIGH}

t_{SYNC_LOW}

t_{SYNC_PERIOD}

µS

kHz

Sync Frequency

^±Guaranteed by design, but not production tested.

²Output jitter directly dependent on input clock jitter.

SLOT 1

SLOT 2

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

WRITE TO

03 26

DATA

PR4

t_{S2_PDOWN}

BIT_CLK NOT TO SCALE

Figure 6. Link Low Power Mode Timing

Table 18.

Symbol

Parameter

End of Slot 2 to BIT_CLK, SDATA_IN Low

Min

Typ

Max

±.0

Units

µS

t_{S2_PDOWN}

0

Rev. 0 | Page ±0 of 52

AD1986

BIT_CLK

SYNC

t_RISECLK

t_FALLCLK

t_RISESYNC

t_FALLSYNC

SDATA_IN

SDATA_OUT

t_RISEDIN

t_FALLDIN

t_RISEDOUT

t_FALLDOUT

Figure 7. Signal Rise and Fall Times

Table 19.

Symbol

t_RISECLK

Parameter

Min

Typ

4

Max

Unit

nS

BIT_CLK Rise Time

BIT_CLK Fall Time

SYNC Rise Time

2

6

t_FALLCLK

t_RISESYNC

t_RISEDIN

t_RISEDOUT

SYNC Fall Time

SDATA_IN Rise Time

SDATA_IN Fall Time

SDATA_OUT Rise Time

SDATA_OUT Fall Time

t_CO

t_SETUP

V

IH

V

BIT_CLK

IL

SDATA_OUT

SDATA_IN

SYNC

V

OH

V

OL

t_HOLD

Figure 8. Link Low Power Mode Timing (Detail)

Table 20.

Symbol

t_CO

t_SETUP

t_HOLD

V_IH

V_IL

V_OH

V_OL

Parameter

Min

Typ

Max

Unit

nS

V

Propagation Delay

Setup to Falling Edge of BIT_CLK

25

4

3

Hold from Falling Edge of BIT_CLK

Digital Signal High Level Input Voltage

Digital Signal Low Level Input Voltage

Digital Signal High Level Output Voltage

Digital Signal Low Level Output Voltage

0.65 DV_DD

0.35 DV_DD

0.± DV_DD

0.9 DV_DD

Rev. 0 | Page ±± of 52

AD1986

ABSOLUTE MAXIMUM RATINGS

Table 21.

ENVIRONMENTAL CONDITIONS

Power Supply

Min Max

−0.3 +3.6

−0.3 +6.0

±±0.0

−0.3 AV_DD+ 0.3

−0.3 DV_DD+ 0.3

Unit

V

mA

V

Ambient Temperature Rating

Digital (DV_DD)

Analog (AV_DD)

T_AMB= T_CASE− (PD × θ_CA

)

T_CASE= case temperature in °C

PD = power dissipation in W

θ_CA= thermal resistance (case-to-ambient)

θ_JA= thermal resistance (junction-to-ambient)

θ_JC= thermal resistance (junction-to-case)

Input Current (Except Supply Pins)

Analog Input Voltage (Signal Pins)

Digital Input Voltage (Signal Pins)

Ambient Temperature (Operating)

Commercial

°C

0

–40

+70

+85

Industrial

Storage Temperature

Table 22. Thermal Resistance

−65 +±50

°C

Package

θ_JA

θ_JC

θ_CA

LQFP

76.2°C/W

±7°C/W

59.2°C/W

Stresses greater than those listed under Absolute Maximum

Ratings may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page ±2 of 52

AD1986

PIN CONFIGURATION AND FUNCTION DESCRIPTION

48 47 46 45 44 43 42 41 40 39 38 37

SURR_OUT_R

SURR_OUT_L

1

2

36

35

34

33

32

31

30

29

28

27

26

25

DV

DD

PIN 1

AC97CK

GPO

IDENTIFIER

AV

DD

3

VREF_OUT (C/LFE)

LFE_OUT

4

DV

SS

5

SDATA_OUT

BIT_CLK

AD1986

TOP VIEW

6

CENTER_OUT

7

AV

SS

DV

SS

(Not to Scale)

8

VREF_OUT (LINE_IN)

VREF_OUT (MIC_1/2)

VREF_FILT

SDATA_IN

9

DV

DD

10

11

12

SYNC

RESET

AV

SS

AV

DD

PCBEEP

13 14 15 16 17 18 19 20 21 22 23 24

Figure 9. Pin Configuration

Table 23. Pin Function Descriptions

Mnemonic

AC ’97CK

SDATA_OUT

BIT_CLK

SDATA_IN

SYNC

Pin Number

Input/Ouput

Description

2

5

6

8

±0

±±

I

External Clock In (±4.3±8±8 MHz).

AC Link Serial Data Output. Input Stream.

AC Link Bit Clock. ±2.288 MHz Serial Data Clock.

AC Link Serial Data Input. Output Stream.

AC Link Frame Sync .

O

I/O

I

RESET

AC Link Reset. Master Hardware Reset.

Table 24. Digital Input/Output

Number

Input/

Output Description

Mnemonic

S/PDIF_OUT 48

O

S/PDIF Output.

External Amplifier Power-Down Output.

General-Purpose Output pin. A digital signal that can be used to control external circuitry.

EAPD

GPO

47

3

Table 25. Jack Sense

Mnemonic

Pin Number

Input/Ouput Description

JACK_SENSE_A

JACK_SENSE_B

±6

±7

I

JackSense 0–3 Input

Jack Sense 4–7 Input

Rev. 0 | Page ±3 of 52

AD1986

Table 26. Analog Input/Output

Number

Input/

Ouput Description

Mnemonic

PCBEEP

±2

I

Analog PC Beep Input. Routed to all output capable pins when RESET is asserted.

PHONE_IN

AUX_L

±3

±4

I

Monaural Line Level Input.

Auxiliary Left Channel Input.

AUX_R

±5

I

Auxiliary Right Channel Input.

CD_L

±8

I

CD-Audio-Left Channel.

CD_GND

CD_R

±9

20

I

CD-Audio-Analog-Ground-Reference (for Differential CD Input).

CD-Audio-Right Channel.

MIC_±

MIC_2

2±

22

23

24

3±

32

I

Microphone ± or Line-In-Left Input (See LISEL Bits in Register 0x76).

Microphone 2 or Line-In-Right Input (See LISEL Bits in Register 0x76).

Line-In-Left Channel or Microphone ± Input (See OMS Bits in Register 0x74).

Line-In-Right Channel or Microphone 2 Input (See OMS Bits in Register 0x74).

Center-Channel Output or Microphone ± Input (See OMS Bits in Register 0x74).

Low-Frequency-Enhanced Output or Microphone 2 Input (See OMS Bits in Register 0x74).

Headphone-Out-Left Channel (See HPSEL Bits in Register 0x76).

Headphone-Out-Right Channel (See HPSEL Bits in Register 0x76).

Line-Out (Front)—Left Channel (See LOSEL Bit in Register 0x76) (HP Drive-Capable).

Line-Out (Front)—Right Channel (See LOSEL Bit in Register 0x76) (HP Drive-Capable).

Monaural Output to Telephony Subsystem Speakerphone.

Surround-Left Channel Output or Line-In-Left Input (See LISEL and SOSEL Bits in Register 0x76).

LINE_IN_L

LINE_IN_R

CENTER_OUT

LFE_OUT

HEADPHONE_L 39

HEADPHONE_R 4±

LINE_OUT_L

LINE_OUT_R

MONO_OUT

SURR_OUT_L

SURR_OUT_R

I/O

O

I/O

43

45

37

35

36

Surround-Right Channel Output or Line-In-Right Input (See LISEL and SOSEL Bits in

Register 0x76).

Table 27. Filter/Reference

Number

Input/

Ouput Description

Mnemonic

VREF_FILT

VREF_OUT (MIC)

VREF_OUT

(LINE_IN)

27

28

29

O

Voltage Reference Filter.

Programmable Voltage Reference Output (Intended for MIC Bias on the MIC_±/2 Channels).

Programmable Voltage Reference Output (Intended for MIC Bias on the LINE_IN Channels).

VREF_OUT (C/LFE)

33

O

Programmable Voltage Reference Output (Intended for MIC Bias on the C/LFE Channels).

Table 28. Power and Ground

Input/

Mnemonic Pin Number Ouput

Description

DV_DD

DV_SS

AV_DD

±

9

Digital Supply Voltage (3.3 V).

4

7

Digital Supply Return (Ground).

25

34

38

42

46

26

30

40

44

Analog Supply Voltage (5.0 V or 3.3 V). AV_DDsupplies should be well filtered because supply

noise will degrade audio performance.

I

AV_SS

Analog Supply Return (Ground).

Rev. 0 | Page ±4 of 52

AD1986

AC ’97 REGISTERS

Table 29. Register Map

Reg Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x00 Reset

x

SE4

SE3

SE2

SE±

SE0

ID9

ID8

ID7

ID6

ID5

ID4

ID3

ID2

ID±

ID0

0x0290

0x02 Master Volume

LM

x

LV4

x

LV3

x

LV2

x

LV±

x

LV0

x

RM

x

RV4

V4

RV3

V2

RV2

V2

RV±

V±

RV0

0x8080

0x8000

0x04 Headphones Volume LM

RV0

V0

0x06 Mono Volume

M

0x0A PC Beep

M

A/DS

x

F7

x

F6

x

F5

x

F4

x

F3

x

F2

x

F±

x

F0

x

V3

V4

V2

V3

V±

V2

V0

V±

x

0x8000

0x8008

0x0C Phone Volume

V0

0x0E Microphone Volume LM

x

LV4

LV3

LV2

LV±

LV0

RM

M20

x

RV4

RV3

RV2

RV±

RV0

0x8888

0x±0 Line In Volume

LM

0x±2 CD Volume

LM

x

LV4

LV3

LV2

LV±

LV0

RM

x

RV4

RV3

RV2

RV±

RV0

0x8888

0x±6 AUX Volume

0x±8 Front DAC Volume

0x±A ADC Select

x

LS2

LV2

LS±

LV±

LS0

LV0

MS

x

RS2

RV2

x

RS±

RV±

x

RS0

RV0

x

0x0000

0x8080

0x0000

0x±C ADC Volume

0x20 General Purpose

LM

x

LV3

RM

LPBK

RV3

x

DRSS± DRSS0 MIX

0x24 Audio Int. and Paging I4

I3

I2

I±

I0

x

PG3

REF

PG2

ANL

PG±

DAC

PG0

0xxx00

0x26 Power-Down Ctrl/Stat EAPD

PR6

PR5

PR4

PR3

PR2

PR±

PR0

ADC 0x000x

0x28 Ext’d Audio ID

ID±^±

x

ID0

x

REV±

PRI

REV0

SPCV

AMAP LDAC SDAC CDAC DSA± DSA0

x

SPDF DRA

SPDIF DRA

VRA

0x0BC7

0x0xx0

0x2A Ext’d Audio Stat/Ctrl

PRK

PRJ

x

LDAC SDAC CDAC SPSA± SPSA0

0x2C Front DAC PCM Rate R±5

0x2E Surr. DAC PCM Rate R±5

0x30 C/LFE DAC PCM Rate R±5

R±4

x

R±3

x

R±2

LFE4

LV4

x

R±±

LFE3

LV3

L

R±0

LFE2

LV2

CC6

x

R09

LFE±

LV±

CC5

x

R08

LFE0

LV0

CC4

x

R07

CNTM

RM

R06 R05

R04

CNT4

RV4

CC0

R03

R02

R0±

R00

0xBB80

0x32 ADC PCM Rate

R±5

0x36 C/LFE DAC Volume

LFEM

x

CNT3 CNT2 CNT± CNT0 0x8888

0x38 Surround DAC Volume LM

x

RV3

PRE

RV2

RV±

RV0

0x8888

0x2000

0x3A SPDIF Control

V

VCFG

x

SPSR

x

CC3

CC2 CC±

COPY /AUDIO PRO

0x60 EQ Control

0x62 EQ Data

EQM

x

SYM CHS BCA5 BCA4

BCA3 BCA2 BCA± BCA0 0x8080

CFD3 CFD2 CFD± CFD0 0xxxxx

CFD±5 CFD±4 CFD±3 CFD±2 CFD±± CFD±0 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4

MVREF2 MVREF± MVREF0 x MMDIS x

0x70 Misc. Control Bits 2

x

JSMAP CVREF2 CVREF± CVREF0 x

x

0x0000

0x72 Jack Sense

JS± SPRD JS± DMX JS0 DMX JS MT2 JS MT± JS MT0 JS± EQB JS0 EQB x

x

JS± MD JS0 MD JS± ST JS0 ST JS± INT JS0 INT 0x0000

0x74 Serial Configuration SLOT±6 REGM2 REGM± REGM0 REGM3 OMS2 OMS± OMS0 SPOVR LBKS± LBKS0 INTS

0x76 Misc. Control Bits ± DACZ DMIX± DMIX0 SPRD 2CMIC SOSEL SRU

AC97NC²MSPLT SODIS³CLDIS

0x78 Advanced Jack Sense JS7ST JS7INT JS6ST JS6INT JS5ST JS5INT JS4ST JS4INT JS4-7H x

JSINVB HPSEL± HPSEL0 LOSEL JSINVA LVREF2 LVREF± LVREF0 x

CSWP SPAL SPDZ SPLNK 0x±00±

x

LISEL± LISEL0 MBG± MBG0 0x60±0

JS3MD JS2MD JS3ST JS2ST JS3INT JS2INT 0xxxxx

0x7A Misc. Control Bits 3

x

LOHPEN GPO

MMIX

x

0x0000

0x7C Vendor ID±

0x7E Vendor ID2

F7

T7

F6

T6

F5

T5

F4

F3

F2

F±

F0

T0

S7

S6

S5

S4 S3

S2

S±

S0

0x4±44

T4

T3

T2

T±

REV7 REV6 REV5 REV4

REV3 REV2 REV± REV0 0x5378

0x60± CODEC Class/Rev

0x62± PCI SVID

x

CL4

CL3

CL2

CL±

CL0

RV7

PVI7 PVI6 PVI5

PI7 PI6 PI5

RV6 RV5

RV4

RV3

RV2

RV±

RV0

PVI0 0xFFFF

PI0 0xFFFF

0x0002

PVI±5

PVI±4

PVI±3

PVI±2 PVI±± PVI±0 PVI9

PVI8

PVI4

PVI3

PVI2

PVI±

0x64± PCI SID

PI±5

PI±4

PI±3

PI±2 PI±± PI±0 PI9

PI8

PI4

PI3

PI2

PI±

Rev. 0 | Page ±5 of 52

AD1986

Reg Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x66± Function Select

x

FC3

FC2

FC±

FC0

T/R

0x0000

0x68± Function Information G4

0x6A± Sense Register ST2

G3

G2

G±

S4

G0

S3

INV

S2

DL4

S±

DL3

S0

DL2

OR±

DL± DL0

OR0 SR5

IV

x

FIP

0xXxxx

ST±

ST0

SR4

SR3

SR2

SR±

SR0

^±CODEC is always master, ID bits are read-only 0 (zeros).

²Bits for the AD±98x are backwards-compatible only, AC97NC and MSPLT are read-only ± (ones).

³SODIS/SOSEL were LODIS/LOSEL in the AD±985. Most AD±985 configurations swapped LINE_OUT and SURROUND pins; these bits really operated as SO not LO.

Rev. 0 | Page ±6 of 52

Preliminary Technical Data

REGISTER DETAILS

AD1986

RESET (REGISTER 0x00)

Writing any value to this register performs a register reset, which causes all registers to revert to their default values. The serial

configuration (0x74) register will not reset the SLOT16, REGM [2:0], SPOVR, SPAL, SPDZ, and SPLNK. These bits are reset on a hard,

hardware, or power-on reset. The REGM and serial configuration bits are only reset only by an external hardware reset.

The AC ’97, Revision 2.3, Page 1 registers CODEC class/rev (0x601), PCI SVID (0x621), PCI SID (0x641), function information (0x681—

per supported function), and sense register ST [3:0] bits (0x6A1 D [15:13]—per supported function) are only reset on a power-on reset.

To satisfy the AC ’97, Revision 2.3 requirements, these registers/bits are sticky across all software and hardware resets.

Reading this register returns the ID code of the part and a code for the type of 3D stereo enhancement.

Reg Name D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x00 Reset

x

SE4

SE3

SE2

SE±

SE0

ID9 ID8

ID7

ID6

ID5

ID4

ID3

ID2

ID±

ID0

0x0290

Table 30.

Register

Function

The ID decodes the capabilities of the AD±986 based on the functions.

ID [9:0] (RO)

(Identify

Capability)

Bit

Function

AD1986

ID [9:0]

ID0

ID±

ID2

ID3

ID4

ID5

ID6

ID7

ID8

ID9

Dedicated MIC PCM In channel

Reserved (per AC ’97, Revision 2.3)

Bass and treble control

Simulated stereo (mono to stereo)

Headphone out support

Loudness (bass boost) support

±8-bit DAC resolution

20-bit DAC resolution

±8-bit ADC resolution

20-bit ADC resolution

0

±

0x290

0

±

0

±

SE [4:0] (RO)

(Stereo

The AD±986 does not provide hardware 3D stereo enhancement

(all bits are zero).

Default: 0x00

Enhancement)

x

Reserved.

Default: 0

MASTER VOLUME (REGISTER 0x02)

This register controls the LINE_OUT, SURROUND, and CENTER/LFE outputs’ mute and volume controls in unison. Each volume sub-

register contains five bits, generating 32 volume steps of −1.5 dB each for a range of 0 dB to −46.5dB.

The headphone output (HP_OUT) mute and volume are controlled separately by the headphones volume register (0x04).The monaural

output (MONO_OUT) mute and volume is controlled separately by the mono volume register (0x06). To control the LINE_OUT,

SURROUND, and CENTER/LFE volumes separately use the front DAC volume register (0x18) for LINE_OUT; the surround DAC

Volume register (0x38) for SURROUND; and the C/LFE DAC volume register (0x36) for CENTER/LFE.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

D3

D2

D1

D0

Default

0x02 Master

Volume

LM

x

LV4 LV3 LV2 LV± LV0 RM

x

RV4 RV3 RV2 RV± RV0 0x8080

Rev. 0 | Page ±7 of 52

AD1986

Preliminary Technical Data

Table 31.

Register

Function

L/RV [4:0]

(Left/Right

Volume)

Left/right volume controls the left/right channel output gains from 0 dB to –46.5 dB.

The least significant bit represents –±.5 dB.

L/RM

L/RV [4:0]

0 0000

0 ±±±±

± ±±±±

x xxxx

Function

Default

0

±

0 dB

Default

−22.5 dB attenuation

−46.5 dB attenuation

Muted

L/RM

(Left/right mute)

Mutes the left/right channels independently.

Default: muted (0x±)

Default: 0

x

Reserved.

HEADPHONE VOLUME (REGISTER 0x04)

This register controls the HP_OUT mute and volume controls. Each volume subregister contains five bits, generating 32 volume steps of

−1.5 dB each for a range of 0 dB to −46.5 dB.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

D3

D2

D1

D0

Default

0x04 Headphones LM

Volume

x

LV4 LV3 LV2 LV± LV0 RM

x

RV4 RV3 RV2 RV± RV0 0x8080

Table 32.

Register

Function

L/RV [4:0]

(Left/Right

Volume)

Left/right volume controls the left/right channel output gains from 0 dB to –46.5 dB.

The least significant bit represents –±.5 dB.

L/RM

L/RV [4:0]

0 0000

0 ±±±±

± ±±±±

x xxxx

Function

Default

0

±

0 dB

Default

−22.5 dB attenuation

−46.5 dB attenuation

Muted

L/RM

(Left/Right Mute)

Mutes the left/right channels independently.

Default: muted (0x±)

Default: 0

x

Reserved.

MONO VOLUME (REGISTER 0x06)

This register controls the MONO_OUT mute and volume control. The volume register contains five bits, generating 32 volume steps of

−1.5 dB each for a range of 0 dB to −46.5 dB.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

V4 V3 V2 V± V0 0x8000

0x06 Mono Volume

M

x

Table 33.

Register

Function

Volume controls the output gain from 0 dB to –46.5 dB. The least significant bit represents -±.5 dB.

V [4:0]

(Volume)

M

0

±

V [4:0]

0 0000

0 ±±±±

± ±±±±

x xxxx

Function

Default

0 dB

Default

−22.5 dB attenuation

−46.5 dB attenuation

Muted

M (Mute)

x

Mutes the output.

Reserved.

Default: muted (0x±)

Default: 0

Rev. 0 | Page ±8 of 52

Preliminary Technical Data

AD1986

PC BEEP (REGISTER 0x0A)

This controls the level of the Analog PC beep or the level and frequency of the Digital PC beep. The volume register contains four bits,

generating 16 volume steps of −3.0 dB each for a range of 0 dB to −45.0 dB. The tone frequency can be set between 47 Hz to 12,000 Hz or

disabled.

Per Intel’s BIOS writer’s guide, the PC beep signal should play via headphone out, line out, and mono out paths. BIOS algorithms should

unmute the PC beep register and the path to each output, and set the volume levels for playback.

When the AD1986 is in reset (the external RESET pin is low), the PCBEEP_IN pin is connected internally to all of the device output pins

(HEADPHONE L/R, LINE_OUT L/R, MONO_OUT, SURROUND L/R, and CENTER/LFE). There are no amplifiers or attenuators on

this path and the external circuitry connected to this pin should anticipate the drive requirements for the multiple output sources.

Headphones connected to output pins will substantially load the signal.

Reg

0x0A PC

Beep

Name

D15 D14

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

F7 F6 F5 F4 F3 F2 F± F0 V3 V2 V± V0 0x8000

M

A/DS

x

Table 34.

Register

Function

V [3:0]

(Analog or

Digital

Controls the gain into the output mixer from 0 dB to −45.0 dB. The least significant bit represents −3.0 dB. The gain default

is 0 dB and muted.

M

0

V3...V0

0000

Function

0 dB

Default

Volume)

Default

0

±

±±±±

xxxx

−45 dB attenuation

Muted

F [7:0]

(PC Beep

Frequency)

The result of dividing the 48 kHz clock by four times this number, allowing tones from 47 Hz to ±2 kHz. A value of 0x00

disables internal PC beep generation. The digitally-generated signal is close to a square wave and is not intended to be a

high quality signal.

F7...F0

0000

Function

Disabled

Default

000±

±±±±

±2,000 Hz tone

47 Hz tone

A/DS

(PC Beep

Source)

Selects either the digital PC beep generator (= 0) or analog PCBEEP pin (= ±). When the

CODEC is in reset mode the analog PCBEEP pin is routed to the outputs via a high

impedance path. Once ot of reset, this bit must be programmed to a ± to pass through any

signals on the analog PCBEEP pin. Designers may choose not to connect the analog PCBEEP

pin and use the digital PC beep generator solely.

Default: digitally-selected

(0x0)

M

When this bit is set to ±, the PC beep signal (analog or digital) is muted.

Default: muted (0x±)

Default: 0

(PC Beep

Mute)

x

Reserved.

PHONE VOLUME (REGISTER 0x0C)

This register controls the PHONE_IN mute and gain to the analog mixer section. The volume register contains five bits, generating

32 volume steps of 1.5 dB each for a range of 12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).

Reg

Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

V4 V3 V2 V± V0 0x8008

0x0C Phone

Volume

M

x

Rev. 0 | Page ±9 of 52

AD1986

Preliminary Technical Data

Table 35.

Register

Function

Controls the gain of this input to the analog mixer from ±2.0 dB to −34.5 dB. The least significant bit represents −±.5 dB.

V [4:0]

(Volume)

MV

0

±

[4:0]

Function

±2 dB gain

0 dB

−34.5 dB attenuation

Muted

Default

0 0000

0 ±000

± ±±±±

x xxxx

Default

M (Mute)

x

Mutes the input to the analog mixer.

Reserved.

Default: muted (0x±)

Default: 0

MICROPHONE VOLUME (REGISTER 0x0E)

This register controls the MIC_1 (left) and MIC_2 (right) channels’ gain, boost, and mute to the analog mixer section. The volume

register contains five bits, generating 32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the

record ADC gain (see Register 0x1C).

In typical stereo microphone applications, the signal paths must be identical and should be set to the same gain, boost, and mute values.

With stereo controls, this input is capable of nonmicrophone sources by disabling the microphone boost (M20 Bit = 0).

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6

D5 D4

D3

D2

D1

D0

Default

0x0E Microphone LM

Volume

x

LV4 LV3 LV2 LV± LV0 RM M20

x RV4 RV3 RV2 RV± RV0 0x8888

Table 36.

Register

Function

Controls the left/right channel gains of this input to the analog mixer from +±2 dB to −34.5 dB. The least significant bit

L/RV [4:0]

(Left/Right represents −±.5 dB.

Volume)

L/RM

L/RV [4:0]

Function

±2 dB gain

0 dB

−34.5 dB attenuation

Mute

Default

0

±

0 0000

0 ±000

± ±±±±

x xxxx

Default

M20

(MIC_±/2

Gain

Enables additional gain to increase the microphone sensitivity. This controls the boost of both the MIC_± and MIC_2 channels.

The nominal gain boost by default is 20 dB; however, MBG0 [±:0] bits (Register 0x76), allow changing the gain boost to ±0 dB

or 30 dB if necessary.

Boost)

M20

MGB0 [1:0]

Boost Gain

0 dB gain

20 dB gain

±0 dB gain

Mute

0

±

xx

00

0±

x xxxx

Default: disabled

Default

L/RM

(Left/Right

Mute)

Mutes the left/right channels independently.

Default: muted (0x±)

Default: 0

x

Reserved.

Rev. 0 | Page 20 of 52

Preliminary Technical Data

AD1986

LINE IN VOLUME (REGISTER 0x10)

This register controls the LINE_IN gain and mute to the analog mixer section. The volume register contains five bits, generating

32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

D3

D2

D1

D0

Default

0x±0 Line In

Volume

LM

x

LV4 LV3 LV2 LV± LV0 RM

x

RV4 RV3 RV2 RV± RV0 0x8888

Table 37.

Register

Function

L/RV [4:0]

(Left/Right

Volume)

Controls the left/right channel gains of this input to the analog mixer from ±2 dB to −34.5 dB. The least significant bit

represents −±.5 dB.

L/RM

L/RV [4:0]

0 0000

0 ±000

± ±±±±

x xxxx

Function

±2 dB gain

0 dB

Default

0

±

Default

−34.5 dB attenuation

Muted

L/RM

(Left/Right

Mute)

Mutes the left/right channels independently.

Default: muted (0x±)

Default: 0

x

Reserved.

CD VOLUME (REGISTER 0x12)

This register controls the CD gain and mute to the analog mixer section. The volume register contains five bits, generating 32 volume

steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).

Many operating systems will play CDs directly using the digital data from the CD tracks. This control will only affect CD audio playback

if it is enabled for analog and this input is connected to the CD player analog connection.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

D3

D2

D1

D0

Default

0x±2 CD Volume LM

x

LV4 LV3 LV2 LV± LV0 RM

x

RV4 RV3 RV2 RV± RV0 0x8888

Table 38.

Register

Function

L/RV [4:0]

(Left/Right

Volume)

Controls the left/right channel gains of this input to the analog mixer from +±2 dB to –34.5 dB. The least significant bit

represents –±.5 dB.

L/RM

L/RV [4:0]

0 0000

0 ±000

Function

±2 dB gain

0 dB

Default

0

Default

± ±±±±

−34.5 dB attenuation

Muted

±

x xxxx

L/RM

(Left/Right

Mute)

Mutes the left/right channels independently.

Default: muted (0x±)

Default: 0

x

Reserved.

Rev. 0 | Page 2± of 52

AD1986

Preliminary Technical Data

AUX VOLUME (REGISTER 0x16)

This register controls the AUX_IN gain and mute to the analog mixer section. The volume register contains five bits, generating

32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB. This does not control the record ADC gain (see Register 0x1C).

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

D3

D2

D1

D0

Default

0x±6 AUX

Volume

LM

x

LV4 LV3 LV2 LV± LV0 RM

x

RV4 RV3 RV2 RV± RV0 0x8888

Table 39.

Register

Function

L/RV [4:0]

(Left/Right

Volume)

Controls the left/right channel gains of this input to the analog mixer from +±2 dB to −34.5 dB. The least significant bit

represents −±.5 dB.

L/RM

L/RV [4:0]

0 0000

0 ±000

± ±±±±

x xxxx

Function

±2 dB gain

0 dB

Default

0

±

Default

−34.5 dB attenuation

Mute

L/RM

(Left/Right

Mute)

Mutes the left/right channels independently.

Default: muted (0x±)

Default: 0

x

Reserved.

FRONT DAC VOLUME (REGISTER 0x18)

This register controls the front DAC gain and mute to the analog mixer section. The volume register contains five bits, generating

32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

D3

D2

D1

D0

Default

0x±8 Front DAC

Volume

LM LV4 LV3 LV2 LV± LV0 RM RV4 RV3 RV2 RV± RV0 0x8888

x

Table 40.

Register

Function

L/RV [4:0]

(Left/Right Volume)

Controls the left/right channel gains of this input to the analog mixer from +±2 dB to −34.5 dB. The least significant

bit represents −±.5 dB.

L/RM

L/RV [4:0]

0 0000

0 ±000

± ±±±±

x xxxx

Function

Default

0

±

+±2 dB gain

0 dB

−34.5 dB attenuation

Mute

Default

L/RM

(Left/Right Mute)

Mutes the left/right channels independently.

Default: muted (0x±)

Default: 0

x

Reserved.

Rev. 0 | Page 22 of 52

Preliminary Technical Data

AD1986

ADC SELECT (REGISTER 0x1A)

This register selects the record source for the ADC, independently for the right and left channels. The default value is 0x0000, which

corresponds to the MIC_1/2 input for both channels.

Reg

0x±A ADC

Select

Name

D15 D14 D13 D12 D11 D10 D9

D8

D7 D6 D5 D4 D3 D2

D1

D0

Default

x

LS2

LS± LS0

x

RS2 RS± RS0 0x0000

Table 41.

Register

LS [2:0]

000

00±

Left Record Source

Function

Default

Left

LS [2:0]

(Left Record Select)

MIC_±/2 selector left channel

CD_IN

0±0

Muted

0±±

AUX_IN

Left

±00

LINE_IN

Left

±0±

±±0

±±±

Stereo output mix

Mono output mix

PHONE_IN

Left

Mono

RS [2:0]

(Right Record Select)

RS [2:0]

000

00±

Right Record Source

MIC_±/2 selector left channel

CD_IN

Default

Right

0±0

Muted

0±±

±00

±0±

±±0

AUX_IN

LINE_IN

Stereo output mix

Mono output mix

PHONE_IN

Right

Mono

±±±

Table 42. Microphone Selector

OMS [2:0]¹

000

00±

0±x

MMIX²

2CMIC³

MS⁴

Left Channel⁵

Right Channel

0

±

0

±

0

±

0

±

0

±

x

0

±

x

0

±

x

0

±

x

0

±

0

±

x

0

±

0

±

x

0

±

0

±

x

0

±

0

±

x

MIC_± (default)

MIC_2

MIC_±

MIC_2

MIC_±

MIC_± + MIC_2 (mixed)

LINE_IN left

LINE_IN right

LINE_IN left

LINE_IN right

Line in—left + right (mixed)

CENTER

0±x

LFE

CENTER

LFE

CENTER

CENTER + LFE (mixed)

MIC_± + CENTER (mixed)

MIC_2 + LFE (mixed)

±00

MIC_± + CENTER (mixed)

MIC_2 + LFE (mixed)

MIC_± + CENTER (mixed)

MIC_± + MIC_2 + CENTER + LFE (mixed)

Rev. 0 | Page 23 of 52

AD1986

Preliminary Technical Data

OMS [2:0]¹

MMIX²

2CMIC³

MS⁴

Left Channel⁵

Right Channel

±0±

±±0

±±±

0

±

0

±

0

±

0

±

x

0

±

x

0

±

x

0

±

0

±

x

0

±

0

±

x

0

±

0

±

x

MIC_± + LINE_IN left (mixed)

MIC_2 + LINE_IN right (mixed)

MIC_± + LINE_IN left (mixed)

MIC_2 + LINE_IN right (mixed)

MIC_± + MIC_2 + LINE_IN left + LINE right (mixed)

LINE_IN left + CENTER (mixed)

LINE_IN right + LFE (mixed)

LINE_IN left + CENTER (mixed)

LINE_IN right + LFE (mixed)

LINE_IN left + CENTER (mixed)

LINE_IN left + LINE_IN right + CENTER + LFE (mixed)

MIC_± + LINE_IN left + CENTER (mixed)

MIC_2 + LINE_IN right + LFE (mixed)

MIC_± + LINE_IN left + CENTER (mixed)

MIC_2 + LINE_IN right + LFE (mixed)

MIC_± + LINE_IN left + CENTER (mixed)

MIC_± + MIC_2 + LINE_IN left + LINE_IN right + CENTER + LFE (mixed)

^±To select the alternate pins as a microphone source, see the OMS [2:0] bit (Register 0x74).

²To mix the left/right MIC channels see MMIX bit (Register 0x7A).

³For dual MIC recording see 2CMIC bit (Register 0x76) to enable simultaneous recording into L/R channels.

⁴To swap left/right MIC channels, see the MS bit (Register 0x20) for MIC_±/2 selection.

⁵The MONO_OUT pin may be connected to the left channel of the microphone selector and is affected by these bits.

ADC VOLUME (REGISTER 0x1C)

This register controls the mute and gain of the ADC record path. The volume register contains four bits, generating 16 volume steps of

1.5 dB each for a range of 0 dB to 22.5 dB.

Reg

Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3

D2

D1

D0

Default

0x±C ADC Volume LM

x

LV3 LV2 LV± LV0 RM

x

RV3 RV2 RV± RV0 0x8080

Table 43.

Register

Function

L/RV [4:0]

(Left/Right

Volume)

Controls the left/right channel gains of this input to the analog mixer from 0 dB to 22.5 dB The least significant bit

represents ±.5 dB.

L/RM

L/RV [3:0]

0000

Function

0 dB

Default

0

±

Default

±000

±±±±

xxxx

±2.0 dB gain

22.5 dB gain

Muted

L/RM

(Left/Right Mute)

Mutes the left/right channels independently.

Default: muted (0x±)

Default: 0

x

Reserved.

Rev. 0 | Page 24 of 52

Preliminary Technical Data

AD1986

GENERAL-PURPOSE (REGISTER 0x20)

This register should be read before writing to generate a mask for only the bit(s) that need to be changed.

Reg Name

D15 D14 D13 D12 D11

D10

D9

D8 D7

D6 D5 D4 D3 D2 D1 D0 Default

0x0000

0x20 General-

Purpose

x

DRSS± DRSS0 MIX MS LPBK

x

Table 44.

Register

Function

Default

LPBK

(Loop-

Back

This bit enables the digital internal loop back from the ADC to the front DAC. This feature is normally used for

testing and troubleshooting. See LBKS bit in Register 0x74 for changing the loop back path to use the

SURROUND or CENTER/LFE DACs.

Default:

disabled

(0x0)

Control)

MS

(MIC

Select)

Used in conjunction with the OMS [2:0] (0x74 D±0:08]), 2CMIC (0x76 D06) and MMIX (0x7A D02). Selects which

MIC input goes into the ADC0 record selector’s MIC channel inputs. When set, this bit swaps the left and right

channels. Selects mono output audio source.

MIX

0

±

Mono Output Connection

(Mono

Output

Select)

MIX—Connected to the mono mixer output.

MIC—Connected to the left channel of the MIC selector and swap.

Default

DRSS [±:0] The DRSS bits specify the slots for the n+± sample outputs. PCM L (n+±) and PCM R (n+±) data are by default

(Double

Rate Slot

Select)

provided in output Slots ±0 and ±±.

DRSS [1:0]

Function

00

0±

±x

PCM L, R (n+±) data is on Slots ±0 and ±±

PCM L, R (n+±) data is on Slots 7 and 8

Reserved

Default

x

Reserved.

Default: 0

AUDIO INT AND PAGING (REGISTER 0x24)

This register controls the audio interrupt and register paging mechanisms.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3

D2

D1

D0

Default

0x24 Audio Int and I4

Paging

I3 I2 I± I0 PG3 PG2 PG± PG0 0xxx00

x

Table 45.

Register

Function

PG [3:0]

(Page Selector

(Read/Write))

This register is used to select a descriptor of ±6 word pages between Registers 0x60 to 0x6F. A value of 0x0 is used to

select vendor specific space to maintain compatibility with AC ’97 Revision 2.2 vendor specific registers. System

software can determine implemented pages by writing the page number and reading the value back. If the value read

back does not match the value written, the page is not implemented. All implemented pages must be in consecutive

order (i.e. Page 0x2 cannot be implemented without Page 0x±).

PG [3:0]

Addressing Page Selection

Page 0 (vendor) registers

Page ID 0±, registers defined in AC ’97, Revision 2.3

Reserved

Default

000 (Page 0)

00± (Page ±)

Page 0xh–0xF

Default

I0

Software should not unmask the interrupt unless ensured by the AC ’97 controller that no conflict is possible with

modem Slot ±2—GPI functionality. AC ’97 Revision 2.2 compliant controllers will not likely support audio CODEC

interrupt infrastructure. In that case, software can poll the interrupt status after initiating a sense cycle and waiting for

sense cycle max delay (defined by software) to determine if an interrupting event has occurred.

(Interrupt Enable

(Read/Write))

I0

0

±

Interrupt Mask Status

Interrupt generation is masked

Interrupt generation is unmasked

Default

Rev. 0 | Page 25 of 52

AD1986

Preliminary Technical Data

Register

Function

I±

Writing a ± to this bit causes a sense cycle start if supported. If a sense cycle is in progress, writing a 0 to this bit will

abort the sense cycle. The data in the sense result register (0x6A, Page 0±) may or may not be valid, as determined by

the IV bit.

(Sense Cycle

(Read/Write))

I1

Read

Write

0

Sense cycle completed (or not initiated)

Default

Aborts sense cycle (if in

process)

±

Sense cycle still in process

Initiate sense cycle

These bits will indicate the cause(s) of an interrupt. This information should be used to service the correct interrupting

event(s). If the Interrupt Status (Bit I4) is set, one or both of these bits must be set to indicate the interrupt cause.

Hardware will reset these bits back to zero when the interrupt status bit is cleared.

I [3:2]

(Interrupt Cause

(RO))

I2

0

Interrupt Status

Sense status has not changed (did not cause interrupt). Default

Sense cycle completed or new sense information is available

±

I3

0

GPIO status change did not cause interrupt

GPIO status change caused interrupt

±

I4

Interrupt event is cleared by writing a ± to this bit. The interrupt bit will change regardless of condition of interrupt

enable (I0) status. An interrupt in the GPI in Slot ±2 in the AC link will follow this bit change when interrupt enable (I0)

is unmasked. If this bit is set, one or both of I3 or I2 must be set to indicate the interrupt cause.

(Interrupt Status

(Read/Write))

I4

Read

Write

0

±

Interrupt clear

Interrupt generated

Default

No operation

Clears interrupt

Default: 0

x

Reserved.

POWER-DOWN CTRL/STAT (REGISTER 0x26)

The ready bits are read only; writing to REF, ANL, DAC, and ADC has no effect. These bits indicate the status for the AD1986

subsections. If the bit is 1 then that subsection is ready. ‘Ready’ is defined as the subsection able to perform in its nominal state.

Reg Name

D15

D14 D13 D12 D11 D10 D9

D8

D7 D6 D5 D4 D3 D2

D1

D0

Default

0x26 Power-

Down

EAPD PR6 PR5 PR4 PR3 PR2 PR± PR0

x

REF ANL DAC ADC 0x000x

Ctrl/Stat

Table 46.

Register

ADC

ADC Status

0

±

ADC not ready

ADC (RO)

(ADC Section

Status (RO))

ADC sections ready to transmit data

DAC

Front DAC Status

ADC (RO)

((Front DAC

Status (RO))

0

±

ADC not ready

ADC sections ready to transmit data

Analog Status

ANL (RO)

ANL

(Analog

0

±

Analog amplifiers, attenuators and mixers not ready

Analog amplifiers, attenuators and mixers ready

Amplifiers,

Attenuators and

Mixers Status

(RO))

Rev. 0 | Page 26 of 52

Preliminary Technical Data

AD1986

Register

ADC

ADC Status

REF (RO)

VREF_OUT pin output states controlled by the CV_REF, MV_REF, and LV_REFcontrols in Register 0x70.

(Voltage

REF

0

±

V_REFStatus

References, V_REF

and VREF_OUT

status (read

only))

Voltage References, VREF and VREF_OUT not ready.

Voltage References, VREF, and VREF_OUT up to nominal level.

PR0

PR±

PR2

PR3

All ADCs and input selectors’ power down: clearing this bit enables VREF regardless of the state of PR3.

Default: all ADCs and input muxs powered on (0x0).

All DACs power down. Also powers down the EQ circuitry. Clearing this bit enables VREF regardless of the state of PR3.

Default: all DACs and EQ powered on (0x0).

Analog mixer power down. (valid if PR7 = 0).

Default: analog mixer powered on (0x0).

All V_REFand V_REF_OUT pins power down. May be used in combination with PR2 or by itself. If all the ADCs and DACs are

not powered down, setting this bit will have no effect on the V_REFand will only power down VREF_OUT.

Default: All VREFand VREF_OUT pins powered on (0x0).

PR4

PR5

AC-Link Interface power down. The reference and the mixer can be either up or down, but all power-up sequences

must be allowed to run to completion before PR5 and PR4 are both set. In multiple-CODEC systems, the master

CODEC’s PR4 bit controls the slave CODEC. In the slave CODEC the PR4 bit has no effect except to enable or disable PR5.

Default: AC-link Interface powered on (0x0).

Internal Clocks disabled.

PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down (e.g. PR0, PR±, PR4). The reference and the

mixer can be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4

are both set. In multiple CODEC systems, the master CODEC’s PR5 controls the slave CODEC. PR5 is effective in the slave

CODEC if the master's PR5 bit is clear.

Default: internal clocks enabled (0x0).

PR6

Powers down the headphone amplifiers.

Default: HP amp powered on (0x0).

EAPD

EAPD Pin Status

0

±

Sets the EAPD pin low, enabling an external power amplifier.

Sets the EAPD pin high, shutting the external power amplifier off.

Default

x

Reserved.

Default: 0

EXT’D AUDIO ID (REGISTER 0x28)

The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates one

or more of the extended audio features are supported.

Reg

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x28

Ext’d Audio ID

ID±

ID0

x

X

REV±

REV0

AMAP

LDAC

SDAC

CDAC

DSA±

DSA0

x

SPDF

DRA

VRA

0x0BC7

Table 47.

Register

VRA (RO)

SPDIF (RO)

DRA (RO)

DSA [±:0]

Description

Setting Function

Variable rate PCM audio: read only

SPDIF support: read only

= ±

Variable rate PCM audio supported

SPDIF transmitter supported (IEC958)

Double rate audio: read only

DAC slot assignment (read/write)

Double rate audio supported for DAC0 L/R

Front DAC

Surround DAC

C/LFE DAC

Default

DSA [1:0]

Left

3

7

6

±0

Right

Left

7

6

±0

3

Right

Left

6

±0

3

Right

00

0±

±0

±±

4

8

9

±±

8

9

±±

4

9

±±

4

Default

7

8

Rev. 0 | Page 27 of 52

AD1986

Preliminary Technical Data

Register

CDAC (RO)

SDAC (RO)

LDAC (RO)

AMAP (RO)

REV [±:0] (RO)

ID [±:0] (RO)

x

Description

Setting Function

PCM CENTER DAC: read only

PCM Surround DAC: read only

PCM LFE DAC: read only

Slot DAC mappings: read only

AC97 version: read only

CODEC configuration: read only

Reserved

= ±

PCM center DAC supported

CM Surround DACs supported

= ±

PCM LFE DAC supported

CODEC ID based slot/DAC mappings

CODEC is AC ’97, Revision 2.3 compliant

Primary AC ‘97

= ±

= ±0

= 00

Default: 0

EXT’D AUDIO STAT/CTRL (REGISTER 0x2A)

The extended audio status and control register is a read/write register that provides status and control of the extended audio features.

Reg

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x2A

Ext’d Audio Stat/Ctrl

x

PRK

PRJ

PRI

SPCV

x

LDAC

SDAC

CDAC

SPSA±

SPSA0

x

SPDIF

DRA

VRA

0x0xx0

Table 48.

Register

Function

Enables variable rate audio mode. Enables sample rate registers and SLOTREQ signaling.

VRA

(Variable Rate

Audio)

VRA

VRA State

Default

0

±

Disabled, sample rate 48 kHz for all ADCs and DACs

Enabled, ADCs and DACs can be set to variable sample rates

Default

DRA

(Double Rate

Audio)

DRA = ±. Enables double-rate audio mode in which data from PCM L and PCM R in Output Slots 3 and 4 is used in

conjunction with PCM L (n + ±) and PCM R (n + ±) data to provide DAC streams at twice the sample rate designated by the

PCM front sample rate control register. When using the double rate audio, only the front DACs are supported and all other

DACs (surround, center, and LFE) are automatically powered down. The slot that contains the additional data is

determined by the DRSS[±:0] bits (0x20 D [±±:±0]). Note that DRA can be used without VRA; in which case the converter

rates are forced to 96 kHz if DRA = ±.

DRA

DRA State

Default

0

±

Disabled, DACs sample at the programmed rate

Enabled, DACs sample at twice (2×) the programmed rate

Default

SPDIF

SPDIF transmitter subsystem enable/disable bit (read/write)

This bit is also used to validate that the SPDIF transmitter output is actually enabled. The SPDIF bit is only allowed to be set

high, if the SPDIF pin (48) is pulled down at power-up enabling the CODEC transmitter logic. If the SPDIF pin is floating or

pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a low, indicating that the SPDIF

transmitter is not available. This bit must always be read back, to verify that the SPDIF transmitter is actually enabled.

SPDIF

Function

0

±

Disables the S/PDIF transmitter

Enables the S/PDIF transmitter

Default

AC '97 Revision 2.2 AMAP compliant default SPDIF slot assignments.

SPSA [±:0]

(SPDIF Slot

Assignment

Bits:

SPSA [1:0]

S/PDIF Slot Assignment

3 and 4

00

0±

±0

±±

CDAC

0

Default

7 and 8

6 and 9

(Read/Write))

±0 and ±±

CDAC (RO)

(CENTER DAC

Status (RO))

CENTER DAC Status

CENTER DAC not ready

CENTER DAC section ready to receive data

Surround DAC not ready

Surround DAC section ready to receive data

±

0

±

Rev. 0 | Page 28 of 52

Preliminary Technical Data

AD1986

Register

Function

LDAC (RO)

(LFE DAC

Status (RO))

LDAC

LFE DAC Status

0

±

LFE DAC not ready

LFE DAC section ready to receive data

SPCV (RO)

(SPDIF

Indicates the status of the SPDIF transmitter subsystem, enabling the driver to determine if the currently programmed

SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status.

Configuration

Valid (RO))

SPCV

S/PDIF Configuration Status

0

±

Invalid SPDIF configuration {SPSA, SPSR, DAC slot rate, DRS}

Valid SPDIF configuration

PRI

Actual status reflected in the CDAC (0x3A D06) bit.

(Center DAC

Power-Down)

PRI

0

±

CENTER DAC Power Status

Power-on CENTER DAC

Power-down CENTER DAC

Default

PRJ

Actual status reflected in the SDAC bit.

(Surround

DACs Power-

Down)

PRJ

0

±

Surround DACs Power Control

Power-on surround DACs

Power-down surround DACs

PRK

Actual status reflected in the LDAC bit.

(LFE DAC

Power-Down)

PRK

LFE DACs Power Control

0

Power-on LFE DAC

Default

±

Power-down LFE DAC

x

Reserved.

Default: 0

FRONT DAC PCM RATE (REGISTER 0x2C)

This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit

(0x2A D00) is 0 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.

To use 96 kHz in AC ’97 mode set the double rate audio (DRA) bit (0x2A D01). When using DRA in AC ’97, only the front DACs are

supported and all other DACs (surround, center, and LFE) are automatically powered down.

Reg

Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

0x2C Front DAC PCM

Rate

R±5 R±4 R±3 R±2 R±± R±0 R9 R8 R7 R6 R5 R4 R3 R2 R± R0 0xBB80

Table 49.

Register Function

R [±5:0]

(Sample

Rate)

The sampling frequency range is from 7 kHz (0x0±B58) to 48 kHz (0xBB80) in ± Hz increments. If 0 is written to VRA, then the

sample rates are reset to 48k.

Rev. 0 | Page 29 of 52

AD1986

Preliminary Technical Data

SURROUND DAC PCM RATE (REGISTER 0x2E)

This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit

(0x2A D00) is 0, this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.

If the DRA bit (0x2A D01) is set, the surround DAC is inoperative and automatically powered down.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

0x2E SURR_± DAC PCM R±5 R±4 R±3 R±2 R±± R±0 R9 R8 R7 R6 R5 R4 R3 R2 R± R0 0xBB80

Rate

Table 50.

Register Function

R [±5:0]

(Sample

Rate)

The sampling frequency range is from 7 kHz (0x0±B58) to 48 kHz (0xBB80) in ± Hz increments. If zero is written to VRA then the

sample rates are reset to 48k.

C/LFE DAC PCM RATE (REGISTER 0x30)

This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit

(0x2A D00) is 0 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.

If the DRA bit (0x2A D01) is set, the C/LFE DAC is inoperative and automatically powered down.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

R±5 R±4 R±3 R±2 R±± R±0 R9 R8 R7 R6 R5 R4 R3 R2 R± R0 0xBB80

0x30 C/LFE DAC

PCM Rate

Table 51.

Register Function

R [±5:0]

(Sample

Rate)

The sampling frequency range is from 7 kHz (0x0±B58) to 48 kHz (0xBB80) in ± Hz increments. If 0 is written to VRA then the

sample rates are reset to 48k.

ADC PCM RATE (REGISTER 0x32)

This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit (0x2A

D00) is 0 (zero) this register is forced to 48 kHz (0xBB80). If VRA is 1, this register may be programmed with the actual sample rate.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

R±5 R±4 R±3 R±2 R±± R±0 R9 R8 R7 R6 R5 R4 R3 R2 R± R0 0xBB80

0x32 ADC 0 PCM

Rate

Table 52.

Register Function

R [±5:0]

(Sample

Rate)

The sampling frequency range is from 7 kHz (0x0±B58) to 48 kHz (0xBB80) in ± Hz increments. If 0 is written to VRA then the

sample rates are reset to 48k.

Rev. 0 | Page 30 of 52

Preliminary Technical Data

AD1986

C/LFE DAC VOLUME (REGISTER 0x36)

This register controls the CENTER/LFE DAC gain and mute to the output selector section. The volume register contains five bits,

generating 32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB.

Note that the left/right association of the CENTER and LFE channels can be swapped at the CODEC outputs by setting the CSWP bit in

Register 74h. These controls remain unchanged regardless of the state of CSWP.

Reg

Name

D15

D14 D13 D12

D11

D10

D9

D8

D7

D6 D5 D4

D3

D2

D1

D0

Default

0x36 C/LFE

DAC

LFEM

x

LFE4 LFE3 LFE2 LFE± LFE0 CNTM

x

CNT4 CNT3 CNT2 CNT± CNT0 0x8888

Volume

Table 53.

Register

CNT [4:0]

Function

Controls the gain of the CENTER channel to the output selector section from +±2.0 dB to −34.5 dB. The least significant

(Center Volume) bit represents −±.5 dB.

CNTM

CNT [4:0]

Function

Default

0

±

0 0000

0 ±000

± ±±±±

x xxxx

+±2 dB gain

0 dB attenuation

−34.5 dB attenuation

Muted

Default

CNTM

Mutes the center channel.

Default: muted (0x±)

(Center Mute)

LFE [4:0]

(LFE Volume)

Controls the gain of the LFE channel to the output selector section from +±2.0 dB to −34.5 dB. The least significant bit

represents −±.5 dB.

LFEM

LFE[4:0]

0 0000

0 ±000

± ±±±±

x xxxx

Function

0

±

+±2 dB gain

0 dB attenuation

−34.5 dB attenuation

Muted

Default

LFEM

(LFE Mute)

Mutes the LFE channel.

Default: muted (0x±)

Default: 0

x

Reserved.

SURROUND DAC VOLUME (REGISTER 0x38)

This register controls the SURROUND DAC gain and mute to the output selector section. The volume register contains five bits,

generating 32 volume steps of −1.5 dB each for a range of +12.0 dB to −34.5 dB.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

D3

D2

D1

D0

Default

0x±8 Surround

DAC

LM

x

LV4 LV3 LV2 LV± LV0 RM

x

RV4 RV3 RV2 RV± RV0 0x8888

Volume

Table 54.

Register

Function

L/RV [4:0]

(Left/Right

Volume)

Controls the left/right channel gains of this input to the output selector section from +±2 dB to -34.5 dB. The least

significant bit represents −±.5 dB.

L/RM

L/RV [4:0]

0 0000

0 ±000

± ±±±±

x xxxx

Function

Default

0

±

+±2 dB gain

0 dB

−34.5 dB attenuation

Muted

Default

L/RM

(Left/Right

Mute)

Mutes the left/right channels independently.

Default: muted (0x±)

Default: 0

x

Reserved.

Rev. 0 | Page 3± of 52

AD1986

Preliminary Technical Data

SPDIF CONTROL (REGISTER 0x3A)

Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe

in the V-case). With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in

Register 0x2A is 0). This ensures that control and status information start up correctly at the beginning of SPDIF transmission.

Reg

Name D15 D14

D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

/AUDIO

D0

Default

SPDIF

0x3A

V

VCFG SPSR

x

L

CC6 CC5 CC4 CC3 CC2 CC± CC0 PRE COPY

PRO 20000x

Control

Table 55.

Register

Function

Indicates professional use of the audio stream.

PRO

(Professional)

PRO

State

Default

0

±

Consumer use of channel

Professional use of channel

Default

/AUDIO

(Nonaudio)

Indicates that the data is PCM or another format (such as AC3).

/AUDIO

State

0

±

Data in PCM format

Data in non-PCM format

COPY

(Copyright)

Allows receivers to make copies of the digital data.

COPY

State

0

±

Copyright asserted

Copyright not asserted

PRE

(Pre-emphasis)

Disables filter pre-emphasis.

PRE

0

State

Filter pre-emphasis is 50/±5 µsec

±

No pre-emphasis

CC [6:0]

(Category Code)

Programmed according to IEC standards, or as appropriate.

Chooses between 48.0 kHz and 44.± kHz S/PDIF transmitter rate.

L

(Generation Level)

SPSR

(SPDIF Transmit

Sample Rate)

SPSR

Transmit Sample Rate

44.± kHz

48.0 kHz

0

±

Default

VCFG

(Validity Force Bit)

When asserted, this bit forces the SPDIF stream validity flag (bit < 28 > within each SPDIF L/R subframe) to be controlled by

the validity bit (D±5) in Register 0x3A (SPDIF control register).

VCFG

V

0

±

Validity Bit State

Reset Default: 0

Default

0

Managed by CODEC error detection logic

Forced high, indicating subframe data is

invalid

±

0

±

Forced low, indicating subframe data is valid

Forced high, indicating subframe data is

invalid

V

This bit affects the validity flag, (bit <28 > transmitted in each SPDIF L/R subframe) and enables the SPDIF transmitter to

maintain connection during error or mute conditions. Note that the VCFG bit (0x3A D±4) will force the validity flag high (valid)

or low (invalid). See the VCFG bit description.

(Validity)

V

State

0

Each SPDIF subframe (L+R) has bit <28> set to ±

This tags both samples as invalid

Default

±

Each SPDIF subframe (L+R) has bit <28> set to 0 for valid data and ± for invalid data (error condition)

Default: 0

x

Reserved.

Rev. 0 | Page 32 of 52

Preliminary Technical Data

AD1986

EQ CONTROL REGISTER (REGISTER 0x60)

Register 0x60 is a read/write register that controls equalizer function and data setup. The register also contains the Biquad and coefficient

address pointer, which is used in conjunction with the EQ data register (0x78) to setup the equalizer coefficients. The reset default

disables the equalizer function until the coefficients can be properly set up by the software and sets the symmetry bit to allow equal

coefficients for left and right channels.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5

D4

D3

D2

D1

D0

Default

0x60 EQ

Control

EQM SYM CHS BCA5 BCA4 BCA3 BCA2 BCA± BCA0 0x8080

x

Table 56. Biquad and Coefficient Address Pointer

BCA [5,0]

Biquad 0

Coef a0

Coef a±

Coef a2

Coef b±

Coef b2

BCA [5,0] = 0±±0±±

BCA [5,0] = 0±±0±0

BCA [5,0] = 0±±00±

BCA [5,0] = 0±±±0±

BCA [5,0] = 0±±±00

Biquad 3

Biquad 4

Coef a2

Coef b±

Coef b2

Coef a0

Coef a±

Coef a2

Coef b±

Coef b2

BCA [5,0] = ±0±000

BCA [5,0] = ±0±±00

BCA [5,0] = ±0±0±±

BCA [5,0] = ±0±±±±

BCA [5,0] = ±0±±±0

BCA [5,0] = ±0±±0±

BCA [5,0] = ±±000±

BCA [5,0] = ±±0000

Biquad ±

Coef a0

Coef a±

Coef a2

Coef b±

Coef b2

BCA [5,0] = ±00000

BCA [5,0] = 0±±±±±

BCA [5,0] = 0±±±±0

BCA [5,0] = ±000±0

BCA [5,0] = ±0000±

Biquad 5

Coef a0

Coef a±

Coef a2

Coef b±

Coef b2

BCA [5,0] = ±±0±00

BCA [5,0] = ±±00±±

BCA [5,0] = ±±00±0

BCA [5,0] = ±±0±±0

BCA [5,0] = ±±0±0±

Biquad 2

Coef a0

Coef a±

Coef a2

Coef b±

Coef b2

BCA [5,0] = ±00±0±

BCA [5,0] = ±00±00

BCA [5,0] = ±000±±

BCA [5,0] = ±00±±±

BCA [5,0] = ±00±±0

Biquad 6

Coef a0

Coef a±

Coef a2

Coef b±

Coef b2

BCA [5,0] = ±±±00±

BCA [5,0] = ±±±000

BCA [5,0] = ±±0±±±

BCA [5,0] = ±±±0±±

BCA [5,0] = ±±±0±0

Biquad 3

Coef a0

Coef a±

BCA [5,0] = ±0±0±0

BCA [5,0] = ±0±00±

Table 57.

Register

Function

CHS

Swaps the blocks that are used for symmetry coefficients. Only valid when the SYM bit is set.

(Channel

Select)

CHS

Function

Default

0

±

Selects left channel coefficients data block

Selects right channel coefficients data block

Default

SYM

When set to ± this bit indicates that the left and right channel coefficients are equal.

(Symmetry)

This shortens the coefficients setup sequence since only the left channel coefficients need to be addressed and setup. The

right channel coefficients are simultaneously copied into memory.

SYM

Function

0

±

Left and right channels can use different coefficients

Indicates that the left and right channel coefficients are equal

Default

EQM

(Equalizer

Mute)

When set to ±, this bit disables the equalizer function (allows all data pass-through). The reset default sets this bit to ±

disabling the equalizer function until the biquad coefficients can be properly set.

EQM

Function

0

EQ is enabled.

±

EQ is disabled. Data will pass-thru without change.

Default

x

Reserved.

Default: 0

Rev. 0 | Page 33 of 52

AD1986

Preliminary Technical Data

EQ DATA REGISTER (REGISTER 0x62)

This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from the

address pointed by the BCA bits in the EQ CNTRL register (0x60). Data will only be written to memory, if the EQM bit (Register 0x60

bit 15) is asserted.

Reg

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x62

EQ

Data

CFD±5

CFD±4

CFD±3

CFD±2

CFD±±

CFD±0

CFD9

CFD8

CFD7

CFD6

CFD5

CFD4

CFD3

CFD2

CFD±

CFD0

0xxxxx

Table 58.

Register

CFD [±5:0]

Function

The biquad coefficients are fixed point format values with ±6 bits of resolution. The CFD±5 bit is the MSB and the CFD0 bit is

(Coefficient the LSB.

Data)

MISC CONTROL BITS 2 (REGISTER 0x70)

Reg

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x70

Misc Control

Bits 2

x

MVREF

2

MVREF

±

MVREF

0

x

MMDIS

x

JSMAP

CVREF

2

CVREF

±

CVREF

0

x

0x0000

Table 59.

Register

Function

CVREF [2:0]

(C/LFE VREF_OUT

Control)

Sets the voltage/state of the C/LFE VREF_OUT signal. VREF_OUT is used to power microphone style devices

plugged into the connected jack circuitry. The VREF_OUT pin must be connected to both the left and right

channels through external resistors to function properly. Selections other than those defined are invalid and

should not be programmed.

C/LFE VREF_OUT Setting

CVREF [2:0]

000

5.0 AV_DD

Hi-Z

3.3 V AV_DD

Hi-Z

Default

00±

0±0

2.25 V

0V

2.25 V

0V

±00

3.70 V

2.25 V

JSMAP

(Jack Sense Mapping)

The AD±986 supports two different methods of mapping the JACK_SENSE_A/B resistor tree to bits JS [7:0]. Use

these bits to change from the default mapping to the alternate method.

JSMAP

Function

0

±

Default Jack Sense mapping

Alternate Jack Sense mapping

Default

MMDIS

(Mono Mute Disable)

Disables the automatic muting of the MONO_OUT pin by jack sense events (see advanced jack sense bits JS [3:0]

(0x76 D [05:04], 0x72 D [05:04]).

MMDIS

Function

0

±

Automute can occur

Automute disabled

Default

MVREF [2:0]

(MIC VREF_OUT)

Sets the voltage/state of the microphone VREF_OUT signal. VREF_OUT is used to power microphone style devices

plugged into the connected jack circuitry. The VREF_OUT pin must be connected to both the left and right

channels through external resistors to function properly. Selections other than those defined are invalid and

should not be programmed.

MIC_1/2 VREF_OUT Setting

MV_REF[2:0]

000

5.0 AV_DD

Hi-Z

3.3 V AV_DD

Hi-Z

Default

00±

0±0

2.25 V

0 V

2.25 V

0 V

±00

3.70 V

2.25 V

x

Reserved.

Default: 0

Rev. 0 | Page 34 of 52

Preliminary Technical Data

AD1986

JACK SENSE (REGISTER 0x72)

All register bits are read/write except for JS0ST and JS1ST, which are read only. Important: Please refer to Table 72 to understand how

JACK_SENSE_A and JACK_SENSE_B codec pins translate to JS1and JS0.

Reg Name D15

0x72 Jack

JS±

D14

D13

D12

D11

D10

D9

D8

D7 D6 D5

JS± JS0 JS± JS0 JS± JS0 0x0000

MD MD ST ST INT INT

D4

D3 D2 D1 D0 Default

JS±

JS0

JSMT JSMT JSMT JS±

2

JS0

x

Sense SPRD DMX DMX

±

0

EQB EQB

Table 60.

Register

Function

JS0INT

(JS0

Indicates JS0 has generated an interrupt. Remains set until the software services JS0 interrupt; i.e., JS0 ISR should clear this

bit by writing a 0 to it.

Interrupt

Status)

±. Interrupts are generated by valid state changes of JS pins.

2. Interrupt to the system is actually an OR combination of this bit and JS3 JS0 INT.

3. The interrupt implementation path is selected by the INTS bit (Register 0x74).

4. It is also possible to generate a software system interrupt by writing a ± to this bit.

JS0INT

Read

Write

0

±

JS0 did not generate interrupt

JS0 generated interrupt

No operation

Clears JS0INT bit

JS±INT

(JS±

Indicates JS± has generated an interrupt. Remains set until the software services JS± interrupt; i.e., JS± ISR should clear this

bit by writing a 0 to it. See JS0INT description above for additional details.

Interrupt

Status)

JS1INT

Read

Write

0

±

JS± did not generate interrupt

JS± generated interrupt

No operation

Clears JS±INT

JS0ST (RO)

(JS0 State

(RO))

This bit always reports the logic state of JS0.

On MIC jack sensing: depending on the applications circuit, the logic state for jack sense pins can be the opposite of that on

other jacks. Software needs to be aware of this is interpreting the JS event as a plug in our out event.

JS0ST

Function

Default

0

±

JS0 is low (0)

JS0 is high (±)

JS±ST (RO)

(JS± State

(read only))

This bit always reports the logic state of JS±. MIC jack sensing: depending on the applications circuit, the logic state for JS

pins can be the opposite to the other jacks.

JS1ST

Function

0

±

JS± is low (0)

JS is high (±)

JS0MD

This bit selects the operation mode for JS0.

(JS0 MODE)

JS0MD

Function

0

±

Jack sense mode—JS0INT must be polled by software

Interrupt mode—CODEC will generate an interrupt on JS0 event

Default

JS±MD

(JS± MODE)

This bit selects the operation mode for JS±.

JS1MD

Function

0

±

Jack sense mode—JS±INT must be polled by software

Interrupt mode—CODEC will generate an interrupt on JS± event

JS0EQB

(JS0 EQ

Bypass

Enable)

This bit enables JS0 to control the EQ bypass. When this bit is set to ±, JS0 = ± will cause the EQ to be bypassed.

JS0EQB

Function

0

±

JS0 does not affect EQ

JS0 = ± will cause the EQ to be bypassed

Default

JS±EQB

(JS± EQ

Bypass

Enable)

This bit enables JS± to control the EQ bypass. When this bit is set to ±, JS±=± will cause the EQ to be bypassed.

JS1EQB

Function

0

±

JS± does not affect EQ

JS± = ± will cause the EQ to be bypassed

Default

Rev. 0 | Page 35 of 52

AD1986

Preliminary Technical Data

Register

Function

JSMT [2,0]

(JS Mute

Enable

These 3 bits select and enable the jack sense muting action. See Table 6±.

selector)

JS0DMX

This bit enables JS0 to control the down-mix function. This function allows a digital mix of 6-channel audio into 2-channel

audio. The mix can then be routed to the stereo LINE_OUT or HP_OUT jacks. When this bit is set to ±, JS0 = ± will activate the

down-mix conversion. See DMIX description in Register 0x76. The DMIX bits select the down-mix implementation type and

can also force the function to be activated.

(JS0 Down-

Mix Control

Enable)

JS0DMX

Function

0

±

JS0 does not affect down mix

JS0 = ± activates the 6- to 2-channel down mix

Default

JS±DMX

This bit enables JS± to control the down-mix function (see the JS0DMx description above). When this bit is set to ±, JS± = ±

will activate the down-mix conversion.

(JS± Down-

Mix Control

Enable)

JS1DMX

Function

0

±

JS± does not affect down-mix

JS± = ± activates the 6- to 2-channel down-mix

Default

JSSPRD

(JS Spread

control

This bit enables the 2-channel to 6-channel audio spread function when JSs are active (Logic State ±). Note that the SPRD bit

can also force the Spread function without being gated by the jack senses. Please see this bit’s description in Register 0x76

for a better understanding of the Spread function.

enable)

JSSPRD

Function

0

±

JS± does not affect spread

J±0 = ± activates spread

Default

x

Reserved.

Default: 0

Table 61. Jack Sense Mute Selections (JSMT)

HP

OUT

LINE

OUT

C/LFE

OUT

SURR

OUT

MONO

OUT

REF JS1

JS0

JSMT2

JSMT1

JSMT0

NOTES

0

±

2

3

4

5

OUT (0)

IN (±)

0

±

ACTIVE

FMUTE

ACTIVE

FMUTE

ACTIVE

FMUTE

ACTIVE

JS0 and JS± ignored

OUT (0)

IN (±)

OUT (0)

IN (±)

OUT (0)

IN (±)

JS0 no mute action

JS± mutes mono and enables

LINE_OUT + SURR_OUT +

C/LFE

6

7

8

IN (±)

OUT (0)

IN (±)

0

±

0

ACTIVE

FMUTE

ACTIVE

FMUTE

ACTIVE

FMUTE

ACTIVE

IN (±)

STANDARD 6 CHAN CONFIG

OUT (0)

JS0 no mute action, SWAPPED

HP_OUT and LINE_OUT

9

OUT (0)

IN (±)

0

±

0

FMUTE

ACTIVE

FMUTE

ACTIVE

JS± mutes mono and enables

HP_OUT + SURR_OUT + C/LFE

±0

±±

IN (±)

OUT (0)

IN (±)

0

±

0

ACTIVE

FMUTE

STANDARD 6 CHAN CONFIG

no swap

±2

±3

±4

±5

±6

OUT (0)

IN (±)

OUT (0)

IN (±)

0

±

0

±

0

**

**RESERVED

**

OUT (0)

IN (±)

**

IN (±)

**

OUT (0)

ACTIVE

FMUTE

ACTIVE

JS0 = 0 and JS± = 0

enables MONO

±7

±8

±9

OUT (0)

IN (±)

±

0

ACTIVE

FMUTE

ACTIVE

FMUTE

ACTIVE

FMUTE

JS± = ± enabled

FRONT only

OUT (0)

IN (±)

JS0 = ± and JS± = 0

enables all rear

IN (±)

6 CHAN CONFIG with front

jack wrap back

Rev. 0 | Page 36 of 52

Preliminary Technical Data

AD1986

HP

OUT

LINE

OUT

C/LFE

OUT

SURR

OUT

MONO

OUT

REF JS1

JS0

JSMT2

JSMT1

JSMT0

NOTES

20

2±

OUT (0)

IN (±)

±

0

±

FMUTE

ACTIVE

JS0 no mute action

OUT (0)

JS± mutes mono and enables

all rear.

22

23

IN (±)

OUT (0)

IN (±)

±

0

±

ACTIVE

FMUTE

STANDARD 6 CHAN CONFIG

swapped HP_OUT and

LINE_OUT

24

25

26

27

28

29

30

3±

OUT (0)

IN (±)

OUT (0)

IN (±)

±

0

±

**

**RESERVED

OUT (0)

IN (±)

OUT (0)

IN (±)

OUT (0)

IN (±)

**RESERVED

OUT (0)

IN (±)

FMUTE = Output is forced to mute independent of the respective volume register setting.

ACTIVE = Output is not muted and its status is dependent on the respective volume register setting.

OUT = Nothing is plugged into the jack and therefore the JS status is 0 (via the load resistor pull-down action).

IN = Jack has plug inserted and therefore the JS status is 1 (via the CODEC JS pin internal pull-up).

SERIAL CONFIGURATION (REGISTER 0x74)

When Register 0x00 is written (soft reset) the SLOT 16, REGM [2:0], SPOVR, SPAL, SPDZ, and SPLNK bits do not reset. All bits are reset

on a hardware reset or power-on reset.

Reg

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x74

Serial

Configuration

SLOT

±6

REGM2

REGM±

REGM0

REGM3

OMS2

OMS±

OM0

SPOVR

LBKS±

LBKS0

INTS

CSWP

SPAL

SPDZ

SP

LNK

0x±00±

Table 62.

Register

Function

Default

SPLNK

(S/PDIF

LINK)

This bit enables the S/PDIF to link with the front DACs for data requesting. When linked the S/PDIF and front DACs should be

set to the same data rate as they both generate data requests at the front DAC’s request rate.

SPLNK

Function

0

±

S/PDIF and front DACs are not linked

S/PDIF and front DACs are linked

Default

SPDZ

(S/PDIF

DACZ)

Sets data fill mode for S/PDIF transmitter FIFO under-runs. When this bit is set to ON (±) the S/PDIF and ADC rates should be

set to the same rate.

SPDZ

On Under-Runs

0

±

Repeat last sample out the S/PDIF stream

Forces midscale sample out the S/PDIF stream

S/PDIF Transmitter Source

Default

SPAL

(S/PDIF

ADC Loop

Around)

0

±

Connected to the AC-LINK stream

Connected to the digital ADC stream

(CSWP

Swaps the CENTER/LFE channels. Some systems have a swapped external connection for the CENTER and LFE channels.

CENTER/LFE Setting this bit will swap these channels internal to the CODEC. Note that the CENTER and LFE controls do not change and

Swap)

remain at the same addresses and bit assignments.

CSWP

CENTER Pin

CENTER channel

LFE channel

LFE Pin

0

±

LFE channel

CENTER channel

Default

INTS

(Interrupt

Mode

This bit selects the audio interrupt implementation path. Note that this bit does not generate an interrupt, rather it steers the

path of the generated interrupt.

INTS

Interrupt Mode

Select)

0

Bit 0 SLOT ±2 (modem interrupt)

Default

Rev. 0 | Page 37 of 52

AD1986

Preliminary Technical Data

Register

Function

Default

±

Slot 6 valid bit (MIC ADC interrupt)

LBKS [±:0]

Loop-Back

Selection

These bits select the internal digital loop-back path when LPBK bit is active (see Register 0x20).

LBKS [1:0]

Interrupt Mode

00

0±

±0

Loop back through the front DACs

Loop back through the SURROUND DACs

Loop back through the center and LFE DACs (center

DAC loops back from the ADC left channel, the LFE

DAC from the ADC right channel)

Default

±±

Reserved

SPOVR

Use this bit to enable S/PDIF operation even if the external S/PDIF detection resistor is not installed.

(S/PDIF

Enable

Override)

SPOVR

S/PDIF Detection

0

External resistor determines the presence of

S/PDIF

Default

±

Enable S/PDIF operation

OMS [2:0]

Optional

Selects the source of the microphone gain noost amplifiers. These bits work in conjuction with the 2CMIC (0x76 D06),

MS (0x20 D08), and MMIX (0x7A D08) bits.

Microphone

Selector

OMS [2:0]

000

Left Channel

MIC pins

Default

00±

LINE_IN pins

0±x

C/LFE pins

±00

±0±

±±0

±±±

Mix of MIC and C/LFE pins

Mix of MIC and LINE_IN pins

Mix of LINE_IN and C/LFE pins

Mix of MIC, LINE_IN and C/LFE pins

REGM [3:0]

Bit mask indicating which CODEC is being accessed in a chained CODEC configuration.

REGM0—Master CODEC register mask

Default

REGM±—Slave ± CODEC register mask

REGM2—Slave 2 CODEC register mask

REGM3—Slave 3 CODEC register mask

SLOT ±6

Enable ±6-bit slot mode: SLOT±6 makes all AC link slots ±6 bits in length, formatted into ±6 slots. This is a preferred mode for

DSP serial port interfacing.

SLOT 16

Function

0

±

Standard AC ’97 operation

All ac link S slots are ±6 bits

Default

x

Reserved

Default: 0

Rev. 0 | Page 38 of 52

Preliminary Technical Data

AD1986

MISC CONTROL BITS 1 (REGISTER 0x76)

Reg

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

MBG0

Default

76h

Misc Control Bits ±

DACZ

AC97NC

MSPLT

SODIS

CLDIS

x

DMIX±

DMIX0

SPRD

2CMIC

SOSEL

SRU

LISEL±

LISEL0

MBG±

60±0

Table 63.

Register

MBG [±:0]

(MIC Boost Gain Select

Register)

Function

These two bits allow changing both MIC preamp gain blocks from the nominal 20 dB gain boost. Both MIC_±/2

and MIC_2 preamps will be set to the same selected gain. This gain setting only takes affect while bit D6 (M20)

on the MIC volume register (0x0E) is set to ±, otherwise the MIC boost blocks have a gain of 0 dB.

MGB [1:0]

Microphone Boost Gain

Default

00

0±

±0

±±

20 dB

±0 dB

30 dB

Reserved

Default

LISEL [±:0]

Selects the source of the internal LINE_IN signals.

(LINE_IN Selector)

LISEL [1:0]

LINE_IN Selection

00

0±

±x

LINE_IN pins

Default

SURROUND pins—Places SURROUND outputs in Hi-Z state

MIC_±/2 pins

SRU

Controls all DAC sample rate locking.

(Sample Rate Unlock)

SRU

0

±

Surround State

All DAC sample rates are locked to the front sample rate

Front, surround and LFE sample rates can be set independently

SOSEL

Selects either the surround DAC or analog mixer as the source driving the SURROUND output pin amplifier.

(Surround Amplifier

Input Selection)

SOSEL

Surround Source

Surround DACs

Analog Mixer

0

±

Default

2CMIC

(2-Channel MIC Select)

Used in conjunction with the OMS [2:0] (0x74 D±0:08]), MS (0x20 D08), and MMIX (0x7A D02) bits to set the

microphone selection. This bit enables simultaneous recording from MIC_± and MIC_2 inputs, using a stereo

microphone array. If the MMIX (0x7A D02) bit is set this bit is ignored.

2CMIC

2 Channel MIC State

0

±

Both outputs are driven by the left channel of the selector

Stereo operation, the left and right channels are driven

separately

Default

SPRD

(Spread Enable)

This bit enables spreading of 2-channel media to all 6-output channels. This function is implemented in the

analog section by using the output selector controls lines for the center/LFE, surround and LINE_OUT output

channels. The jack sense pins can also be setup to control (gate) this function depending on the JSSPRD bit (see

Register 0x72). The SPRD bit operates independently and does not affect the LOSEL and HPSEL operation.

SPRD

Spread State

0

±

No spreading occurs unless activated by jack sense

The SPDR selector drives the center and LFE outputs from the

MONO_OUT

Default

CLDIS

(C/LFE Output Enable)

Controls the Hi-Z state of the SURROUND_L/R output pins. Pins are placed into a Hi-Z mode by software control

or when they are selected as inputs to the MIC_±/2 selector (see the OMS [2:0] bits 740x D [±0:08]).

CLDIS

C/LFE Output State

Outputs enabled

Outputs tristated

0

±

Default

Rev. 0 | Page 39 of 52

AD1986

Preliminary Technical Data

Register

Function

DMIX [±:0]

(DOWN MIX Mode

Select)

Provides analog down-mixing of the center, LFE and/or surround channels into the mixer channels. This allows

the full content of 5.± or quad media to be played through stereo headphones or speakers. The jack sense pins

can also be setup to control (gate) this function depending on the JS0DMx and JS±DMx bits (0x72 D [±4:±3]).

DMIX [1:0]

Down-Mix State

0x

±0

No down-mix unless activated by jack sense

Selects 6-to-4 down-mix. The center and LFE channels are

summed equally into the Mixer L/R channels

Default

±±

Selects 6-to-2 down-mix. In addition to the center and LFE

channels, the SURROUND channels are summed into the

mixer L/R channels

SODIS

(Surround Output

Enable)

Controls the Hi-Z state of the SURROUND output pins. Pins are placed into a Hi-Z mode by software control or

when they are selected as inputs to the LINE_IN selector (see the LISEL [±:0] bits 0x76 D [03:02]).

CLDIS

SURROUND_OUT State

Outputs enabled

Outputs tri-stated (Hi-Z)

0

±

Default

MSPLT (RO)

(Mute Split)

Separates the left and right mutes on all volume registers. This bit is read-only ± (one) on the AD±986 indicating

that mute split is always enabled.

AC ‘97NC (RO)

Changes addressing to ADI model (vs. true AC ’97 definition). This bit is read-only ± (one) on the AD±986

(AC ‘97 No Compatibility indicating that ADI addressing is always enabled.

Mode)

DACZ

Determines DAC data fill under starved condition.

(DAC Zero-Fill)

DACZ

DAC Fill State

0

±

DAC data is repeated when DACs are starved for data

DAC data is zero-filled when DACs are starved for data

Default

x

Reserved.

Default: 0

ADVANCED JACK SENSE (REGISTER 0x78)

All register bits are read/write except for JSxST bits, which are read-only. Important: Please refer to Table 72 to understand how

JACK_SENSE_A and JACK_SENSE_B codec pins translate to JS7…JS2.

Reg Name

D15 D14 D13 D12 D11 D10 D9 D8 D7

D6 D5

JS3 JS2 JS3 JS2 JS3 JS2 0xxxxx

MD MD ST ST INT INT

D4

D3 D2 D1

D0

Default

0x78 Advanced

Jack Sense

JS7

ST

JS7

INT

JS6

ST

JS6

INT

JS5

ST

JS5

INT

JS4 JS4 JS4-

ST INT 7H

x

Table 64.

Register

Function

JS [7:2] INT

Indicates JSx has generated an interrupt. Remains set until the software services JSx interrupt; i.e., JSx ISR should clear

this bit by writing a 0 to it.

±. Interrupts are generated by valid state changes of JSx.

2. Interrupt to the system is actually an OR combination of this bit and JS7 JS0 INT.

3. Interrupt implementation path is selected by the INTS bit (Register 0x74).

4. It is also possible to generate a software system interrupt by writing a ± to this bit.

JS [7:4] INT

Read

Write

Default

0

±

JSx logic is not interrupting

Sx logic interrupted

Clears JSx interrupt

Generates a software interrupt

Default

JS [7:4] ST (RO) This bit always reports the logic state of JS7 thru 4 detection logic.

JS [7:4] ST

Jack State

0

±

No jack present

Jack detected

JS [3:2] MD

This bit selects the operation mode for JS2 and JS3.

JS [3:2] MD

Interrupt Mode

0

±

Jack Sense Mode—jack sense state requires software polling

Interrupt Mode—jack sense evetns will generate interrupts

Default

Rev. 0 | Page 40 of 52

Preliminary Technical Data

AD1986

Register

Function

JS4–7H

Interrupt

Mode Select

This bit selects the audio interrupt implementation path (for JS4 to 7). This bit does not generate an interrupt, rather it

steers the path of the generated interrupt.

JS4 to 7H

Interrupt Mode—JS4 to 7

0

±

Bit 0 SLOT ±2 (modem interrupt)

Slot 6 valid bit (MIC ADC interrupt)

Default

x

Reserved

Default: 0

MISC CONTROL BITS 3 (REGISTER 0x7A)

Reg

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x7A

Misc Control Bits 3 JSINVB

HPSEL±

HPSEL0

LOSEL

JSINVA

LVREF 2

LVREF±

LVREF 0

x

LOHPEN

GPO

MMIX

x

0x0000

Table 65.

Register

MMIX

Function

Used in conjunction with the OMS [2:0] (0x74 D±0:08), MS (0x20 D08), and 2CMIC (0x76 D06) bits to mix the microphone

selector left/right channels. If the MMIX bit is set, the 2CMIC and MS bits are ignored.

MMIX

Function

Default

0

±

Microphone channels are not mixed

The left/right channels from the microphone selector are mixed

Default

Sets the state of the GPO pin

GPO

Function

0

±

GPO pin is at logic low (DV_SS)

GPO pin is at logic high (DV_DD)

Default

LOHPEN

Enables the headphone drive on the LINE_OUT pins. Disabling the headphone drive is the same as powering it down (see

the PR6 bit (0x26 D±4)).

LOHPEN

Function

0

±

LINE_OUT headphone drive is disabled

LINE_OUT headphone drive is enabled

Default

LVREF [2:0]

(Line In

VREF_OUT)

Sets the voltage/state of the LINE_IN VREF_OUT signal. VREF_OUT is used to power microphone style devices plugged into

the connected jack circuitry. The VREF_OUT pin must be connected to both the left and right channels through external

resistors to function properly. Selections other than those defined are invalid and should not be programmed.

LINE_IN VREF_OUT Setting

LVREF [2:0]

000

5.0 AV_DD

Hi-Z

3.3 V AV_DD

Hi-Z

Default

00±

0±0

2.25 V

0V

2.25 V

0 V

±00

3.70 V

2.25 V

LOSEL

This bit allows the LINE_OUT output amplifiers to be driven by the mixer or the surround DACs. The main purpose for this is

to allow swapping of the frontand surround channels to make better use of the SURR/HP_OUT output amplifiers. This bit

should normally be used in tandem with the HPSEL bit (see below).

(LINE_OUT

Amplifiers

Input Select)

LOSEL

LINE_OUT Select

0

LINE_OUT amplifiers are driven by the

analog mixer outputs

Default

±

LINE_OUT amplifiers are driven by the

surround DAC

JSINVA

SENSE_A: Select the style of switches used on the audio jacks connected to Sense A.

Jack Sense

Invert

JSINVA

Jack Sense Invert—SENSE_A

0

SENSE_A configured for normally-

open (NO) switches

Default

±

SENSE_A configured for normally-closed

(NC) switches

Rev. 0 | Page 4± of 52

AD1986

Preliminary Technical Data

Register

Function

This bit allows the headphone power amps to be driven from the surround DACs, C/LFE DACs, or from the mixer outputs.

HPSEL [±:0]

(Headphone

Amplifier

HPSEL [1:0]

HP_OUT Selection

00

Outputs are driven by the mixer

outputs

Default

Input Select)

0±

±x

Outputs are driven by the surround

DACs

Outputs are driven by the C/LFE DACs

JSINVB

SENSE_B: Select the style of switches used on the audio jacks connected to Sense B.

(Jack Sense

Invert)

JSINVB

0

Jack Sense Invert—SENSE_B

JACK_SENSE_B configured for normally-

open (NO) switches

Default

±

JACK_SENSE_B configured for normally-

closed (NC) switches

x

Reserved.

Default: 0

VENDOR ID REGISTERS (REGISTER 0x7C to 0x7E)

Reg

Name

D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5

D4

D3

D2

D1

D0

Default

0x7C Vendor

ID ±

F7

F6

F5

F4

F3

F2

F±

F0

S7

S6

S5

S4

S3

S2

S±

S0

0x4±44

0x7E Vendor

ID 2

T7

T6

T5

T4

T3

T2

T±

T0

REV7

REV6

REV5

REV4

REV3

REV2

REV±

REV0

0x5378

Table 66.

Register

S [7:0]

F [7:0]

T [7:0]

Function

This register is ASCII encoded to A.

This register is ASCII encoded to D.

This register is ASCII encoded to S.

REV [7:0]

This register is set to 0x78, identifying the AD±986.

CODEC CLASS/REVISION REGISTER (REGISTER 0x60)

Reg

Name

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x60± CODEC

Class/Rev

x

CL4 CL3 CL2 CL± CL0 RV7 RV6 RV5 RV4 RV3 RV2 RV± RV0 0x0002

Table 67.

Register

Function

Default

RV [7:0]

(Revision ID:

(RO))

These bits specify a device specific revision identifier. The vendor chooses this value. Zero is an acceptable

value. This field should be viewed as a vendor defined extension to the CODEC ID. This number changes

with new CODEC stepping of the same CODEC ID. This number will increment with each stepping/rev. of

the CODEC chip.

CL [4:0]

(CODEC

The AD±986 will return 0x00 from this register. This is a CODEC vendor specific field to define software

compatibility for the CODEC. Software reads this field together with CODEC vendor ID (Register 7C–0x7E)

Compatibility to determine vendor specific programming interface compatibility. Software can rely on vendor specific

Class (RO))

register behavior to be compatible among vendor CODECs of the same class.

0x00

Field not implemented

0x0±-0x±F

Reserved.

Vendor specific compatibility class code

x

Default: 0

Rev. 0 | Page 42 of 52

Preliminary Technical Data

AD1986

PCI SUBSYSTEM VENDOR ID REGISTER (REGISTER 0x62, PAGE 01)

This register is only reset by power-on. It is used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specification)

and must not be reset by soft or hardware resets.

Reg

0x62± PCI

SVID

Name D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

PVI±5 PVI±4 PVI±3 PVI±2 PVI±± PVI±0 PVI9 PVI8 PVI7 PVI6 PVI5 PVI4 PVI3 PVI2 PVI± PVI0 0xFFFF

Table 68.

Register

Function

PVI [±5:0]

PCI Sub

System

Optional per AC ‘97 specifications, should be implemented as read/write on AD±986.

This field provides the PCI subsystem vendor ID of the audio or modem subassembly vendor (i.e., CNR manufacturer,

motherboard vendor). This is NOT the CODEC vendor PCI vendor ID or the AC ’97 controller PCI vendor ID. If data is not

available it should return 0xFFFF.

Vendor ID

PCI SUBSYSTEM DEVICE ID REGISTER (REGISTER 0x64, PAGE 01)

This register is only reset by power-on. It is used by the BIOS to store configuration information (per AC’97 v2.3 specification) and must

not be reset by soft or hardware resets.

Reg

Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

0x64± PCI SID

PI±5 PI±4 PI±3 PI±2 PI±± PI±0 PI9 PI8 PI7 PI6 PI5 PI4 PI3 PI2 PI± PI0 0xFFFF

Table 69.

Register

Function

PI [±5:0]

(PCI Vendor

ID)

Optional per AC ‘97 specifications, should be implemented as read/write on the AD±986. This field provides the PCI

subsystem ID of the audio or modem subassembly (i.e., CNR model, motherboard SKU). This is NOT the CODEC vendor PCI

ID or the AC ’97 controller PCI ID. Information in this field must be available, because the AC ’97 controller reads when the

CODEC ready is asserted in the AC link. If data is not available it should return FFFFh.

FUNCTION SELECT REGISTER (REGISTER 0x66, PAGE 01)

This register is used to select which function (analog I/O pins), information and I/O (0x6801), and sense (0x6A01) registers apply to it.

The AD1986 associates FC = 0x0 with surround functions and FC = 0x01 with front functions. These are changed in the AD1986 to align

with the new device pin-out and to separate LINE_OUT functions.

Reg

Name

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

D3

D2

D1

D0 Default

0x66± Function

Select

x

FC3 FC2 FC± FC0 T/R 0x0000

Rev. 0 | Page 43 of 52

AD1986

Preliminary Technical Data

Table 70.

Register

Function

T/R

(FIP or Ring

Selection Bit)

This bit sets which jack conductor the sense value is measured from. Software will program the corresponding rng/tp

selector bit together with the I/O number in bits FC [3:0]. Once software programs the value and properly reads it back to

confirm selection and implementation, it will access the rest of the bits fields in the descriptor. Mono inputs and outputs

should report the relevant function and sense information when T/R is set to 0 (tip). The FIP bit should report 0 (Page

0x0±, Register 0x68, Bit 0 reports no function information present) when T/R is set to a ± on a mono input or output.

T/R

0

±

Function

Tip (left channel)

Ring (right channel)

Default

FC [3:0]

Function Code

Bits

These bits specify the type of audio function described by this page. These bits are read/write and represent current

AC ’97 Revision 2.2 defined I/O capabilities. Software will program the corresponding I/O number in this field together

with the tip/ring selector bit T/R. Once software programs the value and properly reads it back to confirm selection and

implementation, it will access the rest of the bits fields in the descriptor.

FC [3:0]

0x0

Function

DAC ± (master out). maps to front DACs (L/R)

Default

0x±

DAC 2 (AUX out). maps to surround DACs (L/R)

0x2

0x3

DAC 3 (C/LFE). maps to C/LFE DACs

S/P-DIF out

0x4

Phone in

0x5

0x6

0x7

MIC_± (Mic select = 0)

MIC_2 (Mic select = ±)

Line in

0x8

CD in

0x9

Video in

Not supported on the AD±986

0xA

Aux in

0xB

Mono out

0xC

0xD–0xF

Reserved.

Headphone ut

Reserved

x

Default: 0

INFORMATION AND I/O REGISTER (REGISTER 0x68, PAGE 01)

This address represents multiple registers (one for each supported function code (FC [3:0] bits (0x66 D [04:01])). These values are only

reset by power-on. It is used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specifications) and must not be reset

by soft or hardware resets.

Reg

Name

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4 D3 D2 D1 D0 Default

FIP 0xxxxx

0x68± Information G4

and I/O

G3

G2

G±

G0

INV

DL4 DL3 DL2 DL± DL0 IV

x

Table 71.

Register

Function

FIP (RO)

CODEC default. When set to a ±, this bit indicates that the G [4:0], INV, DL [4:0] (in Register 0x68±), and ST [2:0] (in

Register 0x6A±) bits are supported and are read/write capable. This bit set to a 0 indicates that the G [4:0], INV, DL [4:0], and

ST [2:0] bits are not supported, and are read-only with a value of 0. Mono inputs and outputs should report the relevant

function and sense information when T/R is set to 0 (tip). The FIP bit should report 0 (Page 0x0±, Register 0x68, Bit 0 reports

no function information present) when T/R is set to a ± on a mono input or output.

(Function

Information

Present)

FIP

0

±

Function

Function information not supported

Function information supported

Power-on default

Rev. 0 | Page 44 of 52

Preliminary Technical Data

AD1986

Register

Function

Indicates whether a sensing method is provided by the CODEC and if information field is valid. This field is updated by the

IV

(Information CODEC.

Valid Bit)

IV

Function

0

After CODEC reset de-assertion, it indicates the CODEC does NOT provide sensing logic and this bit will be

Read-Only. After a sense cycle is completed indicates that no information is provided on the sensing method.

±

After CODEC reset de-assertion, it indicates the CODEC provides sensing logic for this I/O and this bit is

Read/Write. After clearing this bit by writing ±, when a sense cycle is completed indicates that there is valid

information in the remaining descriptor bits. Writing 0 to this bit has no effect.

DL [4:0]

(Buffer

Delays,

A number representing a delay measurement for the input and output channels. The default value is the delay internal to

the CODEC. The BIOS may add to this value the known delays external to the CODEC, such as for an external amplifier, logic,

etc. Software will use this value to accurately calculate audio stream position with respect to what is been reproduced or

recorded. These values are in 20.83 microsecond (±/48000 second) units. For output channels, this timing is from the end of

AC link frame in which the sample is provided, until the time the analog signal appears at the output pin. For input streams,

this is from when the analog signal is presented at the pin until the representative sample is provided on the AC link. Analog

to analog paths are not considered in this measurement. The measurement is a typical measurement, at a 48 KHz sample

rate, with minimal in-CODEC processing (i.e., 3D effects are turned off.) An example of an audio output delay is filter group

delay and FIFO or other sample buffers in the path. So when an audio PCM sample is written to the CODEC in an AC ’97

frame it will be delayed before the output pin is updated to that value.

Read/Write)

DL [4:0]

0x00

0x0±-0x±E

0x±F

Function

Information not provided

Buffer delay: 20.83 µs per unit

Reserved

INV

(Inversion

Bit,

Indicates that the CODEC presents a ±80 degree phase shift to the signal. This bit is only reset by a power-on reset, since it is

typically written by the system BIOS and is not reset by CODEC hard or soft resets as long as power remains applied to the

CODEC.

Read/Write,

CODEC

Default)

INV

0

±

Function

No phase shift

Signal is shifted by ±80° from the source signal

G [4:0]

(Gain Bits

The CODEC updates these bits with the gain value (dB relative to level-out) in ±.5 dBV increments, not including the volume

control gains. For example, if the volume gain is to 0 dB, then the output pin should be at the 0 dB level. Any difference in

(Read/Write)) the gain is reflected here. When relevant, the BIOS updates this bit to take into consideration external amplifiers or other

external logic that it knows about. G [3:0] indicates the magnitude of the gain. G [4] indicates whether the value is a gain or

attenuation—essentially it is a sign bit. These bits are only reset by a power-on reset as they are typically written by the

system BIOS and are not reset by CODEC hard or soft resets as long as power remains applied to the CODEC.

G4

G [3:0]

0000

000±

...

±±±±

000±

...

Gain/Attenuation (dB Relative to Level-Out)

0

0 dB

+±.5 dB

+±.5 dB × G [3:0]

+24.0 dB

0

−±.5 dB

−±.5 dB × G [3:0]

−24.0 dB

±

x

±±±±

Reserved

Default: 0

Rev. 0 | Page 45 of 52

AD1986

Preliminary Technical Data

SENSE REGISTER (REGISTER 0x6A, PAGE 01)

This address represents multiple registers (one for each supported function code (FC [3:0] bits (0x66 D [04:01])). The ST [2:0] bits are

only reset by power-on. They are used by the BIOS to store configuration information (per AC ’97 Revision 2.3 specifications) and must

not be reset by soft, hard or hardware resets. The remaining bits are the result of the last sense operation performed by the impedance

sensing circuitry.

Reg

0x6A± Sense

Register

Name

D15 D14 D13 D12 D11 D10 D9 D8 D7

D6

D5 D4 D3 D2 D1 D0 Default

ST2

ST±

ST0

S4

S3

S2

S± S0 OR± OR0 SR5 SR4 SR3 SR2 SR± SR0 0xxxxx

Table 72.

Register

Function

Default

SR [5:0] (RO)

(Sense Result

Bits, RO)

These bits are used to report a vendor specific fingerprint or value. (resistance, impedance, reactance,

etc. Used with the OR bits which are the multiplying factor.

Default: 0

OR [±:0] (RO)

(Order Bits)

These bits indicate the order the sense result bits SR [5:0] are using. For example, if measuring resistance SR = ±/OR =

±±: the result is ± KΩ.

OR [1:0]

Order Value

00

0±

±0

±±

±0⁰—SR bits indicate the actual impedance in ohms

±0^±—SSR bits indicate the impedance in ohms × ±0

±0²—SR bits indicate the impedance in ohms × ±00

±0³—SSR bits indicate the impedance in ohms × ±,000

Default

S [4:0] (RO)

Sensed bits meaning relates to the I/O being sensed as input or output. Read only. Sensed bits (when output sense

cycle initiated). This field allows for the reporting of the type of output peripheral/device plugged in the jack. Values

specified below should be interrogated with the SR [5:0] and OR [±:0] for accurate reporting.

S [4:0]

0x00

0x0±

0x02

Sense Value

Data not valid. Indicates that the reported value(s) is invalid

No connection. Indicates that there are no connected devices

Indicates a specific fingerprint value for devices that are not specified or are

unknown

Default

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Speakers (8 Ω)

Speakers (4 Ω)

Powered speakers

Stereo headphone

SPDIF out (electrical)

SPDIF out (TOS)

Mono headset (mono speaker left channel and mic. Read Functions 5 and 6 for

matching microphone)

0x0A

Allows a vendor to report sensing other type of devices/peripherals. SR [5:0]

together with OR [±:0] provide information regarding the type of device sensed

0x0B–0x0E

0x0F

0x±0–0x±F

Reserved

Unknown (use fingerprint)

Reserved

S [4:0] (RO)

Sensed bits (when input sense cycle initiated). This field allows for the reporting of the type of input peripheral/device

plugged in the jack. Values specified below should be interrogated with the SR [5:0] and OR [±:0] bits for accurate

reporting.

ST [2:0]

0x±0

0x±±

Sense Value

Data not valid. Indicates that the reported value(s) is invalid

No connection. Indicates that there are no connected devices

Default

0x±2

Indicates a specific fingerprint value for devices that are not specified or are

unknown

0x±3

Microphone (mono)

Rev. 0 | Page 46 of 52

Preliminary Technical Data

AD1986

Register

Function

0x±4

Default

Microphone (stereo)

0x±5

0x±6

0x±7

Stereo line in (CE device attached)

Mono line in (CE device attached)

SPDIF In (electrical)

0x±8

SPDIF In (TOS)

0x±9

Headset (mono speaker left channel and mic.) Read Functions 0 to 3 for matching

DAC out

0x±A

Allows a vendor to report sensing other types of devices/peripherals. SR [5:0]

together with OR [±:0] provide information regarding the type of device sensed

0x±B–0x±E

0x±F

Reserved

Unknown (use fingerprint)

ST [2:0]

This field describes the location of the jack in the system. This field is updated by the BIOS. This bits is only reset by a

power-on reset as it is typically written by the system BIOS and is not reset by CODEC hard or soft resets as long as

power remains applied to the CODEC.

(Connector/Jack

location Bits,

Read/Write)

ST [2:0]

Jack Location

0x0

Rear I/O panel

Power-on

default

0x±

Front panel

0x2

Motherboard

0x3

0x4–0x6

0x7

Dock/external

Reserved

No connection/unused I/O

Rev. 0 | Page 47 of 52

AD1986

Preliminary Technical Data

JACK PRESENCE DETECTION

sense style for SENSE_B is controlled by the JSINVB bit

(Register 0x7A D15). Writing a 1 to these bits will configure the

corresponding sense circuit for normally closed instead of

normally open switch types.

The AD1986 uses two jack sense lines for presence detection on

up to eight external jacks. These lines, combined with the

device detection circuitry, enable software to determine

whether there is a device plugged into the circuit and what type

of device it is. With this feature, software can reconfigure jacks

and amplifiers as necessary to insure proper audio operation.

Wrap-back jacks cannot be used in microphone-capable cir-

cuits. For this reason isolated switches are recommended. The

codec defaults to sensing NO style switches and this method is

preferred.

Jack presence is detected using a resistor tree arrangement. Up

to four jacks can be sensed on a single sense line by using a

different value resistance for each jack between the sense line

and ground (AV_SS). Each sense line must have a single 2.49k 1%

resistor connected between the sense line and AV_DD. The

specific resistor values for each jack are shown in Table 73. One

percent tolerance resistors should be used for all jack presence

circuitry to insure accurate detection.

Normally-Open Switches

If a connection is not present, do not install the sense resistor

pertaining to that connection.

If a connection is present, but there is no related switch (such

as an internal connection), install the sense resistor pertaining

to that connection.

AUDIO JACK STYLES (NC/NO)

Normally Closed Switches

The jack sense lines on the AD1986 can be programmed for use

with normally-open (NO) or normally closed (NC) switch

types. Current standard stereo audio jacks have wrap-back pins

that are normally closed. New audio jacks use isolated, normally

open switches, which are required for resistive ladder jack

presence detection. Each sense group (A or B) must have the

same style of jack for presence detection to function correctly.

However, the group (A or B) sense type can be programmed

separately to accommodate systems with different styles of jacks

on the front versus rear panel.

Connections capable of MIC bias require isolated switches to

function correctly. When using normally closed, wrap-back

switches, the jack resistor must be split into two values. One

value connects the sense line to the jack switch and the other

connects the related audio connection to AV_SS. The total

resistance (sense line to AV_SS) must equal the value specified in

Table 73.

If a connection is not present, install the sense resistors

pertaining to that connection.

The AD1986 defaults to the isolated, normally open switch

types on power up. The jack sense style for SENSE_A is

controlled by the JSINVA bit (Register. 0x7A D11). The jack

If a connection is present, but there is no related switch (such

as an internal connection), do not install the sense resistors

pertaining to that connection.

Table 73. Jack Sense Mapping

JACK_SENSE_A

JACK_SENSE_B

Resister (1% tolerance)

Mnemonic

Jack

D

C

B

A

JS

Mnemonic

LINE OUT

C/LFE

SURROUND

AUX IN

Jack

JS

4.99k

±0.0k

20.0k

40.2k

JS7

JS4

JS5

JS±

H

G

F

JS0

JS3

JS2

JS6

LINE IN

MIC_±/2

HP_OUT

E

Rev. 0 | Page 48 of 52

Preliminary Technical Data

AD1986

MICROPHONE SELECTION/MIXING

MIC 1

CENTER

LINE IN L

NID: 0x0F

MIC Select: OMS[2:0]

0x74 D10-D08

DEF=000 (MIC 1/2)

G

MIC LEFT

000-MIC 1/2

001-Line In

01x-C/LFE

100-MIC+C/LFE

101-MIC+Line In

110-C/LFE+Line In

111-MIC+C/LFE+Line

NID: 0x11

MIC Boost: AC97

M20 0x0E D6 DEF=0

MGB[1:0] 0x76 D[1:0] DEF=00

MIC Swap: AC97

MS 0x20 D08 DEF=0

2CMIC 0x76 D06 DEF=0

MMIX 0x7A D02 DEF=0

MGB

M20

0

[1:0]

xx

Gain

0dB

1

00

01

10

11

+20dB

+10dB

+30dB

reserved

Azalia

MSWP[2:0] 0x7A D02:00

MMIX 2CMIC MS

MSWP2 MSWP1 MSWP0 Right

NID: 0x2B

Azalia

MGBL[1:0] 0x70 D[1:0]

MGBR[1:0} 0x70 D[14:13]

MIC 2

LFE

Left

MIC

0

1

0

1

x

0

1

0

1

x

MIC

1

2

1

2

1

2

MGBL/R

[1:0]

00

Gain

0dB

MIC 1+2 MIC 1+2

LINE IN R

01

10

11

+10dB

+20dB

+30dB

MIC RIGHT

NID: 0x27

G

NID: 0x28

NID: 0x29

NID: 0x2A

Figure 10. Microphone Selection/Mixing Block Diagram

Rev. 0 | Page 49 of 52

AD1986

Preliminary Technical Data

OUTLINE DIMENSIONS

0.75

0.60

0.45

9.00 BSC

SQ

1.60

MAX

37

36

48

1

PIN 1

SEATING

PLANE

10°

6°

2°

7.00

BSC SQ

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

VIEW A

7°

3.5

0°

25

24

12

°

13

0.15

0.05

SEATING

PLANE

0.27

0.22

0.17

0.08 MAX

COPLANARITY

0.50

BSC

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026BBC

Figure 11. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD±986JSTZ^±

AD±986JSTZ^±-REEL

AD±986BSTZ^±

AD±986BSTZ^±-REEL

Temperature Range

Package Description

48-Lead LQFP, Tray

48-Lead LQFP, Reel

48-Lead LQFP, Tray

48-Lead LQFP, Reel

Package Option

ST-48

0°C to +70°C

–40°C to +85°C

^±Z = Pb-free part.

Rev. 0 | Page 50 of 52

Preliminary Technical Data

NOTES

AD1986

Rev. 0 | Page 5± of 52

AD1986

NOTES

Preliminary Technical Data

trademarks are the property of their respective owners.

D04785-0-10/04(0)

Rev. 0 | Page 52 of 52


型号：	AD1986
厂家：	ADI
描述：	AC ’97 SoundMAX CODEC AC '97的SoundMAX编解码器解码器编解码器
文件：	总52页 (文件大小：2003K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD1986 [ADI]

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AD1986AJCPZ

AD1986AJCPZ-REEL

AD1986AJCPZ-RL

AD1986AJSTZ

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AD1986BSTZ

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