AD1991ASVZRL [ADI]
Class D/1-Bit Audio Power Amplifier Output Stage;
| 型号： | AD1991ASVZRL |
| 厂家： | 
ADI |
| 描述： | Class D/1-Bit Audio Power Amplifier Output Stage |
| 文件： | 总11页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Class D/1-Bit Audio Power Output Stage
AD1991
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
2-Channel Mode
Class D/1-Bit Audio Power Output Stage
5 V Analog and Digital Supply Voltages
Power Stage Power Supply 8 V to 20 V
Output Power @ 0.1% THD + N
Stereo Mode
AV
DD
DV
DD
PV
DD
6
OUTA
3
A1
A2
INA
2 ꢀ 20 W @ 4 ꢁ @ 14.4 V
2 ꢀ 20 W @ 8 ꢁ @ 20 V
LEFT
INPUT
Mono Mode
1 ꢀ 40 W @ 4 ꢁ @ 20 V
RON < 320 mꢁ (per Transistor)
Efficiency > 85% @ Full Power/8 ꢁ
Clickless Mute Function
B1
B2
INB
OUTB
3
LEVEL SHIFTER
AND
SWITCH CONTROL
H-BRIDGE
OUTC
3
Turn-On and Turn-Off Pop Suppression
Short-Circuit Protection
Overtemperature Protection
Data Loss Protection
2-Channel BTL Outputs or
4-Channel Single-Ended Outputs
52-Lead Exposed Pad TQFP Package
Low Cost DMOS Process
C1
C2
INC
RIGHT
INPUT
D1
D2
IND
OUTD
3
،n
CURRENT OVERLOAD
CLK
RST/PDN
MUTE
THERMAL SHUTDOWN
THERMAL WARNING
DATA LOSS
THERMAL PROTECTION
SHORT-CIRCUIT PROTECTION
MUTE CONTROL
APPLICATIONS
PC Audio Systems
Minicomponents
Automotive Amplifiers
Home Theater Systems
Televisions
4
2
14
AGND DGND
TEST
CONTROL
PGND
4-Channel Mode
AV
DD
DV
DD
PV
DD
6
GENERAL DESCRIPTION
The AD1991 is a 2-channel BTL or 4-channel single-ended
class D audio power output stage. The part is configured during
reset to be in either 2-channel mode or 4-channel mode.
A1
A2
OUTA
3
INA
INB
LOAD
REQUIRING
DC VOLTAGE
SUPPLY
To protect the IC as well as the connected speakers, the AD1991
provides turn-on and turn-off pop suppression, short-circuit
protection, and overtemperature shutdown. To control the IC,
a power-down/reset input and a mute pin are available.
B1
B2
OUTB
3
LEVEL SHIFTER
AND
SWITCH CONTROL
The output stage can be operated over a power supply range
from 8 V to 20 V.
H-BRIDGE
C1
C2
OUTC
3
INC
In 2-channel mode, Transistors A1, B2, C1, and D2 are turned
on by a Logic 1 on inputs INA and INC, and Transistors A2,
B1, C2, and D1 are turned on by a Logic 0 on inputs INA and
INC. In 4-channel mode, Transistors A1, B1, C1, and D1 are
turned on by a Logic 1 on the four inputs, and Transistors A2,
B2, C2, and D2 are turned on by a Logic 0 on the four inputs
(see the Functional Block Diagrams).
D1
D2
OUTD
3
IND
LOAD
REQUIRING
DC VOLTAGE
SUPPLY
،n
CLK
CURRENT OVERLOAD
THERMAL SHUTDOWN
THERMAL WARNING
DATA LOSS
THERMAL PROTECTION
SHORT-CIRCUIT PROTECTION
MUTE CONTROL
RST/PDN
MUTE
4
2
14
REV. 0
AGND DGND
TEST
PGND
CONTROL
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reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(AVDD = 5 V, DVDD = 5 V, PVDDX = 20 V, Ambient Temperature = 25ꢂC,
AD1991–SPECIFICATIONS1 Load Impedance = 8 ꢁ, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions
OUTPUT POWER PO (f = 1 kHz SINE WAVE)2
20
20
87
W
W
%
RL = 4 Ω, PVDDX = 14 V
RL = 8 Ω, PVDDX = 20 V
f = 1 kHz, PO = 20 W, RL = 8 Ω
EFFICIENCY
RON
Per High-Side Transistor
Per Low-Side Transistor
Temperature Coefficient
THERMAL WARNING ACTIVE
THERMAL SHUTDOWN ACTIVE
OVERCURRENT SHUTDOWN ACTIVE
260
190
0.7
135
150
5
320
235
mΩ
mΩ
mΩ/°C
°C
@ 1 A
@ 1 A
Die temperature
Die temperature
°C
3.8
6.75
A
POWER SUPPLIES
Supply Voltage AVDD
Supply Voltage DVDD
Supply Voltage PVDDX
Power-Down Current
AVDD
DVDD
PVDDX
Operating Current
AVDD
DVDD
4.5
4.5
6.5
5.0
5.0
8 to 20
5.5
5.5
22.5
V
V
V
6
1
17
14
13
µA
µA
µA
RST/PDN held low
RST/PDN held low
RST/PDN held low
1.8
4
40
2.75
5.2
mA
mA
mA
PVDDX
50:50 384 kHz square wave on
INA and INC
DIGITAL I/O
Input Voltage High
Input Voltage Low
2.0
DVDD
1.2
V
V
Output Voltage High
Output Voltage Low
Leakage Current on Digital Inputs
DVDD – 0.8
V
V
µA
@ 2 mA
@ 2 mA
0.4
10
NOTES
1Performance of both channels is identical.
2Measurement requires PWM modulator.
Specifications subject to change without notice.
(Guaranteed over –40ꢂC to +85ꢂC, AVDD = DVDD = 5 V ꢃ 10%, PVDDX = 20 V ꢃ 10%,
Edge Speed = Slowest, Nonoverlap Time = Shortest.)
DIGITAL TIMING CHARACTERISTICS
Symbol
Parameter
Min
Typ
Max
Unit
tPDL
tPST
tNOL
tPDRP
tMSU
tMH
Input transition to output initial response
Power transistor switching time
Nonoverlap time
RST/PDN minimum low pulsewidth
Mode pin setup time before RST/PDN going high
Mode pin hold time after RST/PDN going high
MUTE asserted to output initial response
30
ns
ns
ns
ns
ns
ns
s
3.5
25 to 40
20
5
5
tMPDL
3
Specifications subject to change without notice.
–2–
REV. 0
AD1991
INA
tPST
tPST
tPST
tPST
tNOL
tNOL
tPDL
tPDL
OUTA
OUTB
Figure 1. Output Timing
tPDRP
RST/PDN
MODEx
tMSU
tMH
Figure 2. RESET and Mode Timing
MUTE
tPST
tPST
OUTx
tMPDL
tMPDL
Figure 3. MUTE Timing
REV. 0
–3–
AD1991
ABSOLUTE MAXIMUM RATINGS1
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
(TA = 25°C, unless otherwise noted.)
AVDD, DVDD to AGND, DGND . . . . . . . . . . –0.3 V to +6.5 V
PVDDX to PGNDx2 . . . . . . . . . . . . . . . . . . . –0.3 V to +30.0 V
AGND to DGND to PGNDx . . . . . . . . . . . . –0.3 V to +0.3 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +0.5 V
Operating Temperature Range (Ambient)
2Including any induced voltage due to inductive load.
3With respect to the temperature of the exposed pad.
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
θ
JC Thermal Resistance3 . . . . . . . . . . . . . . . . . . . . . . . 1°C/W
Lead Temperature
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD1991ASV
AD1991ASVRL
EVAL-AD1991EB
–40°C to +85°C
–40°C to +85°C
Thin Quad Flat Pack [TQFP]
Thin Quad Flat Pack [TQFP]
Evaluation Board
SV-52
SV-52
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD1991 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–4–
REV. 0
AD1991
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
39
38
37
36
35
34
33
32
31
30
29
28
27
PGND1
OUTA
OUTA
OUTA
PGND2
OUTC
OUTC
OUTC
PIN 1
IDENTIFIER
3
4
5
PV
PV
DD1
DD2
PV
6
PV
DD1
DD2
AD1991
TOP VIEW
(Not to Scale)
PV
7
PV
DD1
DD2
8
OUTB
OUTB
OUTD
9
OUTD
10
11
OUTB
OUTD
PGND2
PGND2
PGND2
PGND1
PGND1 12
13
PGND1
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN FUNCTION DESCRIPTIONS
Mnemonic In/Out Description
Pin No.
1
PGND1
OUTA
PVDD1
OUTB
PGND1
ERR3
Negative power supply for high power Transistors A2 and B2.
Output of transistor pair A1 and A2.
Positive power supply for high power Transistors A1 and B1.
Output of transistor pair B1 and B2.
Negative power supply for high power Transistors A2 and B2.
Edge speed setting MSB during RESET/active low thermal shutdown error output during
normal operation.
Edge speed setting Bit 1 during RESET/active low thermal warning error output during
normal operation.
Nonoverlap time setting MSB during RESET/active thermal low shutdown error output
during normal operation.
Nonoverlap time setting Bit 1 during RESET/active low data-loss error output or low-side
transistor disable input during normal operation.
2, 3, 4
5, 6, 7
8, 9, 10
11, 12, 13
14
O
O
I/O
I/O
I/O
I/O
15
16
17
ERR2
ERR1
ERR0
18
19
INA
INB
I
I
Control pin for Transistors A1 and A2 always; also control pin for B1 and B2 in 2-channel mode.
Edge speed setting LSB during RESET/during normal operation, control pin for Transistors
B1 and B2 in 4-channel mode; no function in 2-channel mode.
Positive power supply for low power digital circuitry.
Negative power supply for low power digital circuitry.
Active low clickless mute input.
Control pin for Transistors C1 and C2 always; also control pin for D1 and D2 in 2-channel mode.
Nonoverlap time setting LSB during RESET/during normal operation, control pin for Transis-
tors D1 and D2 in 4-channel mode; no function in 2-channel mode.
Active low RESET/power-down input.
20
21
22
23
24
DVDD
DGND
MUTE
INC
I
I
I
IND
25
26
RST/PDN
CLK
I
I
External clock input in external clock mode.
27, 28, 29
30, 31, 32
33, 34, 35
36, 37, 38
PGND2
OUTD
PVDD2
Negative power supply for high power Transistors C2 and D2.
Output of transistor pair D1 and D2.
Positive power supply for high power Transistors C1 and D1.
Output of transistor pair C1 and C2.
O
O
OUTC
39, 40, 41, 42 PGND2
43, 45, 48, 49 AGND
Negative power supply for high power Transistors C2 and D2.
Negative power supply for low power analog circuitry.
44
46
MODE0
AVDD
Clock source select (referenced to AGND); normally connected to AGND.
Positive power supply for low power analog circuitry.
47
MODE1
PGND1
I
Channel mode select (referenced to AGND).
Negative power supply for high power Transistors A2 and B2.
50, 51, 52
REV. 0
–5–
AD1991
FUNCTIONAL DESCRIPTION
4-Channel Mode
Device Architecture
The 4-channel mode has two types of configuration: audio and
power supply. Neither of these configurations require data loss
detection. In the audio configuration, each single-ended load is
connected to the output through a blocking capacitor, which
prevents dc from reaching the load, thereby negating the need
for data loss detection. While in the power supply configuration,
it is desired to maintain a dc voltage on the load, also negating
the need for data loss detection. When used in the power supply
configuration, the four low-side transistors can also be disabled
and left permanently open if desired. This allows the loads to be
driven by switching only the high-side transistor on and off.
ERR0 is an input in 4-channel mode and is used to select
whether the four low-side transistors are enabled or disabled,
with 0 selecting disabled and 1 selecting enabled. Table IV
summarizes the function of ERR0 in this mode. Table V shows
the input/output relationship.
The AD1991 is an 8-transistor, audio, power output stage. The
AD1991 is arranged internally as four transistor pairs that can
be used as two H-bridge outputs (2-channel mode) or as four
single-ended outputs (4-channel mode), using either two or four
TTL compatible inputs to control the transistors. A dead time
is automatically provided between the switching of the high-
side transistor and low-side transistor when the control inputs
change level, to ensure that both the high-side transistor and
low-side transistor are never on at the same time.
Clock Source and Channel Mode Selection
When the AD1991 is brought out of reset, the logic levels on
MODE0 and MODE1 are latched internally. MODE0 determines
the internal state machine clock source. MODE1 determines the
channel mode and the function of ERR0 (see Tables I and II.)
When the internal clock is used, the CLK pin should not be
connected.
Table IV. ERR0 Function in 4-Channel Mode
ERR0 Low-Side Transistor Status
Table I. Clock Source Selection
MODE0
CLK Source
0
1
Disabled
Enabled
0
1
Internal
External
Table V. Input/Output Relationship in 4-Channel Mode
Table II. Channel Mode Selection
Input
Controlled Output
MODE1 Channel Mode
ERR0 Function
INA
INB
INC
IND
OUTA
OUTB
OUTC
OUTD
0
1
2-Channel Mode
4-Channel Mode
Data Loss Detection Output
Low-Side Disable Input
2-Channel Mode
1-Channel Mode
Two loads are connected differentially—across OUTA and OUTB
and across OUTC and OUTD. Inputs INB and IND are unused
and should be tied to an appropriate dc voltage (see the Edge
Speed and Nonoverlap Settings section). In this mode, ERR0 is
an error output used to indicate data loss, which occurs when
there are no transitions on INA or INC for more than 50 ms.
This signal condition is hazardous in 2-channel mode because it
can cause a potentially large and harmful dc voltage across the
differential loads. Table III shows the input/output relationship.
One load is connected differentially—across OUTA and OUTC,
and OUTB and OUTD. This mono operation is established
by configuring the part for 2-channel mode and externally
connecting INA to INC, OUTA to OUTC, and OUTB to
OUTD (see Figure 4).
Thermal Protection
The AD1991 features thermal protection. When the die tempera-
ture exceeds approximately 135°C, the thermal warning error
output (ERR2) is asserted. If the die temperature exceeds
approximately 150°C, the thermal shutdown error output (ERR3)
is asserted. If this occurs, the part shuts down to prevent damage
to the part. When the die temperature drops below approximately
120°C, both error outputs de-assert and the part returns to nor-
mal operation.
Table III. Input/Output Relationship in 2-Channel Mode
Input
Controlled Output
INA
INC
OUTA, OUTB
OUTC, OUTD
Overcurrent Protection
The AD1991 features overcurrent or short-circuit protection. If
the current through any power transistors exceeds 5 A, the part
is muted and the overcurrent error output (ERR1) is asserted.
This is a latched error and does not clear automatically. To clear
the error condition and restore normal operation, the part must
be reset or MUTE must be asserted and de-asserted.
–6–
REV. 0
AD1991
AV
DD
DV
DD
PV
INPUT
Table VI. Edge Speed Settings
DD
6
ERR3 ERR2 INB Edge Speed
A1
A2
OUTA
3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1 (Slowest Edge Speed)
2
3
4
5
6
7
INA
B1
B2
OUTB
3
INB
LEVEL SHIFTER
AND
SWITCH CONTROL
H-BRIDGE
8 (Fastest Edge Speed)
C1
C2
OUTC
3
INC
IND
Nonoverlap Time
The nonoverlap time is set by using the three pins, ERR1, ERR0,
and IND, when RST/PDN is low. The levels on the three pins
are latched by the rising edge of RST/PDN. The latched value
determines the nonoverlap time thereafter, until RST/PDN is
brought low. Table VII shows the appropriate logic levels for
the corresponding nonoverlap times. Note that IND is internally
inverted, resulting in the nonmonotonic sequence in Table VII.
D1
D2
OUTD
3
ꢄn
CURRENT OVERLOAD
CLK
RST/PDN
MUTE
THERMAL SHUTDOWN
THERMAL WARNING
DATA LOSS
THERMAL PROTECTION
SHORT-CIRCUIT PROTECTION
MUTE CONTROL
Note that ERR3, ERR2, ERR1, and ERR0 are driven outputs
under normal operation and, therefore, should never be tied to a
dc voltage. The part contains internal 300 kΩ pull-up resistors
to pull these pins high during reset. If it is desired to set them
low to achieve a particular edge speed or nonoverlap time, this
should be done by pulling them low through resistors between
10 kΩ and 50 kΩ.
4
2
14
AGND DGND
TEST
CONTROL
PGND
Figure 4. Functional Block Diagram (1-Channel Mode)
EDGE SPEED AND NONOVERLAP SETTINGS
Table VII. Nonoverlap Time Settings
The AD1991 allows the user to select from one of eight different
edge speeds and from one of eight different nonoverlap times.
This allows the user to make a trade-off between distortion,
efficiency, overshooting at the outputs, and EMI. The following
sections describe the method used to program the settings.
ERR1 ERR0
IND Nonoverlap Time
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1 (Shortest Nonoverlap Time)
2
3
4
5
6
7
Edge Speed
The edge speed is set by using the three pins, ERR3, ERR2, and
INB, when RST/PDN is low. The levels on the three pins are
latched by the rising edge of RST/PDN. The latched value deter-
mines the edge speed thereafter, until RST/PDN is brought low.
Table VI shows the appropriate logic levels for the corresponding
edge speeds. Note that INB is internally inverted, resulting in
the nonmonotonic sequence in Table VI.
8 (Longest Nonoverlap Time)
REV. 0
–7–
AD1991
APPLICATION CONSIDERATIONS
junction (die) and the case (package) for each watt of power
dissipated in the die. The AD1991 is specified with a JC of
1°C/W, which means that for each watt of power dissipated in
the part, the junction (or die) temperature will be 1ºC higher
than the case (or package) temperature.
Good board layout and decoupling are vital for correct operation
of the AD1991. Due to the fact that the part switches high currents,
there is the potential for large PVDD bounce each time a transis-
tor transitions. This can cause unpredictable operation of the part.
To avoid this potential problem, close chip decoupling is essen-
tial. It is also recommended that the decoupling capacitors be
placed on the same side of the board as the AD1991 and connected
directly to the PVDD and PGND pins. By placing the decoupling
capacitors on the other side of the board and decoupling through
vias, the effectiveness of the decoupling is reduced. This is
because vias have inductive properties and, therefore, prevent
very fast discharge of the decoupling capacitors. Best operation
is achieved with at least one decoupling capacitor on each side of
the AD1991 or optionally two capacitors per side can be used to
further reduce the series resistance of the capacitor. If these
decoupling recommendations cannot be followed and decoupling
through vias is the only option, the vias should be made as large
as possible to increase surface area, thereby reducing inductance
and resistance.
The value of CA, the difference between the case and ambient
temperatures, is entirely dependent on the size of heat sink
attached to the case, the material used, the method of attach-
ment, and the airflow over the heat sink. The value of CA is
specified as 26°C/W for no heat sink and no airflow over the device.
Finally, JA is the sum of the JC and CA values, and will be
between 1°C/W and 27°C/W depending on the heat sink used.
This is the temperature difference between the junction (die) and
ambient temperature around the case (package) for each watt
dissipated in the part.
The AD1991 is specified to have a thermal shutdown of typically
150°C die temperature. Good design procedures allow for a
margin, so the system should be designed such that the AD1991
die never goes above 140°C. Knowing the maximum desirable
die temperature, the efficiency of the AD1991, the maximum
ambient temperature, and the maximum power that will be
delivered to the load, the necessary CA can be calculated. For an
8 Ω load, the AD1991 has a typical efficiency of 87%, which
can be reduced slightly to be conservative. For this example,
assume an 85% efficiency. If the power delivered to the loads is
to be 2 ϫ 20 W rms continuous power, the power dissipated in
the AD1991 can be calculated as follows:
Figures 5 and 6 show two possible layouts to provide close chip
decoupling. In both cases, the PVDD to PGND decoupling is as
close as possible to the pins of the AD1991. One solution uses
surface-mount capacitors that offer low inductance; however, each
output (OUTA, OUTB, OUTC, and OUTD) must be brought
through vias to another layer of the board to be brought to the
LC filter. The other solution uses through-hole capacitors that
have higher inductance but allow the outputs to connect directly
to the LC filter. In this solution, the inductor for OUTA and
OUTC would span the PVDD trace. These diagrams show four
decoupling capacitors from PVDD to PGND; however, this may
not be necessary if capacitors with low series resistance are
used. Another close chip capacitor is used for AVDD to AGND
decoupling, with the actual power connections to the capacitors
being done through vias. This is quite acceptable since AVDD is
a low current stable supply. Finally, a close chip capacitor is used
to decouple DVDD to DGND. This is quite important since DVDD
is a digital supply whose current will change dynamically and,
Power Supplied to Loads = 40 W rms
Total Power Supplied to the AD1991 = (40/85 ϫ 100) = 47 W rms
Power Dissipated in the AD1991 = 7 W rms
If the ambient temperature can reach 85°C maximum, the allowable
difference between the die temperature and ambient temperature
is (140 – 85) = 55°C. This gives a JA requirement of (55/7) =
7.9°C/W. This requires a heat sink that gives a CA of 6.9°C/W.
The size and type of heat sink required can now be calculated.
If adequate heat sinking is not applied to the AD1991, the system
will suffer from the AD1991 going into thermal shutdown. It is
advisable to also use the thermal warning output on the AD1991
to attenuate the power being delivered to help prevent thermal
shutdown.
therefore, requires good decoupling. For both PVDD and DVDD
additional reservoir capacitors should be used to augment the
close chip decoupling, especially for PVDD, which usually has very
large transients.
,
THERMAL CONSIDERATIONS
POWER-UP CONSIDERATIONS
Careful consideration must be given to heat sinking the AD1991,
particularly in applications where the ambient temperature can
be much higher than normal room temperature. The three
thermal resistances of JC, CA, and JA should be known in
order to correctly heat sink the part. These values specify the
temperature difference between two points, per unit power
dissipation. JC specifies the temperature difference between the
Careful power-up is necessary when using the AD1991 to
ensure correct operation and to avoid possible latch-up issues.
The AD1991 should be held in RESET with MUTEB asserted
until all three power supplies have stabilized. Once the supplies
have stabilized, the part can be brought out of RESET, and
following this, MUTEB can be negated.
–8–
REV. 0
AD1991
PV PLANE
DD
CAP
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
AGND PLANE
3
4
5
6
PGND
PLANE
7
8
32
31
30
29
28
27
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CAP
Figure 5. Layout Using Surface-Mount Capacitors (4 × 10 nF or 2 × 22 nF Recommended)
PV
PLANE
CAP
DD
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
AGND PLANE
3
4
5
6
PGND
PLANE
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CAP
Figure 6. Layout Using Through-Hole Capacitors (4 × 10 nF or 2 × 22 nF Recommended)
REV. 0
–9–
AD1991
AV
AV
DV
DV
PV
PV
DD
DD
DD
FEEDBACK
AV
DV
DD
DD
DD
DD
DD
ANALOG INPUT_L
GND
PWM_L
GND
MODULATOR
AD1991
ANALOG INPUT_R
PWM_R
AGND DGND FEEDBACK
AGND DGND
PGND
PGND
AGND DGND
Figure 7. Simplified System Schematic for Analog-In, Analog-Out System
–10–
REV. 0
AD1991
OUTLINE DIMENSIONS
52-Lead Thin Quad Flat Package, Exposed Pad [TQFP/EP]
(SV-52)
Dimensions shown in millimeters
12.00
BSC SQ
52
40
40
52
1
39
39
1
BOTTOM VIEW
(PINS UP)
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
EXPOSED
PAD
6.50
SQ
13
27
27
13
14
26
26
14
0.65
BSC
0.38
0.32
0.22
1.05
1.00
0.95
1.20
MAX
VIEW A
7ꢂ
3.5ꢂ
0ꢂ
0.20
0.09
SEATING
PLANE
0.15
0.05
0.75
0.60
0.45
VIEW A
COMPLIANT TO JEDEC STANDARDS MS-026ACC
WITH THE EXCEPTION THAT THE EXPOSED DIE PAD SHALL BE
COPLANAR WITH BOTTOM OF PACKAGE WITHIN 0.05 MILLIMETERS.
REV. 0
–11–
相关型号：
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