AD22050 [ADI]
Single-Supply Sensor Interface Amplifier; 单电源传感器接口放大器
| 型号： | AD22050 |
| 厂家： | 
ADI |
| 描述： | Single-Supply Sensor Interface Amplifier |
| 文件： | 总8页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Supply Sensor
Interface Amplifier
a
AD22050
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Gain of
؋
20. Alterable from ؋
1 to ؋
160 Input CMR from Below Ground to 6
؋
(VS – 1 V) Output Span 20 mV to (VS – 0.2) V
1-, 2-, 3-Pole Low-Pass Filtering Available
Accurate Midscale Offset Capability
Differential Input Resistance 400 k⍀
Drives 1 k⍀ Load to +4 V Using VS = +5 V
Supply Voltage: +3.0 V to +36 V
Transient Spike Protection and RFI Filters Included
Peak Input Voltage (40 ms): 60 V
Reversed Supply Protection: –34 V
Operating Temperature Range: –40؇C to +125؇C
+V
OFS A1
A2
S
AD22050
IN+
IN–
A1
A2
OUT
GND
APPLICATIONS
Current Sensing
Motor Control
Interface for Pressure Transducers, Position Indicators,
Strain Gages, and Other Low Level Signal Sources
GENERAL DESCRIPTION
a +5 V supply with excellent rejection of this common-mode
voltage. This is achieved by the use of a special resistive attenua-
tor at the input, laser trimmed to a very high differential balance.
The AD22050 is a single-supply difference amplifier for ampli-
fying and low-pass filtering small differential voltages (typically
100 mV FS at a gain of 40) from sources having a large common-
mode voltage.
Provisions are included for optional low-pass filtering and gain
adjustment. An accurate midscale offset feature allows bipolar
signals to be amplified.
Supply voltages from +3.0 V to +36 V can be used. The input
common-mode range extends from below ground to +24 V using
+V (CAR BATTERY)
S
+5V
SOLENOID
LOAD
ANALOG OUTPUT
4V PER AMP
100m⍀
200k⍀
AD22050
CORNER FREQUENCY
= 0.796Hz-F
CMOS DRIVER
CHASSIS
C
POWER
DARLINGTON
ANALOG GROUND
SINGLE-POLE LOW-PASS FILTERING, GAIN: 40
Figure 1. Typical Application Circuit for a Current Sensor Interface
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(T = +25؇C, V = +5 V, and VCM = 0, RL = 10 k⍀ unless otherwise noted)
AD22050–SPECIFICATIONS
A
S
Parameter
Test Conditions
Min
Typ
Max
Units
INPUTS (Pins 1 and 8)
+CMR
–CMR
CMRRLF
CMRRHF
RINCM
RMATCH
RINDIFF
Positive Common-Mode Range
Negative Common-Mode Range
Common-Mode Rejection Ratio
Common-Mode Rejection Ratio
Common-Mode Input Resistances Pin 1 or Pin 8 to Pin 2
Matching of Resistances
TA = TMIN to TMAX
TA = TMIN to +85°C
f ≤ 10 Hz
+24
V
V
dB
dB
kΩ
%
–1.0
80
60
180
90
75
240
±0.5
400
f = 10 kHz
300
Differential Input Resistance
Pin 1 to Pin 8
280
kΩ
PREAMPLIFIER
GCL
VO
Closed-Loop Gain1
9.7
+0.01
97
10.0
100
10.3
+4.8
103
Output Voltage Range (Pin 3)
V
kΩ
RO
Output Resistance2
OUTPUT BUFFER
GCL
VO
RO
Closed-Loop Gain1
RLOAD ≥ 10 kΩ
TA = TMIN to TMAX
VO ≥ 0.1 V dc, IO < 1 mA
1.94
+0.02
2.0
2.0
2.06
+4.8
Output Voltage Range3
Output Resistance (Pin 5)
V
Ω
OVERALL SYSTEM
G
Gain1
VO ≥ 0.1 V dc
TA = TMIN to TMAX
19.9
19.8
–1
20.0
0.03
20.1
20.2
1
3
0.51
Over Temperature
Input Offset Voltage4
Over Temperature
Midscale Offset (Pin 7) Scaling
Input Resistance
Short-Circuit Output Current
–3 dB Bandwidth
VOS
mV
mV
V/V
kΩ
mA
kHz
V/µs
µV/√Hz
TA = TMIN to TMAX
–3
OFS
0.49
2.5
7
0.50
3.0
11
30
0.2
Pin 7 to Pin 2
TA = TMIN to TMAX
VO = +1 V dc
IOSC
BW–3 dB
SR
25
Slew Rate
NSD
Noise Spectral Density3
f = 100 Hz to 10 kHz
0.2
POWER SUPPLY
VS
IS
Operating Range
TA = TMIN to TMAX
TA = +25°C, VS = +5 V
3.0
5
200
36
500
V
µA
Quiescent Supply Current5
TEMPERATURE RANGE
TOP
Operating Temperature Range
–40
+125
°C
NOTES
1Specified for default mode, i.e., with no external components. The overall gain is trimmed to 0.5%, while the individual gains of A1 and A2 may be subject to a
maximum ±3% tolerance. Note that the actual gain in a particular application can be modified by the use of external resistor networks.
2The actual output resistance of A1 is only a few ohms, but access to this output, via Pin 3, is always through the resistor R12 (see Figure 16) which is 100 kΩ,
trimmed to ± 3%.
3For VCM ≤ 20 V. For VCM > 20 V, VOL 1 mV/V × VCM
.
4Referred to the input (Pins 1 and 8).
5With VDM = 0 V. Differential mode signals are referred to as VDM, while VCM refers to common-mode voltages—see the section Product Description and Figure 3.
All min and max specifications are guaranteed, although only those marked in boldface are tested on all production units at final test.
Specifications subject to change without notice.
ORDERING GUIDE
Model
Temperature Range
Package Descriptions Package Options
AD22050N
AD22050R
AD22050R-Reel
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Plastic DIP
Plastic SOIC
Tape and Reel
N-8
SO-8
SO-8*
*Quantities must be in increments of 2,500 pieces each.
–2–
REV. C
AD22050
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATIONS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to +36 V
Peak Input Voltage (40 ms) . . . . . . . . . . . . . . . . . . . . . . +60 V
VOFS (Pin 7 to Pin 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+20 V
Reversed Supply Voltage Protection . . . . . . . . . . . . . . . –34 V
Operating Temperature . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Plastic Mini-DIP Package
(N-8)
Plastic SOIC Package
(SO-8)
1
2
3
4
8
7
6
5
+IN
–IN
GND
A1
1
2
3
4
8
7
6
5
+IN
–IN
GND
A1
AD22050
TOP VIEW
(Not to Scale)
OFFSET
AD22050
TOP VIEW
(Not to Scale)
OFFSET
+V
S
+V
S
A2
OUT
A2
OUT
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; the functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD22050 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
(Pin 6), permitting the conditioning and processing of bipolar
signals (see Strain Gage Interface section).
PRODUCT DESCRIPTION
The AD22050 is a single-supply difference amplifier consisting
of a precision balanced attenuator, a very low drift preamplifier
and an output buffer amplifier (A1 and A2, respectively, in
Figure 2). It has been designed so that small differential sig-
nals (VDM in Figure 3) can be accurately amplified and filtered
in the presence of large common-mode voltages (VCM) without
the use of any other active components.
The output buffer A2 has a gain of ×2, setting the precalibrated,
overall gain of the AD22050, with no external components, to
×20. (This gain is easily user-configurable—see Altering the
Gain section for details.)
The dynamic properties of the AD22050 are optimized for
interfacing to transducers; in particular, current sensing shunt
resistors. Its rejection of large, high frequency, common-mode
signals makes it superior to that of many alternative approaches.
This is due to the very careful design of the input attenuator and
the close integration of this highly balanced, high impedance
system with the preamplifier.
+V
OFS A1
A2
S
AD22050
IN+
IN–
A2
A1
OUT
GND
APPLICATIONS
The AD22050 can be used wherever a high gain, single-supply
differencing amplifier is required, and where a finite input resis-
tance (240 kΩ to ground, 400 kΩ between differential inputs)
can be tolerated. In particular, the ability to handle a common-
mode input considerably larger than the supply voltage is fre-
quently of value.
Figure 2. Simplified Schematic
The resistive attenuator network is situated at the input to the
AD22050 (Pins 1 and 8), allowing the common-mode voltage at
Pins 1 and 8 to be six times greater than that which can be toler-
ated by the actual input to A1. As a result, the input common-
mode range extends to 6× (VS – 1 V).
Also, the output can run down to within 20 mV of ground,
provided it is not called on to sink any load current. Finally, the
output can be offset to half of a full-scale reference voltage (with
a tolerance of ±2%) to allow a bipolar input signal.
Two small filter capacitors (not shown in Figure 2) have been
included at the inputs of A1 to minimize the effects of any spuri-
ous RF signals present in the signal.
ALTERING THE GAIN
The gain of the preamplifier, from the attenuator input (Pins 1
and 8) to its output at Pin 3, is ×10 and that of the output
buffer, from Pin 4 to Pin 5, is ×2, thus making the overall de-
fault gain ×20. The overall gain is accurately trimmed (to within
±0.5%). In some cases, it may be desirable to provide for some
variation in the gain; for example, in absorbing the scaling error
of a transducer.
Internal feedback around A1 sets the closed-loop gain of the
preamplifier to ×10 from the input pins; the output of A1 is
connected to Pin 3 via a 100 kΩ resistor, which is trimmed to
±3% (R12 in Figure 2) to facilitate the low-pass filtering of the
signal of interest (see Low-Pass Filtering section). The inclusion
of an additional resistive network allows the output of A1 to be
offset to an optional voltage of one half of that supplied to Pin 7;
in many cases this offset would be +VS/2 by tying Pin 7 to +VS
Figure 3 shows a general method for trimming the gain, either
upward or downward, by an amount dependent on the resistor,
R. The gain range, expressed as a percentage of the overall gain,
REV. C
–3–
AD22050
is given by (10 MΩ/R)%. Thus, the adjustment range would be
±2% for R = 5 MΩ; ± 10% for R = 1 MΩ, etc.
now multiplied by the factor R/(R–100k); for example, it is
doubled for R = 200 kΩ. Overall gains of up to ×160 (R = 114 kΩ)
are readily achievable in this way. Note, however, that the accu-
racy of the gain becomes critically dependent on resistor value at
high gains. Also, the effective input offset voltage at Pins 1 and
8 (about six times the actual offset of A1) limits the part’s use in
very high gain, dc-coupled applications. The gain may be trimmed
by using a fixed and variable resistor in series (see, for example,
Figure 10).
ANALOG
OUTPUT
+IN OFS +V OUT
S
V
DM
AD22050
–IN GND A1 A2
R
؎GAIN ADJUST
20k⍀ MIN
(SEE TEXT)
V
CM
ANALOG
OUTPUT
ANALOG
COMMON
V
= DIFFERENTIAL VOLTAGE, V = COMMOM-MODE VOLTAGE
CM
DM
+IN OFS +V OUT
S
20R
R – 100k
Figure 3. Altering Gain to Accommodate Transducer
Scaling Error
GAIN = ––––––––
V
DM
CM
AD22050
R
–IN
GND A1 A2
GAIN
In addition to the method above, another method may be used
to vary the gain. Many applications will call for a gain higher
than ×20, and some require a lower gain. Both of these situa-
tions are readily accommodated by the addition of one external
resistor, plus an optional potentiometer if gain adjustment is
required (for example, to absorb a calibration error in a trans-
ducer).
R = 100k –––––––––
POINT X
(SEE TEXT)
GAIN – 20
V
ANALOG
COMMON
Figure 5. Achieving Gains Greater Than ×20
Once again, a small offset voltage will arise from an imbalance
in source resistances and the finite bias currents inherently
present at the input of A2. In most applications this additional
offset error (about 130 µV at ×40) will be comparable with the
specified offset range and will therefore introduce negligible
skew. It may, however, be essentially eliminated by the addition
of a resistor in series with the parallel sum of R and 100 kΩ
(i.e., at “Point X” in Figure 5) so the total series resistance is
maintained at 100 kΩ. For example, at a gain of ×30, when
R = 300 kΩ and the parallel sum of R and 100 kΩ is 75 kΩ, the
padding resistor should be 25 kΩ. A 50 kΩ pot would provide
an offset range of about ±2.25 mV referred to the output, or
±75 µV referred to the attenuator input. A specific example is
shown in Figure 12.
Decreasing the Gain. See Figure 4. Since the output of the
preamplifier has an output resistance of 100 kΩ, an external
resistor connected from Pin 4 to ground will precisely lower the
gain by a factor R/(100k+R). When configuring the AD22050
for any gain, the maximum input and the power supply being
used should be considered, since either the preamplifier or the
output buffer will reach its full-scale output (approximately
VS – 0.2 V) with large differential input voltages. The input of
the AD22050 is limited to no greater than (V – 0.2)/10, for
overall gains less than 10, since the preamplifier, with its fixed
gain of ×10, reaches its full scale output before the output
buffer. For VS = 5 V this is 0.48 V. For gains greater than 10,
however, the swing at the buffer output reaches its full-scale first
and limits the AD22050 input to (VS – 0.2)/G, where G is the
overall gain. Increasing the power supply voltage increases the
allowable maximum input. For VS = 5 V and a nominal gain of
20, the maximum input is 240 mV.
LOW-PASS FILTERING
In many transducer applications it is necessary to filter the sig-
nal to remove spurious high frequency components, including
noise, or to extract the mean value of a fluctuating signal with a
peak-to-average ratio (PAR) greater than unity. For example, a
full wave rectified sinusoid has a PAR of 1.57, a raised cosine
has a PAR of 2 and a half wave sinusoid has a PAR of 3.14.
Signals having large spikes may have PARs of 10 or more.
The overall bandwidth is unaffected by changes in gain using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to A2. In many
cases this can be ignored but, if desired, can be nulled by insert-
ing a resistor in series with Pin 4 (at “Point X” in Figure 4) of
value 100 kΩ minus the parallel sum of R and 100 kΩ. For
example, with R = 100 kΩ (giving a total gain of ×10), the op-
tional offset nulling resistor is 50 kΩ.
When implementing a filter, the PAR should be considered so
the output of the AD22050 preamplifier (A1) does not clip
before A2 does, since this nonlinearity would be averaged and
appear as an error at the output. To avoid this error both ampli-
fiers should be made to clip at the same time. This condition is
achieved when the PAR is no greater than the gain of the second
amplifier (2 for the default configuration). For example, if a
PAR of 5 is expected, the gain of A2 should be increased to 5.
ANALOG
OUTPUT
+V
+IN OFS
OUT
S
20R
GAIN = ––––––––
R + 100k
V
DM
CM
AD22050
Low-pass filters can be implemented in several ways using the
features provided by the AD22050. In the simplest case, a
single-pole filter (20 dB/decade) is formed when the output of
A1 is connected to the input of A2 via the internal 100 kΩ resis-
tor by strapping Pins 3 and 4, and a capacitor added from this
node to ground, as shown in Figure 6. The dc gain remains ×20,
and the gain trim shown in Figure 3 may still be used. If a resis-
tor is added across the capacitor to lower the gain, the corner
frequency will increase; it should be calculated using the parallel
sum of the resistor and 100 kΩ.
–IN
GND A1 A2
GAIN
R = 100k –––––––––
20 – GAIN
POINT X
(SEE TEXT)
R
V
ANALOG
COMMON
Figure 4. Achieving Gains Less Than ×20
Increasing the Gain. The gain can be raised by connecting a
resistor from the output of the buffer amplifier (Pin 5) to its
noninverting input (Pin 4) as shown in Figure 5. The gain is
–4–
REV. C
AD22050
ANALOG
OUTPUT
A three-pole filter (with roll-off 60 dB/decade) can be formed by
adding a passive RC network at the output forming a real pole.
A three-pole filter with a corner frequency f3 has the same
attenuation a one-pole filter of corner f1 has at a frequency
1
CORNER FREQUENCY =
+IN OFS +V OUT
S
2C
؋
100k V
V
DM
AD22050
GND A1 A2
3
THAT IS, 1.59Hz-F
–IN
√f3 /f1, where the attenuation is 30 Log (f3/f1) (see the graph in
Figure 9). Using equal capacitor values, and a resistor of
160 kΩ, the corner-frequency calibration remains 1 Hz-µF.
(C IS IN FARADS)
C
CM
FREQUENCY
ANALOG
COMMON
ATTENUATION
Figure 6. Connections for Single-Pole, Low-Pass Filter
–20dB/DECADE
–60dB/DECADE
If the gain is raised using a resistor, as shown in Figure 5, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 kΩ (for which the gain
would be doubled) the corner frequency is now 0.796 Hz-µF,
(0.039 µF for a 20 Hz corner).
ANALOG
OUTPUT
A 1-POLE FILTER, CORNER f ,
1
AND A 3-POLE FILTER, CORNER f ,
30LOG (f /f )
3
3
1
HAVE THE SAME ATTENUATION,
+IN OFS +V OUT
S
3
–30LOG (f /f ), AT FREQUENCY (f /f
1)
3
1
3
C
V
AD22050
DM
–IN GND A1 A2
CORNER
FREQUENCY = 1Hz-F
3
f
f
3
1
(f /f )
3 1
255k⍀
Figure 9. Comparative Responses of One- and Three-Pole
Low-Pass Filters
V
CM
C
ANALOG
COMMON
Figure 7. Connections for Conveniently Scaled, Two-Pole,
Low-Pass Filter
CURRENT SENSOR INTERFACE
A typical automotive application making use of the large
common-mode range is shown in Figure 10.
A two-pole filter (with a roll-off of 40 dB/decade) can be imple-
mented using the connections shown in Figure 7. This is a
Sallen & Key form based on a ×2 amplifier. It is useful to remem-
ber that a two-pole filter with a corner frequency f2 and a
one-pole filter with a corner at f1 have the same attenuation at
+V (BATTERY)
S
+5V
SOLENOID
LOAD
ANALOG OUTPUT
4V PER AMP
FLYBACK
DIODE
2
the frequency (f2 /f1). The attenuation at that frequency is
+IN OFS +V OUT
191k⍀
S
40 Log(f2/f1). This is illustrated in Figure 8. Using the standard
resistor value shown, and equal capacitors (in Figure 7), the
corner frequency is conveniently scaled at 1 Hz-µF (0.05 µF for
a 20 Hz corner). A maximally flat response occurs when the
resistor is lowered to 196 kΩ and the scaling is then 1.145 Hz-
µF. The output offset is raised by about 4 mV (equivalent to
200 µV at the input pins).
100m⍀
؎5% SENSOR
CALIBRATION
AD22050
GND A1 A2
–IN
20k⍀
CORNER FREQUENCY
= 0.796Hz-F
(0.22F FOR f = 3.6Hz)
CMOS DRIVER
CHASSIS
C
POWER
ANALOG COMMON
DARLINGTON
FREQUENCY
Figure 10. Current Sensor Interface. Gain Is ×40, Single-
ATTENUATION
Pole Low-Pass Filtering
–40dB/DECADE
The current in a load, here shown as a solenoid, is controlled by
a power transistor that is either cut off or saturated by a pulse at
its base; the duty-cycle of the pulse determines the average
current. This current is sensed in a small resistor. The aver-
age differential voltage across this resistor is typically 100 mV,
although its peak value will be higher by an amount that
depends on the inductance of the load and the control fre-
quency. The common-mode voltage, on the other hand, extends
from roughly 1 V above ground, when the transistor is satu-
rated, to about 1.5 V above the battery voltage, when the tran-
sistor is cut off and the diode conducts.
–20dB/DECADE
40LOG (f /f )
2
1
A 1-POLE FILTER, CORNER f ,
1
AND A 2-POLE FILTER, CORNER f ,
2
HAVE THE SAME ATTENUATION,
2
–40LOG (f /f ), AT FREQUENCY f /f
1
2
1
2
2
(f /f )
2 1
f
f
1
2
If the maximum battery voltage spikes up to +20 V, the common-
mode voltage at the input can be as high as 21.5 V. This can be
measured using even a +5 V supply for the AD22050.
Figure 8. Comparative Responses of One- and Two-Pole
Low-Pass Filters
REV. C
–5–
AD22050
To produce a full-scale output of +4 V, a gain ×40 is used, adjust-
able by ±5% to absorb the tolerance in the sense resistor. There is
sufficient headroom to allow at least a 10% overrange (to +4.4 V).
The roughly triangular voltage across the sense resistor is aver-
aged by a single-pole low-pass filter, here set with a corner fre-
quency of fC = 3.6 Hz, which provides about 30 dB of attenuation
at 100 Hz. A higher rate of attenuation can be obtained by a
two-pole filter having fC = 20 Hz, as shown in Figure 11. Al-
though this circuit uses two separate capacitors, the total capaci-
tance is less than half that needed for the single-pole filter.
An ac excitation of up to ±2 V can also be used because the
common-mode range of the AD22050 extends to –1 V. Assum-
ing a full-scale bridge output (VG) of ±10 mV, a gain of ×100
might be used to provide an output of ±1 V (a full-scale range
of +1.5 V to +3.5 V). This gain is achieved using the method
discussed in connection with Figure 5. Note that the gain-
setting resistor does not affect the accuracy of the midscale
offset. (However, if the gain were lowered, using a resistor to
ground, this offset would no longer be accurate.) A VOS nulling
pot is included for illustrative purposes. One-, two- and three-
pole filtering can also be implemented, as discussed in the
Low-Pass Filtering section.
+5V
+V (BATTERY)
S
SOLENOID
LOAD
ANALOG
OUTPUT
Using the Midscale Offset Feature
FLYBACK
DIODE
Figure 13 shows a more detailed schematic of the output am-
plifier A2. Because this is a single supply device, the output
stage has no pull-down transistor. Such a transistor would limit
the minimum output to several hundred millivolts above
ground. When using the AD22050 in unipolar mode (Pin 7
grounded), the resistors making up the feedback network also
act as a pull-down for the output stage.
432k⍀
50k⍀
+IN OFS +V OUT
S
C
100m⍀
AD22050
–IN
GND A1 A2
127k⍀
CMOS DRIVER
CHASSIS
CORNER FREQUENCY
= 1Hz-F
C
(0.05F FOR f = 20Hz)
+V
S
C
ANALOG
COMMON
POWER
DARLINGTON
A2
OUT
Figure 11. Illustration of Two-Pole Low-Pass Filtering
10k⍀
R
L
95k⍀
20k⍀
STRAIN GAGE INTERFACE: MIDSCALE OFFSET
FEATURE
OFS
20k⍀
The AD22050 can be used to interface a strain gage to a subse-
quent process where only a single supply voltage is available. In
this application, the midscale offset feature is valuable, since the
output of the bridge may have either polarity. Figure 12 shows
typical connections.
GND
Figure 13. Detailed Schematic of Output Amplifier A2
If the output is called upon to source current (not sink), then it
can swing almost completely to ground (within 20 mV). How-
ever, if the offset pin is connected to some positive voltage
source, this source will “pull up” the output voltage, thereby
limiting the minimum output swing. With no external load the
minimum output voltage possible is VOFS/2. For example, if Pin
7 is connected to +5 V, the minimum output voltage is equal
to the offset voltage of 2.5 V. By adding an additional load, as
shown, the output swing toward ground can be extended.
+V
S
ANALOG OUTPUT
125k⍀
(SETS GAIN
TO
؋
100) R
R
R
R
+IN OFS +V OUT
S
V
G
AD22050
–IN GND A1 A2
R
L
10k⍀
100k⍀
NULL
V
OS
OPTIONAL
LP FILTER
The relationship is described by:
ANALOG COMMON
Figure 12. Typical Connections for a Strain Gage Interface
Using the Offset Feature
1
2
RL
VOUT
>
VOFS
RL +20 kΩ*
*This 20 kΩ resistor is internal to the AD22050 and can vary by ± 30%.
The offset is obtained by connecting Pin 7 (OFS) to the supply
voltage. In this way, the output of the AD22050 is centered to
midway between the supply and ground. In many systems the
supply will also serve as the reference voltage for a subsequent
A/D converter. Alternatively, Pin 7 may be tied to the reference
voltage from an independent source. The AD22050 is trimmed
to guarantee an accuracy of ±2% on the 0.5 ratio between the
voltage on Pin 7 and the output.
where RL is an externally applied load resistor. However, RL
cannot be made arbitrarily small since this would require exces-
sive current from the output. The output current should be
limited to 5 mA total.
–6–
REV. C
AD22050
APPLICATION HINTS
Frequency Compensation
network helps to absorb the additional charge, effectively lower-
ing the high frequency output impedance of the AD22050. For
these applications the output signal should be taken from the
midpoint of the RLAG–CLAG combination as shown in Figure 15.
As are all closed-loop op amp circuits, the AD22050 is sensi-
tive to capacitive loading at its output. However, the AD22050
is sensitive at higher output voltages due to nonlinear effects in
the rail-to-rail design of the buffer amplifier (A2). In this
amplifier the output stage gain increases with increasing output
voltage. This behavior does not affect dc parameters such as
gain accuracy or linearity; however, it can compromise ac sta-
bility. When operating from a power supply of 5 V or less (and,
therefore, VOUT < 5 V), the AD22050 can drive capacitive
loads up to 25 pF with no external components. When operat-
ing at higher supply voltages (which are associated with higher
output voltages) and/or driving larger capacitive loads, an ex-
ternal compensation network should be used. Figure 14 shows
an R-C “snubber” circuit loading the output of the AD22050.
Since the perturbations from the analog-to-digital converter are
small, the output of the AD22050 will appear to be a low
impedance. The transient response will, therefore, have a
time constant governed by the product of the two lag compo-
nents, CLAG × RLAG. For the values shown in Figure 15, this
time constant is programmed at approximately 10 µs. There-
fore, if samples are taken at several tens of microseconds or more,
there will be negligible “stacking up” of the charge injections.
+V
S
AD22050
LOAD
A2
This combination, in conjunction with the internal 20 kΩ resis-
tance, forms a lag network. This network attenuates the open-
loop gain of the amplifier at higher frequencies. The ratio of
RLAG to the load seen by the AD22050 determines the high
frequency attenuation seen by the op amp. If RLAG is made 1/
20th of the total load resistance (≈20 kΩʈRL), then 26 dB of
attenuation is obtained at higher frequencies. The capacitor
(CLAG) is used to control the frequency of the compensation
network. It should be set to form a 5 µs time constant with the
resistor (RLAG). Table I shows the recommended values of
RLAG and CLAG for various values of external load resistor RL.
Ten percent tolerance on these components is acceptable.
10k⍀
10k⍀
R
R
L
C
LAG
L
C
LAG
Figure 14. Using an R-C Network for Compensation
+V
S
AD22050
A2
1k⍀
Alternatively, the signal may be taken from the midpoint of
IN
R
LAG–CLAG. This output is particularly useful when driving
0.01F
PROCESSOR
10k⍀
10k⍀
A/D
CMOS analog-to-digital converters. For more information see
the section Driving Charged Redistributed A/D Converters.
Note that when implementing this network large signal re-
sponse is compromised. This occurs because there is no active
pull-down and the lag capacitor must discharge through the
internal feedback resistor (20 kΩ) giving a fairly long-time
constant. For example if CLAG = 0.01 µF, the large signal nega-
tive slew characteristic is a decaying exponential with a time
constant of ≈200 µs.
Figure 15. Recommended Circuit for Driving CMOS A/D
Converters
UNDERSTANDING THE AD22050
Figure 16 shows the main elements of the AD22050. The signal
inputs at Pins 1 and 8 are first applied to dual resistive attenua-
tors R1 through R4, whose purpose is to reduce the common-
mode voltage at the input to the preamplifier. The attenuated
signal is then applied to a feedback amplifier based on the very
low drift op amp, A1. The differential voltage across the inputs
is accurately amplified in the presence of common-mode volt-
ages of many times the supply voltage. The overall common-
mode response is minimized by precise laser trimming of R3
and R4, giving the AD22050 a common-mode rejection ratio
(CMRR) of at least 80 dB (10,000:1).
Table I. Compensation Components vs. External Load
Resistor
RL
RLAG
CLAG
>100 kΩ
> 50 kΩ
> 20 kΩ
> 10 kΩ
> 5 kΩ
470 Ω
390 Ω
270 Ω
200 Ω
100 Ω
47 Ω
0.01 µF
0.01 µF
0.047 µF
0.047 µF
0.1 µF
> 2 kΩ
0.22 µF
The common-mode range of A1 extends from slightly below
ground to 1 V below +VS (at the minimum temperature of
–40°C). Since an attenuation ratio of about 6 is used, the input
common-mode range is –1 V to +24 V using a +5 V supply.
Small filter capacitors C1 and C2 are included to minimize the
effects of spurious RF signals at the inputs, which might cause
dc errors due to the rectification effects at the input to A1. At
high frequencies, even a small imbalance in these components
would seriously degrade the CMRR, so a special high frequency
trim is also carried out during manufacture.
Driving Charge Redistribution A/D Converters
When driving CMOS ADCs, such as those embedded in popu-
lar microcontrollers, the charge injection (∆Q) can cause a
significant deflection in the AD22050 output voltage. Though
generally of short duration, this deflection may persist until
after the sample period of the ADC has expired. It is due to the
relatively high open-loop output impedance of the AD22050.
The effect can be significantly reduced by including the same
R-C network recommended for improving stability (see Fre-
quency Compensation section). The large capacitor in the lag
REV. C
–7–
AD22050
A unique method of feedback around A1, provided by R9 and
R7, sets the closed-loop gain of the preamplifier to ×10 (from
the input pins). The feedback network is balanced by the inclu-
sion of R6 and R8. The small value of R7 results in a more
practical value for R9 (which would have to be 2 MΩ if the
feedback were taken directly to the inputs of A1). R8 is not
directly connected to ground, but to an optional voltage of one
half that is applied to Pin 7 (OFS). It is trimmed to within
close tolerances through R10 and R11. This allows the output
of A1 to be offset to midscale, typically +VS/2, by tying Pins 6
and 7 together. (For an example of the use of this feature, see
Figure 12.) The gain is adjusted by the single resistor R5,
which acts only on the differential signal. More importantly, it
also results in much less feed forward of the common-mode
signal to the output of A1, which, being a single-supply circuit,
has no means of pulling this output down toward ground in
those circumstances where the common-mode input is very
positive while the net differential signal is small. (The output of
A1 is the collector of a PNP transistor whose emitter is tied to
+VS.) R16 is specifically included to alleviate this problem.
and Key filter can be formed (see Low-Pass Filtering section)
and also provides a means for setting the overall gain to values
other than ×20 (see Altering the Gain section).
The output buffer has a gain of ×2, set by the feedback network
around op amp A2, formed by R15 and R13ʈR14. Note that this
gain is not trimmed to a precise value, but may have a tolerance
of ±3% (max). Only the overall gain of A1 and A2 is trimmed to
within ±0.5% by R5. As a consequence, the gain of A1 may be
in error by ±3% (max) as the trim to R5 absorbs the initial error
in the gain of A2. In most applications Pins 3 and 4 are simply
tied together, but the output buffer can be used independently if
desired. The offset voltage of A2 is nulled during manufacture.
R17 is included to minimize the offset due to bias currents. It is
recommended, in applications where A2 is used independently
and the source resistance is less than 100 kΩ, that the necessary
extra resistance should be included.
The output of A2 is the collector of a PNP transistor whose
emitter is tied to +VS. The bias current out of the inverting
input of this amplifier generates an offset voltage of about +1 mV
in R13ʈR14, which is passed directly to the output via R15. This
sets the lowest output that can be reached when there is no load
resistor. However, the output can drive a 1 kΩ load to at least
+4.5 V when +VS = +5 V. If operation to much lower minimum
voltages is essential, a load resistor can be added externally.
The output of the preamplifier is connected to Pin 3 via R12, a
100 kΩ resistor that is trimmed to within ±3%. The inclusion
of R12 allows a low-pass filter to be formed, with an accurate
time constant, by placing a capacitor from Pin 3 to ground. By
separating the connections at Pins 3 and 4, a two-pole Sallen
+V
A1
A2
S
AD22050
C1
5pF
R12
100k⍀
R18
1k⍀
R1
200k⍀
IN+
IN–
R19 1k⍀
A1
OUT
A2
C2
5pF
R2
200k⍀
R17
95k⍀
R3
41k⍀
R4
R5
2.6k⍀
R8
9k⍀
R15
10k⍀
R9
10k⍀
41k⍀
R6
250k⍀
R14
20k⍀
R11
2k⍀
R7
250⍀
R16
10k⍀
GND
OFS
R10
2k⍀
R13
20k⍀
Figure 16. Simplified Schematic of AD22050, Including Component Values
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic SOIC Package
(SO-8)
Plastic Mini-DIP Package
(N-8)
0.430 (10.92)
0.348 (8.84)
0.1968 (5.00)
0.1890 (4.80)
8
5
8
1
5
4
0.280 (7.11)
0.240 (6.10)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
4
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
؋
45؇ 0.0098 (0.25)
0.0040 (0.10)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
8؇
0؇
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
–8–
REV. C
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