AD261AND-5 [ADI]

High Speed, Logic Isolator; 高速逻辑隔离器


型号：	AD261AND-5
厂家：	ADI
描述：	High Speed, Logic Isolator 高速逻辑隔离器
文件：	总6页 (文件大小：186K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

High Speed, Logic Isolator

AD261

FEATURES

FUNCTIO NAL BLO CK D IAGRAM

Isolation Test Voltage: To 3.5 kV rm s

Five Isolated Logic Lines: Available in Six I/ O Configurations

Logic Signal Bandw idth: 20 MHz (m in)

CMV Transient Im m unity: 10 kV/ ␮s m in

Waveform Edge Transm ission Sym m etry: ؎1 ns

Field and System Output Enable/ Three-State Functions

Perform ance Rated Over –25؇C to +85؇C

UL1950, IEC950, EN60950 Certification (VDE, CE, Pending)

LATCH

THREE-

LINE 0

LINE 1

LINE 2

LINE 3

LINE 4

STATE

LATCH

THREE-

STATE

LATCH

THREE-

STATE

APPLICATIONS

LATCH

PLC/ DCS Analog Input and Output Cards

Com m unications Bus Isolation

General Data Acquisition Applications

IGBT Motor Drive Controls

THREE-

STATE

LATCH

THREE-

STATE

High Speed Digital I/ O Ports

ENABLE

+5V dc

ENABLE

+5V dc

SYS

FLD

+5V dc

GENERAL D ESCRIP TIO N

FLD

SYS

T he AD261 is designed to isolate five digital control signals

to/from a microcontroller and its related field I/O components.

Six models allow all I/O combinations from five input lines to

five output lines, including combinations in between. Every

AD261 effectively replaces up to five opto-isolators.

5Vdc RTN

5V RTN

SYS

FLD

FIELD

SYSTEM

TYPICAL MODEL

(AD261-2)

Each line of the AD261 has a bandwidth of 20 MHz (min) with

a propagation delay of only 14 ns, which allows for extremely

fast data transmission. Output waveform symmetry is maintained

to within ±1 ns of the input so the AD261 can be used to accu-

rately isolate time-based PWM signals.

P RO D UCT H IGH LIGH TS

Six Isolated Logic Line I/O Configurations Available: T he

AD261 is available in six pin-compatible versions of I/O con-

figurations to meet a wide variety of requirements.

All field or system output pins of the AD261 can be set to a high

resistance three-state level by use of the two enable pins. A field

output three-stated offers a convenient method of presetting

logic levels at power-up by use of pull-up/down resistors. Sys-

tem side outputs being three-stated allows for easy multiplexing

of multiple AD261s.

Wide Bandwidth with Minim al Edge Error: The AD261

affords extremely fast isolation of logic signals due to its 20 MHz

bandwidth and 14 ns propagation delay. It maintains a wave-

form input-to-output edge transition error of typically less than

±1 ns (total) for positive vs. negative transition.

3.5 k V r m s Test Volta ge Isola tion Ra tin g: T he AD261

B Grade is rated to operate at 1.25 kV rms and is 100% pro-

duction tested at 3.5 kV rms, using a standard ADI test method.

T he isolation barrier of the AD261 B Grade is 100% tested

as high as 3.5 kV rms (system to field). T he barrier design also

provides excellent common-mode transient immunity from

10 kV/µs common-mode voltage excursions of field side termi-

nals relative to the system side, with no false output triggering

on either side.

High Tr a nsient Im m unity: T he AD261 rejects common-

mode transients slewing at up to 10 kV/µs without false trigger-

ing or damage to the device.

Each output is updated within nanoseconds by input logic tran-

sitions, the AD261 also has a continuous output update feature

that automatically updates each output based on the dc level of

the input. T his guarantees the output is always valid 10 µs after

a fault condition or after the power-up reset interval.

(Continued on page 5)

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

Fax: 781/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

(Typical at T = +25؇C, +5 V dc , +5 V dc , t = 50 ns max unless otherwise noted)

AD261–SPECIFICATIONS

SYS

FLD RR

P aram eter

Conditions

Min

Typ

Max

Units

INPUT CHARACT ERIST ICS

T hreshold Voltage

Positive T ransition (V_{T +}

)

+5 V dc_SYS= 4.5 V

+5 V dc_SYS= 5.5 V

+5 V dc_SYS= 4.5 V

+5 V dc_SYS= 5.5 V

+5 V dc_SYS= 4.5 V

+5 V dc_SYS= 5.5 V

2.0

3.0

0.9

1.2

0.4

0.5

2.7

3.2

1.8

2.2

0.9

1.0

3.15

4.2

2.2

3.0

1.4

1.5

µA

Negative T ransition (V_{T –}

Hysteresis Voltage (V_H)

)

Input Capacitance (C_IN

Input Bias Current (I_IN

)

Per Input

0.5

OUT PUT CHARACT ERIST ICS

Output Voltage¹

High Level (V_OH

)

+5 V dc_SYS= 4.5 V, | I_O| = 0.02 mA

+5 V dc_SYS= 4.5 V, | I_O| = 4 mA

+5 V dc_SYS= 4.5 V, | I_O| = 0.02 mA

+5 V dc_SYS= 4.5 V, | I_O| = 4 mA

4.4

3.7

Low Level (V_OL

)

0.1

0.4

Output T hree-State Leakage Current

ENABLE_SYS/FLD@ Logic Low/High Level Respectively

0.5

µA

DYNAMIC RESPONSE ¹(Refer to Figure 2)

Max Logic Signal Frequency (f_MIN

Waveform Edge Symmetry Error (t_ERROR

Logic Edge Propagation Delay (t_PHL, t_PLH

Minimum Pulsewidth (t_PWMIN

)

50% Duty Cycle, +5 V dc_SYS= 5 V

t_PHLvs. t_PLH

MHz

)

±1

)

Max Output Update Delay on Fault or After

Power-Up Reset Interval (≈ 30 µs)²

µs

ISOLAT ION BARRIER RAT ING³

Operating Isolation Voltage (V_CMV

)

AD261A

AD261B

AD261A

AD261B

375

1250

V rms

V/µs

Isolation Rating T est Voltage (V_{CMV TEST}

)

1750

3500

10,000

Transient Immunity (V_TRANSIENT

)

Isolation Mode Capacitance (C_ISO

Capacitive Leakage Current (I_LEAD

)

Total Capacitance, All Lines

240 V rms @ 60 Hz

µA rms

POWER SUPPLY

Supply Voltage (+5 V dc_SYSand +5 V dc_FLD

Power Dissipation Capacitance

)

Rated Performance

Operating

Effective, per Input, Either Side

Effective per Output, Either Side—No Load

Each, +5 V dc_{SYS & FLD}

4.5

4.0

5.5

5.75

V dc

Quiescent Supply Current

Supply Current

All Lines @ 10 MHz (Sum of +5 V dc_{SYS & FLD}

)

TEMPERATURE RANGE

Rated Performance (T_A)⁵

–25

–40

+85

°C

Storage (T_STG

)

NOT ES

¹For best performance, bypass +5 V dc supplies to com., at or near the device (0.01 µF). +5 V dc supplies are also internally bypassed with 0.05 µF.

²As the supply voltage is applied to either side of the AD261, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 30 µs after the point

where +5 V dc_{SYS & FLD}passes above 3.3 V.

³“Operating” isolation voltage is derived from the Isolation T est Voltage in accordance with such methods as found in VDE-0883 wherein a device will be “hi-pot”

tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 80 pC of discharge may be considered the

same as a hi-pot test (but nondestructive).

⁴Partial Discharge at 80 pC T HLD.

⁵Supply Current will increase slightly, but otherwise the unit will function within specification to –40°C.

Specifications are subject to change without notice.

REV. 0

–2–

AD261

ABSO LUTE MAXIMUM RATINGS*

P aram eter

Conditions

Min Typ Max Units

Supply Voltage (+5 V dc_{SYS & FLD}

DC Input Voltage (V_{IN MAX}

DC Output Voltage (V_{OUT MAX}

Clamp Diode Input Current (I_IK

Clamp Diode Output Current (I_OK

Output DC Current, per Pin (I_OUT

)

–0.5

+6.0

+0.5

+25

+50

+85

°C

)

Referred to +5 V dc_{SYS & FLD}and 5 V RTN_{SYS & FLD}Respectively –0.5

Referred to +5 V RTN_{SYS & FLD}and 5 V dc_{SYS & FLD}Respectively –0.5

)

For V_I< –0.5 V or V_I> 5 V RT N_{SYS & FLD}+0.5 V

For V_O< –0.5 V or V_O> 5 V RT N_{SYS & FLD}+0.5 V

–25

–50

–40

)

DC Current, V_CCor GND (I_CCor I_GND

Storage T emperature (T_{ST G}

Lead T emperature (Soldering, 10 sec)

Electrostatic Protection (V_ESD

)

+300 °C

)

Per MIL-ST D-883, Method 3015

4.5

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. T his is a stress rating only; functional operation of the device

at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended

periods may effect device reliability.

I/O CO NFIGURATIO NS AVAILABLE

P IN CO NFIGURATIO N

T he AD261 is available in several configurations. T he choice of

model is determined by the desired number of input vs. output

lines. All models have identical footprints with the power and

enable pins always being in the same locations.

ENABLE

+5V dc

5V RTN

SYSTEM

SYS

P IN FUNCTIO N D ESCRIP TIO NS

SYS

P in

Mnem onic

Function

1–5*

S0 T hrough S4 Digital Xmt or Rcv from F0 T hrough F4

ENABLE_SYS

+5 V dc_SYS

5 V RT N_SYS

System Output Enable/T hree-State

System Power Supply (+5 V dc Input)

System Power Supply Common

Not Present On Unit

BOTTOM VIEW

9–14

5 V RT N_FLD

+5 V dc_FLD

ENABLE_FLD

Field Power Supply Common

Field Power Supply (+5 V Input)

Field Output Enable/T hree-State

5V RTN

+5V dc

ENABLE

FLD

FIELD

18–22* F0 T hrough F4 Digital Xmt or Rcv from S0 T hrough S4

*Function of pin determined by model. Refer to T able I.

O RD ERING GUID E

Model

Num ber

Isolation

Ratings

P ackage

D escription

P ackage

O ption

D escription

AD261AND-0

AD261AND-1

AD261AND-2

AD261AND-3

AD261AND-4

AD261AND-5

0 Inputs, 5 Outputs

1 Input, 4 Outputs

2 Inputs, 3 Outputs

3 Inputs, 2 Outputs

4 Inputs, 1 Output

5 Inputs, 0 Outputs

1.75 kV rms

Plastic DIP

ND-22A

AD261BND-0

AD261BND-1

AD261BND-2

AD261BND-3

AD261BND-4

AD261BND-5

0 Inputs, 5 Outputs

1 Input, 4 Outputs

2 Inputs, 3 Outputs

3 Inputs, 2 Outputs

4 Inputs, 1 Output

5 Inputs, 0 Outputs

3.5 kV rms

Plastic DIP

ND-22A

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD261 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–3–

AD261

AD 261 CO NFIGURATIO NS

AD261-0

AD261-2

LATCH

LINE 0

LINE 1

LINE 0

LINE 1

LINE 2

LATCH

LINE 2

LINE 3

LINE 4

LATCH

LINE 3

LINE 4

LATCH

ENABLE

FLD

ENABLE

+5V dc

ENABLE

+5V dc

ENABLE

+5V dc

SYS

FLD

+5V dc

FLD

SYS

5V dc RTN

5V RTN

FLD

5V RTN

SYS

5V RTN

SYS

FLD

FIELD

SYSTEM

AD261-3

AD261-1

LATCH

THREE-

STATE

LINE 0

LINE 1

LINE 0

LINE 1

LINE 2

LINE 3

LINE 4

LATCH

THREE-

STATE

LATCH

LINE 2

LINE 3

LINE 4

THREE-

STATE

LATCH

THREE-

STATE

LATCH

THREE-

STATE

ENABLE

+5V dc

ENABLE

FLD

SYS

ENABLE

+5V dc

FLD

SYS

+5V dc

5V RTN

+5V dc

FLD

SYS

5V dc RTN

5V RTN

FLD

5V RTN

SYS

FLD

SYS

FIELD

SYSTEM

FIELD

SYSTEM

REV. 0

–4–

AD261

AD 261 CO NFIGURATIO NS

AD261-4

AD261-5

LATCH

LINE 0

LINE 1

LINE 0

LINE 1

LATCH

LINE 2

LINE 3

LINE 4

LINE 2

LINE 3

LINE 4

LATCH

ENABLE

+5V dc

ENABLE

+5V dc

ENABLE

+5V dc

SYS

FLD

+5V dc

5V RTN

FLD

SYS

5V dc RTN

5V RTN

SYS

FLD

SYS

FLD

FIELD

SYSTEM

(Continued from page 1)

GENERAL ATTRIBUTES

T he AD261 provides five HCMOS compatible isolated logic

lines with ≥ 10 kV/µs common-mode transient immunity.

Field a nd System Ena ble Functions: Both the isolated and

nonisolated sides of the AD261 have ENABLE pins that three-

state all outputs. Upon reenabling these pins, all outputs are

updated to reflect the current input logic level.

T he case design and pin arrangement provides greater than

18 mm spacing between field and system side conductors, pro-

viding CSA/IS and IEC creepage spacing consistent with 750 V

mains isolation.

CE Cer tifia ble: Simply by adding the external bypass capacitors

at the supply pins, the AD261 can attain CE certification in

most applications (to the EMC directive) and conformance to

the low voltage (safety) directive is assured by the EN60950

certification.

T he five unidirectional logic lines have six possible combina-

tions of “ins” and “outs,” or transmitter/receiver pairs; hence

there are six AD261 part configurations (see T able I).

Each 20 MHz logic line has a Schmidt trigger input and a three-

state output (on the other side of the isolation barrier) and 14 ns of

propagation delay. A single enable pin on either side of the

barrier causes all outputs on that side to go three-state and all

inputs (driven pins) to ignore their inputs and retain their last

known state.

Table I. Model Num ber and P inout Function

P in AD 261-0

AD 261-1 AD 261-2 AD 261-3 AD 261-4 AD 261-5

S0 (Xmt)

S1 (Xmt)

S2 (Xmt)

S3 (Xmt)

S4 (Xmt)

ENABLE_SYS

+5 V dc_SYS

5 V RT N_SYS

S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Xmt) S0 (Rcv)

S1 (Xmt) S1 (Xmt) S1 (Xmt) S1 (Rcv) S1 (Rcv)

S2 (Xmt) S2 (Xmt) S2 (Rcv) S2 (Rcv) S2 (Rcv)

S3 (Xmt) S3 (Rcv) S3 (Rcv) S3 (Rcv) S3 (Rcv)

S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv) S4 (Rcv)

Note: All unused logic inputs (1–5) should be tied either high or low,

but not left floating.

Edge “fidelity,” or the difference in propagation time for rising

and falling edges, is typically less than ±1 ns.

Power consumption, unlike opto-isolators, is a function of operat-

ing frequency. Each logic line barrier driver requires about 160 µA

per MHz and each receiver 40 µA per MHz plus, of course, 4 mA

total idle current (each side). T he supply current diminishes

slightly with increasing temperature (about –0.03%/°C).

9–14

Not Present

5 V RTN_FLD

+5 V dc_FLD

ENABLE_FLD

F0 (Rcv)

F1 (Rcv)

F2 (Rcv)

F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Rcv) F0 (Xmt)

F1 (Rcv) F1 (Rcv) F1 (Rcv) F1 (Xmt) F1 (Xmt)

F2 (Rcv) F2 (Rcv) F2 (Xmt) F2 (Xmt) F2 (Xmt)

F3 (Rcv) F3 (Xmt) F3 (Xmt) F3 (Xmt) F3 (Xmt)

F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt) F4 (Xmt)

T he total capacitance spanning the isolation barrier is less than

10 pF.

F3 (Rcv)

F4 (Rcv)

T he minimum period of a pulse that can be accurately coupled

across the barrier is about 25 ns. T herefore the maximum

square-wave frequency of operation is 20 MHz.

*Pin function is the same on all models, as shown in the AD261-0 column.

REV. 0

–5–

AD261

SCHMITT

TRIGGER

BUFFER

3.5kV

ISOLATION

BARRIER

Logic information is sent across the barrier as “set-hi/set-lo”

data that is derived from logic level transitions of the input. At

power-up or after a fault condition, an output might not repre-

sent the state of the respective channel input to the isolator. An

internal circuit operates in the background which interrogates

all inputs about every 5 µs and in the absence of logic transi-

tions, sends appropriate “set-hi” or “set-lo” data across the

barrier.

DATA

RECEIVER BUFFER

OUTPUT

DRIVER

OUT

DATA IN

ENABLE

D Q

ENABLE

CONTINUOUS

UPDATE CIRCUIT

GATED

TRANSPARENT

LATCH

Figure 1. Sim plified Block Diagram

Recovery time from a fault condition or at power-up is thus

between 5 µs and 10 µs.

POSITIVE GOING

INPUT THRESHOLD

HYSTERESIS

NEGATIVE GOING

INPUT

INPUT THRESHOLD

63%

OUTPUT

37%

t_ff

PROPAGATION DELAY

t_PD= 14ns

DELAY LINE

14ns

BUFFER

EFFECTIVE

CIRCUIT

MODEL

100⍀

5pF

INPUT

5pF

OUTPUT

CAPACITANCE

t_rr

= t_ff= 100⍀ x C

TOTAL OUTPUT CAPACITANCE

0.5ns – NO LOAD

= 5.5ns INTO 50pF

TOTAL DELAY = t_PDt_rr= 13ns (NO LOAD), 18ns (50pF LOAD)

Figure 2. Typical Tim ing and Delay Models

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

22-P in P lastic D IP

(ND -22A)

0.550 (13.97)

1.500 (38.1) MAX

MAX

0.440

(11.18)

MAX

END VIEW

SIDE VIEW

0.100

(2.54)

0.350

(8.89)

0.050 (1.27)

PIN 1

0.160 (4.06)

0.140 (3.56)

0.020

0.010

(0.508

0.254)

16 PLACES

0.075 (1.91)

BOTTOM

VIEW

SYSTEM

0.250

(6.35)

0.738* (18.75)

FIELD

0.050

(1.27)

0.650 (16.51)

*CREEPAGE PATH (SUBTRACT APPROXIMATELY

0.079 (2mm) FOR SOLDER PAD RADII ON PC BOARD.

THIS SPACING SUPPORTS THE INTRINSICALLY SAFE

RATING OF 750V.

–6–

REV. 0

AD261AND-5 [ADI]

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