AD2S44UM10B [ADI]

IC SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, MDIP32, 1.750 X 1.050 INCH, 0.225 INCH HEIGHT, DIP-32, Position Converter;


型号：	AD2S44UM10B
厂家：	ADI
描述：	IC SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, MDIP32, 1.750 X 1.050 INCH, 0.225 INCH HEIGHT, DIP-32, Position Converter 输入元件转换器
文件：	总12页 (文件大小：301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Low Cost, 14-Bit, Dual Channel

Synchro/Resolver-to-Digital Converter

Data Sheet

AD2S44

The core of each conversion is performed by state-of-the-art mono-

lithic, integrated circuits manufactured by the Analog Devices, Inc.,

proprietary BiMOS II process, which combines the advantages of

low power CMOS digital logic with bipolar linear circuits. The

use of these ICs keeps the internal component count low and

ensures high reliability.

FEATURES

Low per-channel cost

32-lead DIL hybrid package

2.6 arc minute accuracy

14-bit resolution

Built-in test

Independent reference inputs

High tracking rate

BIT

The built-in test (

) facility can be used in failsafe systems to

provide an indication of whether the converter is tracking

accurately.

APPLICATIONS

Gimbal/gyro control systems

Robotics

Engine controllers

Coordinate conversion

Military servo control systems

Fire control systems

Avionic systems

Each channel incorporates a high accuracy differential condi-

tioning circuit for signal inputs providing more than 74 dB of

common-mode rejection. Options are available for both synchro

and resolver format inputs. The converter output is via a three-state

transparent latch allowing data to be read without interruption

of the converter operation. The A/ and

control lines select

the channel and present the digital position to the common

data outputs.

Antenna monitoring

CNC machine tooling

The AD2S44 also features independent reference inputs where

different reference frequencies can be used for each channel.

GENERAL DESCRIPTION

The AD2S44 is a 14-bit dual channel, continuous tracking synchro/

resolver-to-digital converter. It has been designed specifically

for applications where space, weight, and cost are at a premium.

Each 32-lead hybrid device contains two independent Type II servo

loop tracking converters. The ratiometric conversion technique

employed provides excellent noise immunity and tolerance of

long lead lengths.

All components are 100% tested at −55°C, +25°C, and +125°C.

Devices are processed to high reliability screening standards

and receive further levels of testing and screening to ensure

high levels of reliability.

FUNCTIONAL BLOCK DIAGRAM

(A)

REFERENCE

CONDITIONER

S1 (A)

S2 (A)

HIGH

SPEED

SIN/COS

MULTIPLIER

PHASE-

SENSITIVE

DETECTOR

GND

SYNCHRO/

RESOLVER

CONDITIONER

UP-DOWN

COUNTER

ERROR

AMP

INTEGRATOR

VCO

–V

S3 (A)

S4 (A)

BIT

BUILT-IN

TEST

DETECTION

A/B

THREE-

STATE

AD2S44

DB1 (MSB)

OUTPUT

LATCHES

DB14 (LSB)

S1 (B)

S2 (B)

HIGH

SPEED

SIN/COS

MULTIPLIER

SYNCHRO/

RESOLVER

CONDITIONER

PHASE-

SENSITIVE

DETECTOR

UP-DOWN

COUNTER

ERROR

AMP

VCO

INTEGRATOR

S3 (B)

S4 (B)

(B)

REFERENCE

CONDITIONER

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD2S44

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Output Enable ( )......................................................................8

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Table of Contents.............................................................................. 2

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Theory of Operation ........................................................................ 7

Connecting the Converter........................................................... 7

BIT

Built-In Test (

).........................................................................8

Scaling for Nonstandard Signals .................................................9

Dynamic Performance..................................................................9

Acceleration Error.........................................................................9

Reliability..................................................................................... 10

Processing for High Reliability (B Suffix)............................... 10

Other Products ........................................................................... 10

Outline Dimensions....................................................................... 11

Ordering Guide .......................................................................... 11

Ordering Information................................................................ 11

Channel Select (A/ ) ................................................................... 7

REVISION HISTORY

Changes to Processing for High Reliability Section and

10/11—Rev. A to Rev. B

Other Products Section ................................................................. 10

Updated Outline Dimensions....................................................... 11

Changes to Ordering Guide.......................................................... 11

Changes to Ordering Information ............................................... 11

Changes to Figure 1.......................................................................... 1

Changes to Figure 3.......................................................................... 7

08/08—Rev. 0 to Rev. A

Updated Format................................................................ Universal

Changes to Specifications Section.................................................. 3

Changes to Absolute Maximum Ratings Section......................... 5

Deleted Standard Processing Section............................................. 7

10/89—Revision 0: Initial Version

Rev. B | Page 2 of 12

Data Sheet

AD2S44

SPECIFICATIONS

V_S= 15 V at T_A= 25°C, unless otherwise noted.

Table 1.

Parameter

PERFORMANCE

Accuracy¹

Min Typ

Max

Unit

Test Conditions/Comments

AD2S44-UMB²

−4.0

−2.6

−4.0

+4.0

+2.6

+4.0

Arc minutes

Rev/sec

Bits

−55°C to +125°C

−25°C to +85°C

−55°C to +125°C

AD2S44-TMB²

Tracking Rate

Resolution (1 LSB = 1.3 Arc Minutes)

Repeatability

Signal/Reference Frequency

Bandwidth

Output coding parallel natural binary

LSB

400

100

2600 Hz

SIGNAL INPUTS

Signal Voltage

Input Impedance

90 V Signal

11.8 or 90

V rms

See the Ordering Information section

Resistive tolerance 2%

200

kΩ

11.8 V Signal

Common-Mode Rejection

Common-Mode Range

90 V Signal

250

V dc

11.8 V Signal

REFERENCE INPUTS

Reference Voltage

Input Impedance

115 V

26 or 115

V rms

See the Ordering Information section

Resistive tolerance 5%

270

kΩ

26 V

Common-Mode Range

115 V

26 V

210

V dc

sec^–2

ACCELERATION CONSTANT

STEP RESPONSE

Large Step^{1, 2}

62,000

179° to 1 LSB of error

2° to 1 LSB of error

Small Step^{1, 2}

POWER LINES

+V_S= +15 V^{1, 2}

–V_S= −15 V^{1, 2}

Power Dissipation

DIGITAL INPUTS

1.7

1.9

Quiescent condition

V_IL

V_IH

A/B

0.7

0.4

V dc

I_IL= 5 µA

I_IH= 5 µA

2.0

2.4

V_IL

V_IH

V dc

I_IL= 1.2 mA

I_IH= –60 µA

DIGITAL OUTPUTS (DB1 to DB14)

1, 2

V_OL

V dc

µA

I_IL= 1.2 mA

I_OH= 60 µA

1, 2

V_OH

Three-State Leakage Current

Drive Capability

LSTTL loads

Rev. B | Page 3 of 12

AD2S44

Data Sheet

Parameter

Min Typ

Max

640

200

Unit

Test Conditions/Comments

DATA TRANSFER

Time to Data Stable (After Negative Edge of OE

or Change of Level of A/B)

See Figure 6

t_S

Time to Data in High Impedance State

(After Positive Edge of OE)

t_R

t_P

Time for Repetitive Strobing of Selected Channel 200

BUILT-IN TEST OUTPUT (BIT)

Sense

V_OL

Active low

Low = error condition

I_OL= 3.2 mA

0.4

V dc

V_OH

2.4

V dc

LSTTL loads

LSB

I_OH= −160 µA

Drive Capability

Error Condition Set

Error Condition Cleared

LSB

¹Specified overtemperature range, −55°C to +125°C, and for: (a) 10% signal and reference amplitude variation; (b) 10% signal and reference harmonic distortion; (c)

5% power supply variation; and (d) 10% variation in reference frequency.

²These parameters are 100% tested at nominal values of power supplies, input signal voltages, and operating frequency. All other parameters are guaranteed by

design, not tested.

Rev. B | Page 4 of 12

Data Sheet

AD2S44

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

+V_Sto GND

+17.25 V dc

–V_Sto GND

−17.25 V dc

Any Logic Input to GND

Maximum Junction Temperature

S1, S2, S3, S4 Pins (Line-to-Line)¹

90 V Option

+6.0 V dc (maximum)

−0.4 V dc (minimum)

150°C

ESD CAUTION

600 V dc

80 V dc

11.8 V Option

S1, S2, S3, S4 Pins to GND

90 V Option

11.8 V Option

600 V dc

80 V dc

R_HIPins to R_LOPins

26 V, 115 V Options

R_HIPins to R_LOPins to GND

26 V, 115 V Options

Storage Temperature Range

Operating Temperature Range

600 V dc

−65°C to +150°C

−55°C to +125°C

¹On synchro input options, line-to-line voltage refers to the differential voltages

of S2 (A)/S2 (B) to S1 (A)/S1 (B), S1 (A)/S1 (B) to S3 (A)/S3 (B), and S3 (A)/S3 (B)

to S2 (A)/S2 (B). On resolver input options, line-to-line levels refer to the S1 (A)/

S1 (B) to S3 (A)/S3 (B) and S2 (A)/S2 (B) to S4 (A)/S4 (B) voltages.

Rev. B | Page 5 of 12

AD2S44

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DB8

DB9

DB7

DB6

DB10

DB5

DB11

DB4

DB12

DB3

DB13

DB2

DB14 (LSB)

DB1 (MSB)

AD2S44

TOP VIEW

(Not to Scale)

–V

A/B

BIT

GND

(A)

(B)

S4 (A)

S3 (A)

S4 (B)

S3 (B)

S2 (A) 15

18 S2 (B)

S1 (A)

S1 (B)

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

1 to 7

Mnemonic

Description

DB8 to DB14 (LSB)

Parallel Output Data Bits.

Output Enable Input.

A/B

Channel A or Channel B Select Input.

Built-In Test Error Output.

BIT

13 to 16

17 to 20

R_LO(A)

R_HI(A)

S4 (A) to S1 (A)

S1 (B) to S4 (B)

R_HI(B)

R_LO(B)

GND

–V_S

Input Pin for Channel A Reference Low.

Input Pin for Channel A Reference High.

Channel A Input Signal.

Channel B Input Signal.

Input Pin for Channel B Reference High.

Input Pin for Channel B Reference Low.

Power Supply Ground. This pin is electrically connected to the case.

Negative Power Supply.

+V_S

Positive Power Supply.

26 to 32

DB1 (MSB) to DB7

Parallel Output Data Bits.

Rev. B | Page 6 of 12

Data Sheet

AD2S44

THEORY OF OPERATION

The AD2S44 operates on a tracking principle. The output digital

word continually tracks the position of the synchro/resolver

shaft without the need for external convert commands and

status wait loops. As the transducer moves through a position

equivalent to the least significant bit weighting, the output

digital word is updated.

A phase sensitive detector, integrator, and voltage-controlled

oscillator (VCO) form a closed-loop system that seeks to null sin

(θ − ϕ). When this is accomplished, the word state of the up-down

counter (ϕ) equals the synchro/resolver shaft angle (θ), to within

the rated accuracy of the converter.

CONNECTING THE CONVERTER

Each channel is identical in operation, sharing power supply

and output pins. Both channels operate continuously and

independently of each other. The digital output from either

channel is available after switching the channel select and

output enable inputs.

The power supply voltages connected to −V_Sand +V_Sare to be

15 V and cannot be reversed.

It is suggested that a parallel combination of a ceramic 100 nF

capacitor and a tantalum 6.8 µF capacitor be placed from each

of the supply pins to GND.

If the device is a synchro-to-digital converter, the 3-wire synchro

output is connected to the S1, S2, and S3 pins on the unit, and

a solid-state Scott T input conditioner converts these signals into

resolver format given by

The pin marked GND is connected electrically to the case and

is to be taken to 0 V potential in the system.

The digital output is taken from Pin 26 to Pin 32 and from Pin 1

to Pin 7. Pin 26 is the MSB, and Pin 7 is the LSB.

V₁= K E₀sin ωt sin θ

V₂= K E₀sin ωt cos θ

The reference connections are made to the R_HIpins and the R_LO

pins. In the case of a synchro, the signals are connected to the

S1, S2, and S3 pins, according to the following convention:

where:

θ is the angle of the synchro shaft.

E₀sin ωt is the reference signal.

K is the transformation ratio of the input signal conditioner.

_S1−S3= E_RLO−RHIsin ωt sin θ

_S3−S2= E_RLO−RHIsin ωt sin (θ − 120°)

_S2−S1= E_RLO−RHIsin ωt sin (θ – 240°)

If the unit is a resolver-to-digital converter, the 4-wire resolver

output is connected directly to the S1, S2, S3, and S4 pins on

the unit.

For a resolver, the signals are connected to the S1, S2, S3, and S4

pins, according to the following convention:

To understand the conversion process, assume that the current

word state of the up-down counter is ϕ. V₁is multiplied by cos ϕ,

and V₂is multiplied by sin ϕ to give the following:

_S1−S3= E_RLO−RHIsin ωt sin θ

_S2−S4= E_RLO−RHIsin ωt cos θ

CHANNEL SELECT (A/B)

K E₀sin ωt sin θ cos ϕ

K E₀sin ωt cos θ sin ϕ

A/ is the channel select input. A Logic 1 selects Channel A, and

a Logic 0 selects Channel B. Data becomes valid 640 ns after A/

is toggled. Timing information is shown in Figure 4 and Figure 5.

These signals are subtracted by the error amplifier to give

K E₀sin ωt (sin θ cos ϕ − cos θ sin ϕ)

K E₀sin ωt sin (θ − ϕ)

_HI(A)

REFERENCE

CONDITIONER

R_LO(A)

+V_S

V₁

S1 (A)

S2 (A)

HIGH

SPEED

SIN/COS

MULTIPLIER

PHASE-

SENSITIVE

DETECTOR

GND

SYNCHRO/

RESOLVER

CONDITIONER

UP-DOWN

COUNTER

ERROR

AMP

INTEGRATOR

VCO

–V_S

BIT

S3 (A)

S4 (A)

V₂

BUILT-IN

TEST

DETECTION

A/B

THREE-

STATE

OUTPUT

LATCHES

AD2S44

DB1 (MSB)

DB14 (LSB)

S1 (B)

S2 (B)

HIGH

SYNCHRO/

RESOLVER

CONDITIONER

PHASE-

SENSITIVE

DETECTOR

SPEED

SIN/COS

UP-DOWN

COUNTER

ERROR

AMP

VCO

INTEGRATOR

S3 (B)

S4 (B)

MULTIPLIER

_HI(B)

REFERENCE

CONDITIONER

R_LO(B)

Figure 3. Functional Block Diagram

Rev. B | Page 7 of 12

AD2S44

Data Sheet

OUTPUT ENABLE (OE)

BUILT-IN TEST (BIT)

is the output enable input; the signal is active low. When set

BIT

The

is the built-in test error output, which provides an over-

to Logic 1, DB1 to DB14 are in high impedance state. When

is set to Logic 0, DB1 to DB14 represent the angle of the transducer

shaft to within the stated accuracy of the converter (see bit weights

in Table 4). Data becomes valid 640 ns after the

Timing information is shown in Figure 4 and Figure 5 and

detailed in Table 1.

velocity or fault indication signal for the channel selected via A/ .

The error voltage of each channel is continuously monitored. When

the error exceeds 50 bits for the currently selected channel, the

is switched.

BIT

output goes low, indicating that an error greater than approx-

imately one angular degree exists, and the data is, therefore, invalid.

BIT

The

set the

BIT

signal has a built-in hysteresis; that is, the error required to

is greater than the error required for it to be cleared.

is set when the error exceeds 55 LSBs and is cleared when

BIT

Table 4. Bit Weight

Bit No.

1 (MSB)

The

Weight (Degrees)

180.0000

90.0000

45.0000

22.5000

11.2500

5.6250

the error goes below 45 LSBs. This mode of operation guarantees

BIT

that the

BIT

does not flicker when the error threshold is crossed.

is valid for the selected channel approximately 50 ns after

The

the change in the state of A/ . In most instances, the error condi-

BIT

tion that sets the

must persist for at least one period of the

BIT

reference signal prior to the

responding to the condition.

2.8125

1.4063

0.7031

0.3516

0.1758

BIT

Table 5.

Condition

Power-Up Transient The BIT returns to a logic high state after

Output Faults

Description

Response

the AD2S44 position output synchronizes

with the angle input to within 1°.

0.0879

Normally, the BIT is low at power-up for

a period less than or equal to the large

signal step response settling time of the

AD2S44 after the V_Ssupplies have

14 ( LSB)

0.0439

0.0220

stabilized to within 5% of their final values.

Step Input > 1°

The BIT returns to a logic high state after

the selected channel of the AD2S44 has

settled to within 1° of the input angle

resulting from an instantaneous step.

A/B

Excessive Velocity

Signal Failure

The BIT is driven to a logic low if the

maximum tracking rate of the AD2S44 is

exceeded (20 rps typical).

t_S

t_R

The BIT may be driven to a logic low state if

all signal voltages to the selected channel

are lost.

DATA

BITS

(1 TO 14)

CHANNEL B

VALID*

CHANNEL A

VALID*

Converter/System

Failure

Any failure that causes the AD2S44 to fail

to track the input synchro/resolver angles

drives the BIT to a logic low. This may

include, but is not limited to, acceleration

conditions, poor supply voltage regulation,

or excessive noise on the signal connections.

*CONVERTER DATA OUTPUT IS INHIBITED FROM UPDATES

DURING CHANNEL VALID.

Figure 4. Repetitive Reading of One Channel

t_P

A/B

t_R

t_S

DATA

BITS

(1 TO 14)

DATA

VALID*

DATA

VALID*

*CONVERTER DATA OUTPUT IS INHIBITED FROM UPDATES

DURING CHANNEL VALID.

Figure 5. Alternative Reading of Each Channel

Rev. B | Page 8 of 12

Data Sheet

AD2S44

The gain and phase diagrams are shown in Figure 7 and Figure 8.

SCALING FOR NONSTANDARD SIGNALS

A feature of these converters is that the signal and reference inputs

can be resistively scaled to accommodate nonstandard input signal

and reference voltages that are outside the nominal 10% limits of

the converter. Using this technique, it is possible to use a standard

converter with a personality card in systems where a wide range

of input and reference voltages are encountered.

–3

–6

–9

The accuracy of the converter is affected by the matching accu-

racies of resistors used for external scaling. For resolver format

options, it is critical that the value of the resistors on the S1 (A)/

S1 (B) to S3 (A)/S3 (B) signal input pair be precisely matched to

the S4 (A)/S4 (B) to S2 (A)/S2 (B) input pair. For synchro options,

the three resistors on the S1, S2, and S3 pins must be matched. In

general, a 0.1% mismatch between resistor values contributes an

additional 1.7 arc minutes of error to the conversion. In addition,

imbalances in resistor values can greatly reduce the common-

mode rejection ratio of the signal inputs.

–12

–15

100

FREQUENCY (Hz)

Figure 7. Gain Plot

180

135

To calculate the values of the external scaling resistors, add

2.222 kΩ for each volt of signal in series with the S1, S2, S3, and

S4 pins (no resistor is required on the S4 pins for synchro options)

and add 3 kΩ extra per volt of reference in series with the R_LO

pins and the R_HIpins.

–45

–90

DYNAMIC PERFORMANCE

1 + sT

OUT

–135

–180

Figure 6. Transfer Function of AD2S44

100

The transfer function of the converter is as follows:

Open-loop transfer function

FREQUENCY (Hz)

Figure 8. Phase Plot

1 + sT

θ_OUT

θ_IN

ACCELERATION ERROR

K_a

s²1 + sT₂

A tracking converter employing a Type II servo loop does not

suffer any velocity lag. However, there is an additional error

due to acceleration. This error is defined using the acceleration

constant (K_a) of the converter

Closed-loop transfer function

1 + sT

θ_OUT

θ_IN

1 + sT + s²K_a+ s³T₂K_a

K_a= Input Acceleration/Error in Output Angle

The numerator and denominator must have consistent angular

units. For example, if K_ais expressed in sec^–2, the input accelera-

tion is to be specified in degrees/sec²and the output angle error is

to be specified in degrees. Alternatively, the angular unit of measure

can also be in units such as radians, arc minutes, or LSBs.

where:

K_a= 62000 sec^–2.

T₁= 0.0061 sec.

T₂= 0.001 sec.

Rev. B | Page 9 of 12

AD2S44

Data Sheet

K_adoes not define maximum acceleration; it defines only the

error due to acceleration. The maximum acceleration of which

the AD2S44 keeps track is approximate to 5 × K_a= 310,000°/sec²

or about 800 revolutions/sec².

PROCESSING FOR HIGH RELIABILITY (B SUFFIX)

As a part of the high reliability manufacturing procedure, all

converters receive the processing shown in Table 6.

Table 6.

K_acan be used to predict the output position error due to input

acceleration. For example, an acceleration of 50 revolutions/sec²

with K_a= 62,000 is calculated using the following equation:

Process¹

Conditions

Precap Visual Inspection

Temperature Cycling

Constant Acceleration

Interim Electrical Tests

Operating Burn In

MIL-STD-883, Method 2017

10 cycles, –65°C to +150°C

5000 Gs, Y1 plane









LSB

Input Acceleration

@ 25°C









sec

160 hours @ 125°C

MIL-STD-883, Method 1014

Performed at T_MIN, T_AMB, T_MAX

Errors in LSBs =

K_a

[

sec⁻²

]

Seal Test, Fine and Gross

Final Electrical Test

















rev

LSB

rev

External Visual Inspection MIL-STD-883, Method 2009

× 2¹⁴

¹Test and screening data supplied by request.

















sec

=13.2 LSBs

sec⁻²

]

OTHER PRODUCTS

62,000

[

Analog Devices manufactures many other products concerned

with the conversion of synchro/resolver data, such as the

SDC/RDC1740 series and the AD2S80A series.

RELIABILITY

The reliability of these products is very high due to the extensive

use of custom chip circuits that decrease the active component

count. Calculations of the MTBF figure under various environ-

mental conditions are available upon request from Analog

Devices.

Hybrid

The SDC/RDC1740 is a hybrid synchro/resolver-to-digital

converter with internal isolating micro transformers.

Monolithic

Figure 9 shows the MTBF in years vs. case temperature for

Naval Sheltered conditions calculated in accordance with the

Mil-Hdbk-217E.

The AD2S80A series are ICs performing resolver-to-digital

conversion with accuracies up to 2 arc minutes and 16-bit

resolution.

100

105

125

TEMPERATURE (°C)

Figure 9. MTBF vs. Temperature

Rev. B | Page 10 of 12

Data Sheet

AD2S44

OUTLINE DIMENSIONS

1.728 (43.89) MAX

1.102 (27.99)

1.079 (27.41)

PIN 1

INDICATOR

(NOTE 1)

0.025 (0.64)

0.015 (0.38)

0.225 (5.72)

MAX

0.192 (4.88)

0.152 (3.86)

0.206 (5.23)

0.186 (4.72)

0.015 (0.38)

0.008 (0.20)

0.910 (23.11)

0.890 (22.61)

0.120 (3.05)

MAX

0.025 (0.64)

MIN

0.100 (2.54)

BSC

0.023 (0.58)

0.014 (0.36)

0.070 (1.78)

0.030 (0.76)

NOTES:

1. INDEX AREA IS INDICATED BY A NOTCH OR LEAD ONE

IDENTIFICATION MARK LOCATED ADJACENT TO LEAD ONE.

2. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 10. 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H]

(DH-32E)

Dimensions shown in inches and (millimeters)

ORDERING GUIDE

Model

Temperature Range

−55°C to +125°C

Package Description

Package Option

AD2S44–TM11B

AD2S44–TM12B

AD2S44–TM18B

AD2S44–UM18B

32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H]

DH-32E

ORDERING INFORMATION

AD2S44- XM

When ordering, the converter part numbers are to be suffixed by

a two-letter code defining the accuracy grade, and a two digit

numeric code defining the signal/reference voltage and frequency.

All the standard options, and their option codes, are shown in

Figure 11. For nonstandard configurations, contact Analog

Devices.

HIGH-REL PROCESSING

Z = 0* SIGNAL, 2V REFERENCE, 2V RESOLVER

Z = 1

Z = 2

Z = 3* SIGNAL, 11.8V REFERENCE, 11.8V RESOLVER

Z = 4* SIGNAL, 26V REFERENCE, 26V RESOLVER

BASE PART

SIGNAL, 11.8V REFERENCE, 26V SYNCHRO

SIGNAL, 90V REFERENCE, 115V SYNCHRO

BASE PART

NUMBER

Z = 8

SIGNAL, 11.8V REFERENCE, 26V RESOLVER

For example, the AD2S44–TM12B is the correct part number

for a component that operates with 90 V signal, 115 V reference

synchro format inputs and yields a 4.0 arc minutes accuracy

over the −55°C to +125°C temperature range processed to high

reliability standards.

Y = 1

400Hz TO 2.6kHz REFERENCE FREQUENCY

X = U –55°C TO +125°C OPERATING TEMPERATURE

RANGE

±4.0 ARC MIN ACCURACY

±2.6 ARC MIN ACCURACY (–25°C TO +85°C)

X = T

–55°C TO +125°C OPERATING TEMPERATURE

RANGE±4.0 ARC MIN ACCURACY

X = S* –55°C TO +125°C OPERATING TEMPERATURE

RANGE±5.2 ARC MIN ACCURACY

*MODEL IS OBSOLETE AND NO LONGER AVAILABLE.

Figure 11.

Rev. B | Page 11 of 12

AD2S44

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D02947-0-10/11(B)

Rev. B | Page 12 of 12

AD2S44UM10B [ADI]

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