AD4114BCPZ-RL7 [ADI]
Single Supply, Multichannel, 31.25 kSPS, 24-Bit, Sigma-Delta ADC with ±10 V Inputs;
| 型号： | AD4114BCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Single Supply, Multichannel, 31.25 kSPS, 24-Bit, Sigma-Delta ADC with ±10 V Inputs |
| 文件： | 总49页 (文件大小：549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Supply, Multichannel, 31.25 kSPS,
24-Bit, Sigma-Delta ADC with 1ꢀ ꢁ ꢂnputꢃ
AD4114
Data Sheet
FEATURES
GENERAL DESCRIPTION
24-bit ADC with integrated AFE
The AD4114 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ)
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
Channel scan data rate of 6.21 kSPS per channel
(161 μs settling)
analog-to-digital converter (ADC) that integrates an analog
front end (AFE) for fully differential or single-ended, high
impedance (≥1 MΩ), bipolar, 1ꢀ ꢁ voltage inputs.
17.3 noise free bits at 1007 SPS per channel
120 dB common mode rejection of 50 Hz and 60 Hz at 20
SPS per channel
10 V inputs, either 8 differential or 16 single-ended
VIN pin absolute maximum rating: 65 V
Absolute input pin voltage up to 20 V
Minimum 1 MΩ impedance
The AD4114 integrates key analog and digital signal conditioning
blocks to configure eight individual setups for each analog input
channel in use. The AD4114 features a maximum channel scan
rate of 6.21 kSPS (161 μs) for fully settled data.
The embedded 2.5 ꢁ, low drift ( 5 ppmꢂ/C), band gap internal
reference (with output reference buffer) reduces the external
component count.
0.07% TUE at 25°C
On-chip 2.5 V reference
0.12% initial accuracy at 25°C, 5 ppmꢀ°C (typical) drift
Internal or external clock
Power supplies
AVDD = 3.0 V to 5.5 V
The digital filter allows flexible settings, including simultaneous
5ꢀ Hz and 6ꢀ Hz rejection at a 27.27 SPS output data rate. The user
can select different filter settings depending on the requirements of
each channel in the application. The automatic channel sequencer
enables the ADC to switch through each enabled channel.
IOVDD = 2 V to 5.5 V
The precision performance of the AD4114 is achieved by
integrating the proprietary iPassives® technology from Analog
Devices, Inc. The AD4114 is factory calibrated to achieve a high
degree of specified accuracy.
Total current consumption AVDD + IOVDD (IDD) = 3.9 mA
Temperature range: −40°C to +105°C
3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)
SPI, QSPI, MICROWIRE, and DSP compatible
The AD4114 operates with a single power supply that allows
simplified use in galvanically isolated applications. The specified
operating temperature range is −4ꢀ/C to +1ꢀ5/C. The AD4114
is housed in a 4ꢀ-lead, 6 mm × 6 mm LFCSP.
APPLICATIONS
Process control
Programmable logic controller (PLC) and distributed control
system (DCS) modules
Instrumentation and measurement
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
AD4114
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Calibration Modes ..................................................................... 29
Digital Interface.............................................................................. 3ꢀ
Checksum Protection ................................................................ 3ꢀ
CRC Calculation......................................................................... 31
Integrated Functions...................................................................... 33
General-Purpose InputꢂOutput ............................................... 33
External Multiplexer Control................................................... 33
Delay ............................................................................................ 33
16-Bit and 24-Bit Conversions................................................. 33
DOUT_RESET ........................................................................... 33
Synchronization ......................................................................... 33
Error Flags................................................................................... 34
DATA_STAT Function............................................................. 34
IOSTRENGTH Function .......................................................... 34
Internal Temperature Sensor ................................................... 35
Applications Information ............................................................. 36
Grounding and Layout.............................................................. 36
Register Summary .......................................................................... 37
Register Details ............................................................................... 39
Communications Register ........................................................ 39
Status Register............................................................................. 4ꢀ
ADC Mode Register................................................................... 41
Interface Mode Register ............................................................ 42
Register Check............................................................................ 43
Data Register............................................................................... 43
GPIO Configuration Register................................................... 44
ID Register .................................................................................. 45
Channel Register ꢀ to Channel Register 15............................ 45
Applications ...................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications .................................................................................... 4
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings ........................................................... 8
Thermal Resistance...................................................................... 8
Electrostatic Discharge (ESD) Ratings...................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions ............................ 9
Typical Performance Characteristics........................................... 11
Theory of Operation ...................................................................... 14
Power Supplies............................................................................ 15
Digital Communication ............................................................ 15
AD4114 Reset.............................................................................. 16
Configuration Overview............................................................ 16
Noise Performance and Resolution ............................................. 19
Circuit Description......................................................................... 2ꢀ
Muliplexer ................................................................................... 2ꢀ
ꢁoltage Inputs............................................................................. 2ꢀ
Absolute Input Pin ꢁoltages..................................................... 21
Data Output Coding .................................................................. 21
AD4114 Reference Options ...................................................... 21
Buffered Reference Input .......................................................... 23
Clock Source ............................................................................... 23
Digital Filter .................................................................................... 24
Sinc5 + Sinc1 Filter .................................................................... 24
Sinc3 Filter................................................................................... 24
Single-Cycle Settling Mode....................................................... 25
Enhanced 5ꢀ Hz and 6ꢀ Hz Rejection Filters......................... 25
Operating Modes............................................................................ 27
Continuous Conversion Mode................................................. 27
Continuous Read Mode ............................................................ 27
Single Conversion Mode........................................................... 27
Standby Mode and Power-Down Mode ................................. 29
Setup Configuration Register ꢀ to Setup Configuration
Regsiter 7 ..................................................................................... 46
Filter Configuration Register ꢀ to Filter Configuration
Register 7 ..................................................................................... 47
Offset Register ꢀ to Offset Register 7....................................... 48
Gain Register ꢀ to Gain Register 7........................................... 48
Outline Dimensions....................................................................... 49
Ordering Guide .......................................................................... 49
REVISION HISTORY
7/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 49
Data Sheet
AD4114
FUNCTꢂONAL BLOCK DꢂAGRAM
AVDD REGCAPA
REF– REF+ REFOUT
IOVDD REGCAPD
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
1.8V
LDO
INTERNAL
REFERENCE
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
RAIL-TO-RAIL
REFERENCE
CS
INPUT BUFFERS
VIN6
SCLK
DIN
PRECISION
VIN7
VIN8
VOLTAGE
SERIAL
INTERFACE
DIGITAL
FILTER
DIVIDER
MUX
VIN9
VIN10
Σ-Δ ADC
DOUT/RDY
SYNC
VIN11
VIN12
VIN13
VIN14
ERROR
VIN15
VINCOM
AD4114
VBIAS–
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
GPO CONTROL
TEMPERATURE
SENSOR
AVSS
GPIO0 GPIO1 GPO2 GPO3
XTAL1 XTAL2/CLKIO
Figure 1.
Rev. 0 | Page 3 of 49
AD4114
Data Sheet
SPECꢂFꢂCATꢂONS
AꢁDD = 3.ꢀ ꢁ to 5.5 ꢁ, IOꢁDD = 2 ꢁ to 5.5 ꢁ, REF− = AꢁSS = ꢀ ꢁ, DGND = ꢀ ꢁ, ꢁBIAS− = ꢀ ꢁ, REF+ = 2.5 ꢁ, internal master clock
(MCLK) = 2 MHz, TA = TMIN to TMAX (−4ꢀ/C to +1ꢀ5/C), unless otherwise noted. ꢁREF is the reference voltage, FS is full scale, and FSR is
full-scale range.
Table 1.
Parameter
Test ConditionsꢀComments
Min
Typ
Max
Unit
VOLTAGE INPUTS
Differential Input Voltage Range1
Specified performance
Functional
AVDD ≥ 4.75 V
AVDD = 3.0 V
−10
−VREF × 10
−20
+10
+VREF × 10
+20
V
V
V
V
Absolute Input Pin Voltage
−12
+12
Input Impedance
Offset Error2
Offset Drift
Gain Error
Gain Drift
1
MΩ
mV
μV/°C
% FS
ppm/°C
% FSR
TA = 25°C
TA = 25°C
1.5
7
0.05
1
0.01
Integral Nonlinearity (INL)
Total Unadjusted Error (TUE)3
TA = 25°C, internal VREF
TA = −40°C to +105°C, internal VREF
TA = 25°C, external VREF
TA = −40°C to +105°C, external VREF
AVDD for input voltage (VIN) = 1 V
0.07
0.1
0.07
0.8
% FSR
% FSR
% FSR
% FSR
dB
Power Supply Rejection Ratio (PSRR)
70
Common-Mode Rejection Ratio (CMRR) VIN = 1 V
At DC
85
120
dB
dB
At 50 Hz and 60 Hz
20 Hz output data rate (postfilter), 50 Hz
1 Hz and 60 Hz 1 Hz
Normal Mode Rejection3
50 Hz 1 Hz and 60 Hz 1 Hz
Internal clock, 20 SPS ODR (postfilter)
External clock, 20 SPS ODR (postfilter)
See Table 16 and Table 17
71
85
90
90
dB
dB
Resolution
Noise
See Table 16 and Table 17
ADC SPEED AND PERFORMANCE
ADC Output Data Rate (ODR)
No Missing Codes3
INTERNAL REFERENCE
Output Voltage
One channel, see Table 16
Excluding sinc3 filter ≥ 15 kHz notch
100 nF external capacitor to AVSS
REFOUT with respect to AVSS
REFOUT, TA = 25°C
1.25
24
31,250
SPS
Bits
2.5
5
V
%
Initial Accuracy3, 4
−0.12
−10
+0.12
+12
+10
Temperature Coefficient
Reference Load Current (ILOAD
PSRR
ppm/°C
mA
dB
ppm/m
A
)
AVDD (line regulation)
95
32
5
Load Regulation (∆VOUT/∆ILOAD
)
Voltage Noise (eN)
Voltage Noise Density
Turn On Settling Time
Short-Circuit Current (ISC)
EXTERNAL REFERENCE INPUTS
Differential Input Range
Absolute Voltage Limits
Buffers Disabled
0.1 Hz to 10 Hz, 2.5 V reference
1 kHz, 2.5 V reference
100 nF REFOUT capacitor
4.5
215
200
25
μV rms
nV/√Hz
μs
mA
VREF = (REF+) − (REF−)
1
2.5
AVDD
V
AVSS −
0.05
AVSS
AVDD +
0.05
AVDD
V
V
Buffers Enabled
External Reference Input Current
Rev. 0 | Page 4 of 49
Data Sheet
AD4114
Parameter
Test ConditionsꢀComments
Min
Typ
Max
Unit
Buffers Disabled
Input Current
9
μA/V
Input Current Drift
External clock
Internal clock
0.75
2
nA/V/°C
nA/V/°C
Buffers Enabled
Input Current
100
nA
Input Current Drift
Normal Mode Rejection
CMRR
0.25
nA/°C
95
dB
TEMPERATURE SENSOR
Accuracy
Sensitivity
After user calibration at 25°C
With respect to AVSS
2
477
°C
μV/K
GENERAL-PURPOSE OUTPUTS
GPIO0, GPIO1, GPO2, GPO3
Floating State Output Capacitance
Output Voltage3
5
pF
High (VOH
Low (VOL
CLOCK
Internal Clock
Frequency
Accuracy
)
Source current (ISOURCE) = 200 μA
Sink current (ISINK) = 800 μA
AVDD − 1
−2.5%
V
V
)
AVSS + 0.4
+2.5%
2
MHz
%
Duty Cycle
Output Voltage
VOH
50
%
0.8 ×
IOVDD
V
V
VOL
0.4
Crystal
Frequency
14
30
16
10
2
16.384
MHz
μs
MHz
%
Start-Up Time
External Clock (CLKIO)
Duty Cycle
2.048
70
50
LOGIC INPUTS
Input Voltage3
High (VINH
)
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
2 V ≤ IOVDD < 2.3 V
0.65 ×
IOVDD
0.7 ×
IOVDD
V
V
V
Low (VINL
)
0.35 ×
IOVDD
2.3 V ≤ IOVDD ≤ 5.5 V
IOVDD ≥ 2.7 V
IOVDD < 2.7 V
0.7
0.25
0.2
V
V
V
μA
Hysteresis
0.08
0.04
−10
Leakage Current
LOGIC OUTPUT (DOUT/RDY)
Output Voltage3
VOH
+10
IOVDD ≥ 4.5 V, ISOURCE = 1 mA
0.8 ×
IOVDD
0.8 ×
IOVDD
V
V
V
2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 μA
IOVDD < 2.7 V, ISOURCE = 200 μA
0.8 ×
IOVDD
Rev. 0 | Page 5 of 49
AD4114
Data Sheet
Parameter
Test ConditionsꢀComments
IOVDD ≥ 4.5 V, ISINK = 2 mA
2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA
IOVDD < 2.7 V, ISINK = 400 μA
Floating state
Min
Typ
Max
0.4
0.4
0.4
+10
Unit
V
V
V
μA
pF
VOL
Leakage Current
Output Capacitance
POWER REQUIREMENTS
Power Supply Voltage
AVDD to AVSS
AVSS to DGND
IOVDD to DGND
IOVDD to AVSS
−10
Floating state
10
3.0
−2.75
2
5.5
0
5.5
6.35
V
V
V
V
For AVSS < DGND
POWER SUPPLY CURRENTS6
All outputs unloaded, digital inputs connected
to IOVDD or DGND
Full Operating Mode
AVDD Current
IOVDD Current
Including internal reference
Internal clock
All VIN = 0 V
3.3
0.6
200
180
3.8
0.8
mA
mA
μA
Standby Mode
Power-Down Mode
POWER DISSIPATION6
Full Operating Mode
Standby Mode
All VIN = 0 V
μA
19.5
900
1
mW
μW
mW
Power-Down Mode
1 The full specification is guaranteed for a differential input signal of 10 V. The device is functional up to a differential input signal of VREF × 10. However, the specified
absolute pin voltage must not be exceeded for the proper function.
2 Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected.
3 Specification is not production tested but is supported by characterization data at the initial product release.
4 This specification includes moisture sensitivity level (MSL) preconditioning effects.
5 VOUT is the output voltage.
6 This specification is with no load on the REFOUT pin and the digital output pins.
TIMING CHARACTERISTICS
IOꢁDD = 2 ꢁ to 5.5 ꢁ, DGND = ꢀ ꢁ, Input Logic ꢀ = ꢀ ꢁ, Input Logic 1 = IOꢁDD, capacitive load (CLOAD) = 2ꢀ pF, unless otherwise
noted.
Table 2.
Parameter1, 2
Limit at TMIN, or TMAX
Unit
Test ConditionsꢀComments
SCLK
t3
t4
25
25
ns min
ns min
SCLK high pulse width
SCLK low pulse width
READ OPERATION
t1
0
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
CS falling edge to DOUT/RDY active time
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
SCLK active edge to data valid delay4
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
Bus relinquish time after CS inactive edge
15
40
0
12.5
25
2.5
20
0
3
t2
5
t5
t6
t7
SCLK inactive edge to CS inactive edge
10
SCLK inactive edge to DOUT/RDY high/low
Rev. 0 | Page 6 of 49
Data Sheet
AD4114
Parameter1, 2
Limit at TMIN, or TMAX
Unit
Test ConditionsꢀComments
WRITE OPERATION
t8
0
8
8
5
ns min
ns min
ns min
ns min
CS falling edge to SCLK active edge setup time4
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
t9
t10
t11
1 Sample tested during initial release to ensure compliance.
2 See Figure 2 and Figure 3.
3 This parameter is defined as the time required for the output to cross the VOL or VOH limit.
4 The SCLK active edge is the falling edge of SCLK.
5
RDY
DOUT/
RDY
is
returns high after a data register read. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/
high. Ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.
Timing Diagrams
CS (I)
t6
t1
t5
MSB
LSB
DOUT/RDY (O)
t7
t2
t3
SCLK (I)
t4
I = INPUT, O = OUTPUT
Figure 2. Read Cycle Timing Diagram
CS (I)
t11
t8
SCLK (I)
DIN (I)
t9
t10
MSB
LSB
I = INPUT, O = OUTPUT
Figure 3. Write Cycle Timing Diagram
Rev. 0 | Page 7 of 49
AD4114
Data Sheet
ABSOLUTE MAXꢂMUM RATꢂNGS
TA = 25/C, unless otherwise noted.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 3.
Parameter
Rating
AVDD to AVSS
AVDD to DGND
IOVDD to DGND
IOVDD to AVSS
AVSS to DGND
VINx to AVSS
Reference Input Voltage to AVSS
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Digital Input Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Lead Soldering, Reflow Temperature
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +7.5 V
−3.25 V to +0.3 V
−65 V to +65 V
−0.3 V to AVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
10 mA
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages
θJC is the thermal resistance from the junction to the package case.
Table 4. Thermal Resistance
Package Type
CP-40-151
θJA
342
θJC
2.633
Unit
°C/W
1 4-Layer JEDEC PCB.
2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
PCB with 16 thermal vias. θJA is specified for a device soldered on a JEDEC
test PCB for surface-mount packages. See JEDEC JESD51.
−40°C to +105°C
−65°C to +150°C
150°C
3 A cold plate is attached to the PCB bottom and measured at the exposed paddle.
260°C
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSIꢂESDAꢂJEDEC JS-ꢀꢀ1.
Charged device model (CDM) per ANSIꢂESDAꢂJEDEC JS-ꢀꢀ2.
ESD Ratings for AD4114
Table 5. AD4114, 40-Lead LFCSP
ESD Model
Withstand Threshold (v)
Class
1C
C3
HBM
CDM
1000
1250
ESD CAUTION
Rev. 0 | Page 8 of 49
Data Sheet
AD4114
PꢂN CONFꢂGURATꢂON AND FUNCTꢂON DESCRꢂPTꢂONS
VINCOM
VIN0
1
2
3
4
5
6
7
8
9
30 VIN8
29 VIN7
VIN1
28 VIN6
VIN2
VIN3
REFOUT
REGCAPA
AVSS
27 VIN5
AD4114
26 VIN4
TOP VIEW
25 GPO2
24 GPIO1
23 GPIO0
22 REGCAPD
21 DGND
(Not to Scale)
AVDD
DNC 10
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT ANYTHING TO DNC.
DNC IS INTERNALLY CONNECTED TO AVSS.
2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON
THE PCB THAT IS UNDER THE EXPOSED PAD TO CONFER MECHANICAL
STRENGTH TO THE PACKAGE AND FOR HEAT DISSIPATION. THE EXPOSED
PAD MUST BE CONNECTED TO AVSS THROUGH THIS PAD ON THE PCB.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic1 Type2 Description
1
2
3
4
5
6
7
VINCOM
AI
Voltage Input Common. Voltage inputs are referenced to VINCOM when the inputs are configured as
single-ended. Connect VINCOM to analog ground.
Voltage Input 0. VIN0 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN1 in differential configuration.
Voltage Input 1. VIN1 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN0 in differential configuration.
Voltage Input 2. VIN2 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN3 in differential configuration.
Voltage Input 3. VIN3 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN2 in differential configuration.
Internal Reference Buffered Output. The output is 2.5 V with respect to AVSS. Decouple REFOUT to AVSS
using a 0.1 μF capacitor.
Analog Low Dropout (LDO) Regulator Output. Decouple REGCAPA to AVSS using a 1 μF capacitor and a
0.1 μF capacitor.
VIN0
AI
VIN1
AI
VIN2
AI
VIN3
AI
REFOUT
REGCAPA
AO
AO
8
9
10
11
12
13
AVSS
AVDD
DNC
VBIAS−
XTAL1
XTAL2/CLKIO AI/DI
P
P
N/A
AI
AI
Negative Analog Supply. AVSS ranges from −2.75 V to 0 V and is nominally set to 0 V.
Analog Supply Voltage. AVDD ranges from 3.0 V to 5.5 V with respect to AVSS.
Do Not Connect. Do not connect anything to DNC. DNC is internally connected to AVSS.
Voltage Bias Negative. VBIAS− sets the bias voltage for the voltage input AFE. Connect VBIAS− to AVSS.
Input 1 for Crystal.
Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADC Mode Register
section for more information.
14
DOUT/RDY
DO
Serial Data Output/Data Ready Output. The DOUT/RDY dual-purpose pin functions as a serial data output
pin to access the output shift register on the ADC. The output shift register can contain data from any on-
chip data or control registers. The data-word or control word information is placed on the DOUT/RDY pin
on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is
tristated. When CS is low and a register is not being read, DOUT/RDY operates as a data ready pin and
goes low to indicate the completion of a conversion. If the data is not read after the conversion, the pin
goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a
processor that indicates that valid data is available.
15
DIN
DI
Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to
the control registers on the ADC, and the register address (RA) bits of the communications register
identify the appropriate register. Data is clocked in on the rising edge of SCLK.
16
17
SCLK
CS
DI
DI
Serial Clock Input. The SCLK serial clock input is used for data transfers to and from the ADC. SCLK has a
Schmitt triggered input.
Chip Select Input. CS is an active low logic input used to select the ADC. Use CS to select the ADC in
systems with more than one device on the serial bus. CS can be hardwired low to allow the ADC to
Rev. 0 | Page 9 of 49
AD4114
Data Sheet
Pin No. Mnemonic1
Type2 Description
operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. When CS is
high, the DOUT/RDY output is tristated.
18
ERROR
DI/O
Error Input/Output or General-Purpose Output. ERROR can be used in one of the following three modes:
Active low error input mode. This mode sets the ADC_ERROR bit in the status register.
Active low, open-drain error output mode. The status register error bits are mapped to the ERROR pin.
The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error
on any device can be observed.
General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON register.
ERROR is referenced between IOVDD and DGND.
19
20
SYNC
DI
P
Synchronization Input. SYNC allows digital filter and analog modulator synchronization when using
multiple devices.
Digital Input/Output Supply Voltage. The IOVDD voltage ranges from 2 V to 5.5 V (nominal). IOVDD is
independent of AVDD. For example, IOVDD operates at 3.3 V when AVDD equals 5 V, or vice versa. If
AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.
IOVDD
21
22
DGND
REGCAPD
P
AO
Digital Ground.
Digital LDO Regulator Output. REGCAPD is for decoupling purposes only. Decouple REGCAPD to DGND
using a 1 μF capacitor.
23
24
25
26
GPIO0
GPIO1
GPO2
VIN4
DI/O
DI/O
DO
General-Purpose Input/Output 0. Logic input/output on GPIO0 is referred to the AVDD and AVSS supplies.
General-Purpose Input/Output 1. Logic input/output on GPIO1 is referred to the AVDD and AVSS supplies.
General-Purpose Output 2. Logic output on GPO2 is referred to the AVDD and AVSS supplies.
Voltage Input 4. VIN4 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN5 in differential configuration.
AI
27
28
29
30
31
32
33
34
35
36
37
VIN5
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
Voltage Input 5. VIN5 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN4 in differential configuration.
Voltage Input 6. VIN6 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN7 in differential configuration.
Voltage Input 7. VIN7 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN6 in differential configuration.
Voltage Input 8. VIN8 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN9 in differential configuration.
Voltage Input 9. VIN9 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN8 in differential configuration.
Voltage Input 10. VIN10 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN11 in differential configuration.
Voltage Input 11. VIN11 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN10 in differential configuration.
Voltage Input 12. VIN12 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN13 in differential configuration.
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
VIN12
VIN13
VIN14
VIN15
Voltage Input 13. VIN13 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN12 in differential configuration.
Voltage Input 14. VIN14 is either referenced to VINCOM in single-ended configuration or referenced to a
positive input of an input pair with VIN15 in differential configuration.
Voltage Input 15. VIN15 is either referenced to VINCOM in single-ended configuration or referenced to a
negative input of an input pair with VIN14 in differential configuration.
38
39
GPO3
REF−
DO
AI
General-Purpose Output 3. Logic output on GPO3 is referred to the AVDD and AVSS supplies.
Reference Input Negative Terminal. The REF− voltage can span from AVSS to AVDD − 1 V. The reference
can be selected through the REF_SELx bits in the setup configuration registers.
40
REF+
EP
AI
P
Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. The
REF+ voltage can span from AVDD to AVSS + 1 V. The reference can be selected through the REF_SELx bits in
the setup configuration registers.
Exposed Pad. Solder the exposed pad to a similar pad on the PCB that is under the exposed pad to confer
mechanical strength to the package and for heat dissipation. The exposed pad must be connected to
AVSS through this pad on the PCB.
1 The dual function pin mnemonics are referenced by the relevant function only throughout this data sheet.
2 AI is analog input, AO is analog output, P is power supply, N/A is not applicable, DI is digital input, DO is digital output, and DI/O is bidirectional digital input/output.
Rev. 0 | Page 10 of 49
Data Sheet
AD4114
TYPꢂCAL PERFORMANCE CHARACTERꢂSTꢂCS
8388198
500
450
8388197
8388196
8388195
8388194
8388193
8388192
8388191
400
350
300
250
200
150
100
50
0
0
200
400
600
800
1000
8388192 8388193 8388194 8388195 8388196 8388197
SAMPLE NUMBER
ADC CODE
Figure 5. Noise (Output Data Rate = 1.25 SPS)
Figure 8. Histogram (Output Data Rate = 1.25 SPS)
8388240
8388230
8388220
8388210
8388200
8388190
8388180
8388170
8388160
8388150
8388140
45
40
35
30
25
20
15
10
5
0
0
200
400
600
800
1000
SAMPLE NUMBER
ADC CODE
Figure 9. Histogram (Output Data Rate = 2.5 kSPS)
Figure 6. Noise (Output Data Rate = 2.5 kSPS)
30
25
20
15
10
8388280
8388260
8388240
8388220
8388200
8388180
8388160
8388140
8388120
8388100
8388080
8388060
5
0
0
200
400
600
800
1000
SAMPLE NUMBER
ADC CODE
Figure 10. Histogram (Output Data Rate = 31.25 kSPS)
Figure 7. Noise (Output Data Rate = 31.25 kSPS)
Rev. 0 | Page 11 of 49
AD4114
Data Sheet
–60
2.01
2.00
1.99
1.98
1.97
1.96
1.95
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
10
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
20
30
40
50
60
V
FREQUENCY (Hz)
IN
Figure 11. CMRR vs. VIN Frequency (VIN = 0.1 V, Output Data Rate = 20 SPS,
Enhanced Filter)
Figure 14. Internal Oscillator Frequency vs. Temperature
5
–40
–50
–60
4
3
–70
2
–80
1
–90
0
–100
–110
–1
1
10
100
1k
V FREQUENCY (Hz)
IN
10k
100k
1M
10M
100M
–10
–8
–6
–4
–2
0
2
4
6
8
10
V
(V)
IN
Figure 12. INL vs. VIN
Figure 15. PSRR vs. VIN Frequency
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
0
0
–2.7
–2.1
–1.5
–0.9
–0.3
0.3
0.9
1.5
1.996 1.997 1.998 1.999 2.000 2.001 2.002 2.003
FREQUENCY (MHz)
OFFSET ERROR (mV)
Figure 13. Internal Oscillator Frequency and
Accuracy Distribution Histogram
Figure 16. Offset Error Distribution Histogram
Rev. 0 | Page 12 of 49
Data Sheet
AD4114
45
40
35
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
0.07
0.17
0.27
0.37
0.47
0.57
0.67
0.77
1
2
3
4
5
6
OFFSET ERROR DRIFT (µV/°C)
GAIN ERROR DRIFT (ppm/°C)
Figure 17. Offset Error Drift Distribution Histogram
Figure 19. Gain Error Drift Distribution Histogram
40
35
30
25
20
15
10
5
0
–0.040 –0.034 –0.028 –0.022 –0.016 –0.010 –0.004
GAIN ERROR (% of Full Scale)
Figure 18. Gain Error Distribution Histogram
Rev. 0 | Page 13 of 49
AD4114
Data Sheet
THEORY OF OPERATꢂON
The AD4114 offers a fast settling, high resolution, multiplexed
ADC with high levels of configurability, including the following
features:
The AD4114 includes two separate linear regulator blocks for
the analog and digital circuitry. The analog LDO regulator
regulates the AꢁDD supply to 1.8 ꢁ.
The linear regulator for the digital IOꢁDD supply performs a
function similar to the LDO regulator and regulates the input
voltage applied at the IOꢁDD pin to 1.8 ꢁ. The serial interface
signals always operate from the IOꢁDD supply seen at the pin.
For example, if 3.3 ꢁ is applied to the IOꢁDD pin, the interface
logic inputs and outputs operate at this level.
Eight fully differential voltage inputs or 16 single-ended
voltage inputs.
High impedance voltage divider with integrated precision
matched resistors.
Embedded proprietary iPassives® technology within a
small device footprint.
Per channel configurability where up to eight different
setups can be defined. A separate setup can be mapped to
each channel. Each setup allows the user to configure
whether the buffers are enabled or disabled, gain and offset
correction, filter type, ODR, and reference source selection.
Highly configurable, digital filter enabling conversion rates up
to 31.25 kSPS on a single channel and 6.21 kSPS switching.
The AD4114 is designed for a multitude of factory automation
and process control applications, including PLC and DCS
modules. The AD4114 reduces overall system cost and design
burden and maintains a high level of accuracy. The AD4114
offers the following system benefits:
A single 5 ꢁ power supply.
Guaranteed minimum 1 MΩ input impedance.
Overrange voltage greater than 1ꢀ ꢁ.
Reduced calibration costs.
The AD4114 includes a precision, 2.5 ꢁ, low drift ( 5 ppmꢂ/C),
band gap internal reference. Use this reference in ADC conversions
to reduce the external component count. When enabled, the
internal reference is output to the REFOUT pin. The internal
reference can be used as a low noise biasing voltage for the external
circuitry and must be connected to a ꢀ.1 ꢃF decoupling capacitor.
High channel count.
16MHz
CX2
CX1
OPTIONAL EXTERNAL
CRYSTAL CIRCUITRY
CAPACITORS
12
13
XTAL1
XTAL2/CLKIO
CLKIN
OPTIONAL
EXTERNAL
CLOCK
INPUT
DOUT/RDY 14
DOUT/RDY
DIN
2
3
VIN0
VIN1
15
DIN
16
SCLK
CS
SCLK
17
CS
IOVDD
0.1µF
20
21
IOVDD
DGND
AD4114
37
VIN15
REGCAPD 22
0.1µF
1µF
AVDD
AVDD
REFOUT
9
1
VINCOM
0.1µF
6
7
0.1µF
11
VBIAS–
REGCAPA
0.1µF
1µF
AVSS
8
Figure 20. Typical Connection Diagram
Rev. 0 | Page 14 of 49
Data Sheet
AD4114
register. Therefore, all communication begins by writing to the
communications register.
POWER SUPPLIES
The AD4114 has two independent power supply pins, AꢁDD
and IOꢁDD. The AD4114 has no specific requirements for a
power supply sequence. However, when all power supplies are
stable, a device reset is required. See the AD4114 Reset section
for information on how to reset the device.
The data written to the communications register determines which
register is accessed and if the next operation is a read or write.
The RA bits (Bits[5:ꢀ] in Register Address ꢀxꢀꢀ) determine the
specific register to which the read or write operation applies
(see Table 2ꢀ).
AꢁDD powers the internal 1.8 ꢁ analog LDO regulator that
powers the ADC core. AꢁDD also powers the crosspoint
multiplexer and integrated input buffers. AꢁDD is referenced to
AꢁSS, and AꢁDD − AꢁSS = 5 ꢁ. AꢁDD and AꢁSS can be a
single 5 ꢁ supply or 2.5 ꢁ split supplies. Consider the absolute
maximum ratings when using split supplies (see the Absolute
Maximum Ratings section).
When the read or write operation to the selected register is
complete, the interface returns to the default state to expect a
write operation to the communications register.
Figure 22 and Figure 23 show a write to and a read from a
register by writing the 8-bit command to the communications
register followed by the data for the addressed register. Figure 22
shows an 8-bit command with the register address followed by
8 bits, 16 bits, or 24 bits of data where the data length on DIN
depends on the selected register. Figure 23 shows an 8-bit
command with the register address followed by 8 bits, 16 bits,
24 bits, or 32 bits of data where the data length on DOUT
depends on the selected register.
IOꢁDD powers the internal 1.8 ꢁ digital LDO regulator that
powers the ADC digital logic. IOꢁDD sets the voltage levels for
the serial peripheral interface (SPI) of the ADC. IOꢁDD is
referenced to DGND, and the voltage from IOꢁDD to DGND can
vary from 2 ꢁ (minimum) to 5.5 ꢁ (maximum).
Single-Supply Operation (AVSS = DGND)
To verify correct communication with the device, read the ID
register. The ID register is a read only register and contains the
value of ꢀx3ꢀDX, where x means don’t care, for the AD4114. The
communication register and ID register details are described in
Table 7 and Table 8.
When the AD4114 is powered from a single supply connected
to AꢁDD, the supply must be 5 ꢁ. In this configuration, AꢁSS
and DGND can be shorted together on a single ground plane.
IOꢁDD can range from 2 ꢁ to 5.5 ꢁ in this unipolar input
configuration.
8-BIT COMMAND
UP TO 24-BIT INPUT
8-BIT CRC
CS
DIGITAL COMMUNICATION
The AD4114 has either a 3-wire or 4-wire SPI interface that is
compatible with QSPI™, MICROWIRE®, and digital signal
processors (DSPs). The interface operates in SPI Mode 3 and can
CMD
DATA
CRC
DIN
CS
be operated with tied low. In SPI Mode 3, SCLK idles high, the
SCLK
falling edge of SCLK is the drive edge, and the rising edge of
SCLK is the sample edge. Data is clocked out on the falling
(drive) edge and data is clocked in on the rising (sample) edge.
Figure 22. Writing to a Register
8-BIT COMMAND UP TO 32-BIT OUTPUT
8-BIT CRC
CS
DRIVE EDGE
SAMPLE EDGE
CMD
DIN
DOUT/
RDY
DATA
CRC
Figure 21. SPI Mode 3 SCLK Edges
Accessing the ADC Register Map
SCLK
The communications register controls access to the full ADC
register map. This register is an 8-bit, write only register. On
power-up or after a reset, the digital interface defaults to a state
where the interface expects a write to the communications
Figure 23. Reading from a Register
Table 7. Communications Register Bit Map
Register
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RꢀW
0x00
COMMS
[7:0]
WEN
R/W
RA
0x00
W
Table 8. ID Register Bit Map
Register
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0x30DX
RꢀW
0x07
ID
[15:0]
ID
R
Rev. 0 | Page 15 of 49
AD4114
Data Sheet
Figure 24 shows an overview of the suggested flow for changing
the ADC configuration divided into the following three blocks:
AD4114 RESET
When a power-up cycle completes and the power supplies are
stable, a device reset is required. If interface synchronization is
lost, a device reset is required. A write operation of at least 64 serial
clock cycles with DIN high returns the ADC to the default state
by resetting the entire device, including the register contents.
Channel configuration
Setup configuration
ADC mode and interface mode configuration
Channel Configuration
CS
CS
Alternatively, if
is used with the digital interface, returning
The AD4114 has 16 independent channels and eight independent
setups. The user can select any input pair on any channel, as
well as any of the eight setups for any channel, which allows full
flexibility in the channel configuration. This flexibility allows per
channel configuration when using differential inputs and single-
ended inputs because each channel can have an individual
dedicated setup.
high sets the digital interface to the default state and halts any
serial interface operation.
CONFIGURATION OVERVIEW
After a power-on or reset, the AD4114 default configuration is
as follows:
Channel configuration: Channel ꢀ is enabled, the ꢁINꢀ
and ꢁIN1 pair is selected as the input. Setup ꢀ is selected
(see the Setup Configuration section for more information).
Setup configuration: the analog input buffers and the
reference input buffers are disabled. The REF+ and REF− pins
are selected as the reference source. Note that for this setup,
the default channel does not operate correctly because the
input buffers must be enabled for a ꢁINx input.
Channel Registers
The channel registers select which voltage input is used for the
corresponding channel. Each channel register contains a channel
enableꢂdisable bit and the setup selection bits that select from
eight available setups to use for the channel.
When the AD4114 operates with more than one channel enabled,
the channel sequencer cycles through the enabled channels in
sequential order from Channel ꢀ to Channel 15. If a channel is
disabled, that channel is skipped by the sequencer. Details on
the channel register for Channel ꢀ are shown in Table 9.
Filter configuration: the sinc5 + sinc1 filter is selected and
the maximum output data rate of 31.25 kSPS is selected.
ADC mode: continuous conversion mode and the internal
oscillator are enabled. The internal reference is disabled.
Interface mode: cyclic redundancy check (CRC) and the
data and status output are disabled.
Note that only a few of the register setting options are shown in
this example list. For full register information, see the Register
Details section.
A
CHANNEL CONFIGURATION
SELECT INPUT AND SETUP FOR EACH ADC CHANNEL
B
C
SETUP CONFIGURATION
8 POSSIBLE ADC SETUPS
SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE
ADC MODE AND INTERFACE MODE CONFIGURATION
SELECT ADC OPERATING MODE, CLOCK SOURCE,
ENABLE CRC, DATA AND STATUS, AND MORE
Figure 24. Suggested ADC Configuration Flow
Table 9. Channel Register 0 Bit Map
Register
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RꢀW
0x10
CH0
[15:8]
[7:0]
CH_EN0
SETUP_SEL0
Reserved
INPUT0[9:8]
0x8001
R/W
INPUT0[7:0]
Rev. 0 | Page 16 of 49
Data Sheet
AD4114
Setup Configuration
Setup Configuration Registers
The AD4114 has eight independent setups. Each setup consists
of the following four types of registers:
The setup configuration registers allow the user to select between
bipolar mode and unipolar mode to determine the ADC output
coding. The user can also select the reference source using these
registers. Three reference source options are available: a reference
connected between the REF+ and REF− pins, the internal
reference, or using AꢁDD – AꢁSS as the reference. The input
and reference buffers can also be enabled or disabled using
these registers.
Setup configuration register
Filter configuration register
Gain register
Offset register
For example, Setup ꢀ consists of Setup Configuration Register ꢀ,
Filter Configuration Register ꢀ, Gain Register ꢀ, and Offset
Register ꢀ. Figure 25 shows the grouping of these registers. The
setup is selectable from the channel registers (see the Channel
Configuration section), which allows each channel to be assigned
to one of the eight separate setups. Table 1ꢀ through Table 13 show
the four registers that are associated with Setup ꢀ. This structure is
repeated for Setup 1 to Setup 7.
Filter Configuration Registers
The filter configuration registers select which digital filter is
used at the output of the ADC modulator. Set the bits in these
registers to select the order of the filter and the output data rate.
For more information, see the Digital Filter section.
SETUP CONFIGURATION
REGISTERS
FILTER CONFIGURATION
REGISTERS
GAIN REGISTERS
OFFSET REGISTERS
SETUPCON0
SETUPCON1
SETUPCON2
SETUPCON3
SETUPCON4
SETUPCON5
SETUPCON6
SETUPCON7
FILTCON0
FILTCON1
FILTCON2
FILTCON3
FILTCON4
FILTCON5
FILTCON6
FILTCON7
GAIN0
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
OFFSET0
0x30
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
OFFSET1
0x31
OFFSET2
0x32
OFFSET3
0x33
OFFSET4
0x34
OFFSET5
0x35
OFFSET6
0x36
OFFSET7
0x37
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
GAIN CORRECTION
OPTIONALLY
OFFSET CORRECTION
OPTIONALLY PROGRAMMED
PER SETUP AS REQUIRED
PROGRAMMED
PER SETUP AS REQUIRED
INPUT BUFFERS
REFERENCE INPUT BUFFERS
REFERENCE SOURCE
31.25kSPS TO 2.5SPS
SINC5 + SINC1
SINC3
SINC3 MAP
ENHANCED 50Hz OR 60Hz
Figure 25. ADC Setup Register Grouping
Table 10. Setup Configuration Register 0
Register Name
Bits Bit 7
Bit 6
Bit 5 Bit 4
BI_UNIPOLAR0
Bit 3
Bit 2
Bit 1 Bit 0 Reset
RꢀW
0x20
SETUPCON0 [15:8]
Reserved
REFBUF0+ REFBUF0− INBUF0
Reserved
0x1000 R/W
[7:0] Reserved
REF_SEL0
Table 11. Filter Configuration Register 0
Register
Name
Bits
[15:8] SINC3_MAP0
[7:0] Reserved
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3
Reserved
Bit 2 Bit 1 Bit 0 Reset
ENHFILT0 0x0500
RꢀW
0x28
FILTCON0
ENHFILTEN0
R/W
ORDER0
ODR0
Table 12. Gain Register 0
Register
Name
Bits
Bits[23:0]
Reset
RꢀW
R/W
0x38
GAIN0
[23:0]
GAIN0
0x5XXXX0
Table 13. Offset Register 0
Register
Name
Bits
Bits[23:0]
Reset
RꢀW
R/W
0x30
OFFSET0
[23:0]
OFFSET0
0x800000
Rev. 0 | Page 17 of 49
AD4114
Data Sheet
also select the standby and power-down modes, as well as any
of the calibration modes. The ADC mode register also contains
the clock source select bits and internal reference enable bit. The
reference select bits are contained in the setup configuration
registers (see the Setup Configuration section for more
information). The details of the ADC mode register are shown in
Table 14.
Gain Registers
The gain registers are 24-bit, read and write registers that hold
the gain calibration coefficient for the ADC. The power-on reset
value of the gain registers is ꢀx5XXXXꢀ.
Offset Registers
The offset registers are 24-bit, read and write registers that hold
the offset calibration coefficient for the ADC. The power-on
reset value of the offset registers is ꢀx8ꢀꢀꢀꢀꢀ.
Interface Mode Register
The interface mode register configures the digital interface
operation. This register allows the user to control data-word
length, CRC enable, data plus status read, and continuous read
mode. The details of this register are shown in Table 15. For more
information, see the Digital Interface section.
ADC Mode and Interface Mode Configuration
The ADC mode register and the interface mode register configure
the core peripherals for the AD4114 to use, as well as the mode
for the digital interface.
ADC Mode Register
The ADC mode register primarily sets the ADC conversion
mode to either continuous or single conversion. The user can
Table 14. ADC Mode Register
Register
Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RꢀW
0x01
ADCMODE
[15:8]
[7:0]
REF_EN
Reserved
Reserved
SING_CYC
Mode
Reserved
Delay
0x2000
R/W
CLOCKSEL
Reserved
Table 15. Interface Mode Register
Register Name Bits Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
Reset
RꢀW
0x02
IFMODE [15:8]
ALT_
SYNC
IOSTRENGTH
Reserved
DOUT_
RESET
0x0000 R/W
[7:0]
CONTREAD DATA_
STAT
REG_
CHECK
Reserved
CRC_EN
Reserved WL16
Rev. 0 | Page 18 of 49
Data Sheet
AD4114
NOꢂSE PERFORMANCE AND RESOLUTꢂON
Table 16 to Table 17 show the rms noise, peak-to-peak noise,
effective resolution, and noise free (peak-to-peak) resolution of
the device for various ODRs. These values are typical and are
measured with an external 2.5 ꢁ reference and with the ADC
continuously converting on multiple channels. The values in
Table 16 and Table 17 are generated for the 1ꢀ ꢁ voltage input
range with a differential input voltage of ꢀ ꢁ. Note that the peak-
to-peak resolution is calculated based on the peak-to-peak noise.
The peak-to-peak resolution represents the resolution for which
there is no code flicker.
Table 16. 10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc5 + Sinc1 Filter
Default Output Data Rate
(SPS), SING_CYC = 0 and
Single Channel Enabled
Output Data Rate (SPS per
Channel), SING_CYC = 1 or
Multiple Channels Enabled
Notch
Frequency
(Hz)
Effective
Resolution
(Bits)
Peak-to-Peak
Resolution
(Bits)
Settling
Time1
Noise
Noise
(μV p-p)
(μV rms)2
31,250
15,625
10,417
5208
2597
1007
504
6211
5181
4444
3115
2597
1007
504
161 μs
193 μs
225 μs
321 μs
385 μs
993 μs
1.99 ms
2.63 ms
4.99 ms
9.99 ms
16.8 ms
20.13 ms
49.98 ms
60.13 ms
100 ms
200 ms
400 ms
800 ms
31,250
15,625
10,417
5208
3906
1157
539
401
206
102
59.98
50
20
16.67
10
5
2.5
74
64
56
41
38
20
15
13
9
18
456
372
348
265
250
128
104
92
71
42
35
23
29
24
18
15
15
9
15.4
15.7
15.8
16.2
16.3
17.3
17.5
17.7
18.1
18.9
19.1
19.2
19.4
19.7
20.1
20.4
20.4
21.1
18.2
18.4
18.9
19
19.9
20.4
20.6
21
21.5
21.7
21.8
22.1
22.4
22.5
22.6
22.7
22.7
381
381
200.3
100.2
59.52
49.68
20
16.67
10
5
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
7
6
5.5
4.4
3.7
3.3
3
2.5
1.25
2.9
2.1
1.25
1 The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
2 The noise values are based on 1000 samples for data rates ≥16.67 SPS per channel and based on 100 samples for data rates ≤10 SPS per channel.
Table 17. 10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc3 Filter
Default Output Data Rate
(SPS), SING_CYC = 0 and
Single Channel Enabled
Output Data Rate (SPS per
Channel), SING_CYC = 1 or
Multiple Channels Enabled
Notch
Frequency
(Hz)
Effective
Resolution
(Bits)
Peak-to-Peak
Resolution
(Bits)
Settling
Time1
Noise
Noise
(μV p-p)
(μV rms)2
31,250
15,625
10,417
5208
2604
1008
504
400.6
200.3
100.16
59.98
50
20.01
16.67
10
5
2.5
10309
5181
3460
1773
867.3
335.9
167.98
133.5
66.77
33.39
19.99
16.67
6.67
97 μs
193 μs
289 μs
577 μs
31,250
15,625
10,417
5208
3906
1157
539
401
206
102
59.98
50
20
16.67
10
5
2.5
1,068
145
55
34
24
14.2
17.1
18.5
19.2
19.6
20.3
20.8
21
21.3
21.7
22
22.1
22.4
22.6
22.7
22.7
22.7
22.7
6,485
920
417
229
152
89
80
60
48
39
30
27
25
24
15
10
9
6
11.6
14.4
15.5
16.4
17
17.8
17.9
18.4
18.7
19
19.4
19.5
19.6
19.7
20.4
21
1.153 ms
2.977 ms
5.953 ms
7.489 ms
14.98 ms
29.95 ms
50.02 ms
60 ms
149.95 ms
180 ms
300 ms
600 ms
1.2 sec
15
11
9.7
7.5
5.7
4.6
4.4
3.7
3.2
2.9
2.6
2.5
1.9
5.56
3.33
1.67
0.83
21.1
21.7
1.25
0.42
2.4 sec
1.25
1 The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
2 The noise values are based on 1000 samples for data rates ≥16.67 SPS per channel and based on 100 samples for data rates ≤ 10 SPS per channel.
Rev. 0 | Page 19 of 49
AD4114
Data Sheet
CꢂRCUꢂT DESCRꢂPTꢂON
resistors that enable an input range of 2ꢀ ꢁ from a single 5 ꢁ
power supply.
MULIPLEXER
The device has 17 voltage input pins, ꢁINꢀ to ꢁIN15 and
ꢁINCOM. Each pin connects to the internal multiplexer. The
multiplexer enables these inputs to be configured as input pairs.
The AD4114 can have up to 16 active channels. When more
than one channel is enabled, the channels are automatically
sequenced in order from the lowest enabled channel number to
the highest enabled channel number. The multiplexer output
connects to the input of the integrated, true rail-to-rail buffers.
These buffers can be bypassed and the multiplexer output can
be directly connected to the ADC switched capacitor input. The
simplified input circuits are shown in Figure 26.
Enable the input buffers in the corresponding setup configuration
register for the voltage input channels (see Table 29).
Fully Differential Inputs
The differential inputs are paired together in the following pairs:
ꢁINꢀ and ꢁIN1, ꢁIN2 and ꢁIN3, ꢁIN4 and ꢁIN5, ꢁIN6 and
ꢁIN7, ꢁIN8 and ꢁIN9, ꢁIN1ꢀ and ꢁIN11, ꢁIN12 and ꢁIN13,
and ꢁIN14 and ꢁIN15.
Single-Ended Inputs
The user can measure up to 16 different single-ended voltage
inputs. In this case, each voltage input must be paired with the
ꢁINCOM pin. Connect the ꢁINCOM pin externally to the
AꢁSS pin.
VOLTAGE INPUTS
The AD4114 can be set up to have either 16 single-ended inputs
or eight fully differential inputs. The voltage divider on the AFE
has a division ratio of 1ꢀ and consists of precision matched
AVDD
AVDD
MULTIPLEXER
222kΩ
1MΩ
222kΩ 222kΩ
VIN0
VIN1
+
AVSS
AVDD
AVSS
1MΩ
AVDD
AVSS
–
1MΩ
VINCOM
VBIAS–
222kΩ
222kΩ 222kΩ
Figure 26. Simplified Voltage Input Circuits
Rev. 0 | Page 20 of 49
Data Sheet
AD4114
ABSOLUTE INPUT PIN VOLTAGES
AVDD = 5V
ABSOLUTE MAXIMUM RATING
NO DAMAGE TO DEVICE
+65V
The AD4114 voltage input pins are specified for an accuracy of
1ꢀ ꢁ, specifically for the differential voltage between any two
voltage input pins.
+30V
+20V
NO LOSS OF ACCURACY ON OTHER CHANNELS
The voltage input pins have separate specifications for the
absolute voltage that can be applied, and the unique design of
the voltage divider network of the analog front end enables
overvoltage robustness on the AD4114, which means the
allowed overvoltages vary depending on the AꢁDD supply.
Figure 27 and Figure 28 show the different degrees of
robustness that can be achieved for AꢁDD = 3 ꢁ and AꢁDD =
5 ꢁ, respectively. Figure 27 and Figure 28 provide a visual
representation and guidance on how an overvoltage on a
voltage pin can affect the overall device accuracy.
GUARANTEED ACCURACY
–20V
–25V
NO LOSS OF ACCURACY ON OTHER CHANNELS
NO DAMAGE TO DEVICE
–65V
ABSOLUTE MAXIMUM RATING
Figure 28. Absolute Input Pin Voltages, AVDD = 5 V
The guaranteed accuracy section of Figure 27 and Figure 28
shows the voltage range that can be applied to a voltage input
pin and achieve guaranteed accuracy.
DATA OUTPUT CODING
When the ADC is configured for unipolar operation, the output
code is natural (straight) binary with a zero differential input
voltage that results in a code of ꢀꢀ … ꢀꢀ, a midscale voltage that
results in a code of 1ꢀꢀ … ꢀꢀꢀ, and a full-scale input voltage
that results in a code of 111 … 111. The output code for any
input voltage is represented with the following equation:
The no loss of accuracy sections show the voltage levels that can
be applied without degrading the accuracy of other channels.
The no damage to device sections show the allowable positive
and negative voltages that can be applied to a voltage input pin
without exceeding the absolute maximum. The performance of
other channels is degraded, but the performance recovers when
the overvoltage is removed. This voltage range is specified as an
absolute maximum rating of 65 ꢁ.
Code = (2N × VIN × ꢀ.1)ꢂVREF
where:
N = 24 (the number of bits).
IN is the input voltage.
REF is the reference voltage.
Operation beyond the maximum operating conditions for
extended periods can affect product reliability.
V
V
When the ADC is configured for bipolar operation, the output
code is offset binary with a negative full-scale voltage that results in
a code of ꢀꢀꢀ … ꢀꢀꢀ, a zero differential input voltage that results
in a code of 1ꢀꢀ … ꢀꢀꢀ, and a positive full-scale input voltage
that results in a code of 111 … 111. The output code for any
analog input voltage is represented with the following equation:
AVDD = 3V
ABSOLUTE MAXIMUM RATING
+65V
NO DAMAGE TO DEVICE
+19V
+12V
NO LOSS OF ACCURACY ON OTHER CHANNELS
Code = 2N – 1 × ((VIN × ꢀ.1ꢂVREF) + 1)
GUARANTEED ACCURACY
AD4114 REFERENCE OPTIONS
–12V
–17V
The AD4114 provides the reference option of either supplying an
external reference to the REF+ and REF− device pins using
AꢁDD – AꢁSS as the reference, or allowing use of the internal
2.5 ꢁ, low noise, low drift reference. To select the reference
source to be used by the analog input, set the REF_SELx bits,
Bits[5:4], in the corresponding setup configuration register
appropriately. The structure of the Setup Configuration Register ꢀ
is shown in Table 29. By default, the AD4114 uses an external
reference on power-up.
NO LOSS OF ACCURACY ON OTHER CHANNELS
NO DAMAGE TO DEVICE
–65V
ABSOLUTE MAXIMUM RATING
Figure 27. Absolute Input Pin Voltages, AVDD = 3 V
Rev. 0 | Page 21 of 49
AD4114
Data Sheet
purposes. The output is connected to a 4.7 ꢃF capacitor that
acts as a reservoir for any dynamic charge required by the ADC
and is followed by another ꢀ.1 ꢃF decoupling capacitor at the
REF+ input. This capacitor is placed as close as possible to the
REF+ and REF− pins.
Internal Reference
The AD4114 includes a low noise, low drift, internal voltage
reference that has a 2.5 ꢁ output. The internal reference is output
on the REFOUT pin after the REF_EN bit in the ADC mode
register is set and is decoupled to AꢁSS with a ꢀ.1 ꢃF capacitor.
The AD4114 internal reference is disabled by default on power-up.
The REF− pin is connected directly to the AꢁSS potential. When
an external reference is used instead of the internal reference to
supply the AD4114, ensure that the REFOUT pin is not hardwired
to AꢁSS, which can draw a large current on power-up. The
internal reference is controlled by the REF_EN bit (Bit 15) in the
ADC mode register, as shown in Table 14. If the internal reference
is not used elsewhere in the application, ensure that the
REF_EN bit is disabled.
External Reference
The AD4114 has a fully differential reference input applied
through the REF+ and REF− pins. Standard low noise, low drift
voltage references, such as the ADR4525, are recommended for
this use. Apply the external reference to the AD4114 reference
pins, as shown in Figure 29. Decouple the output of any external
reference to AꢁSS. As shown in Figure 29, the ADR4525 output
is decoupled with a ꢀ.1 ꢃF capacitor at the output for stability
AD4114
3V TO 18V
ADR45252
REF+
REF–
40
39
0.1µF
2.5V VREF
1
0.1µF
0.1µF
4.7µF
1
1
1
1
1
2
ALL DECOUPLING IS TO AVSS.
ANY OF THE ADR45x FAMILY REFERENCES CAN BE USED.
ADR4525 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY
NEEDED FOR AVDD TO POWER THE REFERENCE V
.
IN
Figure 29. ADR4525 Connected to AD4114 REF+ and REF− Pins
Rev. 0 | Page 22 of 49
Data Sheet
AD4114
External Crystal
BUFFERED REFERENCE INPUT
If higher precision, lower jitter clock sources are required, the
AD4114 can use an external crystal to generate the master clock.
The crystal connects to the XTAL1 and XTAL2ꢂCLKIO pins. The
FA-2ꢀH, a 16 MHz, 1ꢀ ppm, 9 pF crystal from Epson-Toyocom
is available in a surface-mount package and is acceptable for
this use. As shown in Figure 3ꢀ, insert two capacitors (CX1 and
CX2) from the traces connecting the crystal to the XTAL1 and
XTAL2ꢂCLKIO pins. These capacitors allow circuit tuning.
Connect these capacitors to the DGND pin. The value for these
capacitors depends on the length and capacitance of the trace
connections between the crystal and the XTAL1 and XTAL2ꢂ
CLKIO pins. Therefore, the values of these capacitors differ
depending on the PCB layout and the crystal used.
The AD4114 has true rail-to-rail, integrated, precision unity-gain
buffers on both ADC reference inputs. The buffers provide high
input impedance and allow high impedance external sources to
be directly connected to the reference inputs. The integrated
reference buffers can fully drive the internal reference switch
capacitor sampling network to simplify the reference circuit
requirements. Each reference input buffer amplifier is fully
chopped and minimizes the offset error drift and 1ꢂf noise of the
buffer. When using a voltage reference, such as the ADR4525,
these buffers are not required because the reference has proper
decoupling and can drive the reference inputs directly.
CLOCK SOURCE
The AD4114 uses a nominal master clock of 2 MHz and can
source the device sampling clock from one of the following
three sources:
AD4114
1
CX1
12
13
XTAL1
An internal oscillator.
An external crystal. Use a 16 MHz crystal automatically
divided internally to set the 2 MHz clock.
An external clock source.
XTAL2/CLKIO
CX2
1
1
DECOUPLE TO DGND
All output data rates listed in this data sheet relate to a master clock
rate of 2 MHz. Using a lower clock frequency from, for instance,
an external source scales any listed data rate proportionally. To
achieve the specified data rates, particularly rates for rejection
of 5ꢀ Hz and 6ꢀ Hz, use a 2 MHz clock. To select the master
clock source, set the CLOCKSEL bits (Bits[3:2]) in the ADC
mode register, as shown in Table 14. The default operation on
power-up and reset of the AD4114 is to operate with the internal
oscillator. The user can use the SINC3_MAPx bits in the filter
configuration registers to fine tune the output data rate and
filter notch at low output data rates.
Figure 30. External Crystal Connections
The external crystal circuitry can be sensitive to the SCLK edges
depending on the SCLK frequency, IOꢁDD voltage, crystal
circuitry layout, and the crystal used. During crystal startup,
any disturbances caused by the SLCK edges can cause double
edges on the crystal input, which results in invalid conversions
until the crystal voltage reaches a high enough level such that
any interference from the SCLK edges is insufficient to cause
double clocking. To avoid this double clocking, ensure that the
crystal circuitry reaches a sufficient voltage level after startup
before applying any serial clocks.
Internal Oscillator
Because of the nature of the crystal circuitry, it is recommended
to perform empirical testing of the circuit under the required
conditions with the final PCB layout and crystal to ensure
correct operation.
The internal oscillator runs at 16 MHz and is internally divided
down to 2 MHz for the modulator. The internal oscillator can
be used as the ADC master clock and is the default clock source
for the AD4114, which is specified with an accuracy of −2.5% to
+2.5%.
External Clock
The AD4114 can also use an externally supplied clock. In systems
where an externally supplied clock is used, the external clock is
routed to the XTAL2ꢂCLKIO pin. In this configuration, the
XTAL2ꢂCLKIO pin accepts the externally sourced clock and
routes the clock input to the modulator. The logic level of this
clock input is defined by the voltage applied to the IOꢁDD pin.
The internal clock oscillator can be output on the XTAL2ꢂ
CLKIO pin. In this case, the clock output is driven to the
IOꢁDD logic level. This option can affect the dc AD4114
performance because of the disturbance introduced by the
output driver. The extent to which the performance is affected
depends on the IOꢁDD voltage supply. Higher IOꢁDD
voltages create a wider logic output swing from the driver and
affect performance to a greater extent. This effect is further
exaggerated if the IOSTRENGTH bit of the interface mode
register is set at higher IOꢁDD levels (see Table 23).
Rev. 0 | Page 23 of 49
AD4114
Data Sheet
DꢂGꢂTAL FꢂLTER
The AD4114 has the following three flexible filter options to
optimize noise, settling time, and rejection:
SINC3 FILTER
The sinc3 filter achieves optimal single-channel noise performance
at lower rates and is most suitable for single-channel applications.
The sinc3 filter always has a settling time (tSETTLE) equal to the
following equation:
The sinc5 + sinc1 filter.
The sinc3 filter.
Enhanced 5ꢀ Hz and 6ꢀ Hz rejection filters.
t
SETTLE = 3ꢂOutput Data Rate
50Hz AND 60Hz
POSTFILTER
Figure 33 shows the frequency domain filter response for the
sinc3 filter. The sinc3 filter has fast roll-off over frequency and
has wide notches for optimal notch frequency rejection.
SINC1
SINC5
SINC3
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
Figure 31. Digital Filter Block Diagram
To configure the filter and output data rate, set the appropriate
bits in the filter configuration register for the selected setup. Each
channel can use a different setup and, therefore, a different
filter and output data rate. See the Register Details section for
more information.
SINC5 + SINC1 FILTER
The sinc5 + sinc1 filter is targeted at multiplexed applications
and achieves single-cycle settling at output data rates of ≤2.6 kSPS.
The sinc5 block output is fixed at the maximum rate of 31.25 kSPS,
and the sinc1 block output data rate can be varied to control the
final ADC output data rate. Figure 32 shows the frequency
domain response of the sinc5 + sinc1 filter at a 5ꢀ SPS output data
rate. The sinc5 + sinc1 filter has narrow notches and a slow roll-off
over frequency.
–120
0
50
100
FREQUENCY (Hz)
150
Figure 33. Sinc3 Filter Response
The output data rates with the accompanying settling time and
rms noise for the sinc3 filter are shown in Table 17. To fine tune
the output data rate for the sinc3 filter, set the SINC3_MAPx bit in
the appropriate filter configuration register. If this bit is set, the
filter register mapping changes to directly program the sinc3 filter
decimation rate. All other options are eliminated. To calculate
the data rate when on a single channel, use the following
equation:
0
–20
–40
–60
Output Data Rate = fMODꢂ(32 × FILTCONx[14:0])
–80
where:
f
MOD is the modulator rate (MCLKꢂ2) and is equal to 1 MHz.
–100
–120
FILTCONx[14:0] is the contents of the filter configuration
registers with the MSB excluded.
For example, to achieve an output data rate of 5ꢀ SPS with the
SINC3_MAPx bit enabled, set the FILTCONx register,
Bits[14:ꢀ], to a value of 625.
0
50
100
FREQUENCY (Hz)
150
Figure 32. Sinc5 + Sinc1 Filter Response at 50 SPS ODR
The output data rates with the accompanying settling time and
rms noise for the sinc5 + sinc1 filter are shown in Table 16.
Rev. 0 | Page 24 of 49
Data Sheet
AD4114
ANALOG
INPUT
SINGLE-CYCLE SETTLING MODE
FULLY
SETTLED
To configure the AD4114 to be in a single-cycle settling mode,
set the SING_CYC bit in the ADC mode register so that only fully
settled data is output. This mode reduces the output data rate to
be equal to the ADC settling time for the selected output data rate
to achieve single-cycle settling. This bit has no effect on the sinc5 +
sinc1 filter at output data rates of ≤1ꢀ kSPS or when multiple
channels are enabled.
ADC
OUTPUT
tSETTLE
Figure 35. Step Input with Single Cycle Settling
ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS
The enhanced filters provide rejection of 5ꢀ Hz and 6ꢀ Hz
simultaneously and allow the user to trade off settling time and
rejection. These filters can operate at up to 27.27 SPS or reject
up to 9ꢀ dB of 5ꢀ Hz 1 Hz and 6ꢀ Hz 1 Hz interference. These
filters postfilter the output of the sinc5 + sinc1 filter to operate.
For this reason, the user must select the sinc5 + sinc1 filter when
using the enhanced filters to achieve the specified settling time and
noise performance. Table 18 shows the enhanced filter output
data rates with the accompanying settling time, rejection, and
voltage input rms noise and resolution. Figure 36 to Figure 43
show the frequency domain plots of the responses from the
enhanced filters.
Figure 34 shows a step on the analog input with single-cycle
settling mode disabled and the sinc3 filter selected. The analog
input requires at least three cycles after the step change for the
output to reach the final settled value.
ANALOG
INPUT
FULLY
SETTLED
ADC
OUTPUT
1/ODR
Figure 34. Step Input Without Single Cycle Settling
Figure 35 shows the same step on the analog input with single-
cycle settling enabled. The analog input requires at least a single
cycle for the output to be fully settled. The output data rate, as
RDY
indicated by the
signal, reduces to equal the settling time
of the filter at the selected output data rate.
Table 18. Enhanced Filter Output Data Rate, Settling Time, Rejection, and Voltage Input Noise
Output Data
Rate (SPS)
Settling Time Simultaneous Rejection of 50 Hz Noise
Peak-to-Peak
Resolution (Bits)
(ms)
36.67
40.0
50.0
60.0
1 Hz and 60 Hz 1 Hz (dB)1
47
(μV rms)
Comments
27.27
25
20
6.44
6.09
5.54
5.38
19.1
19.2
19.35
19.51
See Figure 36 and Figure 39
See Figure 37 and Figure 40
See Figure 38 and Figure 41
See Figure 42 and Figure 43
62
85
90
16.667
1 Master clock = 2.00 MHz.
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–100
0
100
200
300
400
500
600
0
100
200
300
400
500
600
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 36. 27.27 SPS ODR, 36.67 ms Settling Time
Figure 37. 25 SPS ODR, 40 ms Settling Time
Rev. 0 | Page 25 of 49
AD4114
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–100
100
200
300
400
500
600
40
45
50
55
60
65
70
600
70
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 38. 20 SPS ODR, 50 ms Settling Time
Figure 41. 20 SPS ODR, 50 ms Settling Time (40 Hz to 70 Hz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–100
40
45
50
55
60
65
70
0
100
200
300
400
500
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 39. 27.27 SPS ODR, 36.67 ms Settling Time (40 Hz to 70 Hz)
Figure 42. 16.667 SPS ODR, 60 ms Settling Time
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–100
40
45
50
55
60
65
70
40
45
50
55
60
65
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 40. 25 SPS ODR, 40 ms Settling Time (40 Hz to 70 Hz)
Figure 43. 16.667 SPS ODR, 60 ms Settling Time (40 Hz to 70 Hz)
Rev. 0 | Page 26 of 49
Data Sheet
AD4114
OPERATꢂNG MODES
The AD4114 has nine operating modes that can be set from the
ADC mode register and interface mode register (see Table 22
and Table 23). These modes include the following:
serial clocks are applied to the AD4114 to read the data-word,
the serial output register resets shortly before the next
conversion is complete and the new conversion is placed in the
output serial register. The ADC must be configured for
continuous conversion mode to use continuous read mode. To
enable continuous read mode, set the CONTREAD bit in the
interface mode register. When this bit is set, the only serial
interface operations possible are reads from the data register.
To exit continuous read mode, issue a dummy read of the ADC
Continuous conversion mode
Continuous read mode
Single conversion mode
Standby mode
Power-down mode
Four calibration modes
RDY
data register command (ꢀx44) while the
output is low.
CS
Alternatively, apply a software reset (64 serial clocks with
=
CONTINUOUS CONVERSION MODE
ꢀ and DIN = 1) to reset the ADC and all register contents. The
dummy read and the software reset are the only commands that
the interface recognizes after the interface is placed in
continuous read mode. Hold DIN low in continuous read mode
until an instruction is to be written to the device.
Continuous conversion mode is the default power-up mode
(see Figure 44). The AD4114 converts continuously and the
RDY
bit in the status register goes low each time a conversion is
CS
RDY
output also goes low when a
complete. If
is low, the
conversion is complete. To read a conversion, write to the
communications register to indicate that the next operation is a
read of the data register. When the data-word is read from the
If multiple ADC channels are enabled, each channel is output
in turn with the status bits appended to the data if the DATA_
STAT bit is set in the interface mode register. The four LSBs of
the status register indicate the channel to which the conversion
corresponds.
RDY
data register, the DOUTꢂ
pin goes high. The user can read
this register additional times, if required. However, ensure that
the data register is not accessed at the completion of the next
conversion. Otherwise, the new conversion word is lost.
SINGLE CONVERSION MODE
When several channels are enabled, the ADC automatically
sequences through the enabled channels and performs one
conversion on each channel. When all channels are converted,
the sequence starts again with the first channel. The channels
are converted in order from the lowest enabled channel to the
highest enabled channel. The data register updates as soon as
In single conversion mode (see Figure 46), the AD4114
performs a single conversion and is placed in standby mode
RDY
when the conversion is complete. The
indicate the completion of a conversion. When the data-word is
RDY
output goes low to
read from the data register, the
register can be read several times, if required, even when the
RDY
output goes high. The data
RDY
each conversion is available. The
output pulses low each
output goes high.
time a conversion is available, and the user can then read the
conversion while the ADC converts the next enabled channel.
If several channels are enabled, the ADC automatically sequences
through the enabled channels and performs a conversion on each
If the DATA_STAT bit in the interface mode register is set to 1,
the conversion data and the contents of the status register are
output each time the data register is read. The four LSBs of the
status register indicate the channel to which the conversion
corresponds.
RDY
channel. When the first conversion starts, the
output goes
CS
high and remains high until a valid conversion is available and
RDY
is low. When the conversion is available, the
output goes low
and the ADC selects the next channel and begins a conversion.
The user can read the present conversion while the next
conversion is performed. When the next conversion is
complete, the data register updates, which allows the user a
limited period in which to read the conversion. When the ADC
performs a single conversion on each selected channel, the ADC
returns to standby mode.
CONTINUOUS READ MODE
In continuous read mode (see Figure 45), it is not required to
write to the communications register before reading ADC data.
RDY
Apply only the required number of serial clocks after the
output goes low to indicate the end of a conversion. When the
RDY
If the DATA_STAT bit in the interface mode register is set to 1,
the contents of the status register and the conversion are output
each time the data register is read. The four LSBs of the status
register indicate the channel to which the conversion
corresponds.
conversion is read, the
output returns high until the next
conversion is available. In this mode, the data can be read only
once. Ensure that the data-word is read before the next
conversion is complete. If the user has not read the conversion
before the completion of the next conversion, or if insufficient
Rev. 0 | Page 27 of 49
AD4114
Data Sheet
CS
0x44
0x44
DIN
DATA
DATA
DOUT/RDY
SCLK
Figure 44. SPI Communication in Continuous Conversion Mode
CS
0x02
0x0080
DIN
DATA
DATA
DATA
DOUT/RDY
SCLK
Figure 45. SPI Communication in Continuous Read Mode
CS
0x01
0x8010
0x44
DIN
DATA
DOUT/RDY
SCLK
Figure 46. SPI Communication in Single Conversion Mode
Rev. 0 | Page 28 of 49
Data Sheet
AD4114
When the calibration is complete, the contents of the
STANDBY MODE AND POWER-DOWN MODE
RDY
corresponding offset or gain register update, the
bit in the
CS
is
In standby mode, most blocks are powered down. The LDO
regulators remain active so that the registers maintain the
individual register contents. The crystal oscillator remains
active if selected. To power down the clock in standby mode,
set the CLOCKSEL bits in the ADC mode register to ꢀꢀ
(internal oscillator).
RDY
status register resets, the
output pin returns low (if
low), and the AD4114 reverts to standby mode.
During an internal offset calibration, both modulator inputs are
connected internally to the selected negative analog input pin,
and the user must ensure that the voltage on the selected negative
analog input pin does not exceed the allowed limits and is free
from excessive noise and interference. A full-scale input voltage
automatically connects to the ADC input to perform an
internal full-scale calibration.
In power-down mode, all blocks are powered down, including
the LDO regulators. All registers lose the individual register
contents and the GPIO outputs are placed in three-state. To
prevent accidental entry into power-down mode, place the
ADC in standby mode first. Exiting power-down mode requires a
For system calibrations, apply the system zero-scale (offset) and
system full-scale (gain) voltages to the input pins before initiating
the calibration modes. As a result, errors external to the AD4114
are removed. The calibration range of the ADC gain for a system
full-scale calibration on a voltage input is from 3.75 × ꢁREF to
1ꢀ.5 × ꢁREF. If 1ꢀ.5 × ꢁREF is greater than the absolute input voltage
specification for the applied AꢁDD, use the specification as the
upper limit instead of 1ꢀ.5 × ꢁREF (see the Specifications section).
CS
serial interface reset (64 serial clocks with
= ꢀ and DIN = 1).
A delay of 5ꢀꢀ μs is recommended before issuing a subsequent
serial interface command to allow the LDO regulator to power up.
CALIBRATION MODES
The AD4114 allows the user to perform a two-point calibration
to eliminate any offset and gain errors. The following four
calibration modes are used to eliminate these offset and gain errors
on a per setup basis:
An internal zero-scale calibration only removes the offset error
of the ADC core. This calibration does not remove error from
the resistive front end. A system zero-scale calibration reduces
the offset error to the order of the noise on that channel.
Internal zero-scale calibration mode
Internal full-scale calibration mode
System zero-scale calibration mode
System full-scale calibration mode
From an operational point of view, treat a calibration like another
ADC conversion. Always perform an offset calibration, if required,
before a full-scale calibration. Set the system software to monitor
Only one channel can be active during calibration. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
RDY
RDY
the
bit in the status register or the
output to determine
the end of a calibration via a polling sequence or an interrupt
driven routine. All calibrations require a time equal to the settling
time of the selected filter and output data rate to be completed.
The default value of the offset register is ꢀx8ꢀꢀꢀꢀꢀ, and the
default value of the gain register is ꢀx5XXXXꢀ. The following
equations show the calculations used to scale the ADC conversion
result. In unipolar mode, the ideal relationship (not considering
the ADC gain error and offset error) is calculated as follows:
Any calibration can be performed at any output data rate.
Lower output data rates result in higher calibration accuracy
and the calibration is accurate for all output data rates. A new
offset calibration is required for a given channel if the reference
source for that channel is changed.
Data = ((ꢀ.ꢀ75 × VINꢂVREF) × 223 – (Offset − ꢀx8ꢀꢀꢀꢀꢀ)) ×
(Gainꢂꢀx4ꢀꢀꢀꢀꢀ) × 2
The AD4114 provides access to the on-chip offset and gain
calibration registers to allow the microprocessor to read the
device calibration coefficients and to write the stored calibration
coefficients. A read or write of the offset and gain registers can be
performed at any time except during an internal or self calibration.
In bipolar mode, the ideal relationship (not considering the
ADC gain error and offset error) is calculated as follows:
Data = ((ꢀ.ꢀ75 × VINꢂVREF) × 223 – (Offset − ꢀx8ꢀꢀꢀꢀꢀ)) ×
(Gainꢂꢀx4ꢀꢀꢀꢀꢀ) + ꢀx8ꢀꢀꢀꢀꢀ
To start a calibration, write the relevant value to the Mode bits
RDY
in the ADC mode register, Bits[6:4]. The DOUTꢂ
RDY
pin and the
bit in the status register go high when the calibration initiates.
Rev. 0 | Page 29 of 49
AD4114
Data Sheet
DꢂGꢂTAL ꢂNTERFACE
The programmable functions of the AD4114 are accessible via
CHECKSUM PROTECTION
CS
the SPI. The serial interface consists of four signals: , DIN,
The AD4114 has a checksum mode that can be used to improve
interface robustness. Use the checksum to ensure that only
valid data is written to a register and to allow the data read
from a register to be validated. If an error occurs during a
register write, the CRC_ERROR bit is set in the status register.
To ensure that the register write is complete, read back the
register and verify the checksum.
RDY
SCLK, and DOUTꢂ
. The DIN line transfers data into the
on-chip registers. The DOUT output accesses data from the on-
chip registers. SCLK is the serial clock input for the device. All
data transfers (either on DIN or on DOUT) occur with respect to
the SCLK signal.
RDY
The DOUTꢂ
pin also functions as a data ready signal where
CS
the line goes low if
in the data register. The pin resets high when a read operation
RDY
is low when a new data-word is available
For CRC checksum calculations during a write operation, the
following polynomial is always used:
from the data register is complete. The
output also goes high
x8 + x2 + x + 1
before updating the data register to indicate when not to read from
the device to ensure that a data read is not attempted while the
register is updated. Take care to avoid reading from the data
During read operations, the user can select between this
polynomial and a similar exclusive OR (XOR) function.
The XOR function requires less time to process on the host
microcontroller than the polynomial-based checksum. The
CRC_EN bits in the interface mode register enable and disable
the checksum and allow the user to select between the polynomial
checksum and the simple XOR checksum.
RDY
register when the
data read occurs, always monitor the
RDY
signal is about to go low. To ensure that no
RDY
output. Start reading the
goes low and ensure a sufficient
SCLK rate such that the read is completed before the next
data register as soon as
CS
conversion result. is used to select a device and can be used to
The checksum is appended to the end of each read and write
transaction. The checksum calculation for the write transaction is
calculated using the 8-bit command word and the 8-bit to 24-bit
data. For a read transaction, the checksum is calculated using the
command word and the 8-bit to 32-bit data output. Figure 22
and Figure 23 show SPI write and read transactions, respectively.
decode the AD4114 in systems where several components are
connected to the serial bus.
The timing diagrams in Figure 2 and Figure 3 show interfacing
CS
to the AD4114 using
to decode the device. Figure 2 shows
the timing for a read operation from the AD4114 and Figure 3
shows the timing for a write operation to the AD4114. The user
If checksum protection is enabled when continuous read mode
is active, an implied read data command of ꢀx44 occurs before
each data transmission, which must be accounted for when
calculating the checksum value. The checksum protection ensures
a nonzero checksum value even if the ADC data equals ꢀxꢀꢀꢀꢀꢀꢀ.
RDY
can read from the data register several times even though the
output returns high after the first read operation. Ensure that
the read operations are complete before the next output update
occurs. In continuous read mode, the data register can be read
only once.
CS
To operate the serial interface in 3-wire mode, tie
low. In
lines are used to
communicate with the AD4114. The end of the conversion can
RDY
RDY
this case, the SCLK, DIN, and DOUTꢂ
also be monitored using the
bit in the status register.
CS
To reset the serial interface, write 64 serial clocks with
= ꢀ
and DIN = 1. A reset returns the interface to the state in which the
interface expects a write to the communications register. This
operation resets the contents of all registers to the power-on
values. Following a reset, wait 5ꢀꢀ μs before addressing the serial
interface.
Rev. 0 | Page 30 of 49
Data Sheet
AD4114
MSB is adjacent to the leftmost Logic 1 of the new result and
CRC CALCULATION
the procedure is repeated. This process is repeated until the
original data is reduced to a value less than the polynomial.
This value is the 8-bit checksum.
Polynomial
The checksum, which is eight bits wide, is generated using the
following polynomial:
Example of a Polynomial CRC Calculation—24-Bit Word:
0x654321 (Eight Command Bits and 16-Bit Data)
x8 + x2 + x + 1
To generate the checksum, the data is left shifted by eight bits
to create a number ending in eight Logic ꢀs. The polynomial is
aligned so that the MSB is adjacent to the leftmost Logic 1 of
the data. An XOR function is applied to the data to produce a
new, shorter number. The polynomial is aligned again so that the
An example of generating the 8-bit checksum using the
polynomial-based checksum is as follows:
Initial value
011001010100001100100001
01100101010000110010000100000000
100000111
left shifted eight bits
polynomial
x8 + x2 + x + 1 =
100100100000110010000100000000
100000111
XOR result
polynomial
100011000110010000100000000
100000111
XOR result
polynomial
11111110010000100000000
100000111
XOR result
polynomial value
XOR result
1111101110000100000000
100000111
polynomial value
XOR result
111100000000100000000
100000111
polynomial value
XOR result
11100111000100000000
100000111
polynomial value
XOR result
1100100100100000000
100000111
polynomial value
XOR result
100101010100000000
100000111
polynomial value
XOR result
101101100000000
100000111
polynomial value
XOR result
1101011000000
100000111
polynomial value
XOR result
101010110000
100000111
polynomial value
XOR result
1010001000
100000111
polynomial value
checksum = 0x86.
10000110
Rev. 0 | Page 31 of 49
AD4114
Data Sheet
01100101
01000011
00100110
00100001
00000111
0x65
XOR Calculation
0x43
The checksum, which is eight bits wide, is generated by splitting
the data into bytes and then performing an XOR of the bytes.
XOR result
0x21
Example of an XOR Calculation—24-Bit Word: 0x654321
(Eight Command Bits and 16-Bit Data)
CRC
Using the previous polynomial example, divide the checksum
into three bytes (ꢀx65, ꢀx43, and ꢀx21) which results in the
following XOR calculation:
Rev. 0 | Page 32 of 49
Data Sheet
AD4114
ꢂNTEGRATED FUNCTꢂONS
GENERAL-PURPOSE INPUTꢀOUTPUT
DOUT_RESET
The AD4114 has two general-purpose digital inputꢂoutput pins
(GPIOꢀ and GPIO1) and two general-purpose digital output pins
(GPO2 and GPO3). The GPIOꢀ and GPIO1 pins can be
configured either as inputs or as outputs, but GPO2 and GPO3
are outputs only. To enable the GPIOx and GPOx pins, use the
following bits in the GPIOCON register: IP_ENꢀ and IP_EN1
(or OP_ENꢀ and OP_EN1) for GPIOꢀ and GPIO1, and
OP_EN2_3 for GPO2 and GPO3.
RDY
pin. By default, this
The serial interface uses a shared DOUTꢂ
RDY
pin outputs the
the data from the register being read. When the read is complete,
RDY
signal. During a data read, this pin outputs
the pin reverts to output the
signal after a short, fixed period
of time (t7). Note that this time may be too short for some
CS
microcontrollers and can be extended until the pin is brought
high. Set the DOUT_RESET bit in the interface mode register to 1
CS
to extend the time and require that
must frame each read
When the GPIOꢀ or GPIO1 pin is enabled as an input, the logic
level at the pin is contained in the GP_DATAꢀ bit or
operation and complete the serial interface transaction.
SYNCHRONIZATION
Normal Synchronization
GP_DATA1 bit of the GPIOCON register, respectively. When
the GPIOꢀ, GPIO1, GPO2, or GPO3 pin is enabled as an
output, the GP_DATAꢀ, GP_DATA1, GP_DATA2, or
GP_DATA3 bit, respectively, determines the logic level output
at the pin. The logic levels for these pins are referenced to
AꢁDD and AꢁSS, and the outputs have an amplitude of either
5 ꢁ or 3.3 ꢁ, depending on the AꢁDD − AꢁSS voltage.
When the SYNC_EN bit in the GPIOCON register is set to 1,
SYNC
the
SYNC
pin functions as a synchronization input pin. The
input allows the user to reset the modulator and the
digital filter without affecting any setup conditions on the device.
This reset allows the user to start gathering samples of the
SYNC
analog input from a known point in time, that is, the
ERROR
The
pin can also be used as a general-purpose output if
rising edge. This pin must be low for at least one master clock
cycle to ensure that synchronization occurs. If multiple channels
are enabled, the sequencer is reset to the first enabled channel.
the ERR_EN bits in the GPIOCON register are set to 11. In this
configuration, the ERR_DAT bit in the GPIOCON register
ERROR
determines the logic level output at the
level for the pin is referenced to IOꢁDD and DGND, and the
ERROR
pin. The logic
If multiple AD4114 devices are operated from a common master
clock, the devices can be synchronized so that the corresponding
data registers are updated simultaneously. Synchronization is
typically completed after each AD4114 performs a calibration or
when calibration coefficients are loaded into the device calibration
pin has an active pull-up.
EXTERNAL MULTIPLEXER CONTROL
If an external multiplexer is used to increase the channel count,
the multiplexer logic pins can be controlled using the AD4114
GPIOx and GPOx pins. When the MUX_IO bit is set in the
GPIOCON register, the timing of the GPIOx pins is controlled by
the ADC and the channel change is synchronized with the
ADC, which eliminates any need for external synchronization.
SYNC
registers. A falling edge on the
and the analog modulator and places the AD4114 into a consistent
SYNC
pin resets the digital filter
known state. While the
SYNC
pin is low, the AD4114 remains
rising edge, the modulator and filter
in this state. On the
are taken out of this reset state and the device starts to gather
input samples again on the next master clock edge.
DELAY
The user can insert a programmable delay before the AD4114
starts to take samples. This delay allows an external amplifier or
multiplexer to settle and alleviates the specification requirements
for the external amplifier or multiplexer. Eight programmable
settings, ranging from ꢀ μs to 8 ms, can be set using the delay bits
in the ADC mode register (Register ꢀxꢀ1, Bits[1ꢀ:8]).
The device exits reset on the master clock falling edge following
SYNC
the
are synchronized, take the
rising edge to ensure that all devices begin sampling on the
SYNC
low to high transition. Therefore, when multiple devices
SYNC
pin high on the master clock
master clock falling edge. If the
pin is not taken high in
sufficient time, a difference can occur of one master clock cycle
between the devices. That is, the instant at which conversions
are available differs from device to device by a maximum of one
master clock cycle.
16-BIT AND 24-BIT CONVERSIONS
By default, the AD4114 generates 24-bit conversions. However,
the width of the conversions can be reduced to 16 bits. Set
Bit WL16 in the interface mode register to 1 to round all data
conversions to 16 bits. Clear this bit to set the width of the data
conversions to 24 bits.
SYNC
The
input can also be used as a start conversion command
for a single channel when in normal synchronization mode. In
SYNC
this mode, the rising edge of the
RDY
input starts a conversion
and the falling edge of the
output indicates when the
conversion is complete. The settling time of the filter is required
for each data register update. When the conversion is complete,
SYNC
bring the
start signal.
input low in preparation for the next conversion
Rev. 0 | Page 33 of 49
AD4114
Data Sheet
Alternate Synchronization Mode
ERROR
Input/Output
SYNC
In alternate synchronization mode, the
input operates as a
ERROR
The
pin functions as an error inputꢂoutput pin or as a
start conversion command when several AD4114 channels are
enabled. Set the ALT_SYNC bit in the interface mode register to 1
to enable an alternate synchronization scheme. When the
general-purpose output pin. The ERR_EN bits in the GPIOCON
register determine the function of the pin.
ERROR
When the ERR_EN bits are set to 1ꢀ, the
pin functions
SYNC
input is taken low, the ADC completes the conversion
on the enabled channel, selects the next channel in the sequence,
SYNC
as an open-drain error output. The three error bits in the status
register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are
and then waits until the
input is taken high to start the
output goes low when the conversion is
complete on the current channel and the data register is updated
SYNC
ERROR
OR’ed, inverted, and mapped to the
ERROR
output. Therefore, the
output indicates that an error has occurred. Read the
status register to identify the error source.
ERROR
RDY
conversion. The
with the corresponding conversion. The
input does not
When the ERR_EN bits are set to ꢀ1, the
as an error input. The error output of another component can
ERROR
pin functions
interfere with the sampling on the currently selected channel
but allows the user to control the instant at which the conversion
begins on the next channel in the sequence.
be connected to the AD4114
indicates when an error occurs on either the device or the external
ERROR
input so that the AD4114
Alternate synchronization mode can only be used when several
channels are enabled. Do not use this mode when a single
channel is enabled.
component. The value on the
input is inverted and
OR’ed with the errors from the ADC conversion, and the result
is indicated via the ADC_ERROR bit in the status register. The
ERROR FLAGS
ERROR
value of the
the GPIO configuration register.
ERROR
input is reflected in the ERR_DAT bit in
The status register contains three error bits (ADC_ERROR,
CRC_ERROR, and REG_ERROR) that flag errors in the ADC
conversion, errors in the CRC check, and errors caused by
The
inputꢂoutput is disabled when the ERR_EN bits are
ERROR
set to ꢀꢀ. When the ERR_EN bits are set to 11, the
pin
ERROR
changes in the registers, respectively. The
also indicate that an error has occurred.
output can
operates as a general-purpose output where the ERR_DAT bit
determines the logic level of the pin.
ADC_ERROR
DATA_STAT FUNCTION
The ADC_ERROR bit in the status register flags any errors that
occur during the conversion process. The flag is set when an
overrange or underrange result is output from the ADC. The ADC
also outputs all ꢀs or all 1s when an undervoltage or overvoltage
occurs, respectively. This flag only resets when the overvoltage or
undervoltage is removed. This flag is not reset by a read of the data
register.
The contents of the status register can be appended to each
conversion on the AD4114 using the DATA_STAT bit in the
IFMODE register. This function is useful if several channels are
enabled. Each time a conversion is output, the contents of the
status register are appended. The four LSBs of the status register
indicate to which channel the conversion corresponds. In addition,
the user can determine if any errors are flagged by the error bits.
CRC_ERROR
IOSTRENGTH FUNCTION
If the CRC value that accompanies a write operation does not
correspond with the information sent, the CRC_ERROR flag is
set. The flag resets as soon as the status register is explicitly read.
The serial interface can operate with a power supply as low as
RDY
2 ꢁ. However, at this low voltage, the DOUTꢂ
pin may not
have sufficient drive strength if there is moderate parasitic
capacitance on the PCB or if the SCLK frequency is high. The
IOSTRENGTH bit in the interface mode register increases the
REG_ERROR
The REG_ERROR flag is used in conjunction with the
REG_CHECK bit in the interface mode register. When the
REG_CHECK bit is set, the AD4114 monitors the values in the on-
chip registers. If a bit changes, the REG_ERROR bit is set to 1.
For writes to the on-chip registers, set the REG_CHECK bit to
ꢀ. When the registers are updated, the REG_CHECK bit can be
set to 1. The AD4114 calculates a checksum of the on-chip
registers. If one register value has changed, the REG_ERROR bit is
set to 1. If an error is flagged, set the REG_CHECK bit to ꢀ to clear
the REG_ERROR bit in the status register. The register check
function does not monitor the data register, status register, or
interface mode register.
RDY
drive strength of the DOUTꢂ
pin.
Rev. 0 | Page 34 of 49
Data Sheet
AD4114
The temperature sensor requires the input buffers to be enabled on
both inputs and for the internal reference to be enabled.
INTERNAL TEMPERATURE SENSOR
The AD4114 has an integrated temperature sensor that can be
used as a guide for the ambient temperature at which the device
is operating. The ambient temperature can be used for
diagnostic purposes or as an indicator of when the application
circuit must rerun a calibration routine to consider a shift in
operating temperature. Select the temperature sensor using the
multiplexer in the same way as an input channel.
To use the temperature sensor, calibrate the device in a known
temperature (25/C) and take a conversion as a reference point. The
temperature sensor has a nominal sensitivity of 477 ꢃꢁꢂK. The
difference in this ideal slope and the slope measured calibrates
the temperature sensor. The temperature sensor is specified with
a
2/C typical accuracy after calibration at 25/C. Calculate the
temperature with the following equation:
Temperature = (Conversion Resultꢂ477 μꢁ) − 273.15
Rev. 0 | Page 35 of 49
AD4114
Data Sheet
APPLꢂCATꢂONS ꢂNFORMATꢂON
lines to the AD4114 must use as wide a trace as possible to provide
low impedance paths and reduce glitches on the power supply
line. Shield the fast switching signals, such as clocks, with digital
ground to prevent radiating noise to other sections of the PCB and
never run clock signals near the inputs. Avoid digital and
analog signal crossover. Run traces on opposite sides of the PCB at
right angles to each other. This layout reduces the effects of
feedthrough on the PCB. A microstrip technique is optimal but is
not always possible with a double sided PCB. In this technique, the
component side of the PCB is dedicated to ground planes and
signals are placed on the solder side.
GROUNDING AND LAYOUT
The inputs and reference inputs are differential and most voltages
in the analog modulator are common-mode voltages. The high
common-mode rejection of the device removes common-mode
noise on these inputs. The analog and digital supplies to the
AD4114 are independent and separately pinned out to minimize
coupling between the analog and digital sections of the device. The
digital filter provides rejection of broadband noise on the power
supplies, except at integer multiples of the master clock frequency.
The digital filter also removes noise from the analog inputs and
reference inputs, provided that these noise sources do not saturate
the analog modulator. As a result, the AD4114 is more immune
to noise interference than a conventional high resolution
converter. However, because the resolution of the AD4114 is
high and the noise levels from the converter are low, take care
regarding grounding and layout.
Ensure that proper decoupling is used when using high resolution
ADCs. The AD4114 has two power supply pins, AꢁDD and
IOꢁDD. The AꢁDD pin is referenced to AꢁSS, and the
IOꢁDD pin is referenced to DGND. Decouple AꢁDD with a
1ꢀ μF tantalum capacitor in parallel with a ꢀ.1 μF capacitor to
AꢁSS on each pin. Place the ꢀ.1 μF capacitor as close as possible
to the device on each supply, ideally directly against the device.
Decouple IOꢁDD with a 1ꢀ μF tantalum capacitor in parallel
with a ꢀ.1 μF capacitor to DGND. Decouple all inputs to AꢁSS.
If an external reference is used, decouple the REF+ and
REF− pins to AꢁSS.
The PCB that houses the ADC must be designed so that the
analog and digital sections are separated and confined to
certain areas of the PCB. A minimum etch technique is optimal
for ground planes and results in optimal shielding.
In any layout, the user must keep in mind the flow of currents
in the system to ensure that the paths for all return currents are
as close as possible to the paths that the currents took to reach
the corresponding destinations.
The AD4114 has two on-chip LDO regulators. One regulator
regulates the AꢁDD supply and the other regulates the IOꢁDD
supply. For the REGCAPA pin, use 1 μF and ꢀ.1 μF capacitors to
decouple to AꢁSS. Similarly, for the REGCAPD pin, use a 1 μF
capacitor to decouple to DGND.
Avoid running digital lines under the device. This layout couples
noise onto the die and allows the analog ground plane to run
under the AD4114 to prevent noise coupling. The power supply
Rev. 0 | Page 36 of 49
Data Sheet
AD4114
REGꢂSTER SUMMARY
Table 19. Register Summary
Register Name
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0x00
RꢀW
W
0x00
0x00
0x01
COMMS
Status
[7:0] WEN
[7:0] RDY
W
RA
R/
ADC_ERROR CRC_ERROR REG_ERROR
Channel
0x80
R
ADCMODE [15:8] REF_EN
[7:0] Reserved
Reserved
SING_CYC
Mode
Reserved
Delay
Reserved
0x2000
R/W
CLOCKSEL
IOSTRENGTH
CRC_EN
0x02
0x03
IFMODE
[15:8]
Reserved
ALT_SYNC
Reserved
DOUT_RESET 0x0000
WL16
R/W
[7:0] CONTREAD DATA_STAT REG_CHECK Reserved
Reserved
REGCHECK [23:16]
REGISTER_CHECK[23:16]
REGISTER_CHECK[15:8]
REGISTER_CHECK[7:0]
Data [23:16]
0x000000 R
[15:8]
[7:0]
0x04
Data
[23:0]
[15:8]
[7:0]
0x000000 R
Data [15:8]
Data [7:0]
0x06
0x07
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
GPIOCON [15:8]
[7:0] GP_DATA3
[15:8]
Reserved
OP_EN2_3 MUX_IO
IP_EN0
SYNC_EN
OP_EN1
ERR_EN
ERR_DAT
0x0800
0x30Dx
0x8001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x0001
0x1000
0x1000
R/W
GP_DATA2 IP_EN1
OP_EN0 GP_DATA1 GP_DATA0
ID
ID[15:8]
ID[7:0]
R
[7:0]
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
[15:8] CH_EN0
[7:0]
SETUP_SEL0
Reserved
INPUT0[9:8]
INPUT1[9:8]
INPUT2[9:8]
INPUT3[9:8]
INPUT4[9:8]
INPUT5[9:8]
INPUT6[9:8]
INPUT7[9:8]
INPUT8[9:8]
INPUT9[9:8]
INPUT10[9:8]
INPUT11[9:8]
INPUT12[9:8]
INPUT13[9:8]
INPUT14[9:8]
INPUT15[9:8]
INBUF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INPUT0 [7:0]
INPUT1[7:0]
INPUT2[7:0]
INPUT3[7:0]
INPUT4[7:0]
INPUT5[7:0]
INPUT6[7:0]
INPUT7[7:0]
INPUT8[7:0]
INPUT9[7:0]
Input10[7:0]
INPUT11[7:0]
INPUT12[7:0]
INPUT13[7:0]
INPUT14[7:0]
INPUT15[7:0]
[15:8] CH_EN1
[7:0]
SETUP_SEL1
SETUP_SEL2
SETUP_SEL3
SETUP_SEL4
SETUP_SEL5
SETUP_SEL6
SETUP_SEL7
SETUP_SEL8
SETUP_SEL9
SETUP_SEL10
SETUP_SEL11
SETUP_SEL12
SETUP_SEL13
SETUP_SEL14
SETUP_SEL15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[15:8] CH_EN2
[7:0]
[15:8] CH_EN3
[7:0]
[15:8] CH_EN4
[7:0]
[15:8] CH_EN5
[7:0]
[15:8] CH_EN6
[7:0]
[15:8] CH_EN7
[7:0]
[15:8] CH_EN8
[7:0]
[15:8] CH_EN9
[7:0]
[15:8] CH_EN10
[7:0]
[15:8] CH_EN11
[7:0]
[15:8] CH_EN12
[7:0]
[15:8] CH_EN13
[7:0]
[15:8] CH_EN14
[7:0]
[15:8] CH_EN15
[7:0]
SETUPCON0 [15:8]
[7:0]
Reserved
Reserved
Reserved
Reserved
BI_UNIPOLAR0 REFBUF0+ REFBUF0−
REF_SEL0 Reserved
BI_UNIPOLAR1 REFBUF1+ REFBUF1−
REF_SEL1 Reserved
SETUPCON1 [15:8]
[7:0]
INBUF1
Rev. 0 | Page 37 of 49
AD4114
Data Sheet
Register Name
Bits
Bit 7
Bit 6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INBUF2
Reset
RꢀW
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
SETUPCON2 [15:8]
[7:0]
BI_UNIPOLAR2 REFBUF2+ REFBUF2−
0x1000
R/W
REF_SEL2
Reserved
Reserved
SETUPCON3 [15:8]
[7:0]
BI_UNIPOLAR3 REFBUF3+ REFBUF3−
INBUF3
INBUF4
INBUF5
INBUF6
INBUF7
0x1000
0x1000
0x1000
0x1000
0x1000
0x0500
0x0500
0x0500
0x0500
0x0500
0x0500
0x0500
0x0500
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REF_SEL3
REF_SEL4
SETUPCON4 [15:8]
[7:0]
BI_UNIPOLAR4 REFBUF4+ REFBUF4−
Reserved
SETUPCON5 [15:8]
[7:0]
BI_UNIPOLAR5 REFBUF5+ REFBUF5−
REF_SEL5
Reserved
SETUPCON6 [15:8]
[7:0]
BI_UNIPOLAR6 REFBUF6+ REFBUF6−
REF_SEL6
Reserved
SETUPCON7 [15:8]
[7:0]
BI_UNIPOLAR7 REFBUF7+ REFBUF7−
REF_SEL7
Reserved
ORDER0
Reserved
ORDER1
Reserved
ORDER2
Reserved
ORDER3
Reserved
ORDER4
Reserved
ORDER5
Reserved
ORDER6
Reserved
ORDER7
Reserved
FILTCON0 [15:8] SINC3_MAP0
[7:0] Reserved
ENHFILTEN0
ENHFILTEN1
ENHFILTEN2
ENHFILTEN3
ENHFILTEN4
ENHFILTEN5
ENHFILTEN6
ENHFILTEN7
ENHFILT0
ODR0
ODR1
ODR2
ODR3
ODR4
ODR5
ODR6
ODR7
FILTCON1 [15:8] SINC3_MAP1
[7:0] Reserved
ENHFILT1
ENHFILT2
ENHFILT3
ENHFILT4
ENHFILT5
ENHFILT6
ENHFILT7
FILTCON2 [15:8] SINC3_MAP2
[7:0] Reserved
FILTCON3 [15:8] SINC3_MAP3
[7:0] Reserved
FILTCON4 [15:8] SINC3_MAP4
[7:0] Reserved
FILTCON5 [15:8] SINC3_MAP5
[7:0] Reserved
FILTCON6 [15:8] SINC3_MAP6
[7:0] Reserved
FILTCON7 [15:8] SINC3_MAP7
[7:0] Reserved
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
OFFSET0
OFFSET1
OFFSET2
OFFSET3
OFFSET4
OFFSET5
OFFSET6
OFFSET7
GAIN0
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
OFFSET0[23:0]
0x800000 R/W
0x800000 R/W
0x800000 R/W
0x800000 R/W
0x800000 R/W
0x800000 R/W
0x800000 R/W
0x800000 R/W
0x5XXXX0 R/W
0x5XXXX0 R/W
0x5XXXX0 R/W
0x5XXXX0 R/W
0x5XXXX0 R/W
0x5XXXX0 R/W
0x5XXXX0 R/W
0x5XXXX0 R/W
OFFSET1[23:0]
OFFSET2[23:0]
OFFSET3[23:0]
OFFSET4[23:0]
OFFSET5[23:0]
OFFSET6[23:0]
OFFSET7[23:0]
GAIN0[23:0]
GAIN1[23:0]
GAIN2[23:0]
GAIN3[23:0]
GAIN4[23:0]
GAIN5[23:0]
GAIN6[23:0]
GAIN7[23:0]
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
Rev. 0 | Page 38 of 49
Data Sheet
AD4114
REGꢂSTER DETAꢂLS
COMMUNICATIONS REGISTER
Address: 0x00, Reset: 0x00, Name: COMMS
All access to the on-chip registers must start with a write to the communications register. This write determines which register is
accessed next and whether that operation is a write or a read.
Table 20. Bit Descriptions for COMMS
Bits Bit Name Settings Description
Reset Access
7
6
WEN
R/W
This bit must be low to begin communications with the ADC.
0x0
0x0
W
W
This bit determines if the command is a read or write operation.
0
1
Write command.
Read command.
[5:0] RA
The register address bits determine the register to be read from or written to as part of
the current communication.
0x00
W
000000 Status register.
000001 ADC mode register.
000010 Interface mode register.
000011 Register checksum register.
000100 Data register.
000110 GPIO configuration register.
000111 ID register.
010000 Channel Register 0.
010001 Channel Register 1.
010010 Channel Register 2.
010011 Channel Register 3.
010100 Channel Register 4.
010101 Channel Register 5.
010110 Channel Register 6.
010111 Channel Register 7.
011000 Channel Register 8.
011001 Channel Register 9.
011010 Channel Register 10.
011011 Channel Register 11.
011100 Channel Register 12.
011101 Channel Register 13.
011110 Channel Register 14.
011111 Channel Register 15.
100000 Setup Configuration Register 0.
100001 Setup Configuration Register 1.
100010 Setup Configuration Register 2.
100011 Setup Configuration Register 3.
100100 Setup Configuration Register 4.
100101 Setup Configuration Register 5.
100110 Setup Configuration Register 6.
100111 Setup Configuration Register 7.
101000 Filter Configuration Register 0.
101001 Filter Configuration Register 1.
101010 Filter Configuration Register 2.
101011 Filter Configuration Register 3.
101100 Filter Configuration Register 4.
101101 Filter Configuration Register 5.
101110 Filter Configuration Register 6.
101111 Filter Configuration Register 7.
Rev. 0 | Page 39 of 49
AD4114
Data Sheet
Bits Bit Name Settings Description
110000 Offset Register 0.
110001 Offset Register 1.
110010 Offset Register 2.
110011 Offset Register 3.
110100 Offset Register 4.
110101 Offset Register 5.
110110 Offset Register 6.
110111 Offset Register 7.
111000 Gain Register 0.
111001 Gain Register 1.
111010 Gain Register 2.
111011 Gain Register 3.
111100 Gain Register 4.
111101 Gain Register 5.
111110 Gain Register 6.
111111 Gain Register 7.
Reset Access
STATUS REGISTER
Address: 0x00, Reset: 0x80, Name: Status
The status register is an 8-bit register that contains ADC and serial interface status information. The register can optionally be appended
to the data register by setting the DATA_STAT bit in the interface mode register.
Table 21. Bit Descriptions for STATUS
Bits Bit Name
Settings Description
Reset Access
7
RDY
The status of RDY is output to the DOUT/RDY pin when CS is low and a register is not
0x1
R
being read. This bit goes low when the ADC writes a new result to the data register. In
ADC calibration modes, this bit goes low when the ADC writes the calibration result.
RDY is brought high automatically by a read of the data register.
0
1
New data result available.
Awaiting new data result.
6
ADC_ERROR
By default, this bit indicates if an ADC overrange or underrange occurred. The ADC
result is clamped to 0xFFFFFF for overrange errors and 0x000000 for underrange
errors. This bit is updated when the ADC result is written and is cleared at the next
update after removing the overrange or underrange condition.
0x0
R
0
1
No error.
Error.
5
4
CRC_ERROR
REG_ERROR
This bit indicates if a CRC error occurred during a register write. For register reads, the
host microcontroller determines if a CRC error occurred. This bit is cleared by a read of
this register.
No error.
CRC error.
0x0
0x0
R
R
0
1
This bit indicates if the content of one of the internal registers changes from the value
calculated when the register integrity check is activated. The check is activated by
setting the REG_CHECK bit in the interface mode register. This bit is cleared by
clearing the REG_CHECK bit.
0
1
No error.
Error.
Rev. 0 | Page 40 of 49
Data Sheet
AD4114
Bits Bit Name
Settings Description
These bits indicate which channel was active for the ADC conversion whose result is
Reset Access
[3:0] Channel
0x0
R
currently in the data register. This channel may be different from the channel currently
being converted. The mapping is a direct map from the channel register. Therefore,
Channel 0 results in 0x0 and Channel 15 results in 0xF.
0000 Channel 0.
0001 Channel 1.
0010 Channel 2.
0011 Channel 3.
0100 Channel 4.
0101 Channel 5.
0110 Channel 6.
0111 Channel 7.
1000 Channel 8.
1001 Channel 9.
1010 Channel 10.
1011 Channel 11.
1100 Channel 12.
1101 Channel 13.
1110 Channel 14.
1111 Channel 15.
ADC MODE REGISTER
Address: 0x01, Reset: 0x2000, Name: ADCMODE
The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets
RDY
the filter and the
bits and starts a new conversion or calibration.
Table 22. Bit Descriptions for ADCMODE
Bits
Bit Name Settings Description
Reset Access
15
REF_EN
Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin.
0x0
R/W
0
1
Disabled.
Enabled.
Reserved
14
13
This bit is reserved. Set this bit to 0.
0x0
R/W
R/W
SING_CYC
This bit can be used when only a single channel is active to set the ADC to only output 0x1
at the settled filter data rate.
0
1
Disabled.
Enabled.
[12:11] Reserved
These bits are reserved. Set these bits to 0.
0x0
0x0
R
[10:8]
Delay
These bits allow a programmable delay to be added after a channel switch to allow
the settling of external circuitry before the ADC starts processing its input.
R/W
000 0 μs.
001 32 μs.
010 128 μs.
011 320 μs.
100 800 μs.
101 1.6 ms.
110 4 ms.
111 8 ms.
7
Reserved
This bit is reserved. Set this bit to 0.
0x0
R
Rev. 0 | Page 41 of 49
AD4114
Data Sheet
Bits
Bit Name Settings Description
Reset Access
[6:4]
Mode
These bits control the operating mode of the ADC. See the Operating Modes section
for more information.
0x0
R/W
000 Continuous conversion mode.
001 Single conversion mode.
010 Standby mode.
011 Power-down mode.
100 Internal offset calibration.
101 Internal gain calibration
110 System offset calibration.
111 System gain calibration.
[3:2]
[1:0]
CLOCKSEL
Reserved
These bits select the ADC clock source. Selecting the internal oscillator also enables
the internal oscillator.
00 Internal oscillator
01 Internal oscillator output on the XTAL2/CLKIO pin.
10 External clock input on the XTAL2/CLKIO pin.
11 External crystal on the XTAL1 pin and the XTAL2/CLKIO pin.
These bits are reserved. Set these bits to 0.
0x0
0x0
R/W
R
INTERFACE MODE REGISTER
Address: 0x02, Reset: 0x0000, Name: IFMODE
The interface mode register configures various serial interface options.
Table 23. Bit Descriptions for IFMODE
Bits
Bit Name
Settings Description
Reset Access
[15:13] Reserved
These bits are reserved. Set these bits to 0.
0x0
0x0
R
12
11
ALT_SYNC
This bit enables a different behavior of the SYNC pin to allow the use of SYNC as a
control for conversions when cycling channels.
Disabled.
Enabled.
R/W
0
1
IOSTRENGTH
This bit controls the drive strength of the DOUT/RDY pin. Set this bit when reading
from the serial interface at high speed with a low IOVDD supply and moderate
capacitance.
0x0
R/W
0
1
Disabled (default).
Enabled.
[10:9]
8
Reserved
These bits are reserved. Set these bits to 0.
See the DOUT_RESET section.
Disabled.
0x0
0x0
R
DOUT_RESET
R/W
0
1
Enabled.
7
6
CONTREAD
DATA_STAT
This bit enables the continuous read mode of the ADC data register. The ADC must be
configured in continuous conversion mode to use continuous read mode. For
more details, see the Operating Modes section.
Disabled.
Enabled.
0x0
0x0
R/W
R/W
0
1
This bit enables the status register to be appended to the data register when read
so that channel and status information are transmitted with the data. Appending
the status register is the only way to be sure that the channel bits read from the
status register correspond to the data in the data register.
0
1
Disabled.
Enabled.
Rev. 0 | Page 42 of 49
Data Sheet
AD4114
Bits
Bit Name
Settings Description
This bit enables a register integrity checker, that can be used to monitor any change in
Reset Access
5
REG_CHECK
0x0
R/W
the value of the user registers. To use this feature, configure all other registers as
desired with this bit cleared. Then, write to this register to set the REG_CHECK bit to 1.
If the contents of any of the registers change, the REG_ERROR bit is set in the status
register. To clear the error, set the REG_CHECK bit to 0. Neither the interface mode
register nor the ADC data or status register is included in the registers that are
checked. If a register must have a new value written, this bit must first be cleared.
Otherwise, an error is flagged when the new register contents are written.
0
1
Disabled.
Enabled.
4
Reserved
CRC_EN
This bit is reserved. Set this bit to 0.
0x0
R
[3:2]
These bits enable CRC protection of register reads/writes. CRC increases the
number of bytes in a serial interface transfer by one.
0x00
R/W
00 Disabled.
01 XOR checksum enabled for register read transactions. Register writes still use CRC
with these bits set.
10 CRC checksum enabled for read and write transactions.
This bit is reserved. Set this bit to 0.
1
0
Reserved
WL16
0x0
0x0
R
This bit changes the ADC data register to 16 bits. The ADC is not reset by a write to
the interface mode register. Therefore, the ADC result is not rounded to the correct
word length immediately after writing to these bits. The first new ADC result is correct.
R/W
0
1
24-bit data.
16-bit data.
REGISTER CHECK
Address: 0x03, Reset: 0x000000, Name: REGCHECK
The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit
in the interface mode register must be set for this checksum to operate. Otherwise, the register reads ꢀ.
Table 24. Bit Descriptions for REGCHECK
Bits
Bit Name
Settings Description
This register contains the 24-bit checksum of user registers when the
REG_CHECK bit is set in the interface mode register.
Reset
Access
[23:0] REGISTER_CHECK
0x000000
R
DATA REGISTER
Address: 0x04, Reset: 0x000000, Name: Data
The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the
RDY RDY
output high if it is
BI_UNIPOLARx bits in the setup configuration registers. Reading the data register brings the
bit and the
output is brought high, it is not possible to determine if
RDY
low. The ADC result can be read multiple times. However, because the
another ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the data
register.
Table 25. Bit Descriptions for Data
Bits
Bit Name Settings Description
Reset
Access
[15:0] Data
This register contains the ADC conversion result. If DATA_STAT is set in the interface 0x000000
mode register, the status register is appended to this register when read, making
this a 32-bit register.
R
Rev. 0 | Page 43 of 49
AD4114
Data Sheet
GPIO CONFIGURATION REGISTER
Address: 0x06, Reset: 0x0800, Name: GPIOCON
The GPIO configuration register controls the general-purpose IꢂO pins of the ADC.
Table 26. Bit Descriptions for GPIOCON
Bits
Bit Name
Settings Description
Reset Access
[15:14] Reserved
Reserved.
0x0
0x0
R
R/W
13
12
OP_EN2_3
MUX_IO
GPO2/GPO3 output enable. This bit enables the GPO2 and GPO3 pins. The outputs
are referenced between AVDD and AVSS.
Disabled.
Enabled.
This bit allows the ADC to control an external multiplexer, using GPIO0, GPIO1,
GPO2, and GPO3 in sync with the internal channel sequencing. The analog input pins
used for a channel can still be selected on a per channel basis. Therefore, it is
possible to have a 16-channel multiplexer in front of each analog input pair (VIN0/VIN1
to VIN14/VIN15), giving a total of 128 differential channels. However, only 16
channels at a time can be automatically sequenced. Following the sequence of 16
channels, the user changes the analog input to the next pair of input channels, and it
sequences through the next 16 channels. There is a delay function that allows extra
time for the analog input to settle, in conjunction with any switching of an external
multiplexer (see the delay bits in the ADC mode register).
0
1
0x0
R
11
SYNC_EN
SYNC input enable. This bit enables the SYNC pin as a sync input. When set low, the
SYNC pin holds the ADC and filter in reset until SYNC goes high. An alternative operation
of the SYNC pin is available when the ALT_SYNC bit in the interface mode register is
set. This mode works only when multiple channels are enabled. In such cases, a low on
the SYNC pin does not immediately reset the filter/modulator. Instead, if the SYNC pin is
low when the channel is due to be switched, the modulator and filter are prevented
from starting a new conversion. Bringing SYNC high begins the next conversion. This
alternative sync mode allows SYNC to be used while cycling through channels.
0x1
R/W
0
1
Disabled.
Enabled.
[10:9]
ERR_EN
ERROR
0x0
R/W
pin mode. These bits enable the ERROR pin as an error input/output.
00 Disabled.
01 Enable error input (active low). ERROR is an error input. The inverted readback state
is OR'ed with other error sources and is available in the ADC_ERROR bit in the status
ERROR
register. The
pin state can also be read from the ERR_DAT bit in this register.
10 Enable open-drain error output (active low). ERROR is an open-drain error output.
The status register error bits are OR'ed, inverted, and mapped to the ERROR pin.
ERROR pins of multiple devices can be wired together to a common pull-up resistor
so that an error on any device can be observed.
11 General-purpose output (active low). ERROR is a general-purpose output. The status
of the pin is controlled by the ERR_DAT bit in this register. This output is referenced
between IOVDD and DGND, as opposed to the AVDD and AVSS levels used by the
GPIOx and GPOx pins. The output has an active pull-up resistor in this case.
8
ERR_DAT
ERROR
0x0
R/W
pin data. This bit determines the logic level at the ERROR pin if the pin is
enabled as a general-purpose output. This bit reflects the readback status of the pin
if the pin is enabled as an input.
0
1
Logic 0.
Logic 1.
7
6
GP_DATA3
GP_DATA2
GPIO1 data. This bit is the write data for GPIO1.
GPIO1 = 0.
GPIO1 = 1.
0x0
0x0
R/W
R/W
0
1
GPIO0 data. This bit is the write data for GPIO0.
0
1
GPIO0 = 0.
GPIO0 = 1.
Rev. 0 | Page 44 of 49
Data Sheet
AD4114
Bits
5
Bit Name
IP_EN1
Settings Description
This bit runs GPIO1 into an input. Input is equal to AVDD and AVSS.
Disabled.
Reset Access
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
0
1
Enabled.
4
3
2
IP_EN0
This bit runs GPIO0 into an input. Input is equal to AVDD and AVSS.
0
1
Disabled.
Enabled.
OP_EN1
OP_EN0
This bit runs GPIO1 into an output. Outputs are referenced between AVDD and AVSS.
0
1
Disabled.
Enabled.
This bit runs GPIO0 into an output. Outputs are referenced between AVDD and AVSS.
0
1
Disabled.
Enabled.
1
0
GP_DATA1
GP_DATA0
This bit is the readback or write data for GPIO1.
This bit is the readback or write data for GPIO0.
0x0
0x0
R/W
R/W
ID REGISTER
Address: 0x07, Reset: 0x30DX, Name: ID
The ID register returns a 16-bit ID. For the AD4114, this value is ꢀx3ꢀDX, where x is don’t care.
Table 27. Bit Descriptions for ID
Bits
[15:0]
Bit Name
ID
Settings
Description
Reset
0x30DX
Access
R
Product ID. The ID register returns a 16-bit ID code that is specific to the ADC.
CHANNEL REGISTER 0 TO CHANNEL REGISTER 15
Address: 0x10 to 0x1F, Reset: 0x8001, Name: CH0 to CH15
The channel registers are 16-bit registers that select the currently active channels, the selected inputs for each channel, and the setup to
be used to configure the ADC for that channel. The layout for CHꢀ to CH15 is identical.
Table 28. Bit Descriptions for CH0 to CH15
Bits
Bit Name
Settings
Description
Reset Access
15
CH_ENx
This bit enables Channel x. If more than one channel is enabled, the ADC
automatically sequences between them.
0x1
R/W
0
1
Disabled.
Enabled.
[14:12] SETUP_SELx
These bits identify which of the eight setups is used to configure the ADC for
this channel. A setup comprises a set of four registers: a setup configuration register,
a filter configuration register, an offset register, and a gain register. All channels can
use the same setup, in which case the same 3-bit value must be written to these
bits on all active channels, or up to eight channels can be configured differently.
0x0
R/W
000 Setup 0.
001 Setup 1.
010 Setup 2.
011 Setup 3.
100 Setup 4.
101 Setup 5.
110 Setup 6.
111 Setup 7.
Reserved.
[11:10] Reserved
[9:0] INPUTx
0x0
0x1
R
These bits select which input pair is connected to the input of the ADC for this
channel.
R/W
0000000001 VIN0, VIN1.
0000010000 VIN0, VINCOM.
Rev. 0 | Page 45 of 49
AD4114
Data Sheet
Bits
Bit Name
Settings
Description
Reset Access
0000100000 VIN1, VIN0.
0000110000 VIN1, VINCOM.
0001000011 VIN2, VIN3.
0001010000 VIN2, VINCOM.
0001100010 VIN3, VIN2.
0001110000 VIN3, VINCOM.
0010000101 VIN4, VIN5.
0010010000 VIN4, VINCOM.
0010100100 VIN5, VIN4.
0010110000 VIN5, VINCOM.
0011000111 VIN6, VIN7.
0011010000 VIN6, VINCOM.
0011100110 VIN7, VIN6.
0011110000 VIN7, VINCOM.
0100001001 VIN8, VIN9.
0100010000 VIN8, VINCOM.
0100101000 VIN9, VIN8.
0100110000 VIN9, VINCOM.
0101001011 VIN10, VIN11.
0101010000 VIN10, VINCOM.
0101101010 VIN11, VIN10.
0101110000 VIN11, VINCOM.
0110001101 VIN12, VIN13.
0110010000 VIN12, VINCOM.
0110101100 VIN13, VIN12.
0110110000 VIN13, VINCOM.
0111001111 VIN14, VIN15.
0111010000 VIN14, VINCOM.
0111101110 VIN15, VIN14.
0111110000 VIN15, VINCOM.
1000110010 Temperature sensor.
1010110110 Reference.
SETUP CONFIGURATION REGISTER 0 TO SETUP CONFIGURATION REGSITER 7
Address: 0x20 to 0x27, Reset: 0x1000 Name: SETUPCON0 to SETUPCON7
The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC.
The layout for SETUPCONꢀ to SETUPCON7 is identical.
Table 29. Bit Descriptions for SETUPCON0 to SETUPCON7
Bits
Bit Name
Settings Description
Reset Access
[15:13] Reserved
These bits are reserved. Set these bits to 0.
Bipolar/unipolar. This bit sets the output coding of the ADC for Setup x.
Unipolar coded output.
Bipolar coded output.
0x0
0x1
R
R/W
12
11
10
BI_UNIPOLARx
0
1
REFBUFx+
REFBUFx−
REF+ buffer. This bit enables or disables the REF+ input buffer.
Disabled.
Enabled.
0x0
0x0
R/W
R/W
0
1
REF− buffer. This bit enables or disables the REF− input buffer.
0
1
Disabled.
Enabled.
Rev. 0 | Page 46 of 49
Data Sheet
AD4114
Bits
[9:8]
Bit Name
INBUFx
Settings Description
Input buffer. This bit enables or disables input buffers.
Reset Access
0x0
R/W
00 Disabled.
01 Reserved.
10 Reserved.
11 Enabled.
[7:6]
[5:4]
Reserved
REF_SELx
These bit are reserved. Set these bits to 0.
These bits allow the user to select the reference source for ADC conversion on
Setup x.
0x0
0x0
R
R/W
00 External reference, REF .
10 Internal 2.5 V reference, must be enabled via ADCMODE (see Table 22).
11 AVDD − AVSS.
[3:0]
Reserved
These bits are reserved. Set these bits to 0.
0x0
R
FILTER CONFIGURATION REGISTER 0 TO FILTER CONFIGURATION REGISTER 7
Address: 0x28 to 0x2F, Reset: 0x0500, Name: FILTCON0 to FILTCON7
The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets
any active ADC conversion and restarts converting at the first channel in the sequence. The layout for FILTCONꢀ to FILTCON7 is identical.
Table 30. Bit Descriptions for FILTCON0 to FILTCON7
Bits
Bit Name
Settings Description
Reset Access
15
SINC3_MAPx
If this bit is set, the mapping of the filter register changes to directly program the
0x0
R/W
decimation rate of the sinc3 filter for Setup x. All other options are eliminated. This bit
allows fine tuning of the output data rate and filter notch for rejection of specific
frequencies. The data rate when on a single channel equals fMOD/(32 × FILTCON0[14:0]).
[14:12] Reserved
These bits are reserved. Set these bits to 0.
0x0
0x0
R
11
ENHFILTENx
This bit enables various postfilters for enhanced 50 Hz/60 Hz rejection for Setup x. The
ORDERx bits must be set to 00 to select the sinc5 + sinc1 filter for this function to work.
R/W
0
1
Disabled.
Enabled.
[10:8]
ENHFILTx
These bits select between various postfilters for enhanced 50 Hz/60 Hz rejection for 0x5
Setup x.
R/W
010 27 SPS, 47 dB rejection, 36.7 ms settling.
011 25 SPS, 62 dB rejection, 40 ms settling.
101 20 SPS, 86 dB rejection, 50 ms settling.
110 16.67 SPS, 92 dB rejection, 60 ms settling.
This bit is reserved. Set this bit to 0.
7
Reserved
ORDERx
0x0
0x0
R
[6:5]
These bits control the order of the digital filter that processes the modulator data for
Setup x.
R/W
00 Sinc5 + sinc1 (default).
11 Sinc3.
[4:0]
ODRx
These bits control the output data rate of the ADC and, therefore, the settling time
and noise for Setup x. Rates shown are for a single-channel enabled sinc5 + sinc 1
filter. See Table 16 for multiple channels enabled.
0x0
R/W
00000 31,250 SPS.
00001 31,250 SPS.
00010 31,250 SPS.
00011 31,250 SPS.
00100 31,250 SPS.
00101 31,250 SPS.
00110 15,625 SPS.
00111 10,417 SPS.
01000 5208 SPS.
01001 2597 SPS (2604 SPS for sinc3).
01010 1007 SPS (1008 SPS for sinc3).
Rev. 0 | Page 47 of 49
AD4114
Data Sheet
Bits
Bit Name
Settings Description
Reset Access
01011 503.8 SPS (504 SPS for sinc3).
01100 381 SPS (400.6 SPS for sinc3).
01101 200.3 SPS (200.3 SPS for sinc3).
01110 100.2 SPS (100.16 SPS for sinc3).
01111 59.52 SPS (59.98 SPS for sinc3).
10000 49.68 SPS (50 SPS for sinc3).
10001 20.01 SPS.
10010 16.63 SPS (16.67 SPS for sinc3).
10011 10 SPS.
10100 5 SPS.
10101 2.5 SPS.
10110 1.25 SPS.
OFFSET REGISTER 0 TO OFFSET REGISTER 7
Address: 0x30 to 0x37, Reset: 0x800000, Name: OFFSET0 to OFFSET7
The offset (zero-scale) registers are 16-bit registers that can be used to compensate for any offset error in the ADC or in the system. The
layout for OFFSETꢀ to OFFSET7 is identical.
Table 31. Bit Descriptions for OFFSET0 to OFFSET7
Bits
Bit Name
Settings
Description
Reset
Access
[23:0]
OFFSETx
Offset calibration coefficient for Setup x.
0x800000
R/W
GAIN REGISTER 0 TO GAIN REGISTER 7
Address: 0x38 to 0x3F, Reset: 0x5XXXX0, Name: GAIN0 to GAIN7
The full-scale gain registers are 16-bit registers that can be used to compensate for any gain error in the ADC or in the system. The layout
for GAINꢀ to GAIN7 is identical.
Table 32. Bit Descriptions for GAIN0 to GAIN7
Bits
Bit Name
Settings
Description
Reset1
Access
[23:0]
GAINx
Gain calibration coefficient for Setup x.
0x5XXXX0
R/W
1 X means don’t care.
Rev. 0 | Page 48 of 49
Data Sheet
AD4114
OUTLꢂNE DꢂMENSꢂONS
DETAIL A
(JEDEC 95)
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
AREA
PIN 1
NS
INDICATOR AR EA OP TIO
(SEE DETAIL A)
31
40
30
1
0.50
BSC
4.70
EXPOSED
PAD
4.60 SQ
4.50
21
10
20
11
0.45
0.40
0.35
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1.00
0.95
0.85
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
Figure 47. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.95 mm Package Height
(CP-40-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
AD4114BCPZ
AD4114BCPZ-RL7
EVAL-AD4114SDZ
EVAL-SDP-CB1Z
−40°C to +105°C
−40°C to +105°C
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-40-15
CP-40-15
Evaluation Controller Board
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D023872-7ꢀ20(0)
Rev. 0 | Page 49 of 49
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明