AD50601_技术文档

Fully Accurate, 16-Bit, Unbuffered V_OUT, Quad SPI

Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP

AD5066

Total unadjusted error for the part is <0.8 mV. Zero code error

for the part is 0.05 mV typically.

FEATURES

Low power quad 16-bit nanoDAC, 1 LSB INL

Low total unadjusted error of 0.1 mV typically

Low zero code error of 0.05 mV typically

Individually buffered reference pins

The AD5066 contains a power-down feature that reduces the

current consumption of the device to typically 400 nA at 5 V

and provides software selectable output loads while in power-

down mode.

2.7 V to 5.5 V power supply

Specified over full code range of 0 to 65535

Power-on reset to zero scale or midscale

Per channel power-down with 3 power-down functions

The outputs of all DACs can be updated simultaneously using

LDAC

the hardware

user software selectable DAC channels to update simultaneously.

CLR

function, with the added functionality of

Hardware

with software

override function

LDAC

There is also an asynchronous

that clears all DACs to a

function to programmable code

CLR

software-selectable code—0 V, midscale, or full scale.

Small 16-lead TSSOP

PRODUCT HIGHLIGHTS

APPLICATIONS

1. Quad channel available in 16-lead TSSOP, 1 LSB INL.

2. Individually buffered voltage reference pins.

3. TUE = 0.8 mV max and zero code error = 0.1 mV max.

4. High speed serial interface with clock speeds up to 50 MHz.

5. Three power-down modes available to the user.

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

6. Reset to known output voltage (zero scale or midscale).

GENERAL DESCRIPTION

Table 1. Related Devices

The AD5066 is a low power, 16-bit quad-channel, unbuffered

voltage output nanoDAC® offering relative accuracy specifica-

tions of 1 LSB INL with individual reference pins and can

operate from a single 2.7 V to 5.5 V supply. The AD5066 also

offers a differential accuracy specification of 1 LSB DNL.

Reference buffers are also provided on-chip. The part uses a

versatile 3-wire, low power Schmitt trigger serial interface that

operates at clock rates up to 50 MHz and is compatible with

standard SPI®, QSPI™, MICROWIRE™, and most DSP interface

standards. The AD5066 incorporates a power-on reset circuit

that ensures the DAC output powers up to zero scale or

midscale and remains there until a valid write to the device

takes place.

Part No.

Description

AD5666

AD5025/AD5045/AD5065¹

Quad,16-bit buffered DAC,16 LSB INL, TSSOP

Dual,12-/14-/16-bit buffered nanoDAC,

TSSOP

AD5024/AD5044/AD5064¹

AD5062¹

AD5063¹

AD5061

AD5040/AD5060¹

Quad 16-bit nanoDAC, TSSOP

Single, 16-bit nanoDAC, SOT-23

Single, 16-bit nanoDAC, MSOP

Single,16-bit nanoDAC, 4 LSB INL, SOT-23

14-/16-bit nanoDAC, SOT-23

1

1 LSB INL

FUNCTIONAL BLOCK DIAGRAM

V

A V

REF

B

V

REF

DD

AD5066

LDAC

INPUT

REGISTER

DAC

REGISTER

V

A

DAC A

OUT

SCLK

INPUT

DAC

V

B

C

D

DAC B

DAC C

OUT

REGISTER

INTERFACE

LOGIC

INPUT

REGISTER

DAC

REGISTER

SYNC

DIN

INPUT

REGISTER

DAC

REGISTER

DAC D

POWER-DOWN LOGIC

POWER-ON RESET

POR

V

C V

REF

D

GND

LDAC CLR

REF

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD5066

TABLE OF CONTENTS

Features .............................................................................................. 1

DAC Architecture....................................................................... 15

Reference Buffer ......................................................................... 15

Serial Interface ............................................................................ 15

Input Shift Register .................................................................... 15

Power-On Reset.......................................................................... 17

Clear Code Register ................................................................... 18

Applications....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

Digital-to-Analog Converter .................................................... 15

LDAC

Function........................................................................... 18

Power Supply Bypassing and Grounding................................ 19

Microprocessor Interfacing....................................................... 19

Applications Information .............................................................. 21

Using a Reference as a Power Supply....................................... 21

Bipolar Operation....................................................................... 21

Using the AD5066 with a Galvanically Isolated Interface .... 21

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

REVISION HISTORY

8/10—Rev. 0 to Rev. A

Change to Minimum

High Time, Single

SYNC

Channel Update Parameter, Table 4............................................... 5

7/09—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD5066

SPECIFICATIONS

V_DD= 2.7 V to 5.5 V, 2.0 V ≤ V_REFA, V_REFB, V_REFC, V_REFD ≤ V_DD− 0.4 V, all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

A Grade¹

Min Typ

B Grade¹

Typ

Parameter

Max

Min

Max

Unit

Conditions/Comments

STATIC PERFORMANCE²

Resolution

16

Bits

LSB

Relative Accuracy (INL)

0.5

4

0.5

1

2

T_A= −40°C to +105°C

T_A= −40°C to +125°C

Differential Nonlinearity (DNL)

Total Unadjusted Error (TUE)

Zero-Code Error

0.2

0.1

0.05

0.5

0.01

1

0.8

0.1

0.2

0.1

1

0.8

0.1

LSB

mV

V_DD= 2.7 V, V_REF= 2 V

All 0s loaded to the DAC register

0.05

0.5

0.01

0.005

0.5

Zero-Code Error Drift³

Full-Scale Error

µV/°C

0.05

% FSR All 1s loaded to the DAC register

% FSR

ppm

μV

Gain Error

0.005

0.5

Gain Error Drift³

ppm of FSR/°C

DC Crosstalk³

1

5

1

5

Due to single-channel full-scale

output change

Due to powering down (per channel)

25

5

25

μV

OUTPUT CHARACTERISTICS³

Output Voltage Range

0

V_REF

0

V_REF

V

DC Output Impedance (Normal

Mode)

8

kΩ

Output impedance tolerance 10%

DC Output Impedance

DAC in power-down mode

Output Connected to 100 kΩ

Network

Output Connected to 1 kΩ

Network

Power-Up Time⁴

DC PSRR

100

1

100

1

kΩ

Output impedance tolerance 20 kΩ

Output impedance tolerance 400 Ω

V_DD10%, DAC = full scale

2.9

−120

2.9

−120

µs

dB

REFERENCE INPUTS

Reference Input Range

Reference Current

Reference Input Impedance

LOGIC INPUTS³

2

V_DD− 0.4

1

2

V_DD− 0.4

1

V

µA

MΩ

0.002

40

0.002

40

Per DAC channel

Input Current⁵

1

0.8

1

0.8

µA

V

Input Low Voltage, V_INL

Input High Voltage, V_INH

Pin Capacitance

2.2

2.7

2.2

2.7

4

pF

POWER REQUIREMENTS

V_DD

5.5

3

5.5

3

V

All digital inputs at 0 V or V_DD

DAC active, excludes load current

V_IH= V_DDand V_IL= GND

I_DD

Normal Mode⁶

All Power-Down Modes⁷

2.5

0.4

2.5

0.4

mA

µA

¹Temperature range is −40°C to +125°C, typical at 25°C.

²Linearity calculated using a code range of 0 to 65,535; output unloaded.

³Guaranteed by design and characterization; not production tested.

⁴Time taken to exit power-down mode and enter normal mode, 32^ndclock edge to 90% of DAC midscale value, output unloaded.

⁵Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale.

⁶Interface inactive. All DACs active. DAC outputs unloaded.

⁷All four DACs powered down.

Rev. A | Page 3 of 24

AD5066

AC CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, 2.0 V ≤ V_REFA, V_REFB, V_REFC, V_REFD ≤ V_DD− 0.4 V all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter^{1, 2}

Min Typ

Max Unit

Conditions/Comments³

DYNAMIC PERFORMACE

Output Voltage Settling Time

7.5

12

10

15

µs

¼ to ¾ scale settling to 2 LSB, single channel update, output

unloaded

¼ to ¾ scale settling to 2 LSB, all channel update, output

unloaded

Output Voltage Settling Time

Slew Rate

1.7

3

V/µs

nV-sec

dB

nV-sec

dB

Digital-to-Analog Glitch Impulse

Reference Feedthrough

Digital Feedthrough

Digital Crosstalk

1 LSB change around major carry

V_REF= 3 V 0.5 V p-p, frequency = 60 Hz to 20 MHz

−70

0.02

1.7

3.7

5.4

−83

30

Analog Crosstalk

DAC-to-DAC Crosstalk

Total Harmonic Distortion

Output Noise Spectral Density

V_REF= 3 V 0.2 V p-p, frequency = 10 kHz

nV/√Hz DAC code = 0x8000, 1 kHz

nV/√Hz DAC code = 0x8000, 10 kHz

25

Output Noise

4.7

μV p-p

0.1 Hz to 10 Hz

¹Temperature range is −40°C to +125°C, typical at +25°C.

²See the Terminology section.

³Guaranteed by design and characterization; not production tested.

Rev. A | Page 4 of 24

AD5066

TIMING CHARACTERISTICS

All input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2, V_DD= 2.7 V to

5.5 V, all specifications T_MINto T_MAX, unless otherwise noted. See Figure 2.

Table 4.

Parameter¹

Symbol

Min

20

10

17

5

Typ

Max

Unit

ns

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNC to SCLK Falling Edge Set-Up Time

Data Set-Up Time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

ns

Data Hold Time

5

SCLK Falling Edge to SYNC Rising Edge

Minimum SYNC High Time

Single Channel Update

All Channel Update

SYNC Rising Edge to SCLK Fall Ignore

LDAC Pulse Width Low

30

3

8

µs

ns

µs

t₉

17

20

10

10.6

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

SCLK Falling Edge to LDAC Rising Edge

CLR Pulse Width Low

SCLK Falling Edge to LDAC Falling Edge

CLR Pulse Activation Time

¹Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested.

t₁

t₉

SCLK

t₂

t₈

t₇

t₃

t₄

SYNC

DIN

t₆

t₅

DB31

DB0

t₁₃

t₁₀

1

LDAC

t₁₁

2

LDAC

t₁₂

CLR

t₁

V

4

O UT

1

2

ASYNCHRO NO US LDAC UPDATE M O DE.

SYNCHRO NO US LDAC UPDATE M O DE.

Figure 2. Serial Write Operation

Rev. A | Page 5 of 24

AD5066

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 5.

Parameter

Rating

V_DDto GND

−0.3 V to +7 V

Digital Input Voltage to GND

V_OUTx to GND

V_REFx to GND

−0.3 V to V_DD+ 0.3 V

Operating Temperature Range

Industrial

Storage Temperature Range

ESD CAUTION

−40°C to +125°C

−65°C to +150°C

+150°C

Junction Temperature (T_{J MAX}

)

TSSOP Package

Power Dissipation

θ_JAThermal Impedance

(T_{J MAX}− T_A)/θ_JA

150.4°C/W

Reflow Soldering Peak Temperature

SnPb

Pb-Free

240°C

260°C

Rev. A | Page 6 of 24

AD5066

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LDAC

SYNC

SCLK

DIN

V

GND

DD

AD5066

TOP VIEW

(Not to Scale)

V

B

A

C

V

B

D

REF

OUT

V

REF

OUT

V

D

REF

V

CLR

POR

V

REF

C

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

Load DAC. Logic input. This is used to update the DAC register and, consequently, the analog outputs.

When tied permanently low, the addressed DAC register is updated on the falling edge of the 32^nd

clock. If LDAC is held high during the write cycle, the addressed DAC input shift register is updated but

the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated

simultaneously on the falling edge of LDAC.

LDAC

2

3

SYNC

V_DD

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the

falling edges of the next 32 clocks. If SYNC is taken high before the 32^ndfalling edge, the rising edge of

SYNC acts as an interrupt, and the write sequence is ignored by the device.

Power Supply Input. The AD5066 can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF

capacitor in parallel with a 0.1 µF capacitor to GND.

4

5

6

7

8

V_REF

B

External Reference Voltage Input for DAC B.

External Reference Voltage Input for DAC A.

Unbuffered Analog Output Voltage from DAC A.

Unbuffered Analog Output Voltage from DAC C.

Power-On Reset Pin. Tying this pin to GND powers the DAC outputs to zero scale on power-up. Tying

this pin to V_DDpowers the DAC outputs to midscale.

V_REFA

V_OUT

POR

A

C

9

V_REFC

External Reference Voltage Input for DAC C.

10

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are

ignored. When CLR is activated, the input register and the DAC register are updated with the data

contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.

11

12

13

14

15

V_REF

V_OUT

GND

DIN

D

B

External Reference Voltage Input for DAC D.

Unbuffered Analog Output Voltage from DAC D.

Unbuffered Analog Output Voltage from DAC B.

Ground Reference Point for All Circuitry on the Part.

Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input.

16

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates of up to 50 MHz.

Rev. A | Page 7 of 24

AD5066

TYPICAL PERFORMANCE CHARACTERISTICS

0.3

0.5

0.4

0.2

MAX INL

MIN INL

0.3

0.1

0.2

0

0.1

0

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 5V

DD

= 4.096V

REF

V

= 5V

DD

T = 25°C

A

–0.4

–0.5

T

= 25°C

A

0

10,000

20,000

30,000

CODE

40,000

50,000

60,000

2

3

4

5

REFERENCE VOLTAGE (V)

Figure 4. INL Error vs. Code

Figure 7. INL vs. Reference Input Voltage

0.5

0.4

0.3

0.2

V

= 5V

DD

= 4.096V

REF

T

= 25°C

A

0.3

0.1

0.2

0.1

MAX DNL

MIN DNL

0

–0.1

–0.2

–0.3

–0.4

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 5.5V

DD

= 25°C

T

A

2

3

4

5

0

10,000

20,000 30,000

CODE

40,000

50,000

60,000

REFERENCE VOLTAGE (V)

Figure 8. DNL vs. Reference Input Voltage

Figure 5. DNL Error vs. Code

0.03

0.02

100

80

0.01

60

0

40

MAX TUE

MIN TUE

–0.01

–0.02

–0.03

–0.04

–0.05

–0.06

–0.07

20

0

–20

–40

–60

–80

–100

V

= 5V

DD

= 4.096V

REF

T

= 25°C

A

V

= 5.5V

= 25°C

DD

T

A

0

10,000

20,000

30,000 40,000

CODE

50,000

60,000

2

3

4

5

REFERENCE VOLTAGE (V)

Figure 6. Total Unadjusted Error vs. Code

Figure 9. Total Unadjusted Error vs. Reference Input Voltage

Rev. A | Page 8 of 24

AD5066

1.2

1.0

0.010

0.005

0

0.8

0.6

0.4

0.2

MAX DNL

MIN DNL

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–0.005

–0.010

V

= 5V

DD

= 4.096V

V

T

= 5.5V

REF

DD

= 25°C

A

–40

–20

0

20

40

60

80

100

120

2

3

4

5

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

Figure 10. Gain Error Vs. Reference Input Voltage

Figure 13. DNL vs. Temperature

100

80

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

60

MAX TUE

40

20

0

–20

–40

–60

–80

–100

MIN TUE

V

= 5.5V

DD

= 25°C

T

A

V

= 5V

DD

= 4.096V

REF

–40

–20

0

20

40

60

80

100

120

2

3

4

5

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

Figure 11. Zero-Code Error Vs. Reference Input Voltage

Figure 14. Total Unadjusted Error vs. Temperature

1.2

1.0

50

40

MAX INL

0.8

30

0.6

20

0.4

10

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–10

–20

–30

–40

–50

MIN INL

V

= 5V

V

= 5V

DD

= 4.096V

REF

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 12. INL vs. Temperature

Figure 15. Zero-Code Error vs. Temperature

Rev. A | Page 9 of 24

AD5066

0.0020

0.0015

0.0010

0.0005

0

7

6

5

4

3

2

V

= 5V

DD

DAC OUTPUT UNLOADED

= 25°C

T

A

–0.0005

–0.0010

–0.0015

V

= 5V

1

0

DD

= 4.096V

REF

–0.0020

–40

2.45

2.50

2.55

2.60

2.65

2.70

–20

0

20

40

60

80

100

120

I

POWER-UP (mA)

DD

TEMPERATURE (°C)

Figure 16. Gain Error vs. Temperature

Figure 19. I_DDHistogram V_DD= 5.5 V

0.010

0.005

0

60

50

40

30

20

10

0

V

A

= 5V

DD

= 25°C

T

DAC OUTPUT UNLOADED

+125°C

+25°C

–40°C I POWERDOWN

I

POWERDOWN

DD

POWERDOWN

I

DD

FULL-SCALE ERROR

GAIN ERROR

–0.005

V

= 5V

DD

= 4.096V

REF

T

= 25°C

A

–0.010

2.7

3.2

3.7

4.2

(V)

4.7

5.2

0.2

0.4

0.6

0.8

1.0

V

I

POWERDOWN (µA)

DD

Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage

Figure 20. I_DDPower-Down Histogram

20

5

4

3

2

1

0

V

A

= 5.5V

REF

= 25°C

DD

= 4.096V

T

15

10

V

= 5V

DD

5

0

= 4.096V

REF

T

= 25°C

A

2.7

3.7

4.7

0

10,000

20,000

30,000

40,000

50,000

60,000

V

(V)

DD

DAC CODE

Figure 18. Zero-Code Error vs. Supply Voltage

Figure 21. I_DDvs. Code

Rev. A | Page 10 of 24

AD5066

5

4

3

2

1

0

3.5

V

A

= 5.5V

REF

= 25°C

DD

= 4.096V

1/4 TO 3/4

T

CODE = MIDSCALE

3.0

2.5

2.0

1.5

1.0

0.5

0

3/4 TO 1/4

V

= 4.5V

DD

= 4.096V

REF

OUTPUT AMPLIFIER = AD797

T

= 25°C

A

DAC LOAD = 9pF

–40

–20

0

20

40

60

80

100

120

0

1

2

3

4

5

6

7

A

8

9

10

TEMPERATURE (°C)

TIME (µs)

Figure 22. I_DDvs. Temperature

Figure 25. Settling Time

5

4

3

2

1

0

V

T

= 4.096V

REF

= 25°C

V

A

DD

CODE = MIDSCALE

REF

V

OUT

V

T

= 4.096V

REF

= 25°C

A

2.7

3.0

3.5

4.0

4.5

5.0

5.5

CH1 2.00V CH2 2.00V

CH3 2.00V

M10.00ms

30.20%

CH1

640mV

T

SUPPLY VOLTAGE (V)

Figure 26. POR to 0 V

Figure 23. I_DDvs. Supply Voltage

10

8

V

= 5.5V

DD

V

DD

= 4.096V

REF

T

= 25°C

A

REF

6

4

V

OUT

2

V

= 5.5V

= 4.096V

DD

REF

0

CH1 2.00V CH2 2.00V

CH3 2.00V

M10.00ms

30.20%

CH1

640mV

0

1

2

3

4

5

6

T

DIGITAL INPUT VOLTAGE (V)

Figure 27. POR to MS

Figure 24. I_DDvs. Digital Input Voltage

Rev. A | Page 11 of 24

AD5066

15

10

5

CH1 = SCLK

V

= 5V

DD

= 4.096V

REF

T

= 25°C

A

1

0

CH2 = V

V

= 5V

DD

OUT

POWER-UP TO MIDSCALE

OUTPUT UNLOADED

–5

–10

–15

2

–2

0

2

4

6

8

10

CH1 5V

CH2 500mV

M2µs

55%

A CH2

1.2V

TIME (µs)

T

Figure 28. Exiting PD to MS

Figure 31. Digital Crosstalk

15

20

15

V

= 5V

DD

V

= 4.096V

= 25°C

REF

10

5

T

A

10

5

0

–5

V

T

= 5V

DD

–10

–15

–20

= 4.096V

REF

= 25°C

–10

A

CODE = 0x8000 TO 0x7FFF

OUTPUT UNLOADED WITH 5kΩ AND 200pF

–15

–2

0

2

4

6

8

10

–2

0

2

4

6

8

10

TIME (µs)

Figure 29. Glitch

Figure 32. DAC-to-DAC Crosstalk

15

10

5

4

3

V

= 5V

DD

= 4.096V

REF

T

= 25°C

A

2

1

0

–1

–2

–3

–4

–5

–10

–15

V

= 5V

DD

= 4.096V

REF

T

= 25°C

A

–2

0

2

4

6

8

10

0

1

2

3

4

5

6

7

8

9

10

TIME (µs)

Time (Seconds)

Figure 30. Analog Crosstalk

Figure 33. 1/f Noise

Rev. A | Page 12 of 24

AD5066

0

–10

–20

–30

–40

–50

–60

–70

–80

V

T

= 5V,

DD

= 25ºC

CH1 PEAK TO PEAK

155mV

A

DAC LOADED WITH MIDSCALE

V

= 3.0V ± 200mV p-p

REF

V

OUT

LAST SCLK

V

= 5V

DD

= 4.096V

REF

–90

T

= 25°C

A

–100

CH1 50.0mV

CH2 5.00V

M4.00µs

9.800%

A

CH2

1.80V

5

10

20

30

FREQUENCY (kHz)

40

50

55

T

Figure 34. Total Harmonic Distortion

Figure 37. Glitch Upon Entering Power Down

CH1 PEAK TO PEAK

159mV

CLR

V

OUT

V

OUT

LAST SCLK

V

= 5V

DD

= 4.096V

REF

T

= 25°C

A

CH1 5.00V CH2 2.00V

M2.00ms

10.20%

A

CH1

1.80V

CH1 50.0mV

CH2 5.00V

M4.00µs

9.800%

A

CH2

1.80V

T

CLR

Figure 38. Glitch Upon Exiting Power Down

Figure 35. Hardware

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

1/4 TO 3/4

3/4 TO 1/4

V

= 4.5V

DD

= 4.096V

REF

T

= 25°C

A

1.5

1.6

1.7

1.8

1.9

2

2.1

2.2

2.3

2.4

TIME (µs)

Figure 36. Slew Rate

Rev. A | Page 13 of 24

AD5066

TERMINOLOGY

DC Crosstalk

Relative Accuracy or Integral Nonlinearity (INL)

Relative accuracy or INL is a measure of the maximum

deviation in LSBs from a straight line passing through the

endpoints of the DAC transfer function. Figure 4, Figure 5,

and Figure 6 show typical INL vs. code plots.

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is measured

with a full-scale output change on one DAC (or soft power-down

and power-up) while monitoring another DAC kept at midscale.

It is expressed in microvolts.

Differential Nonlinearity (DNL)

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal

at the DAC output to the reference input when the DAC output

is not being updated (that is,

decibels.

DNL is the difference between the measured change and the

ideal 1 LSB change between any two adjacent codes. A specified

differential nonlinearity of 1 LSB maximum ensures mono-

tonicity. Figure 7, Figure 8, and Figure 9 show typical DNL vs.

code plots.

LDAC

is high). It is expressed in

Digital Feedthrough

Zero-Code Error

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital input pins of the

device but is measured when the DAC is not being written to

Zero-code error is a measure of the output error when zero

code (0x0000) is loaded into the DAC register. Ideally, the

output should be 0 V. The zero-code error is always positive in

the AD5066, because the output of the DAC cannot go below

0 V. Zero-code error is expressed in millivolts. Figure 17 shows

a typical zero-code error vs. supply voltage plot.

SYNC

(

held high). It is specified in nanovolts per second and

measured with one simultaneous DIN and SCLK pulse loaded

to the DAC.

Digital Crosstalk

Gain Error

Digital crosstalk is the glitch impulse transferred to the output

of one DAC at midscale in response to a full-scale code change

(all 0s to all 1s or vice versa) in the input register of another

DAC. It is measured in standalone mode and is expressed in

nanovolts per second.

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale range.

Gain Error Drift

Gain error drift is a measure of the change in gain error with

changes in temperature. It is expressed in (ppm of full-scale

range)/°C.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output

of one DAC due to a change in the output of another DAC. It is

measured by loading one of the input registers with a full-scale

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code

error with a change in temperature. It is expressed in microvolts

per degrees Celsius.

LDAC

code change (all 0s to all 1s or vice versa) while keeping

LDAC

high and then pulsing

low and monitoring the output of

the DAC whose digital code has not changed. The area of the

glitch is expressed in nanovolts per second.

Full-Scale Error

Full-scale error is a measure of the output error when a full-

scale code (0xFFFF) is loaded into the DAC register. Ideally, the

output should be V_REF− 1 LSB. Full-scale error is expressed as a

percentage of the full-scale range.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DAC. This includes both digital and

analog crosstalk. It is measured by loading one of the DACs

with a full-scale code change (all 0s to all 1s or vice versa) with

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nanovolts

per second and is measured when the digital input code is

changed by 1 LSB at the major carry transition (0x7FFF to

0x8000). See Figure 28.

LDAC

low and monitoring the output of another DAC. The

energy of the glitch is expressed in nanovolts per second.

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and its

attenuated version using the DAC. The sine wave is used as

the reference for the DAC, and the THD is a measure of the

harmonics present on the DAC output. It is measured in

decibels.

DC Power Supply Rejection Ratio (PSRR)

DC PSRR indicates how the output of the DAC is affected by

changes in the supply voltage. DC PSRR is the ratio of the

change in V_OUTto a change in V_DDfor full-scale output of the

DAC. It is measured in decibels.

Rev. A | Page 14 of 24

AD5066

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

SERIAL INTERFACE

The AD5066 is a quad 16-bit, serial input, voltage output

nanoDAC. The part operates from supply voltages of 2.7 V to

5.5 V. Data is written to the AD5066 in a 32-bit word format via

a 3-wire serial interface. The AD5066 incorporates a power-on

reset circuit to ensure the DAC output powers up to a known

output state. The devices also have a software power-down mode

that reduces the typical current consumption to typically 400 nA.

SYNC

The AD5066 has a 3-wire serial interface (

, SCLK, and

DIN) that is compatible with SPI, QSPI, MICROWIRE, and

most DSP interface standards. See Figure 2 for a timing diagram

of a typical write sequence.

INPUT SHIFT REGISTER

The input shift register is 32 bits wide (see Figure 40). The first

four bits are don’t cares. The next four bits are the command

bits, C3 to C0 (see Table 7), followed by the 4-bit DAC address

bits, A3 to A0 (see Table 8), and finally the bit data-word. The

data-word comprises of a 16-bit input code followed by four don’t

care bits (see Figure 40). These data bits are transferred to the

Input register on the 32^ndfalling edge of SCLK. Commands can

be executed on individually selected DAC channels or on all DACs.

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

D













V_OUT V_REFIN



2^N

where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register (0 to 65,535).

N is the DAC resolution.

Table 7. Command Definitions

Command

DAC ARCHITECTURE

C3 C2 C1 C0 Description

The DAC architecture of the AD5066 consists of two matched

DAC sections. A simplified circuit diagram is shown in

0

1

Write to Input Register n

Transfer contents of Input Register n to

DAC Register n

Write to Input Register n and update all

DAC Registers

Write to Input Register n and update

DAC Register n

Power down/power up DAC

Load clear code register

Load LDAC register

Reset (power-on reset)

Reserved

Figure 39. The four MSBs of the 16-bit data word are decoded

to drive 15 switches, E1 to E15. Each of these switches connects

one of 15 matched resistors to either GND or the V_REFbuffer

output. The remaining 12 bits of the data word drive the S0 to

S11 switches of a 12-bit voltage mode R-2R ladder network.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V

OUT

2R

E1

2R

E2

2R

S0

2R

S1

2R

E15

S11

V

REF

Reserved

12-BIT R-2R LADDER

FOUR MSBs DECODED

INTO 15 EQUAL

SEGMENTS

Table 8. DAC Input Register Address Bits

Figure 39. DAC Ladder Structure

Address (n)

REFERENCE BUFFER

A3

0

A2

0

A1

0

1

A0

0

1

0

1

Selected DAC Channel

DAC A

DAC B

DAC C

DAC D

All DACs

The AD5066 operates with an external reference. Each of the

four on-board DACs has a dedicated voltage reference pin that

is buffered. The reference input pin has an input range of 2 V

to V_DD− 0.4 V. This input voltage is then used to provide a

buffered reference for the DAC core.

1

DB31 (MSB)

DB0 (LSB)

X

C3

C2

C1

C0

A3

A2

A1

A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X

DATA BITS

COMMAND BITS ADDRESS BITS

Figure 40. Input Shift Register Content

Rev. A | Page 15 of 24

AD5066

When Bit DB9 and Bit DB8 in the control register are set to 0,

the part is configured in normal mode with its normal power

consumption of 2.5 mA at 5 V. However, for the three power-

down modes, the supply current falls to 0.4 µA if all the channels

are powered down. Not only does the supply current fall, but

the output pin is also internally switched from the output of the

DAC to a resistor network of known values. This has the advantage

that the output impedance of the part is known while the part

is in power-down mode. There are three different options: the

output is connected internally to GND through either a 1 kΩ or

a 100 kΩ resistor, or it is left open-circuited (three-state). The

output stage is illustrated in Figure 41.

SYNC

The write sequence begins by bringing the

line low.

SYNC

Bringing the

line low enables the DIN and SCLK input

buffers. Data from the DIN line is clocked into the 32-bit shift

register on the falling edge of SCLK. The serial clock frequency

can be as high as 50 MHz, making the AD5066 compatible with

high speed DSPs. On the 32^ndfalling clock edge, the last data bit

is clocked in, and the programmed function is executed, that is,

a change in the input register contents (see Table 8) and/or a

SYNC

change in the mode of operation. At this stage, the

line

can be kept low or be brought high. In either case, it must be

brought high for a minimum of 2 μs (single-channel update, see

the t₈parameter in Table 4) before the next write sequence so

SYNC

that a falling edge of

can initiate the next write sequence.

high between write sequences for even lower power

operation of the part.

SYNC

DAC

V

OUT

SYNC

Idle

Interrupt

In a normal write sequence, the

least 32 falling edges of SCLK, and the DAC is updated on the

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

SYNC

line is kept low for at

32^ndfalling edge. However, if

is brought high before the

Figure 41. Output Stage During Power-Down Mode

SYNC

32^ndfalling edge, this acts as an interrupt to the write sequence.

The input shift register is reset, and the write sequence is seen

as invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Figure 42).

The bias generator, DAC core, and other associated linear

circuitry are shut down when all channels are powered down.

However, the contents of the DAC register are unaffected when

in power-down mode. The time to exit power-down mode is

typically 2.9 µs (see Figure 27).

Power-Down Modes

The AD5066 can be configured through software, in one of

four different modes: normal mode (default) and three separate

power-down modes (see Table 9). Any or all DACs can be

powered down. Command 0100 is reserved for the power-

down function (see Table 7). These power-down modes are

software-programmable by setting two bits, Bit DB9 and

Bit DB8, in the input shift register. Table 9 shows how the state

of the bits corresponds to the mode of operation of the device.

Any or all DACs (DAC A to DAC D) can be powered down to

the selected mode by setting the corresponding four bits (DB3,

DB2, DB1, DB0) to 1. See Table 10 for the contents of the input

shift register during power-down/power-up operation.

Table 9. Modes of Operation

DB9

DB8

Operating Mode

Normal operation

Power-down modes

1 kΩ to GND

0

1

0

1

100 kΩ to GND

Three-state

SCLK

SYNC

DB31

DB0

DB31

DB0

DIN

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 32 FALLING EDGE

VALID WRITE SEQUENCE:

ND

OUTPUT UPDATES ON THE 32 FALLING EDGE

ND

SYNC

Figure 42.

Interrupt Facility

Rev. A | Page 16 of 24

AD5066

where it is important to know the state of the output of the DAC

while it is in the process of powering up. There is also a software

executable reset function that resets the DAC to the power-on

reset code. Command 0111 is reserved for this reset function

POWER-ON RESET

The AD5066 contains a power-on reset circuit that controls

the output voltage during power-up. By connecting the POR

pin low, the AD5066 output powers up to 0 V; by connecting

the POR pin high, the AD5066 output powers up to midscale.

The output remains powered up at this level until a valid write

sequence is made to the DAC. This is useful in applications

LDAC CLR

(see Table 7). Any events on

reset are ignored.

or

during power-on

Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function

MSB

LSB

DB31 to

DB28

DB23 to

DB27 DB26 DB25 DB24 DB20

DB10 to

DB19

DB4 to

DB9 DB8 DB7

PD1 PD0

Power-down Don’t

mode cares

DB3

DAC D

DB2

DB1

DB0

X

0

1

0

X

DAC C

DAC B

DAC A

Don’t

cares

Command bits (C2 to C0)

Address bits

(A3 to A0)—

don’t cares

Don’t

cares

Power-down/power-up channel

selection—set bit to 1 to select

Rev. A | Page 17 of 24

AD5066

LDAC LDAC

Synchronous

data is read, the DAC registers are updated on the falling edge

LDAC

:

is held permanently low. After new

of the 32^ndSCLK pulse, provided

LDAC LDAC

CLEAR CODE REGISTER

CLR

The AD5066 has a hardware

pin that is an asynchronous

is held low.

is held high then pulsed low to

update. The outputs are not updated at the same time that the

LDAC

CLR

clear input. The

CLR

input is falling edge sensitive. Bringing the

Asynchronous

:

line low clears the contents of the input register and the

DAC registers to the data contained in the user-configurable

CLR

input registers are written to. When

is pulsed low, the

register and sets the analog outputs accordingly (see

DAC registers are updated with the contents of the input

registers.

Table 11). This function can be used in system calibration to

load zero scale, midscale, or full scale to all channels together.

These clear code values are user-programmable by setting two

bits, Bit DB1 and Bit DB0, in the control register (see Table 11).

The default setting clears the outputs to 0 V. Command 0101 is

reserved for loading the clear code register (see Table 7).

Command 0001, 0010 and 0011 (see Table 7) update the DAC

LDAC

Register/Registers, regardless of the level of the

LDAC

Software

Function

Writing to the DAC using Command 0110 loads the 4-bit

Table 11. Clear Code Register

LDAC

register (DB3 to DB0). The default for each channel is

DB1 (CR1)

DB0 (CR0)

Clears to Code

0x0000

0x8000

0xFFFF

No operation

LDAC

0; that is, the

pin works normally. Setting the bits to 1

0

1

0

1

0

1

updates the DAC channel regardless of the state of the hardware

LDAC LDAC

pin, so that it effectively sees the hardware

as being tied low (see Table 12 for the LDAC register mode of

operation.) This flexibility is useful in applications where the

user wants to simultaneously update select channels while the

remainder of the channels are synchronously updating.

The part exits clear code mode on the 32^ndfalling edge of the

CLR

next write to the part. If

sequence, the write is aborted.

CLR

is activated during a write

LDAC

Table 12. Load

Bits

Register

LDAC

CLR

to when

The

pulse activation time (the falling edge of

LDAC

(DB3 to

DB0)

the output starts to change) is typically 10.6 µs. See Table 13 for

contents of the input shift register during the loading clear code

register operation.

Operation

LDAC

1/0

X¹

0

1

Determined by LDAC pin

DAC channels update, overrides the LDAC

pin; DAC channels see LDAC as 0

LDAC FUNCTION

LDAC

Hardware

¹X = don’t care.

The outputs of all DACs can be updated simultaneously using

the hardware LDAC pin, as shown in Figure 2. There are two

methods of using the hardware LDAC pin: synchronously

LDAC

The

over the hardware

bits (DB0 to DB3) to 0 for a DAC channel means that this

LDAC

register gives the user extra flexibility and control

LDAC LDAC

pin (see Table 14). Setting the

LDAC

(

LDAC

permanently low) and asynchronously (

pulsed).

channel’s update is controlled by the hardware

pin.

Table 13. 32-Bit Input Shift Register Contents for Clear Code Function

MSB

LSB

DB31 to DB28

X

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB2 to DB19

X

DB1

1/0

DB0

0

1

0

1

X

1/0

Don’t cares

Command bits (C3 to C0)

Address bits (A3 to A0)

Don’t cares

Clear code register

(CR1 to CR0)

LDAC

Table 14. 32-Bit Input Shift Register Contents for

Overwrite Function

MSB

LSB

DB31

to DB28

DB4

to DB19

DB27 DB26 DB25 DB24 DB23 to DB20

DB3

DB2

DAC C

DB1

DB0

X

0

1

0

X

DAC D

DAC B

DAC A

Don’t cares Command bits (C3 to C0)

Address bits (A3 to A0)—don’t cares

Don’t cares Setting LDAC bit to 1 override LDAC pin

Rev. A | Page 18 of 24

AD5066

AD5066 to 68HC11/68L11 Interface

POWER SUPPLY BYPASSING AND GROUNDING

Figure 44 shows a serial interface between the AD5066 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the AD5066, and the MOSI output drives

When accuracy is important in a circuit, it is helpful to carefully

consider the power supply and ground return layout on the

board. The printed circuit board containing the AD5066 should

have separate analog and digital sections. If the AD5066 is in a

system where other devices require an AGND-to-DGND con-

nection, make the connection at one point only and as close as

possible to the AD5066.

SYNC

DIN of the DAC. A port line (PC7) drives the

signal.

68HC11/68L11*

AD5066*

PC7

SCK

SYNC

Bypass the power supply to the AD5066 with 10 µF and 0.1 µF

capacitors. The capacitors should be physically as close as

possible to the device, with the 0.1 µF capacitor, ideally, right up

against the device. The 10 µF capacitors are the tantalum bead

type. It is important that the 0.1 µF capacitor has low effective

series resistance and low effective series inductance, typical of

common ceramic types of capacitors. This 0.1 µF capacitor

provides a low impedance path to ground for high frequencies

caused by transient currents due to internal logic switching.

SCLK

DIN

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 44. AD5066 to 68HC11/68L11 Interface

The setup conditions for correct operation of this interface are

as follows: The 68HC11/68L11 is configured with its CPOL bit

as 0, and the CPHA bit as 1. When data is being transmitted to

SYNC

the DAC, the

line is taken low (PC7). When the 68HC11/

The power supply line should have as large a trace as possible to

provide a low impedance path and reduce glitch effects on the

supply line. Shield the clocks and other fast switching digital

signals from other parts of the board by digital ground. Avoid

crossover of digital and analog signals if possible. When traces

cross on opposite sides of the board, ensure that they run at

right angles to each other to reduce feedthrough effects through

the board. The best board layout technique is the microstrip

technique, where the component side of the board is dedicated

to the ground plane only, and the signal traces are placed on

the solder side. However, this is not always possible with a

2-layer board.

68L11 is configured as described previously, data appearing on

the MOSI output is valid on the falling edge of SCK. Serial data

from the 68HC11/68L11 is transmitted in 8-bit bytes with only

eight falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. To load data to the AD5066, PC7 is left

low after the first eight bits are transferred, and a second serial

write operation is performed to the DAC. PC7 is taken high at

the end of this procedure.

MICROPROCESSOR INTERFACING

AD5066 to Blackfin® ADSP-BF53X Interface

Figure 43 shows a serial interface between the AD5066 and

the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x

processor family incorporates two dual-channel synchronous

serial ports, SPORT1 and SPORT0, for serial and multipro-

cessor communications. Using SPORT0 to connect to the

AD5066, the setup for the interface is as follows: DT0PRI

drives the DIN pin of the AD5066, TSCLK0 drives the SCLK

SYNC

of the parts, and TFS0 drives

.

ADSP-BF53x*

AD5066*

TFS0

DT0PRI

TSCLK0

SYNC

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 43. AD5066 to Blackfin ADSP-BF53X Interface

Rev. A | Page 19 of 24

AD5066

AD5066 to 80C51/80L51 Interface

80C51/80L51*

AD5066*

Figure 45 shows a serial interface between the AD5066 and the

80C51/80L51 microcontroller. The setup for the interface is as

follows: TxD of the 80C51/80L51 drives SCLK of the AD5066,

RxD drives DIN on the AD5066, and a bit-programmable pin on

P3.3

TxD

RxD

SYNC

SCLK

DIN

SYNC

the port (P3.3) drives the

signal. When data is to be

transmitted to the AD5066, P3.3 is taken low. The 80C51/80L51

transmit data in 8-bit bytes only; thus, only eight falling clock

edges occur in the transmit cycle. To load data to the DAC, P3.3

is left low after the first eight bits are transmitted, and a second,

third, and fourth write cycle is initiated to transmit the second,

third, and fourth byte of data. P3.3 is taken high following the

completion of this cycle. The 80C51/80L51 output the serial

data in a format that has the LSB first. The AD5066 must

receive data with the MSB first. The 80C51/80L51 transmit

routine should take this into account.

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 45. AD5066 to 80C512/80L51 Interface

AD5066 to MICROWIRE Interface

Figure 46 shows an interface between the AD5066 and any

MICROWIRE-compatible device. Serial data is clocked into

the AD5066 on the falling edge of the SCLK.

MICROWIRE*

AD5066*

CS

SK

SO

SYNC

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 46. AD5066 to MICROWIRE Interface

Rev. A | Page 20 of 24

AD5066

APPLICATIONS INFORMATION

R2 = 10kΩ

USING A REFERENCE AS A POWER SUPPLY

+5V

Because the supply current required by the AD5066 is extremely

low, an alternative option is to use a voltage reference to supply

the required voltage to the parts (see Figure 47). This is espe-

cially useful if the power supply is quite noisy or if the system

supply voltages are at some value other than 5 V or 3 V, for

example, 15 V. The voltage reference outputs a steady supply

voltage for the AD5066. If the low dropout REF195 is used, it

must supply 2.5 mA of current to the AD5066 with no load on

the output of the DAC.

R1 = 10kΩ

+5.5V

+5V

AD820/

OP295

±5V

V

REF

V

REF

V

OUT

DD

–5V

0.1µF

10µF

AD5066

3-WIRE

SERIAL INTERFACE

15V

Figure 48. Bipolar Operation with the AD5066

5V

4.5V

REF195

REF194

USING THE AD5066 WITH A GALVANICALLY

ISOLATED INTERFACE

V

REF

DD

SYNC

In process control applications in industrial environments,

it is often necessary to use a galvanically isolated interface to

protect and isolate the controlling circuitry from any hazardous

common-mode voltages that can occur in the area where

the DAC is functioning. iCoupler® provides isolation in excess

of 2.5 kV. The AD5066 uses a 3-wire serial logic interface, so

the ADuM1300 three-channel digital isolator provides the

required isolation (see Figure 49). The power supply to the

part also needs to be isolated, which is done by using a

transformer. On the DAC side of the transformer, a 5 V

regulator provides the 5 V supply required for the AD5066.

3-WIRE

SERIAL

V

x = 0V TO 4.5V

OUT

AD5066

SCLK

DIN

INTERFACE

Figure 47. REF195 as a Power Supply to the AD5066

BIPOLAR OPERATION

The AD5066 has been designed for single-supply operation,

but a bipolar output range is also possible using the circuit in

Figure 48. The circuit gives an output voltage range of 5 V.

Rail-to-rail operation at the amplifier output is achieved

using an AD8638 or AD8639 the output amplifier.

5V

REGULATOR

10µF

0.1µF

POWER

The output voltage for any input code can be calculated as

follows:









D

65,536

R1+ R2

R1

R2

R1

































V = V

×

− V

×



O

DD

V





DD



SCLK

V

SCLK

IA

IB

IC

OA

where:

D = the input code in decimal (0 to 65,535).

_DD= 5 V.

R1 = R2 = 10 kΩ.

ADuM1300

AD5066

V

SDI

V

x

V

SYNC

DIN

OUT

OB

OC

10 × D

65,536





V =

− 5 V





V

DATA

O





GND

This is an output voltage range of 5 V, with 0x0000 corre-

sponding to a −5 V output, and 0xFFFF corresponding to a

+5 V output.

Figure 49. AD5066 with a Galvanically Isolated Interface

Rev. A | Page 21 of 24

AD5066

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 50. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeter

ORDERING GUIDE

Package

Option

Power-On

Reset to Code

Model¹

Temperature Range

−40°C to +125°C

Package Description

16-Lead TSSOP

Accuracy

1 LSB INL

4 LSB INL

Resolution

16 bits

AD5066BRUZ

AD5066BRUZ-REEL7

AD5066ARUZ

RU-16

Zero

AD5066ARUZ-REEL7

¹Z = RoHS Compliant Part.

Rev. A | Page 22 of 24

AD5066

NOTES

Rev. A | Page 23 of 24

AD5066

NOTES

registered trademarks are the property of their respective owners.

D06845-0-8/10(A)

Rev. A | Page 24 of 24


型号：	AD50601
厂家：	ADI
描述：	Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP 完全准确， 16位，无缓冲VOUT ，四路SPI接口， 2.7 V至5.5 V属于nanoDAC采用TSSOP
文件：	总24页 (文件大小：617K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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