AD5061YRJZ-1500RL7_技术文档

16-Bit V_OUTnanoDAC

SPI Interface 2.7 V to 5.5 V, in an SOT-23

Data Sheet

AD5061

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

DD

Single 16-bit digital-to-analog converter (DAC), 4 LSB INL

Power-on reset to midscale or zero-scale

Guaranteed monotonic by design

3 power-down functions

Low power serial interface with Schmitt-triggered inputs

Small 8-lead SOT-23 package, low power

Fast settling time of 4 μs typically

2.7 V to 5.5 V power supply

REF

POWER-ON

RESET

AD5061

BUF

OUTPUT

BUFFER

REF(+)

DAC

REGISTER

V

OUT

AGND

Low glitch on power-up

SYNC interrupt facility

INPUT

CONTROL

LOGIC

POWER-DOWN

CONTROL LOGIC

RESISTOR

NETWORK

APPLICATIONS

Process control

Data acquisition systems

SYNC SCLK DIN

DACGND

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

Figure 1.

GENERAL DESCRIPTION

Table 1. Related Devices

The AD5061, a member of the Analog Devices, Inc., nanoDAC^™

family, is a low power, single 16-bit buffered voltage-out DAC

that operates from a single 2.7 V to 5.5 V supply. The part offers

a relative accuracy specification of ±± ꢀLB and operation is

guaranteed monotonic with a ±1 ꢀLB DNꢀ specification. The

part uses a versatile 3-wire serial interface that operates at clock

rates up to 30 MHz, and is compatible with standard LPI, QLPI™,

MICROWIRE, and DLP interface standards. The reference for

the AD5061 is supplied from an external V_REFpin. A reference

buffer is also provided on-chip. The part incorporates a power-

on reset circuit that ensures the DAC output powers up to mid-

scale or zero scale and remains there until a valid write takes

place to the device. The part contains a power-down feature that

reduces the current consumption of the device to typically

330 nA at 5 V and provides software-selectable output loads

while in power-down mode. The part is put into power-down

mode over the serial interface. Total unadjusted error for the part

is <3 mV. This part exhibits very low glitch on power-up.

Part No.

Description

AD5062

2.7 V to 5.5 V, 16-bit nanoDAC converter,

1 LSB INL, SOT-23

2.7 V to 5.5 V, 16-bit nanoDAC converter,

1 LSB INL, MSOP

2.7 V to 5.5 V, 14-bit/16-bit nanoDAC

converter, 1 LSB INL, SOT-23

AD5063

AD5040/AD5060

PRODUCT HIGHLIGHTS

1. Available in a small 8-lead LOT-23 package.

2. 16-bit resolution, ± ꢀLB INꢀ.

3. ꢀow glitch on power-up.

±. High speed serial interface with clock speeds up to 30 MHz.

5. Three power-down modes available to the user.

6. Reset to known output voltage (midscale or zero scale).

Rev. C

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD5061* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

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DESIGN RESOURCES

• AD5061 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

EVALUATION KITS

• Evaluation Board for the AD5040/AD5060, AD5061 and

AD5062

DISCUSSIONS

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DOCUMENTATION

Data Sheet

• AD5061:16-Bit VOUT nanoDAC™ SPI Interface 2.7 V to 5.5

V, in an SOT-23 Data Sheet

SAMPLE AND BUY

Visit the product page to see pricing options.

User Guides

• UG-923: Evaluating the AD5040/AD5060, AD5061, and

AD5062 16-/14-Bit, nanoDAC

TECHNICAL SUPPORT

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number.

SOFTWARE AND SYSTEMS REQUIREMENTS

• AD5040/AD5060/AD5061/AD5062/AD5063 Software

Evaluation

DOCUMENT FEEDBACK

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REFERENCE MATERIALS

Solutions Bulletins & Brochures

• Digital to Analog Converters ICs Solutions Bulletin

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AD5061

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Reference Buffer ......................................................................... 15

Serial Interface............................................................................ 15

Input Shift Register .................................................................... 15

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

DAC Architecture....................................................................... 15

SYNC

Interrupt .......................................................................... 15

Power-On to Zero-Scale or Midscale ...................................... 16

Software Reset............................................................................. 16

Power-Down Modes .................................................................. 16

Microprocessor Interfacing....................................................... 17

Applications Information.............................................................. 18

Choosing a Reference ................................................................ 18

Bipolar Operation....................................................................... 18

Using a Galvanically-Isolated Interface Chip......................... 19

Power Supply Bypassing and Grounding................................ 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

1/06—Rev. 0 to Rev. A

8/15—Rev. B to Rev. C

Changes to General Description .....................................................1

Changes to Table 2.............................................................................3

Changes to Figure 19 Caption ...................................................... 10

Added Figure 28 to Figure 36 ....................................................... 12

Changes to Serial Interface Section.............................................. 15

Changes to Power-Down Modes Section.................................... 16

Changes to Ordering Guide.......................................................... 20

Changed ADSP-BF53x to ADSP-BF527, ADR43x

to ADR435, and ADuM130x to ADuM1300...................Throughout

Deleted AD5061-to-ADSP-2101/ADSP-2103 Interface Section

and Figure 40; Renumbered Sequentially ...........................................16

Changes to Figure 42...............................................................................17

Changes to Figure 46...............................................................................18

Changes to Figure 47...............................................................................19

7/05—Revision 0: Initial Version

5/11—Rev. A to Rev. B

Changes to Data Sheet Title and Product Highlights Section.... 1

Changes to Ordering Guide .......................................................... 20

Rev. C | Page 2 of 20

Data Sheet

AD5061

SPECIFICATIONS

V_DD= 5.5 V, V_REF= 4.096 V, R_L= unloaded, C_L= unloaded, T_MINto T_MAX, unless otherwise specified.

Table 2.

B Grade¹

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

16

Bits

LSB

Relative Accuracy (INL)²

±0.5

±±

±3.0

±1

−±0°C to +85°C, B grade

−±0°C to +125°C, Y grade

−±0°C to +85°C, B grade

−±0°C to +125°C, Y grade

Guaranteed monotonic, −±0°C to +85°C, B grade

Guaranteed monotonic, −±0°C to +125°C,

Y grade

Total Unadjusted Error (TUE)

Differential Nonlinearity (DNL)

mV

LSB

±1

Gain Error

±0.01

1

±0.02

0.5

±0.05

% of FSR

T_A= −±0°C to +85°C, B grade

T_A= −±0°C to +125°C , Y grade

Gain Error Temperature Coefficient

Offset Error

ppm of FSR/°C

mV

±3.0

T_A= −±0°C to + 85°C, B grade

T_A= −±0°C to + 125°C, Y grade

Offset Error Temperature Coefficient

Full-Scale Error

µV/°C

mV

±0.05

±3.0

All 1s loaded to DAC register,

T_A= −±0°C to +85°C, B grade

All 1s loaded to DAC register,

T_A= −±0°C to +125°C , Y grade

±0.05

OUTPUT CHARACTERISTICS³

Output Voltage Range

0

V_REF

V

Output Voltage Settling Time

±

µs

¼ scale to ¾ scale code transition to ±1LSB,

R_L= 5 KΩ

Output Noise Spectral Density

Output Voltage Noise

Digital-to-Analog Glitch Impulse

Digital Feedthrough

DC Output Impedance (Normal)

DC Output Impedance (Power-Down)

(Output Connected to 1 kΩ Network)

(Output Connected to 100 kΩ Network)

Capacitive Load Stability

6±

DAC code = midscale, 1 kHz

nV/√Hz

µV p-p

nV-s

Ω

6

2

DAC code = midscale , 0.1 Hz to 10 Hz bandwidth

1 LSB change around major carry, R_L= 5 KΩ

DAC code = full-scale

0.003

0.015

Output impedance tolerance ±10%

1

100

kΩ

nF

Output impedance tolerance ±±00 Ω

Output impedance tolerance ±20 kΩ

Loads used: R_L= 5 kΩ, R_L= 100 kΩ, R_L= ∞

1

Output Slew Rate

1.2

60

±5

V/μs

¼ scale to ¾ scale code transition to ±1 LSB,

R_L= 5 kΩ, C_L= 200 pF

DAC code = full-scale, output shorted to GND,

T_A= 25°C

DAC code = zero-scale, output shorted to V_DD,

T_A= 25°C

Time to exit power-down mode to normal

mode of AD5061, 2±^thclock edge to 90% of

DAC final value, output unloaded

Short-Circuit Current

DAC Power-Up Time

mA

DC Power Supply Rejection Ratio

Wideband Spurious-Free Dynamic Range

REFERENCE INPUT/OUTPUT

V_REFInput Range^±

Input Current (Power-Down)

Input Current (Normal)

−92

−67

dB

V_DD±10%, DAC code = full-scale

Output frequency = 10 kHz

2

V_DD− 50

±0.5

mV

µA

±0.1

1

Zero-scale loaded

DC Input Impedance

MΩ

Rev. C | Page 3 of 20

AD5061

Data Sheet

B Grade¹

Typ

Parameter

Min

Max

Unit

Test Conditions/Comments

LOGIC INPUTS

Input Current⁵

Input Low Voltage (V_IL)

±1

±5

0.8

µA

V

V_DD= ±.5 V to 5.5 V

V_DD= 2.7 V to 3.6 V

V_DD= 2.7 V to 5.5 V

V_DD= 2.7 V to 3.6 V

Input High Voltage (V_IH)

2.0

1.8

V

Pin Capacitance

POWER REQUIREMENTS

V_DD

I_DD(Normal Mode)

V_DD= 2.7 V to 5.5 V

±

pF

V

2.7

5.5

1.2

All digital inputs at 0 V or V_DD

DAC active and excluding load current

V_IN= V_DDand V_IL= GND, V_DD= 5.5 V,

1.0

mA

V

_REF= ±.096 V, code = midscale

0.89

V_IN= V_DDand V_IL= GND, V_DD= 3.0 V,

V_REF= ±.096 V, code = midscale

I_DD(All Power-Down Modes)

V_DD= 2.5 V to 5.5 V

1

µA

V_IH= V_DDand V_IL= GND, V_DD= 5.5 V,

V_REF= ±.096 V, code = midscale

0.265

V_IH= V_DDand V_IL= GND, V_DD= 3.0 V,

V

_REF= ±.096 V, code = midscale

¹Temperature range for B grade: −±0°C to +85°C, typical at 25°C; temperature range for Y grade: −±0°C to +125°C.

²Linearity calculated using a reduced code range (160 to 65535).

³Guaranteed by design and characterization, not production tested.

^±The typical output supply headroom performance for various reference voltages at −±0°C can be seen in Figure 27.

⁵Total current flowing into all pins.

Rev. C | Page ± of 20

Data Sheet

AD5061

TIMING CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, all specifications T_MINto T_MAX, unless otherwise specified.

Table 3.

Parameter

Limit¹

Unit

Test Conditions/Comments

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge set-up time

Data set-up time

2

t₁

33

5

3

10

3

2

ns min

t₂

t₃

t_±

t₅

t₆

t₇

t₈

t₉

Data hold time

0

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to next SCLK fall ignore

12

9

¹All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

²Maximum SCLK frequency is 30 MHz.

t₄

t₂

t₁

t₉

SCLK

SYNC

t₇

t₃

t₈

t₆

t₅

DIN

D23

D22

D2

D1

D0

D23

D22

Figure 2. Timing Diagram

Rev. C | Page 5 of 20

AD5061

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 4.

This device is a high performance integrated circuit with an

ESD rating of <2 kV, and is ESD-sensitive. Proper precautions

should be taken for handling and assembly.

Parameter

Rating

V_DDto GND

Digital Input Voltage to GND

V_OUTto GND

−0.3 V to +7.0 V

−0.3 V to V_DD+ 0.3 V

ESD CAUTION

V_REFto GND

Operating Temperature Range

Industrial (B Grade)

−±0°C to + 85°C

Extended Automotive Temperature

Range (Y Grade)

Storage Temperature Range

Maximum Junction Temperature

SOT-23 Package

−±0°C to +125°C

−65°C to +150°C

150°C

Power Dissipation

(T_Jmax − T_A)/θ_JA

206°C/W

±±°C/W

θ_JAThermal Impedance

θ_JCThermal Impedance

Reflow Soldering (Pb-Free)

Peak Temperature

260°C

Time-at-Peak Temperature

ESD

10 sec to ±0 sec

1.5 kV

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. C | Page 6 of 20

Data Sheet

AD5061

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

8

7

6

5

DIN

SCLK

AD5061

V

TOP VIEW

DD

SYNC

(Not to Scale)

DACGND

V

REF

V

AGND

OUT

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

DIN

Serial Data Input. This device has a 2±-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input.

2

3

±

5

6

7

V_DD

V_REF

V_OUT

AGND

DACGND

SYNC

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and V_DDshould be decoupled to GND.

Reference Voltage Input.

Analog Output Voltage from DAC.

Ground Reference Point for Analog Circuitry.

Ground Input to the DAC.

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.

The DAC is updated following the 2±th clock cycle unless SYNC is taken high before this edge, in which case the

rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.

8

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz.

Rev. C | Page 7 of 20

AD5061

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1.6

1.2

1.0

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

T

= 25°C

= 5V, V

DD

REF

A

1.4

V

= 4.096V

REF

DD

1.2

0.8

1.0

0.8

0.6

MAX DNL ERROR @ V = 2.7V

DD

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

MAX DNL ERROR @ V = 5.5V

DD

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

MIN DNL ERROR @ V = 2.7V

DD

MIN DNL ERROR @ V = 5.5V

DD

160

10160

20160

30160

40160

50160

60160

–40

–20

0

20

40

60

80

100

120

140

DAC CODE

TEMPERATURE (°C)

Figure 4. Typical INL Plot

Figure 7. DNL vs. Temperature

1.2

1.0

0.16

0.14

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

T

V

= 25°C

DD

REF

A

= 5V, V

= 4.096V

DD

REF

0.12

0.8

0.10

MAX TUE ERROR @ V

= 2.7V

DD

0.6

0.08

0.06

0.4

0.04

0.2

MAX TUE ERROR @ V

= 5.5V

0.02

DD

MIN TUE ERROR @ V = 5.5V

DD

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

–0.14

–0.16

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

MIN TUE ERROR @ V = 2.7V

DD

–40

–20

0

20

40

60

80

100

120

140

160

10160

20160

30160

40160

TEMPERATURE (°C)

DAC CODE

Figure 5. Typical TUE Plot

Figure 8. TUE vs. Temperature

1.6

1.4

1.6

1.4

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

T

V

= 25°C

= 5V, V

DD

REF

A

= 4.096V

REF

DD

1.2

1.0

MAX INL ERROR @ V = 2.7V

DD

0.8

0.6

0.4

0.2

MAX INL ERROR @ V = 5.5V

DD

MIN INL ERROR @ V = 5.5V

DD

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

MIN INL ERROR @ V = 2.7V

DD

160

10160

20160

30160

40160

–40

–20

0

20

40

60

80

100

120

140

DAC CODE

TEMPERATURE (°C)

Figure 6. Typical DNL Plot

Figure 9. INL vs. Temperature

Rev. C | Page 8 of 20

Data Sheet

AD5061

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

T

= 25°C

A

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

1.4

1.2

DD

REF

DD

REF

CODE = FULL-SCALE

1.0

V

= 5.5V

= 2.7V

0.8

DD

0.6

0.4

MAX DNL ERROR @ V = 5.5V

DD

0.2

DD

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

MIN DNL ERROR @ V = 5.5V

DD

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

–40

–20

0

20

40

60

80

100

120

140

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

Figure 13. Supply Current vs. Temperature

Figure 10. DNL vs. Reference Input Voltage

1.2

1.0

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

T

= 25°C

T

A

= 25°C

A

0.8

0.6

0.4

MAX TUE ERROR @ V

= 5.5V

DD

0.2

0

V

= 5.5V, V = 4.096V

REF

DD

MIN TUE ERROR @ V = 5.5V

DD

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

V

= 3.0V, V = 2.5V

REF

DD

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0

10000

20000

30000

40000

50000

60000

70000

REFERENCE VOLTAGE (V)

DAC CODE

Figure 14. Supply Current vs. Digital Input Code

Figure 11. TUE vs. Reference Input Voltage

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.6

1.4

T

A

= 25°C

V

= 2.5V

= 25°C

REF

T

A

1.2

CODE = MIDSCALE

1.0

0.8

0.6

MAX INL ERROR @ V = 5.5V

DD

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

MIN INL ERROR @ V = 5.5V

DD

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE (V)

Figure 12. INL vs. Reference Input Voltage

Figure 15. Supply Current vs. Supply Voltage

Rev. C | Page 9 of 20

AD5061

Data Sheet

Figure 19. Exiting Power-Down Time to Midscale

Figure 16. Offset vs. Temperature

Figure 17. Digital-to-Analog Glitch Impulse; See Figure 21

Figure 20. 0.1 Hz to 10 Hz Noise Plot

Figure 18. Output Noise Spectral Density

Figure 21. Glitch Energy

Rev. C | Page 10 of 20

Data Sheet

AD5061

0.10

V

= 5.5V, V

= 2.7V, V

= 4.096V

= 2.0V

DD

REF

0.08

0.06

0.04

0.02

0

CH1 = V

DD

GAIN ERROR @ V = 2.7V

DD

GAIN ERROR @ V = 5.5V

DD

–0.02

–0.04

–0.06

–0.08

–0.10

CH2 = V

OUT

V

= 5V V

= 4.096V

DD

REF DD

RAMP RATE = 200µs

T

= 25°C

A

CH1 2V/DIV CH2 1V/DIV TIME BASE = 100µs

–40

–20

0

20

40

60

80

100

120

140

TEMPERATURE (°C)

Figure 22. Gain Error vs. Temperature

Figure 25. Hardware Power-Down Glitch

16

14

12

10

8

CH1 = SCLK

CH2 = SYNC

6

CH3 = V

OUT

4

2

V

T

= 5V V = 4.096V

REF DD

DD

= 25°C

CH4 = TRIGGER

A

0

0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.90 0.91 MORE

BIN

CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV

TIME BASE 1µs/DIV

Figure 26. Exiting Software Power-Down Glitch

Figure 23. I_DDHistogram @ V_DD= 3 V

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

14

12

10

8

6

4

2

0

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 MORE

BIN

REFERENCE VOLTAGE (V)

Figure 27. V_DDHeadroom vs. Reference Voltage.

Figure 24. I_DDHistogram @ V_DD= 5 V

Rev. C | Page 11 of 20

AD5061

Data Sheet

5.05

5.00

4.95

4.90

4.85

4.80

4.75

4.70

4.65

4.60

4.55

V

= 5.0V

= 25°C

DD

C4 = 50mV p-p

1kΩ TO GND

ZERO-SCALE

T

A

DAC = FULL-SCALE

4.70 4.72 4.74 4.76 4.78 4.80 4.82 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00

CH4 20.0mV

M1.00µs

CH1

1.64V

V

(V)

REF

Figure 28. Typical Output Voltage vs. Reference Voltage

Figure 31. Typical Glitch upon Exiting Software Power-Down to Zero-Scale

5.005

5.000

4.995

4.990

4.985

4.980

4.975

V

= 5V

= 25°C

REF

T

A

C2

25mV p-p

C3

4.96V p-p

T

2

C3 FALL

935.0µs

C3 RISE

∞s

NO VALID

T

EDGE

3

5.50 5.45 5.40 5.35 5.30 5.25 5.20 5.15 5.10 5.05 5.00

(V)

CH3 2.00V CH2 50mV

M1.00ms

CH3

1.36V

V

DD

Figure 32. Typical Glitch upon Exiting Hardware Power-Down to Three State

Figure 29. Typical Output Voltage vs. Supply Voltage

C4 = 143mV p-p

C2

30mV p-p

ZERO-SCALE

1kΩ TO GND

C3

4.96V p-p

T

2

C3 FALL

∞s

NO VALID

EDGE

T

C3 RISE

946.2µs

3

CH4 50.0mV

M4.00µs

CH1

1.64V

CH3 2.00V CH2 50mV

M1.00ms

CH3

1.36V

Figure 30. Typical Glitch upon Entering Software Power-Down to Zero-Scale

Figure 33. Typical Glitch upon Entering Hardware Power-Down to Zero-Scale

Rev. C | Page 12 of 20

Data Sheet

AD5061

0.0010

2.1

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

V

= 5.5V

DD

CODE = MIDSCALE

= 4.096V

REF

V

= 5V, V

= 3V, V

= 4.096V

= 2.5V

0.0008

0.0006

0.0004

0.0002

0

DD

REF

10% TO 90% RISE TIME = 0.688µs

SLEW RATE = 1.16V/µs

2.04V

DAC

–0.0002

–0.0004

–0.0006

–0.0008

OUTPUT

V

= 5.5V

DD

1.04V

V

= 3V

DD

–25 –20 –15 –10 –5

0

5

10

15

20

25

30

–10µs –8µs –6µs –4µs –2µs

0

2µs 4µs 6µs 8µs 9.96µs

CURRENT (mA)

Figure 34. Typical Output Load Regulation

Figure 36. Typical Output Slew Rate

0.10

0.08

0.06

0.04

0.02

0

CODE = MIDSCALE

V

= 5V, V

= 3V, V

= 4.096V

= 2.5V

DD

REF

V

= 3V, V = 2.5V

REF

DD

–0.02

–0.04

–0.06

–0.08

–0.10

V

= 5V, V

REF

= 4.096V

0

DD

–25 –20 –15 –10 –5

5

10

15

20

25

30

I

(mA)

OUT

Figure 35. Typical Current Limiting Plot

Rev. C | Page 13 of 20

AD5061

Data Sheet

TERMINOLOGY

Relative Accuracy

Total Unadjusted Error (TUE)

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer function. A

typical INL vs. code plot is shown in Figure 4.

Total unadjusted error is a measure of the output error taking

all the various errors into account. A typical TUE vs. code plot

is shown in Figure 5.

Zero-Code Error Drift

Differential Nonlinearity (DNL)

This is a measure of the change in zero-code error with a

change in temperature. It is expressed in µV/°C.

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent codes.

A specified differential nonlinearity of 1 LSB maximum ensures

monotonicity. This DAC is guaranteed monotonic by design. A

typical AD5061 DNL vs. code plot is shown in Figure 6.

Gain Error Drift

This is a measure of the change in gain error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

Digital-to-Analog Glitch Impulse

Zero-Code Error

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-s and is

measured when the digital input code is changed by 1 LSB at

the major carry transition; see Figure 17 and Figure 21. The

expanded view in Figure 17 shows the glitch generated following

completion of the calibration routine; Figure 21 zooms in on

this glitch.

Zero-code error is a measure of the output error when zero

code (0x0000) is loaded to the DAC register. Ideally, the output

should be 0 V. The zero-code error is always positive in the

AD5061 because the output of the DAC cannot go below 0 V.

This is due to a combination of the offset errors in the DAC and

output amplifier. Zero-code error is expressed in mV.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code (0xFFFF) is loaded to the DAC register. Ideally, the output

should be V_DD− 1 LSB. Full-scale error is expressed in percent

of full-scale range.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the DAC,

but is measured when the DAC output is not updated. It is specified

in nV-s and measured with a full-scale code change on the data

bus; that is, from all 0s to all 1s, and vice versa.

Gain Error

This is a measure of the span error of the DAC. It is the devia-

tion in slope of the DAC transfer characteristic from ideal

expressed as a percent of the full-scale range.

Rev. C | Page 1± of 20

Data Sheet

AD5061

THEORY OF OPERATION

The AD5061 is a single 16-bit, serial input, voltage output DAC.

It operates from supply voltages of 2.7 V to 5.5 V. Data is written to

the AD5061 in a 24-bit word format, via a 3-wire serial interface.

SYNC

line low. Data

The write sequence begins by bringing the

from the DIN line is clocked into the 24-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 30 MHz, making these parts compatible with high speed DSPs.

On the 24th falling clock edge, the last data bit is clocked in and

the programmed function is executed (that is, a change in the DAC

register contents and/or a change in the mode of operation).

The AD5061 incorporates a power-on reset circuit that ensures

the DAC output powers up to zero-scale or midscale. The device

also has a software power-down mode pin that reduces the

typical current consumption to less than 1 µA.

SYNC

At this stage, the

line may be kept low or be brought

DAC ARCHITECTURE

high. In either case, it must be brought high for a minimum of

12 ns before the next write sequence so that a falling edge of

The DAC architecture of the AD5061 consists of two matched

DAC sections. A simplified circuit diagram is shown in Figure 37.

The four MSBs of the 16-bit data word are decoded to drive 15

switches, E1 to E15. Each of these switches connects one of 15

matched resistors to either DACGND or V_REFbuffer output. The

remaining 12 bits of the data word drive switches S0 to S11 of a

12-bit voltage mode R-2R ladder network.

SYNC

can initiate the next write sequence. Because the

buffer draws more current when V_IH= 1.8 V than it does when

V_IH= 0.8 V, should be idled low between write sequences

SYNC

for an even lower power operation of the part. As previously

indicated, however, it must be brought high again just before

the next write sequence.

V

OUT

INPUT SHIFT REGISTER

2R

E2

2R

S0

2R

S1

2R

E1

2R

E15

S11

The input shift register is 24 bits wide; see Figure 38. PD1 and

PD0 are control bits that control which mode of operation the

part is in (normal mode or any one of three power-down modes).

There is a more complete description of the various modes in

the Power-Down Modes section. The next 16 bits are the data

bits. These are transferred to the DAC register on the 24th

falling edge of SCLK.

V

REF

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 37. DAC Ladder Structure

REFERENCE BUFFER

SYNC INTERRUPT

The AD5061 operates with an external reference. The reference

input (V_REF) has an input range of 2 V to V_DD− 50 mV. This

input voltage is then used to provide a buffered reference for the

DAC core.

In a normal write sequence, the

line is kept low for at

SYNC

least 24 falling edges of SCLK and the DAC is updated on the

24th falling edge. However, if is brought high before the

SYNC

24th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as invalid.

Neither an update of the DAC register contents nor a change in

the operating mode occurs; see Figure 40.

SERIAL INTERFACE

SYNC

The AD5061 has a 3-wire serial interface (

, SCLK, and

DIN), which is compatible with SPI, QSPI, and MICROWIRE

interface standards, as well as most DSPs. See Figure 2 for a

timing diagram of a typical write sequence.

DB15 (MSB)

DB0 (LSB)

0

PD1

PD0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DATA BITS

NORMAL OPERATION

3-STATE

0

1

0

1

0

1

100kΩ TO GND

1kΩ TO GND

POWER-DOWN MODES

Figure 38. Input Register Contents

Rev. C | Page 15 of 20

AD5061

Data Sheet

When both bits are set to 0, the part works normally with its

normal power consumption. However, for the three power-

down modes, the supply current falls to less than 1 μA at 5 V

(265 nA at 3 V). Not only does the supply current fall, but the

output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different options.

The output is connected internally to GND through a 1 kΩ

resistor or a 100 kΩ resistor, or it is left open-circuited (3-state).

The output stage is illustrated in Figure 39.

POWER-ON TO ZERO-SCALE OR MIDSCALE

The AD5061 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

the zero-scale or midscale code and the output voltage is zero-

scale or midscale. It remains there until a valid write sequence is

made to the DAC. This is useful in applications where it is

important to know the state of the output of the DAC while it is

in the process of powering up.

SOFTWARE RESET

The device can be put into software reset by setting all bits in

the DAC register to 1; this includes writing 1s to Bit D23 to

Bit D16, which is not the normal mode of operation. Note that

OUTPUT

BUFFER

AD5061

V

OUT

DAC

the

interrupt command cannot be performed if a software

SYNC

reset command is started.

POWER-DOWN

CIRCUITRY

POWER-DOWN MODES

RESISTOR

NETWORK

The AD5061 contains four separate modes of operation. These

modes are software-programmable by setting two bits (DB17

and DB16) in the control register. Table 6 shows how the state

of the bits corresponds to the mode of operation of the device.

Figure 39. Output Stage During Power-Down

The bias generator, the DAC core and other associated linear

circuitry are all shut down when the power-down mode is

activated. However, the contents of the DAC register are

unaffected when in power-down. The time to exit power-down

is typically 2.5 ꢀs for V_DD= 5 V, and 5 ꢀs for V_DD= 3 V;

see Figure 19.

Table 6. Modes of Operation

DB17

DB16

Operating Mode

Normal operation

Power-down mode:

3-state

100 kΩ to GND

1 kΩ to GND

0

1

0

1

SCLK

SYNC

DIN

DB23

DB0

DB23

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24 FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

TH

ON THE 24 FALLING EDGE

SYNC

Figure 40.

Interrupt Facility

Rev. C | Page 16 of 20

Data Sheet

AD5061

MICROPROCESSOR INTERFACING

AD5061-to-80C51/80L51 Interface

AD5061-to-68HC11/68L11 Interface

Figure 43 shows a serial interface between the AD5061 and the

80C51/80L51 microcontroller. The setup for the interface is:

TxD of the 80C51/80L51 drives SCLK of the AD5061 while

Figure 41 shows a serial interface between the AD5061 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK pin of the AD5061, while the MOSI output

SYNC

RxD drives the serial data line of the part. The

signal is

SYNC

drives the serial data line of the DAC. The

signal is

again derived from a bit-programmable pin on the port. In this

case, Port Line P3.3 is used. When data is to be transmitted to

the AD5061, P3.3 is taken low. The 80C51/80L51 transmits data

only in 8-bit bytes; thus only eight falling clock edges occur in

the transmit cycle. To load data to the DAC, P3.3 is left low after

the first eight bits are transmitted, and a second write cycle is

initiated to transmit the second byte of data. P3.3 is taken high

following the completion of this cycle. The 80C51/80L51 out-

puts the serial data in a format that has the LSB first. The AD5061

requires its data with the MSB as the first bit received. The 80C51/

80L51 transmit routine should take this into account.

derived from a port line (PC7). The set-up conditions for

correct operation of this interface require that the 68HC11/

68L11 be configured so that its CPOL bit is 0 and its CPHA bit

is 1. When data is being transmitted to the DAC, the

is taken low (PC7). When the 68HC11/68L11 is configured

where its CPOL bit is 0 and its CPHA bit is 1, data appearing on

the MOSI output is valid on the falling edge of SCK. Serial data

from the 68HC11/68L11 is transmitted in 8-bit bytes with only

eight falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. To load data to the AD5061, PC7 is left

low after the first eight bits are transferred, a second serial write

operation is performed to the DAC, and PC7 is taken high at the

end of this procedure.

SYNC

line

80C51/80L51¹

AD5061¹

P3.3

SYNC

TxD

RxD

SCLK

DIN

68HC11/

AD5061¹

68L11¹

PC7

SCK

SYNC

SCLK

DIN

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 43. AD5061-to-80C51/80L51 Interface

MOSI

AD5061-to-MICROWIRE Interface

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 44 shows an interface between the AD5061 and any

MICROWIRE-compatible device. Serial data is shifted out on

the falling edge of the serial clock and is clocked into the AD5061

on the rising edge of the SK.

Figure 41. AD5061-to-68HC11/68L11 Interface

AD5061-to-Blackfin® ADSP-BF527 Interface

Figure 42 shows a serial interface between the AD5061 and the

Blackfin ADSP-BF527 microprocessor. The ADSP-BF527

processor incorporates two dual-channel synchronous serial

ports, SPORT1 and SPORT0, for serial and multiprocessor

communications. Using SPORT0 to connect to the AD5061, the

setup for the interface is: DT0PRI drives the DIN pin of the

AD5061¹

MICROWIRE¹

CS

SK

SO

SYNC

SCLK

DIN

SYNC

AD5061, while TSCLK0 drives the SCLK of the part; the

is driven from TFS0.

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 44. AD5061-to-MICROWIRE Interface

AD5061¹

ADSP-B527¹

DT0PRI

DIN

TSCLK0

TFS0

SCLK

SYNC

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 42. AD5061-to-Blackfin ADSP-BF527 Interface

Rev. C | Page 17 of 20

AD5061

Data Sheet

APPLICATIONS INFORMATION

Table 7 shows examples of recommended precision references

for use as a supply to the AD5061.

CHOOSING A REFERENCE

To achieve the optimum performance from the AD5061,

thought should be given to the choice of a precision voltage

reference. The AD5061 has just one reference input, V_REF. The

voltage on the reference input is used to supply the positive

input to the DAC. Therefore, any error in the reference is

reflected in the DAC.

Table 7. Precision References Part List for the AD5061

Initial

Accuracy

Part No. (mV max)

0.1 Hz to

10 Hz Noise

(μV p-p typ)

Temperature Drift

(ppm/°C max)

ADR435

ADR425

ADR02

ADR395

2

3

5

3 (SO-8)

3 (SC70)

9 (TSOT-23)

8

3.4

10

8

There are four possible sources of error when choosing a vol-

tage reference for high accuracy applications: initial accuracy,

ppm drift, long-term drift, and output voltage noise. Initial

accuracy on the output voltage of the DAC leads to a full-scale

error in the DAC. To minimize these errors, a reference with

high initial accuracy is preferred. Also, choosing a reference

with an output trim adjustment, such as the ADR435, allows a

system designer to trim out system errors by setting a reference

voltage to a voltage other than the nominal. The trim adjustment

can also be used at the operating temperature to trim out any

errors.

BIPOLAR OPERATION

The AD5061 has been designed for single-supply operation, but

a bipolar output range is also possible using the circuit shown in

Figure 46. The circuit shown yields an output voltage range of

5 V. Rail-to-rail operation at the amplifier output is achievable

using an AD8675/AD820/AD8032 or an OP196/OP295.

Because the supply current required by the AD5061 is extremely

low, the parts are ideal for low supply applications. The ADR395

voltage reference is recommended. This requires less than

100 μA of quiescent current and can, therefore, drive multiple

DACs in one system, if required. It also provides very good

noise performance at 8 μV p-p in the 0.1 Hz to 10 Hz range.

The output voltage for any input code can be calculated as

follows:

D

65536

R1 R2

R1

R2

R1











 

 



















V_O V_DD



V



DD

 









where D represents the input code in decimal (0 to 65536).

With V_REF= 5 V, R1 = R2 = 10 kΩ,

7V

5V

ADR395

10D

65536













V 

5V

O

SYNC

SCLK

DIN

3-WIRE

SERIAL

V

= 0V TO 5V

OUT

AD5061

This is an output voltage range of 5 V with 0x0000 corresponding

to a −5 V output and 0xFFFF corresponding to a +5 V output.

INTERFACE

R2 = 10kΩ

Figure 45. ADR395 as Reference to the AD5061

+5V

R1 = 10kΩ

Long-term drift is a measure of how much the reference drifts

over time. A reference with a tight long-term drift specification

ensures that the overall solution remains relatively stable during

its entire lifetime. The temperature coefficient of a reference’s

output voltage affects INL, DNL, and TUE. A reference with a

tight temperature coefficient specification should be chosen to

reduce temperature dependence of the DAC output voltage on

ambient conditions.

–

AD820/

OP295

+

±5V OUT

AD5061

–5V

V

OUT

V

DD

10µF

0.1µF

3-WIRE

SERIAL

In high accuracy applications, which have a relatively low noise

budget, reference output voltage noise needs to be considered. It

is important to choose a reference with as low an output noise

voltage as practical for the system noise resolution required.

Precision voltage references, such as the ADR435, produce low

output noise in the 0.1 Hz to 10 Hz region.

INTERFACE

Figure 46. Bipolar Operation with the AD5061

Rev. C | Page 18 of 20

Data Sheet

AD5061

USING A GALVANICALLY-ISOLATED INTERFACE

CHIP

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully

consider the power supply and ground return layout on the board.

The printed circuit board containing the AD5061 should have

separate analog and digital sections, each having its own area of

the board. If the AD5061 is in a system where other devices require

an AGND-to-DGND connection, then the connection should

be made at one point only. This ground point should be as close

as possible to the AD5061.

In process control applications in industrial environments, it is

often necessary to use a galvanically-isolated interface to protect

and isolate the controlling circuitry from any hazardous

common-mode voltages that may occur in the area where the

DAC is functioning. iCoupler® provides isolation in excess of

2.5 kV. Because the AD5061 uses a 3-wire serial logic interface,

the ADuM1300 provides an ideal digital solution for the DAC

interface.

The power supply to the AD5061 should be bypassed with 10 μF

and 0.1 μF capacitors. The capacitors should be physically as

close as possible to the device with the 0.1 μF capacitor ideally

right up against the device. The 10 μF capacitors are the tantalum

bead type. It is important that the 0.1 μF capacitor has low effective

series resistance (ESR) and effective series inductance (ESI), as

do common ceramic types of capacitors. This 0.1 μF capacitor

provides a low impedance path to ground for high frequencies

caused by transient currents due to internal logic switching.

The ADuM1300 isolator provides three independent isolation

channels in a variety of channel configurations and data rates. It

operates across the full range from 2.7 V to 5.5 V, providing

compatibility with lower voltage systems and enabling a voltage

translation functionality across the isolation barrier.

Figure 47 shows a typical galvanically-isolated configuration

using the AD5061. The power supply to the part also needs to

be isolated; this is accomplished by using a transformer. On the

DAC side of the transformer, a 5 V regulator provides the 5 V

supply required for the AD5061.

The power supply line itself should have as large a trace as possible

to provide a low impedance path and reduce glitch effects on

the supply line. Clocks and other fast switching digital signals

should be shielded from other parts of the board by digital

ground. Avoid crossover of digital and analog signals, if

possible. When traces cross on opposite sides of the board,

ensure that they run at right angles to each other to reduce

feedthrough effects through the board. The best board layout

technique is the microstrip technique where the component

side of the board is dedicated to the ground plane only, and the

signal traces are placed on the solder side. However, this is not

always possible with a 2-layer board.

5V

REGULATOR

10µF

0.1µF

POWER

V

DD

SCLK

SDI

V1A

V0A

V0B

V0C

SCLK

SYNC

DIN

AD5061

ADuM1300

V

V1B

V1C

OUT

DATA

GND

Figure 47. AD5061 with a Galvanically-Isolated Interface

Rev. C | Page 19 of 20

AD5061

Data Sheet

OUTLINE DIMENSIONS

3.00

2.90

2.80

8

1

7

6

3

5

4

3.00

2.80

2.60

1.70

1.60

1.50

2

PIN 1

INDICATOR

0.65 BSC

1.95

BSC

1.30

1.15

0.90

0.22 MAX

0.08 MIN

1.45 MAX

0.95 MIN

0.60

0.45

0.30

0.15 MAX

0.05 MIN

8°

4°

0°

SEATING

PLANE

0.60

BSC

0.38 MAX

0.22 MIN

COMPLIANT TO JEDEC STANDARDS MO-178-BA

Figure 48. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Range

Package

Description

Package

Option

Model¹

INL

Description

Branding

D±3

D±±

AD5061BRJZ-1REEL7

AD5061BRJZ-1500RL7

AD5061BRJZ-2REEL7

AD5061BRJZ-2500RL7

AD5061YRJZ-1500RL7

AD5061YRJZ-1REEL7

EVAL-AD5061EBZ

−±0°C to +85°C

−±0°C to +125°C

± LSB 2.7 V to 5.5 V, Reset to 0 V

± LSB 2.7 V to 5.5 V, Reset to Midscale

± LSB 2.7 V to 5.5 V, Reset to 0 V

8-Lead SOT-23

Evaluation Board

RJ-8

D6G

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D04762-0-8/15(C)

Rev. C | Page 20 of 20


型号：	AD5061YRJZ-1500RL7
厂家：	ADI
描述：	16-Bit VOUT, nanoDAC®, SPI Interface, 2.7 V to 5.5 V in an SOT-23 光电二极管转换器
文件：	总21页 (文件大小：657K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5061YRJZ-1500RL7 [ADI]

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