AD5064 [ADI]
Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP; 完全准确, 12位/ 14位/ 16位VOUT属于nanoDAC ,四, SPI接口, 4.5 V至5.5 V的TSSOP型号: | AD5064 |
厂家: | ADI |
描述: | Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP |
文件: | 总28页 (文件大小:1271K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC,
Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
AD5024/AD5044/AD5064
FEATURES
GENERAL DESCRIPTION
Low power quad 12-/14-/16-bit DAC, 1 LSB INL
The AD5024/AD5044/AD5064 are low power, quad 12-/14-/
Individual and common voltage reference pin options
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero-scale or midscale
3 power-down functions
Per-channel power-down
16-bit buffered voltage output nanoDAC® DACs that offer relative
accuracy specifications of 1 LSB INL with individual reference
pins and can operate from a single 4.5 V to 5.5 V supply. The
AD5024/AD5044/AD5064 parts also offer a differential accuracy
specification of 1 LSB. The parts use a versatile 3-wire, low
power Schmitt trigger serial interface that operates at clock rates
up to 50 MHz and is compatible with standard SPI, QSPI™,
MICROWIRE™, and DSP interface standards. A reference buffer
is also provided on-chip. The AD5024/AD5044/AD5064 incor-
porate a power-on reset circuit that ensures the DAC output
powers up to zero scale or midscale and remains there until a
valid write takes place to the device. The AD5024/AD5044/
AD5064 contain a power-down feature that reduces the current
consumption of the device to typically 400 nA at 5 V and provides
software selectable output loads while in power-down mode.
Total unadjusted error for the parts is <2 mV.
Low glitch on power-up
Hardware LDAC with LDAC override function
CLR function to programmable code
16-lead TSSOP
Internal reference buffer and internal output amplifier
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
PRODUCT HIGHLIGHTS
1. Quad channel available in 16-lead TSSOP package.
2. 16-bit accurate, 1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 50 MHz.
5. Reset to known output voltage (zero scale or midscale).
Table 1. Related Devices
Part No.
Description
AD5666
AD5063/AD5062
AD5061
Quad,16-bit buffered DAC,16 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL
16-/14-bit nanoDAC, 4 LSB INL, SOT-23
16-/14-bit nanoDAC, 1 LSB INL, SOT-23
AD5060/AD5040
FUNCTIONAL BLOCK DIAGRAM
V
A V
B
REF
V
REF
DD
AD5024/
AD5044/
AD5064
LDAC
BUFFER
BUFFER
BUFFER
BUFFER
DAC
INPUT
V
V
V
V
A
B
C
D
DAC A
DAC B
DAC C
DAC D
OUT
OUT
OUT
OUT
REGISTER
REGISTER
SCLK
DAC
REGISTER
INPUT
REGISTER
INTERFACE
LOGIC
SYNC
DIN
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
POWER-DOWN
POWER-ON
RESET
LOGIC
POR
GND
V
C V
D
REF
LDAC
REF
CLR
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD5024/AD5044/AD5064
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier........................................................................ 18
Serial Interface............................................................................ 18
Standalone Mode........................................................................ 18
Input Shift Register .................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 18
DAC Section................................................................................ 18
DAC Architecture....................................................................... 18
Reference Buffer ......................................................................... 18
SYNC
Interrupt .......................................................................... 19
Power-On Reset.......................................................................... 20
Power-Down Modes .................................................................. 20
Clear Code Register ................................................................... 21
LDAC
Function .......................................................................... 21
Power Supply Bypassing and Grounding................................ 21
Microprocessor Interfacing....................................................... 23
Applications..................................................................................... 24
Using a Reference as a Power Supply....................................... 24
Bipolar Operation....................................................................... 24
Using the AD5024/AD5044/AD5064 with a
Galvanically Isolated Interface ................................................. 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5024/AD5044/AD5064
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to
MAX, unless otherwise noted.
T
Table 2.
B Grade1
Min Typ
A Grade1, 2
Min Typ
Parameter
STATIC PERFORMANCE3
Max
Max
Unit
Conditions/Comments
Resolution
16
14
12
16
Bits
AD5064
AD5044
AD5024
Relative Accuracy
0.5
+0.5
0.25
0.25
0.12
0.12
0.2
1
2
0.5
1
0.25
0.5
1
1.8
0.5
0.5
4
4
LSB
LSB
LSB
AD5064; TA = −40°C to +105°C
AD5064; TA = −40°C to +125°C
AD5044; TA = −40°C to +105°C
AD5044; TA = −40°C to +125°C
AD5024; TA = −40°C to +105°C
AD5024; TA = −40°C to +125°C
Differential Nonlinearity
Offset Error
0.2
0.2
1
1.8
LSB
mV
0.2
Code 512 (AD5064), Code 128 (AD5044),
Code 32 (AD5024) loaded to DAC register
Offset Error Drift4
Full-Scale Error
2
2
μV/°C
0.01
0.005
1
0.0ꢀ
0.05
0.01
0.005
1
0.0ꢀ % FSR
0.05 % FSR
ppm
All 1s loaded to DAC register. VREF <VDD
Gain Error
Gain Temperature Coefficient4
Of FSR/°C
DC Crosstalk
40
40
μV
Due to single channel full-scale output
change, RL = 5 kΩ to GND or VDD
40
0.5
40
40
μV/mA Due to load current change
μV
Due to powering down (per channel)
OUTPUT CHARACTERISTICS4
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Normal Mode
0
VDD
0
VDD
V
nF
1
1
RL = 5 kΩ, RL =100 kΩ, and RL = ∞
0.5
0.5
Ω
Power-Down Mode
Output Connected to
100 kΩ Network
Output Connected to
1 kΩ Network
100
1
100
1
kΩ
kΩ
Output impedance tolerance 400 Ω
Output impedance tolerance 20 Ω
Short-Circuit Current
60
45
4.5
60
45
4.5
mA
mA
μs
DAC = full scale, output shorted to GND
DAC = zero-scale, output shorted to VDD
Time to exit power-down mode to normal
mode of AD5024/AD5044/AD5064, 32nd
clock edge to 90% of DAC midscale value,
output unloaded
Power-Up Time
DC PSRR
−92
−92
dB
VDD 10%, DAC = full scale. VREF < VDD
REFERENCE INPUTS
Reference Input Range
Reference Current
Reference Input Impedance
LOGIC INPUTS
2.5
2.2
VDD
50
2.5
2.2
VDD
50
V
μA
kΩ
35
120
35
120
Per DAC channel
Individual reference option
Input Current5
1
0.8
1
0.8
μA
V
V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance4
4
4
pF
Rev. 0 | Page 3 of 28
AD5024/AD5044/AD5064
B Grade1
Min Typ
A Grade1, 2
Min Typ
Parameter
Max
Max
Unit
Conditions/Comments
POWER REQUIREMENTS
VDD
IDD
4.5
5.5
4.5
5.5
V
DAC active, excludes load current
VIH = VDD and VIL = GND
6
Normal Mode
All Power-Down Modesꢀ
3
0.4
6
2
30
3
0.4
6
2
30
mA
μA
μA
TA = −40°C to +105°C
TA = −40°C to +125°C
1 Temperature range is −40°C to +125°C, typical at 25°C.
2 A grade offered in AD5064 only.
3 Linearity calculated using a reduced code range—AD5064: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output
unloaded.
4 Guaranteed by design and characterization; not production tested.
5 Current flowing into individual digital pins.
6 Interface inactive. All DACs active. DAC outputs unloaded.
ꢀ All four DACs powered down.
Rev. 0 | Page 4 of 28
AD5024/AD5044/AD5064
AC CHARACTERISTICS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD. All specifications TMIN to TMAX, unless otherwise
noted.
Table 3.
Parameter1, 2
Min Typ Max Unit
Conditions/Comments3
Output Voltage Settling Time
5.8
8
μs
¼ to ¾ scale and ¾ to ¼ scale settling to 1 LSB, RL = 5 kΩ,
single channel update including DAC calibration sequence
10.ꢀ 13
μs
¼ to ¾ scale and ¾ to ¼ scale settling to 1 LSB, RL = 5 kΩ, all channel
update including DAC calibration sequence
Slew Rate
1.5
3
−90
0.1
1.9
2
V/μs
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
Digital-to-Analog Glitch Impulse
Reference Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
AC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
1 LSB change around major carry
VREF = 3 V 0.86 V p-p, frequency = 100 Hz to 100 kHz
3.5
6
340
−80
64
60
6
VREF = 3 V 0.86 V p-p
VREF = 3 V 0.2 V p-p, frequency = 10 kHz
nV/√Hz DAC code = 0x8400, 1 kHz
nV/√Hz DAC code = 0x8400, 10 kHz
ꢁV p-p
Output Noise
0.1 Hz to 10 Hz
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +125°C, typical at 25°C.
Rev. 0 | Page 5 of 28
AD5024/AD5044/AD5064
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
VDD = 4.5 V to 5.5 V
;
Parameter1
Unit
Conditions/Comments
t1
t2
t3
t4
t5
t6
tꢀ
t8
20
10
10
16.5
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ꢁs min
ꢁs min
ns min
ns min
ns min
ns min
ns min
ꢁs min
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
5
0
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (single channel update)
Minimum SYNC high time (all channel update)
SYNC rising edge to SCLK fall ignore
LDAC pulse width low
1.9
10.5
1ꢀ
20
20
10
10
10.6
t9
t10
t11
t12
t13
t14
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
1 Guaranteed by design and characterization; not production tested.
t1
t9
SCLK
t2
t8
t3
t4
t7
SYNC
t6
t5
DIN
1
DB23
DB0
t13
t10
LDAC
t11
2
LDAC
t12
CLR
t14
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. 0 | Page 6 of 28
AD5024/AD5044/AD5064
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
VDD to GND
−0.3 V to +ꢀ V
Digital Input Voltage to GND
VOUT to GND
VREF to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial
Storage Temperature Range
−40°C to +125°C
−65°C to +150°C
150°C
ESD CAUTION
Junction Temperature (TJ MAX
)
TSSOP Package
Power Dissipation
(TJ MAX − TA)/θJA
θJA Thermal Impedance
113°C/W
Reflow Soldering Peak Temperature
Pb Free
260°C
Rev. 0 | Page ꢀ of 28
AD5024/AD5044/AD5064
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC
SYNC
1
2
3
4
5
6
7
8
16 SCLK
15 DIN
V
14
13
12
11
10
9
GND
DD
AD5024/
AD5044/
AD5064
V
B
D
OUT
V
V
V
B
A
A
C
REF
REF
V
OUT
TOP VIEW
(Not to Scale)
V
D
REF
OUT
OUT
V
CLR
V
C
POR
REF
Figure 3. 16-Lead TSSOP (RU-16) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on
the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the device.
3
VDD
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4
5
6
ꢀ
8
VREF
VREF
VOUT
VOUT
B
A
A
C
DAC B Reference Input. This is the reference voltage input pin for DAC B.
DAC A Reference Input. This is the reference voltage input pin for DAC A.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Power-On Reset. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up the
part to midscale.
POR
9
VREF
C
DAC C Reference Input .This is the reference voltage input pin for DAC C.
10
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
11
12
13
14
15
VREF
VOUT
VOUT
GND
DIN
D
D
B
DAC D Reference Input .This is the reference voltage input pin for DAC D.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
16
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Rev. 0 | Page 8 of 28
AD5024/AD5044/AD5064
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.2
0
0.4
0.2
0
–0.2
–0.4
–0.2
–0.4
–0.6
–0.8
–1.0
–0.6
–0.8
–1.0
512
16,640
32,768
48,896
12,288
12,288
65,024
16,384
16,384
512
16,640
32,768
48,896
65,024
DAC CODE
DAC CODE
Figure 7. AD5064 DNL
Figure 4. AD5064 INL
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4096
8192
0
512
1024
1536
2048
2560
3072
3584
4096
DAC CODE
DAC CODE
Figure 8. AD5044 DNL
Figure 5. AD5044 INL
1.00
0.75
0.50
0.25
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.25
–0.50
–0.75
–1.00
0
4096
8192
0
512
1024
1536
2048
2560
3072
3584
4096
DAC CODE
DAC CODE
Figure 9. AD5024 DNL
Figure 6. AD5024 INL
Rev. 0 | Page 9 of 28
AD5024/AD5044/AD5064
0.20
1.2
1.0
T
= 25°C
A
0.15
0.8
0.10
0.05
0.6
0.4
MAX TUE ERROR @ V = 5.5V
DD
0.2
0
0
MIN TUE ERROR @ V = 5.5V
DD
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–0.05
–0.10
–0.15
–0.20
512
16,640
32,768
48,896
65,024
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
DAC CODE
REFERENCE VOLTAGE (V)
Figure 10. Total Unadjusted Error (TUE)
Figure 13. TUE vs. Reference Input Voltage
1.6
0.015
0.010
T
= 25°C
A
1.4
1.2
1.0
DAC A
0.8
0.6
MAX INL ERROR @ V = 5.5V
DD
0.005
0
0.4
0.2
DAC B
0
DAC D
DAC C
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
MIN INL ERROR @ V
= 5.5V
DD
–0.005
–0.010
–0.015
V
= 5.5V
= 4.096V
DD
V
REF
120
–60 –40 –20
0
20
40
60
80
100
140
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
Figure 11. INL vs. Reference Input Voltage
Figure 14. Gain Error vs. Temperature
1.6
1.4
0.6
0.5
V
V
= 5.5V
T
= 25°C
DD
A
= 4.096V
REF
1.2
DAC C
1.0
0.4
0.3
0.2
0.1
0
0.8
0.6
0.4
MAX DNL ERROR @ V
= 5.5V
DD
0.2
DAC D
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
MIN DNL ERROR @ V
= 5.5V
DD
–0.1
–0.2
DAC A
DAC B
0
–0.3
–0.4
–60 –40 –20
20
40
60
80
100 120 140
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (ºC)
REFERENCE VOLTAGE (V)
Figure 12. DNL vs. Reference Input Voltage
Figure 15. Offset Error vs. Temperature
Rev. 0 | Page 10 of 28
AD5024/AD5044/AD5064
0.2
0.1
0.010
0.009
0.008
0.007
0.006
GAIN ERROR
0.005
0.004
0.003
0.002
0.001
0
FULL-SCALE ERROR
–0.1
–0.2
0
512
16,640
32,768
48,896
65,024
4.50
4.75
5.00
(V)
5.25
5.50
DAC CODE
V
DD
Figure 19. Supply Current vs. Code
Figure 16. Gain Error and Full-Scale Error vs. Supply Voltage
10.0
7.5
5.0
2.5
0
0.12
0.09
0.06
0.03
0
–40
10
60
110 125
4.50
4.75
5.00
(V)
5.25
5.50
TEMPERATURE (°C)
V
DD
Figure 17. Offset Error Voltage vs. Supply Voltage
Figure 20. Supply Current vs. Temperature
10.0
7.5
5.0
2.5
0
7
6
5
4
3
2
1
0
2.80
4.50
4.75
5.00
(V)
5.25
5.50
2.85
2.90
2.95
(mA)
3.00
3.05
3.10
V
DD
I
DD
Figure 21. Supply Current vs. Supply Voltage
Figure 18. IDD Histogram, VDD = 5.0 V
Rev. 0 | Page 11 of 28
AD5024/AD5044/AD5064
10.0
7.5
5.0
2.5
0
1
3
CH1 2V
CH3 2V
M2ms
T
A CH1
2.52V
1
3
0
2
4
5
20.4%
DIGITAL INPUT VOLTAGE (V)
Figure 22. Supply Current vs. Digital Input Voltage
Figure 25. Power-On Reset to Midscale
5.0
4.5
4.0
3.5
3.0
2.5
CH1 = SCLK
1
V
= 5V, V = 4.096V
REF
DD
= 25ºC
T
A
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
OUTPUT LOADED WITH 5kΩ
AND 200pF TO GND
CH2 = V
V
= 5V
OUT
DD
POWER-UP TO MIDSCALE
2.0
1.5
1.0
0.5
0
2
CH1 5V
CH2 500mV
M2µs
55%
A CH2
1.2V
0
2
4
6
8
10
12
14
T
TIME (µs)
Figure 26. Exiting Power-Down to Midscale
Figure 23. Settling Time
6
5
4
3
2
1
3
1
0
–1
–2
–3
0
2.5
5.0
7.5
10.0
CH1 2V
CH3 2V
M2ms
T
A CH1
2.52V
20.4%
TIME (μs)
Figure 27. Digital-to-Analog Glitch Impulse
Figure 24. Power-On Reset to 0 V
Rev. 0 | Page 12 of 28
AD5024/AD5044/AD5064
0
–10
–20
–30
–40
–50
–60
–70
–80
7
6
V
T
= 5V,
V
T
= 5V, V = 4.096V
REF
DD
= 25ºC
DD
= 25ºC
A
A
DAC LOADED WITH MIDSCALE
V
5
= 3.0V ± 200mV p-p
REF
4
3
2
1
0
–1
–2
–3
–4
–90
–100
0
2.5
5.0
7.5
10.0
5
10
20
30
FREQUENCY (kHz)
40
50
55
TIME (μs)
Figure 28. Analog Crosstalk
Figure 31. Total Harmonic Distortion
7
6
24
22
20
18
16
14
12
10
8
V
T
= 5V, V
REF
= 4.096V
V
T
= 5V, V = 3.0V
REF
DD
= 25°C
DD
= 25°C
A
A
5
4
3
2
1
0
–1
–2
–3
–4
6
4
0
2.5
5.0
7.5
10.0
0
1
2
3
4
5
6
7
8
9
10
TIME (μs)
CAPACITANCE (nF)
Figure 29. DAC-to-DAC Crosstalk
Figure 32. Settling Time vs. Capacitive Load
V
= 5V, V = 4.096V
REF
DD
T
= 25ºC
A
DAC LOADED WITH MIDSCALE
1
2
4s/DIV
CH1 5V
CH2 2V
M2µs
A CH1
2.5V
T 11%
Figure 30. 0.1 Hz to 10 Hz Output Noise Plot
CLR
Figure 33. Hardware
Rev. 0 | Page 13 of 28
AD5024/AD5044/AD5064
10
0.10
0.08
0.06
0.04
0.02
0
CODE = MIDSCALE
= 5V, V = 4.096V
V
DD
REF
0
–10
–20
–30
–40
–0.02
–0.04
–0.06
–0.08
–0.10
CH A
CH B
CH C
–50
CH D
3dB POINT
–60
10
100
1000
10000
–25 –20 –15 –10 –5
0
5
10
15
20
25
30
FREQUENCY (kHz)
I
(mA)
OUT
Figure 34. Multiplying Bandwidth
Figure 37. Typical Current Limiting Plot
5.0
4.5
4.0
3.5
3.0
2.5
CH1 295mV p-p
V
= 5V, V = 4.096V
REF
DD
= 25°C
T
A
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
2.0
1.5
1.0
0.5
0
OUTPUT LOADED WITH 5kΩ
AND 200pF TO GND
0
2
4
6
8
10
12
14
CH1 50mV CH2 5V
M4µs
A CH2
1.2V
T 8.6%
TIME (µs)
Figure 38. Glitch on Entering Power-Down to Zero Scale, No Load
Figure 35. Typical Output Slew Rate
0.0010
0.0008
0.0006
0.0004
0.0002
0
CODE = MIDSCALE
= 5V, V = 4.096V
V
DD
REF
CH1 200mV p-p
–0.0002
–0.0004
–0.0006
–0.0008
V
= 5.5V
DD
CH1 50mV CH2 5V
M4µs
A CH2
1.2V
–25 –20 –15 –10 –5
0
5
10
15
20
25
30
T 8.6%
CURRENT (mA)
Figure 39. Glitch on Entering Power-Down to Zero Scale, 5 kΩ/200 pF Load
Figure 36. Typical Output Load Regulation
Rev. 0 | Page 14 of 28
AD5024/AD5044/AD5064
CH1 170mV p-p
CH1 129mV p-p
CH1 20mV CH2 5V
M4µs
A CH2
1.2V
CH1 20mV CH2 5V
M4µs
A CH2
1.2V
T 8.6%
T 8.6%
Figure 40. Glitch on Exiting Power-Down from Zero Scale, No load
Figure 41. Glitch on Exiting Power-Down from Zero Scale,
5 kΩ/200 pF Load
Rev. 0 | Page 15 of 28
AD5024/AD5044/AD5064
TERMINOLOGY
Relative Accuracy
DC Power Supply Rejection Ratio (PSRR)
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer function.
Figure 4, Figure 5, and Figure 6 show plots of typical INL vs. code.
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2.5 V, and VDD is varied by 10%.
Measured with VREF < VDD
.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of 1 LSB maximum ensures monoto-
nicity. This DAC is guaranteed monotonic by design. Figure 7,
Figure 8 and Figure 9 show plots of typical DNL vs. code.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
Offset Error
Offset error is a measure of the difference between the actual
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
V
OUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
part with Code 512 (AD5064), Code 128 (AD5044), and Code 32
(AD5024) loaded into the DAC register. It can be negative or
positive and is expressed in millivolts.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
Gain Error
LDAC
is not being updated (that is,
decibels.
is high). It is expressed in
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but it is measured when the DAC is not being written
held high). It is specified in nanovolt-seconds and
measured with one simultaneous data and clock pulse loaded
to the DAC.
Offset Error Drift
Offset error drift is a measure of the change in offset error with
a change in temperature. It is expressed in microvolts per degree
Celsius.
SYNC
to (
Gain Temperature Coefficient
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in parts per million of
full-scale range per degree Celsius.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nanovolt-seconds.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VREF − 1 LSB. Full-scale error is expressed as a
Analog Crosstalk
percentage of the full-scale range. Measured with VREF < VDD
.
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping
high, and then pulsing
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nanovolt-
seconds and is measured when the digital input code is changed
by 1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 27.
LDAC
LDAC
low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nanovolt-seconds.
Rev. 0 | Page 16 of 28
AD5024/AD5044/AD5064
DAC-to-DAC Crosstalk
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
LDAC
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nanovolt-seconds.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
Rev. 0 | Page 1ꢀ of 28
AD5024/AD5044/AD5064
THEORY OF OPERATION
DAC SECTION
SERIAL INTERFACE
The AD5024/AD5044/AD5064 are single 12-/14-/16-bit, serial
input, voltage output DACs. The parts operate from supply voltages
of 4.5 V to 5.5 V. Data is written to the AD5024/AD5044/AD5064
in a 32-bit word format via a 3-wire serial interface. The AD5024/
AD5044/AD5064 incorporate a power-on reset circuit that ensures
that the DAC output powers up to a known output state. The
devices also have a software power-down mode that reduces the
typical current consumption to less than 2 μA.
The AD5024/AD5044/AD5064 have a 3-wire serial interface
SYNC
(
, SCLK, and DIN) that is compatible with SPI, QSPI,
and MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
STANDALONE MODE
SYNC
The write sequence begins by bringing the
line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5024/AD5044/AD5064 compatible
with high speed DSPs. On the 32nd falling clock edge, the last
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = VREFIN
×
2N
SYNC
the mode of operation. At this stage, the
line can be kept
where:
low or be brought high. In either case, it must be brought high
for a minimum of 1.9 μs (single channel) before the next write
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535 for the 16-bit AD5064).
N is the DAC resolution.
SYNC
sequence so that a falling edge of
SYNC
can initiate the next
buffer draws more current
SYNC
write sequence. Because the
when VIN = 2.2 V than it does when VIN = 0.8 V,
be idled low between write sequences for even lower power
DAC ARCHITECTURE
should
The DAC architecture of the AD5064 consists of two matched
DAC sections. A simplified circuit diagram is shown in Figure 42.
The four MSBs of the 16-bit data word are decoded to drive 15
switches, E1 to E15. Each of these switches connects one of 15
matched resistors to either GND or the VREF buffer output. The
remaining 12 bits of the data-word drive the S0 to S11 switches
of a 12-bit voltage mode R-2R ladder network.
SYNC
operation of the part. As mentioned previously, however,
must be brought high again just before the next write sequence.
Table 7. Command Definitions
Command
C3 C2 C1 C0 Description
V
OUT
0
0
0
0
0
0
0
0
1
0
1
0
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
2R
2R
S1
2R
2R
E1
2R
E2
2R
2R
S0
E15
S11
V
REF
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Reserved
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 42. DAC Ladder Structure
REFERENCE BUFFER
The AD5024/AD5044/AD5064 operate with an external reference.
Each DAC has a dedicated voltage reference pin. The reference
input pin has an input range of 2.5 V to VDD. This input voltage
is then used to provide a buffered reference for the DAC core.
Reserved
Reserved
Table 8. Address Commands
OUTPUT AMPLIFIER
Address (n)
Selected DAC
Channel
The output buffer amplifier can generate rail-to-rail voltages
on its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 5 kΩ in parallel with
200 pF to GND. The slew rate is 1.5 V/μs with a ¼ to ¾ scale
settling time of 13 μs.
A3
0
0
0
0
A2
0
0
0
0
A1
0
0
1
1
A0
0
1
0
1
DAC A
DAC B
DAC C
DAC D
All DACs
1
1
1
1
Rev. 0 | Page 18 of 28
AD5024/AD5044/AD5064
INPUT SHIFT REGISTER
SYNC INTERRUPT
The AD5024/AD5044/AD5064 input shift register is 32 bits wide.
The first four bits are don’t cares. The next four bits are the com-
mand bits, C3 to C0 (see Table 7), followed by the 4-bit DAC
address bits, A3 to A0 (see Table 8), and finally the bit data-word.
The data-word comprises 12-, 14-, or 16-bit input code followed
by 8, 6, or 4 don’t care bits for the AD5024/AD5044/AD5064
(see Figure 43, Figure 44, and Figure 45). These data bits are
transferred to the DAC register on the 32nd falling edge of SCLK.
SYNC
In a normal write sequence, the
line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
nd
SYNC
32 falling edge. However, if
is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 46).
DB31 (MSB)
DB0 (LSB)
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 43. AD5024 Input Register Content
DB31 (MSB)
DB0 (LSB)
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 44. AD5044 Input Register Content
DB31 (MSB)
DB0 (LSB)
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 45. AD5064 Input Register Content
SCLK
SYNC
DIN
DB31
DB0
DB31
DB0
INVALID WRITE SEQUENCE:
ND
VALID WRITE SEQUENCE, OUTPUT UPDATES
ND
SYNC HIGH BEFORE 32 FALLING EDGE
ON THE 32 FALLING EDGE
SYNC
Figure 46.
Interrupt Facility
Rev. 0 | Page 19 of 28
AD5024/AD5044/AD5064
to DAC A) can be powered down to the selected mode by
setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1.
See Table 10 for the contents of the input shift register during
power-down/power-up operation.
POWER-ON RESET
The AD5024/AD5044/AD5064 contains a power-on reset
circuit that controls the output voltage during power-up. By
connecting the POR pin low, the AD5024/AD5044/AD5064
output powers up to zero scale. Note that this is outside the
linear region of the DAC; by connecting the POR pin high, the
AD5024/AD5044/AD5064 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the
DAC while it is in the process of powering up. There is also a
software executable reset function that resets the DAC to the
power-on reset code. Command 0111 is designated for this
When both Bit DB9 and Bit D8 in the control register are set to
0, the part works normally with its normal power consumption
of 3 mA at 5 V. However, for the three power-down modes, the
supply current falls to 0.4 ꢀA at 5 V. Not only does the supply
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different options. The output is connected internally to GND
through either a 1 kΩ or a 100 kΩ resistor, or it is left open-
circuited (three-state). The output stage is illustrated in Figure 47.
reset function (see Table 7). Any events on
during power-on reset are ignored.
or
LDAC CLR
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 4.5 μs for VDD = 5 V (see Figure 26).
POWER-DOWN MODES
The AD5024/AD5044/AD5064 contain four separate modes of
operation. Command 0100 is designated for the power-down
function (see Table 7). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the control register
(Table 9). Table 9 shows how the state of the bits corresponds to
the mode of operation of the device. Any or all DACs (DAC D
Table 9. Modes of Operation
DB9
DB8
Operating Mode
Normal operation
Power-down modes:
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
0
1
1
1
0
1
Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
MSB
LSB
DB31
to
DB10
to
DB4
to
DB28
DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19
DB9 DB8 DB7
DB3
DB2
DB1
DB0
X
0
1
0
0
X
X
X
X
X
PD1
PD0
X
DAC D DAC C DAC B DAC A
Don’t
cares
Command bits (C2 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Power-
down mode cares
Don’t
Power-down/power-up channel
selection—set bit to 1 to select
AMPLIFIER
DAC
V
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 47. Output Stage During Power-Down
Rev. 0 | Page 20 of 28
AD5024/AD5044/AD5064
If this bit is set to 1, this channel updates synchronously; that is,
the DAC register is updated after new data is read, regardless of
CLEAR CODE REGISTER
CLR
The AD5024/AD5044/AD5064 have a hardware
pin that
LDAC
the state of the hardware
pin.
CLR
is an asynchronous clear input. The
input is falling edge
line low clears the contents of the
input register and the DAC registers to the data contained in
CLR
LDAC
It effectively sees the hardware
pin as being tied low.
CLR
sensitive. Bringing the
LDAC
(See Table 13 for the
register mode of operation.) This
flexibility is useful in applications where the user wants to simul-
taneously update select channels while the rest of the channels
are synchronously updating.
the user-configurable
register and sets the analog outputs
accordingly (see Table 11). This function can be used in system
calibration to load zero scale, midscale, or full scale to all channels
together. Note that zero scale and full scale are outside the linear
region of the DAC. These clear code values are user-programmable
by setting two bits, Bit DB1 and Bit DB0, in the control register
(see Table 11). The default setting clears the outputs to 0 V.
Command 0101 is designated for loading the clear code register
(see Table 7).
Writing to the DAC using Command 0110 loads the 4-bit
LDAC
register (DB3 to DB0). The default for each channel is 0;
LDAC
that is, the
pin works normally. Setting the bits to 1 means
that the DAC channel is updated regardless of the state of the
LDAC
pin.
POWER SUPPLY BYPASSING AND GROUNDING
The part exits clear code mode on the 32nd falling edge of the
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5024/AD5044/
AD5064 should have separate analog and digital sections. If the
AD5024/AD5044/AD5064 is in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5024/AD5044/AD5064.
CLR
next write to the part. If
is activated during a write
sequence, the write is aborted.
CLR
CLR
The
pulse activation time, which is the falling edge of
to when the output starts to change, is typically 10.6 ꢀs. If outside
the DAC linear region, it typically takes 10.6 ꢀs after executing
for the output to start changing (see Figure 33).
CLR
See Table 12 for contents of the input shift register during the
loading clear code register operation.
The power supply to the AD5024/AD5044/AD5064 should
be bypassed with 10 μF and 0.1 μF capacitors. The capacitors
should physically be as close as possible to the device, with the
0.1 μF capacitor ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. It is important that the
0.1 μF capacitor have low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of common
ceramic types of capacitors. This 0.1 μF capacitor provides a low
impedance path to ground for high frequencies caused by
transient currents due to internal logic switching.
LDAC FUNCTION
LDAC
Hardware
Pin
The outputs of all DACs can be updated simultaneously using
LDAC
LDAC
the hardware
Synchronous
pin, as shown in Figure 2.
: After new data is read, the DAC registers
are updated on the falling edge of the 32 SCLK pulse.
can be permanently low or pulsed.
nd
LDAC
LDAC
Asynchronous
: The outputs are not updated at the same
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals, if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip tech-
nique, where the component side of the board is dedicated to the
ground plane only and the signal traces are placed on the solder
side. However, this is not always possible with a 2-layer board.
LDAC
time that the input registers are written to. When
goes
low, the DAC registers are updated with the contents of the
input register.
LDAC
Software
Alternatively, the outputs of all DACs can be updated simulta-
LDAC
Function
neously using the software
Register n and updating all DAC registers. Command 0010 is
LDAC
function by writing to Input
reserved for this software
function.
register gives the user extra flexibility and control
LDAC LDAC
LDAC
The
over the hardware
bit register (DB0 to DB3) to 0 for a DAC channel means that
LDAC
pin (see Table 14). Setting the
this channel’s update is controlled by the hardware
pin.
Rev. 0 | Page 21 of 28
AD5024/AD5044/AD5064
Table 11. Clear Code Register
Clear Code Register
DB1
CR1
0
DB0
CR0
0
Clears to Code
0x0000
0
1
0x8000
1
0
0xFFFF
1
1
No operation
Table 12. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
LSB
DB0
1/0
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2 to DB19
X
DB1
0
1
0
1
X
X
X
X
1/0
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
Clear code register
(CR1 to CR0)
LDAC
Table 13.
Overwrite Definition
Load DAC Register
LDAC Bits (DB3 to DB0)
LDAC Pin
1 or 0
LDAC Operation
0
1
Determined by the LDAC pin
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
X—don’t care
LDAC
Table 14. 32-Bit Input Shift Register Contents for
Overwrite Function
MSB
LSB
DB31 to
DB28
DB4 to
DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19
DB3
DB2
DB1
DB0
X
0
1
1
0
X
X
X
X
X
DAC D
DAC C
DAC B
DAC A
Don’t
cares
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Setting LDAC bits to 1 overrides LDAC pin
Rev. 0 | Page 22 of 28
AD5024/AD5044/AD5064
AD5024/AD5044/AD5064 to 80C51/80L51 Interface
MICROPROCESSOR INTERFACING
Figure 50 shows a serial interface between the AD5024/AD5044/
AD5064 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5024/AD5044/AD5064, and RxD drives the serial
AD5024/AD5044/AD5064 to Blackfin ADSP-BF53x
Interface
Figure 48 shows a serial interface between the AD5024/AD5044/
AD5064 and the Blackfin® ADSP-BF53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5024/AD5044/AD5064, the setup for the interface is as
follows: DT0PRI drives the DIN pin of the AD5024/AD5044/
SYNC
data line of the part. The
signal is again derived from a
bit-programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5024/AD5044/
AD5064, P3.3 is taken low. The 80C51/80L51 transmit data in
8-bit bytes only; thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left low after the
first eight bits are transmitted, and a second write cycle is initiated
to transmit the second byte of data. P3.3 is taken high following
the completion of this cycle. The 80C51/80L51 output the serial
data in a format that has the LSB first. The AD5024/AD5044/
AD5064 must receive data with the MSB first. The 80C51/80L51
transmit routine should take this into account.
SYNC
AD5064, and TSCLK0 drives the SCLK of the parts. The
pin is driven from TFS0.
ADSP-BF53x*
AD5024/
AD5044/
AD5064
*
TFS0
DT0PRI
TSCLK0
SYNC
DIN
80C51/80L51*
AD5024/
AD5044/
AD5064*
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
P3.3
TxD
RxD
SYNC
Figure 48. AD5024/AD5044/AD5064 to Blackfin ADSP-BF53x Interface
SCLK
DIN
AD5024/AD5044/AD5064 to 68HC11/68L11 Interface
Figure 49 shows a serial interface between the AD5024/AD5044/
AD5064 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5024/AD5044/AD5064,
and the MOSI output drives the serial data line of the DAC.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 50. AD5024/AD5044/AD5064 to 80C512/80L51 Interface
AD5024/AD5044/AD5064 to MICROWIRE Interface
68HC11/68L11*
AD5024/
AD5044/
AD5064*
Figure 51 shows an interface between the AD5024/AD5044/
AD5064 and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked into
the AD5024/AD5044/AD5064 on the rising edge of the SCLK.
PC7
SCK
SYNC
SCLK
DIN
MICROWIRE*
AD5024/
MOSI
AD5044/
AD5064
*
*ADDITIONAL PINS OMITTED FOR CLARITY.
CS
SK
SO
SYNC
Figure 49. AD5024/AD5044/AD5064 to 68HC11/68L11 Interface
DIN
SYNC
The
signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 51. AD5024/AD5044/AD5064 to MICROWIRE Interface
SYNC
line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5024/AD5044/
AD5064, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
Rev. 0 | Page 23 of 28
AD5024/AD5044/AD5064
APPLICATIONS
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
USING A REFERENCE AS A POWER SUPPLY
Because the supply current required by the AD5024/AD5044/
AD5064 is extremely low, an alternative option is to use a voltage
reference to supply the required voltage to the parts (see Figure 52).
This is especially useful if the power supply is quite noisy or if
the system supply voltages are at some value other than 5 V (for
example, 15 V). The voltage reference outputs a steady supply
voltage for the AD5024/AD5044/AD5064. If the low dropout
REF195 is used, it must supply 3 mA of current to the AD5024/
AD5044/AD5064, with no load on the output of the DAC. When
the DAC output is loaded, the REF195 also needs to supply the
current to the load. The total current required (with a 5 kΩ
load on the DAC output) is
+5 V output.
R2 = 10kΩ
+5V
+5V
R1 = 10kΩ
AD820/
OP295
±5V
V
V
OUT
DD
0.1µF
10µF
AD5024/
AD5044/
AD5064
–5V
3-WIRE
SERIAL INTERFACE
3 mA + (5 V/5 kΩ) = 4 mA
Figure 53. Bipolar Operation
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 μV) error for the 4 mA current
drawn from it. This corresponds to a 0.196 LSB error.
15V
USING THE AD5024/AD5044/AD5064 WITH A
GALVANICALLY ISOLATED INTERFACE
In process control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where the
DAC is functioning. iCoupler® provides isolation in excess of
2.5 kV. The AD5024/AD5044/AD5064 use a 3-wire serial logic
interface, so the ADuM1300 three-channel digital isolator
provides the required isolation (see Figure 54). The power
supply to the part also needs to be isolated, which is done by
using a transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the AD5024/
AD5044/AD5064.
5V
REF195
V
DD
SYNC
3-WIRE
AD5024/
AD5044/
AD5064
V
= 0V TO 5V
OUT
SERIAL
SCLK
DIN
INTERFACE
Figure 52. REF195 as Power Supply to the AD5024/AD5044/AD5064
BIPOLAR OPERATION
The AD5024/AD5044/AD5064 have been designed for single-
supply operation, but a bipolar output range is also possible using
the circuit shown in Figure 53. The circuit gives an output voltage
range of 5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or an OP295 as the output amplifier.
5V
REGULATOR
10µF
0.1µF
POWER
Assuming VDD = VREF, the output voltage for any input code can
be calculated as follows:
V
DD
SCLK
V
V
V
V
SCLK
IA
IB
IC
OA
AD5024/
AD5044/
AD5064
ADuM1300
⎡
⎤
⎥
⎦
D
65,536
R1 + R2
R1
R2
R1
⎛
⎜
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = VDD
×
×
−V
×
DD
⎢
SDI
V
V
SYNC
DIN
OUT
OB
OC
⎝
⎠
⎣
where D represents the input code in decimal (0 to 65,535).
V
DATA
With VDD = 5 V, R1 = R2 = 10 kΩ,
GND
10× D
⎛
⎜
⎞
⎟
VOUT
=
− 5 V
65,536
⎝
⎠
Figure 54. AD5024/AD5044/AD5064 with a Galvanically Isolated Interface
Rev. 0 | Page 24 of 28
AD5024/AD5044/AD5064
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 55. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
1 LSB INL
1 LSB INL
1 LSB INL
1 LSB INL
1 LSB INL
1 LSB INL
Resolution
16 Bits
16 Bits
14 Bits
14 Bits
12 Bits
12 Bits
Package Description
Package Option
RU-16
RU-16
RU-16
RU-16
AD5064BRUZ1
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
AD5064BRUZ-REELꢀ1
AD5044BRUZ1
AD5044BRUZ-REELꢀ1
AD5024BRUZ1
AD5024BRUZ-REELꢀ1
RU-16
RU-16
1 Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
AD5024/AD5044/AD5064
NOTES
Rev. 0 | Page 26 of 28
AD5024/AD5044/AD5064
NOTES
Rev. 0 | Page 2ꢀ of 28
AD5024/AD5044/AD5064
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06803-0-8/08(0)
Rev. 0 | Page 28 of 28
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