AD5064BRUZ-1REEL7_技术文档

Fully Accurate, 12-/14-/16-Bit V_OUTnanoDAC, Quad,

SPI Interface, 4.5 V to 5.5 V in TSSOP

Data Sheet

AD5024/AD5044/AD5064

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

V_DD

V_REFIN

Low power quad 12-/14-/16-bit DAC, 1 LSB INL

Pin compatible and performance upgrade to AD5666

Individual and common voltage reference pin options

Rail-to-rail operation

4.5 V to 5.5 V power supply

Power-on reset to zero scale or midscale

3 power-down functions and per-channel power-down

AD5064-1

LDAC

BUFFER

INPUT

DAC

V_OUT

A

DAC A

DAC B

DAC C

DAC D

REGISTER

SCLK

INPUT

REGISTER

DAC

REGISTER

V_OUTB

INTERFACE

LOGIC AND

SHIFT

SYNC

DIN

INPUT

REGISTER

DAC

REGISTER

V_OUTC

REGISTER

INPUT

REGISTER

DAC

REGISTER

V_OUTD

SDO

POWER-DOWN

POWER-ON

RESET

LOGIC

Hardware

with software

override function

LDAC

POR

GND

LDAC CLR

function to programmable code

CLR

Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666

SDO daisy-chaining option

14-/16-lead TSSOP

Internal reference buffer and internal output amplifier

V_REFA V_REFB

V_DD

AD5024/

AD5044/

AD5064

LDAC

BUFFER

INPUT

DAC

V_OUT

A

DAC A

DAC B

DAC C

DAC D

REGISTER

APPLICATIONS

SCLK

INPUT

REGISTER

DAC

REGISTER

V_OUTB

INTERFACE

LOGIC AND

SHIFT

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

SYNC

DIN

REGISTER

INPUT

REGISTER

DAC

REGISTER

V_OUT

C

INPUT

REGISTER

DAC

REGISTER

V_OUTD

POWER-DOWN

LOGIC

POWER-ON

RESET

POR

GND

V_REFC V_REFD

LDAC CLR

Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD5024/AD5044/AD5064/AD5064-1 are low power, quad

12-/14-/16-bit buffered voltage output nanoDAC® converters

that offer relative accuracy specifications of 1 LSB INL and 1 LSB

DNL with the AD5024/AD5044/AD5064 individual reference

pin and the AD5064-1 common reference pin options. The

AD5024/AD5044/AD5064/AD5064-1 can operate from a single

4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1

also offer a differential accuracy specification of 1 LSB. The

parts use a versatile 3-wire, low power Schmitt trigger serial

interface that operates at clock rates up to 50 MHz and is compati-

ble with standard SPI, QSPI™, MICROWIRE™, and DSP interface

standards. Integrated reference buffers and output amplifiers are

also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1

incorporate a power-on reset circuit that ensures the DAC

output powers up to zero scale or midscale and remains there

until a valid write takes place to the device. The AD5024/AD5044/

AD5064/AD5064-1 contain a power-down feature that reduces

the current consumption of the device to typically 400 nA at 5 V

and provides software selectable output loads while in power-

down mode. Total unadjusted error for the parts is <2 mV.

1. Quad channel available in 14-/16-lead TSSOP packages.

2. 16-bit accurate, 1 LSB INL.

3. High speed serial interface with clock speeds up to 50 MHz.

4. Reset to known output voltage (zero scale or midscale).

Table 1. Related Devices

Part No.

Description

AD5666

Quad,16-bit buffered DAC,

16 LSB INL, TSSOP

AD5025/AD5045/AD5065 Dual, 16-bit buffered DACs,

1 LSB INL, TSSOP

AD5062, AD5063

16-bit nanoDAC, 1 LSB INL, SOT-23,

MSOP

AD5061

16-bit nanoDAC, 4 LSB INL, SOT-23

AD5040/AD5060

14-/16-bit nanoDAC, 1 LSB INL,

SOT-23

Rev. F

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Technical Support

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AD5024/AD5044/AD5064

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Output Amplifier........................................................................ 19

Serial Interface ............................................................................ 19

Shift Register............................................................................... 19

Modes of Operation ................................................................... 21

Power-On Reset.......................................................................... 22

Power-Down Modes .................................................................. 22

Clear Code Register ................................................................... 23

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 19

Digital-to-Analog Converter .................................................... 19

DAC Architecture....................................................................... 19

Reference Buffer ......................................................................... 19

LDAC

Function .......................................................................... 23

Power Supply Bypassing and Grounding................................ 24

Microprocessor Interfacing....................................................... 25

Applications Information .............................................................. 26

Using a Reference as a Power Supply....................................... 26

Bipolar Operation....................................................................... 26

Using the AD5024/AD5044/AD5064/AD5064-1 with a

Galvanically Isolated Interface ................................................. 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 28

REVISION HISTORY

6/13—Rev. E to Rev. F

Change to Standalone Mode Section ........................................... 21

Added Figure 5...................................................................................6

Changes to Figure 4...........................................................................6

Added Figure 6...................................................................................8

Added Table 6; Renumbered Sequentially .....................................8

Changed Input Shift Register to Shift Register Throughout .......8

Changes to Table 7.............................................................................9

Changes to Typical Performance Characteristics Section ........ 10

Changes to Terminology Section ................................................. 17

Changes to Digital-to-Analog Converter Section, Reference

Buffer Section, Output Amplifier Section, Serial Interface

Section, Shift Register Section, and Table 8................................ 19

Changes to Figure 47, Figure 48, and Figure 49 Captions ........ 20

Added Modes of Operation Section, Daisy-Chaining Section,

Table 10, and Table 11.................................................................... 21

Changes to Table 13 and Power-Down Mode Section .............. 22

Changes to Table 16 ....................................................................... 24

Changes to Figure 52 to Figure 55................................................ 25

Changes to Bipolar Operation Section and Figure 56 to

5/11—Rev. D to Rev. E

Changes to Table 4 ............................................................................ 5

Changes to Figure 4 and Figure 5................................................... 6

8/10—Rev. C to Rev. D

Change to Minimum

High Time (Single Channel

SYNC

Update) Parameter, Table 4 ............................................................. 5

5/10—Rev. B to Rev. C

Changes to Power-On Reset Section............................................ 22

6/09—Rev. A to Rev. B

Changes to Figure 1.......................................................................... 1

3/09—Rev. 0 to Rev. A

Figure 58 .......................................................................................... 26

Added Figure 59 ............................................................................. 27

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 28

Added 14-Lead TSSOP ......................................................Universal

Added Figure 1; Renumbered Sequentially .................................. 1

Changes to Features Section, General Description Section,

Product Highlights Section, Figure 2, and Table 1....................... 1

Changes to Table 2............................................................................ 3

Changes to Timing Characteristics Section and Table 4............. 5

Added Circuit and Timing Diagrams Section and Figure 3....... 5

8/08—Revision 0: Initial Version

Rev. F | Page 2 of 28

Data Sheet

AD5024/AD5044/AD5064

SPECIFICATIONS

V_DD= 4.5 V to 5.5 V, R_L= 5 kΩ to GND, C_L= 200 pF to GND, 2.5 V ≤ V_REFIN≤ V_DD, unless otherwise specified. All specifications T_MINto

T

_MAX, unless otherwise noted.

Table 2.

B Grade¹

Typ

A Grade^{1, 2}

Typ

Parameter

STATIC PERFORMANCE³

Min

Max

Min

Max

Unit

Conditions/Comments

Resolution

16

14

12

16

Bits

LSB

AD5064/AD5064-1

AD5044

AD5024

AD5064/AD5064-1; T_A= −40°C to

+105°C

AD5064/AD5064-1; T_A= −40°C to

+125°C

Relative Accuracy (INL)⁴

0.5

1

2

0.5

4

LSB

0.25

0.12

0.2

1

0.5

1

LSB

mV

AD5044

AD5024

Differential Nonlinearity (DNL)⁴

Total Unadjusted Error

Offset Error^{4, 5}

0.2

1

2

1.8

2

1.8

V_REF= 2.5 V, V_DD= 5.5 V

0.2

2

0.2

2

mV

Offset Error Temperature

µV/°C

Coefficient^{4, 6}

Full-Scale Error⁴

Gain Error⁴

Gain Temperature Coefficient^{4, 6}

All 1s loaded to DAC register, V_REF< V_DD

V_REF< V_DD

0.01

0.005

1

0.07

0.05

0.01

0.005

1

0.07 % FSR

0.05 % FSR

ppm

FSR/°C

DC Crosstalk^{4, 6}

40

µV

Due to single-channel, full-scale output

change, R_L= 5 kΩ to GND or V_DD

40

µV/mA

µV

Due to load current change

Due to powering down (per channel)

OUTPUT CHARACTERISTICS⁶

Output Voltage Range

Capacitive Load Stability

DC Output Impedance

Normal Mode

0

V_DD

1

0

V_DD

1

V

nF

R_L= 5 kΩ, R_L=100 kΩ, and R_L= ∞

0.5

Ω

Power-Down Mode

Output Connected to

100 kΩ Network

Output Connected to

1 kΩ Network

100

1

100

1

kΩ

Output impedance tolerance 20 kΩ

Output impedance tolerance 400 Ω

Short-Circuit Current

60

45

4.5

−92

60

45

4.5

−92

mA

µs

DAC = full scale, output shorted to GND

DAC = zero scale, output shorted to V_DD

Power-Up Time⁷

DC PSRR

dB

V_DD10%, DAC = full scale, V_REF< V_DD

REFERENCE INPUTS

Reference Input Range

Reference Current

2.2

V_DD

50

2.2

V_DD

50

V

µA

35

Per DAC channel; individual reference

option

140

120

32

160

140

120

32

160

µA

kΩ

Single reference option

Individual reference option

Single reference option

Reference Input Impedance

LOGIC INPUTS

Input Current⁸

1

0.8

1

0.8

µA

V

Input Low Voltage, V_INL

Input High Voltage, V_INH

Pin Capacitance⁶

2.2

4

pF

Rev. F | Page 3 of 28

AD5024/AD5044/AD5064

Data Sheet

B Grade¹

Typ

A Grade^{1, 2}

Typ

Parameter

Min

Max

0.4

1

Min

Max

0.4

1

Unit

Conditions/Comments

LOGIC OUTPUTS (SDO)⁹

Output Low Voltage, V_OL

Output High Voltage, V_OH

V

I_SINK= 2 mA

I_SOURCE= 2 mA

V_DD− 1

High Impedance Leakage

Current

High Impedance Output

Capacitance⁶

0.002

7

0.002

7

μA

pF

POWER REQUIREMENTS

V_DD

I_DD

4.5

5.5

4.5

5.5

V

DAC active, excludes load current

V_IH= V_DD, V_IL= GND, Code = midscale

10

Normal Mode

All Power-Down Modes¹¹

4

0.4

6

2

30

4

0.4

6

2

30

mA

µA

T_A= −40°C to +105°C

T_A= −40°C to +125°C

¹Temperature range is −40°C to +125°C, typical at 25°C.

²A grade offered in AD5064 only.

³Linearity and total unadjusted error are calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256;

AD5024: Code 32 to Code 4064. Output unloaded.

⁴See the Terminology section.

⁵Offset error calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064.

Output unloaded

⁶Guaranteed by design and characterization; not production tested.

⁷Time to exit power-down mode to normal mode; 32^ndclock edge to 90% of DAC midscale value, output unloaded.

⁸Current flowing into individual digital pins. V_DD= 5.5 V; V_REF= 4.096 V; Code = midscale.

⁹AD5064-1 only.

¹⁰Interface inactive. All DACs active. DAC outputs unloaded.

¹¹All four DACs powered down.

AC CHARACTERISTICS

V_DD= 4.5 V to 5.5 V, R_L= 5 kΩ to GND, C_L= 200 pF to GND, 2.5 V ≤ V_REFIN≤ V_DD. All specifications T_MINto T_MAX, unless otherwise

noted.

Table 3.

Parameter^{1, 2}

Min Typ Max Unit

Conditions/Comments³

Output Voltage Settling Time

5.8

8

µs

¼ to ¾ scale and ¾ to ¼ scale settling to 1 LSB, R_L= 5 kΩ,

single-channel update

10.7 13

µs

¼ to ¾ scale and ¾ to ¼ scale settling to 1 LSB, R_L= 5 kΩ, all channel

update

Slew Rate

1.5

3

−90

0.1

1.9

2

V/µs

nV-sec

dB

nV-sec

kHz

Digital-to-Analog Glitch Impulse

Reference Feedthrough

Digital Feedthrough

Digital Crosstalk

Analog Crosstalk

DAC-to-DAC Crosstalk

AC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

Output Noise Spectral Density

1 LSB change around major carry

V_REF= 3 V 0.86 V p-p, frequency = 100 Hz to 100 kHz

3.5

6

340

−80

64

60

6

V_REF= 3 V 0.86 V p-p

V_REF= 3 V 0.2 V p-p, frequency = 10 kHz

dB

nV/√Hz DAC code = 0x8400, frequency = 1 kHz

nV/√Hz DAC code = 0x8400, frequency = 10 kHz

μV p-p

Output Noise

0.1 Hz to 10 Hz

¹Guaranteed by design and characterization; not production tested.

²See the Terminology section.

³Temperature range is −40°C to +125°C, typical at 25°C.

Rev. F | Page 4 of 28

Data Sheet

AD5024/AD5044/AD5064

TIMING CHARACTERISTICS

All input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2. See Figure 4 and

Figure 5. V_DD= 4.5 V to 5.5 V. All specifications T_MINto T_MAX, unless otherwise noted.

Table 4.

Parameter¹

Symbol

Min

20

10

17

5

Typ

Max

Unit

ns

µs

ns

µs

ns

µs

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNC to SCLK Falling Edge Setup Time

Data Setup Time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

Data Hold Time

5

SCLK Falling Edge to SYNC Rising Edge

Minimum SYNC High Time (Single Channel Update)

Minimum SYNC High Time (All Channel Update)

SYNC Rising Edge to SCLK Fall Ignore

LDAC Pulse Width Low

30

t₈

3

t₈

8

t₉

17

20

10

10.6

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

SCLK Falling Edge to LDAC Rising Edge

CLR Minimum Pulse Width Low

SCLK Falling Edge to LDAC Falling Edge

CLR Pulse Activation Time

2, 3

SCLK Rising Edge to SDO Valid

SCLK Falling Edge to SYNC Rising Edge

SYNC Rising Edge to SCLK Rising Edge

SYNC Rising Edge to LDAC/CLR Falling Edge (Single Channel Update)

SYNC Rising Edge to LDAC/CLR Falling Edge (All Channel Update)

Power-up Time⁴

t₁₅

t₁₆

22

2

5

2

t₁₇

8

2

t₁₈

2

t₁₈

8

4.5

¹Maximum SCLK frequency is 50 MHz at V_DD= 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.

²Daisy-chain mode only.

³Measured with the load circuit of Figure 3. t₁₅determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only.

⁴Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32^ndclock edge to 90% of DAC midscale value, with output unloaded.

Circuit and Timing Diagrams

2mA

I

OL

V

(MIN) + V (MAX)

OL

OH

TO OUTPUT

2

C

L

50pF

2mA

I

OH

Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications

Rev. F | Page 5 of 28

AD5024/AD5044/AD5064

Data Sheet

t₁

t₉

SCLK

t₂

t₈

t₇

t₃

t₄

SYNC

t₆

t₅

DIN

1

DB31

DB0

t₁₃

t₁₀

LDAC

t₁₁

2

LDAC

t₁₂

CLR

t₁₄

V

OUT

1

2

ASYNCHRONOUS LDAC UPDATE MODE.

SYNCHRONOUS LDAC UPDATE MODE.

Figure 4. Serial Write Operation

SCLK

32

64

t₁₇

t₈

t₄

t

16

SYNC

DIN

t₅

t₆

DB0

DB31

DB0

DB31

INPUT WORD FOR DAC N

INPUT WORD FOR DAC N + 1

INPUT WORD FOR DAC N

t₁₅

DB31

DB0

SDO

UNDEFINED

t₁₈

t₁₀

1

LDAC

t₁₈

t₁₂

CLR

1

IF IN DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY.

Figure 5. Daisy-Chain Timing Diagram

Rev. F | Page 6 of 28

Data Sheet

AD5024/AD5044/AD5064

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 5.

Parameter

Rating

V_DDto GND

−0.3 V to +7 V

Digital Input Voltage to GND

V_OUTto GND

V_REFto GND

−0.3 V to V_DD+ 0.3 V

Operating Temperature Range

Industrial

Storage Temperature Range

−40°C to +125°C

−65°C to +150°C

150°C

ESD CAUTION

Junction Temperature (T_{J MAX}

)

TSSOP Package

Power Dissipation

θ_JAThermal Impedance

(T_{J MAX}− T_A)/θ_JA

113°C/W

Reflow Soldering Peak Temperature

Pb-Free

260°C

Rev. F | Page 7 of 28

AD5024/AD5044/AD5064

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

14

1

2

3

4

5

6

7

SCLK

LDAC

SYNC

13 DIN

V

12 GND

DD

AD5064-1

TOP VIEW

V

11

B

D

V

A

C

OUT

V

10

9

OUT

CLR

SDO

OUT

(Not to Scale)

POR

V

8

REFIN

Figure 6. 14-Lead TSSOP (RU-14)

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

LDAC

LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing

this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows

all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode.

When daisy-chain mode is enabled, this pin cannot be tied permanently low; the LDAC pin should be

used in asynchronous LDAC update mode, as shown in Figure 5, and the LDAC pin must be brought

high after pulsing.

2

3

SYNC

V_DD

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the

falling edges of the next 32 clocks. If SYNC is taken high before the 32^ndfalling edge, the rising edge of

SYNC acts as an interrupt and the write sequence is ignored by the device.

Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled

with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

4

5

6

V_OUT

POR

A

C

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to V_DD

powers up all four DACs to midscale.

7

8

V_REFIN

SDO

This is a common pin for reference input for DAC A, DAC B, DAC C, and DAC D.

Serial Data Output. Can be used to daisy-chain a number of AD5064-1 devices together. The serial data

is transferred on the rising edge of SCLK and is valid on the falling edge of the clock.

9

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are

ignored. When CLR is activated, the input register and the DAC register are updated with the data

contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

10

11

12

13

V_OUT

GND

DIN

D

B

Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the

falling edge of the serial clock input.

14

SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data

can be transferred at rates of up to 50 MHz.

Rev. F | Page 8 of 28

Data Sheet

AD5024/AD5044/AD5064

LDAC

SYNC

1

2

3

4

5

6

7

8

16 SCLK

15 DIN

V

14

13

12

11

10

9

GND

DD

AD5024/

AD5044/

AD5064

V

B

D

OUT

V

B

A

C

REF

V

OUT

TOP VIEW

(Not to Scale)

V

D

REF

OUT

V

CLR

V

C

POR

REF

Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

LDAC

LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing

this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows

all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode.

2

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the

falling edges of the next 32 clocks. If SYNC is taken high before the 32^ndfalling edge, the rising edge of

SYNC acts as an interrupt and the write sequence is ignored by the device.

3

V_DD

Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4

5

6

7

8

V_REF

B

DAC B Reference Input. This is the reference voltage input pin for DAC B.

DAC A Reference Input. This is the reference voltage input pin for DAC A.

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Power-On Reset. Tying this pin to GND powers up the part to 0 V. Tying this pin to V_DDpowers up the

part to midscale.

V_REFA

V_OUT

POR

A

C

9

V_REFC

DAC C Reference Input. This is the reference voltage input pin for DAC C.

10

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are

ignored. When CLR is activated, the input register and the DAC register are updated with the data

contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.

DAC D Reference Input. This is the reference voltage input pin for DAC D.

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

11

12

13

14

15

V_REF

V_OUT

D

B

GND

DIN

Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the

falling edge of the serial clock input.

16

SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data

can be transferred at rates of up to 50 MHz.

Rev. F | Page 9 of 28

AD5024/AD5044/AD5064

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

V

T

= 5V

V

T

= 5V

REF

= 25°C

DD

= 4.096V

REF

0.8

= 25°C

A

0.6

0.4

0.2

0

0.6

0.4

0.2

0

–0.2

–0.4

–0.2

–0.4

–0.6

–0.8

–1.0

–0.6

–0.8

–1.0

512

16,640

32,768

48,896

65,024

16,384

512

16,640

32,768

48,896

65,024

DAC CODE

Figure 11. AD5064/AD5064-1 DNL

Figure 8. AD5064/AD5064-1 INL

1.0

0.8

1.0

0.8

V

= 5V

V

= 5V

= 4.096V

= 25°C

DD

= 4.096V

V

REF

= 25°C

REF

T

A

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

4096

8192

12,288

0

512

1024

1536

2048

2560

3072

3584

4096

DAC CODE

Figure 12. AD5044 DNL

Figure 9. AD5044 INL

1.00

0.75

0.50

0.25

0

1.0

0.8

V

T

= 5V

V

T

= 5V

DD

= 4.096V

REF

= 25°C

A

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.25

–0.50

–0.75

–1.00

0

4096

8192

12,288

0

512

1024

1536

2048

2560

3072

3584

4096

DAC CODE

Figure 13. AD5024 DNL

Figure 10. AD5024 INL

Rev. F | Page 10 of 28

Data Sheet

AD5024/AD5044/AD5064

0.20

1.2

1.0

V

= 5V

T

= 25°C

DD

A

= 4.096V

REF

0.15

T

= 25°C

A

0.8

0.10

0.05

0.6

0.4

0.2

MAX TUE @ V = 5.5V

DD

0

MIN TUE @ V = 5.5V

DD

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–0.05

–0.10

–0.15

–0.20

512

16,640

32,768

48,896

65,024

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

DAC CODE

REFERENCE VOLTAGE (V)

Figure 14. Total Unadjusted Error (TUE)

Figure 17. TUE vs. Reference Input Voltage

1.6

1.4

0.015

0.010

T

= 25°C

A

1.2

1.0

DAC A

0.8

0.6

MAX INL ERROR @ V = 5.5V

DD

0.005

0

0.4

0.2

DAC B

0

DAC D

DAC C

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

MIN INL ERROR @ V = 5.5V

DD

–0.005

–0.010

–0.015

V

= 5.5V

DD

= 4.096V

REF

120

–60 –40 –20

0

20

40

60

80

100

140

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

Figure 15. INL vs. Reference Input Voltage

Figure 18. Gain Error vs. Temperature

1.6

1.4

0.6

0.5

V

= 5.5V

= 4.096V

T

= 25°C

DD

A

V

REF

1.2

DAC C

1.0

0.4

0.3

0.8

0.6

0.4

0.2

0.1

MAX DNL ERROR @ V

= 5.5V

DD

0.2

DAC D

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

0

MIN DNL ERROR @ V = 5.5V

DD

–0.1

–0.2

DAC A

DAC B

0

–0.3

–0.4

–60 –40 –20

20

40

60

80

100 120 140

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

TEMPERATURE (ºC)

REFERENCE VOLTAGE (V)

Figure 16. DNL vs. Reference Input Voltage

Figure 19. Offset Error vs. Temperature

Rev. F | Page 11 of 28

AD5024/AD5044/AD5064

Data Sheet

10

8

0.2

V

A

= 5.5V

REF

= 25°C

V

= 4.096V

DD

REF

= 25°C

= 4.096

T

A

T

0.1

0

6

GAIN ERROR

4

FULL-SCALE ERROR

–0.1

2

0

–0.2

4.50

0

10,000 20,000 30,000 40,000 50,000 60,000 70,000

DAC CODE

4.75

5.00

(V)

5.25

5.50

V

DD

Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage

Figure 23. Supply Current vs. Code

10

8

0.12

V

= 5.5V

= 4.096

V

T

= 4.096V

DD

REF

= 25°C

REF

CODE = MIDSCALE

A

0.09

0.06

0.03

0

6

4

2

0

–40

–20

0

20

40

60

80

100

120

4.50

4.75

5.00

(V)

5.25

5.50

V

DD

TEMPERATURE (°C)

Figure 21. Offset Error Voltage vs. Supply Voltage

Figure 24. Supply Current vs. Temperature

40

35

30

25

20

15

10

5

10

MEAN: 4.11699

SD: 0.0544403

LIMITS: LOW: 3 HIGH: 4.3

CPk: LOW: 6.84 HIGH: 1.12

V

A

= 5.5V

REF

= 25°C

DD

= 4.096

T

8

6

4

2

0

V

= 4.096V

REF

= 25°C

T

A

CODE = MIDSCALE

0

4.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

5.3

5.4

5.5

3.9

4.0

4.1

4.2

4.3

SUPPLY VOLTAGE (V)

I

(mA)

DD POWER-UP

Figure 25. Supply Current vs. Supply Voltage

Figure 22. I_DDHistogram, V_DD= 5.0 V

Rev. F | Page 12 of 28

Data Sheet

AD5024/AD5044/AD5064

10

V

T

= 4.096V

V

= 5.5V

REF

= 25°C

DD

= 4.096

A

REF

OUTPUT UNLOADED

T

= 25°C

A

V

DD

8

6

4

2

0

1

3

DAC A

CH1 2V

CH3 2V

M2ms

20.4%

A CH1

2.52V

0

1

2

3

4

5

T

DIGITAL INPUT VOLTAGE (V)

Figure 26. Supply Current vs. Digital Input Voltage

Figure 29. Power-On Reset to Midscale

5.0

4.5

4.0

3.5

3.0

2.5

CH1 = SCLK

1

V

= 5V, V = 4.096V

REF

DD

= 25ºC

T

A

1/4 SCALE TO 3/4 SCALE

3/4 SCALE TO 1/4 SCALE

OUTPUT LOADED WITH 5kΩ

AND 200pF TO GND

CH2 = V

V

= 5V

DD

OUT

2.0

1.5

1.0

0.5

0

POWER-UP TO MIDSCALE

OUTPUT UNLOADED

2

0

2

4

6

8

10

12

14

CH1 5V

CH2 500mV

M2µs

55%

A CH2

1.2V

T

TIME (µs)

Figure 30. Exiting Power-Down to Midscale

Figure 27. Settling Time

6

5

VDD = 5V

= 4.096V

V

T

= 4.096V

= 25°C

REF

V

REF

A

T

= 25°C

A

V

DD

CODE = 0x8000 TO 0x7FFF

4

3

OUTPUT UNLOADED WITH 5kΩ

AND 200pF

2

1

3

1

0

DAC A

–1

–2

–3

0

2.5

5.0

7.5

10.0

CH1 2V

CH3 2V

M2ms

20.4%

A CH1

2.52V

TIME (μs)

T

Figure 31. Digital-to-Analog Glitch Impulse

Figure 28. Power-On Reset to 0 V

Rev. F | Page 13 of 28

AD5024/AD5044/AD5064

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

7

V

T

= 5V,

V

T

= 5V, V = 4.096V

REF

DD

= 25ºC

DD

= 25ºC

6

5

A

DAC LOADED WITH MIDSCALE

V

= 3.0V ± 200mV p-p

REF

4

3

2

1

0

–1

–2

–3

–4

–90

–100

0

2.5

5.0

7.5

10.0

5

10

20

30

FREQUENCY (kHz)

40

50

55

TIME (μs)

Figure 32. Analog Crosstalk

Figure 35. Total Harmonic Distortion

7

6

5

4

3

2

1

0

24

22

20

18

16

14

12

10

8

V

= 5V, V = 3.0V

REF

V

T

= 5V, V = 4.096V

REF

DD

= 25°C

DD

= 25°C

T

A

1/4 SCALE TO 3/4 SCALE

WITHIN ±1LSB

–1

–2

–3

–4

6

4

0

2.5

5.0

7.5

10.0

0

1

2

3

4

5

6

7

8

9

10

TIME (μs)

CAPACITANCE (nF)

Figure 33. DAC-to-DAC Crosstalk

Figure 36. Settling Time vs. Capacitive Load

V

= 5V, V = 4.096V

REF

DD

= 25ºC

T

A

DAC LOADED WITH MIDSCALE

CLR

1

DAC A

2

V

= 5V

REF

= 25ºC

DD

V

= 4.096V

T

A

4s/DIV

CH1 5V

CH2 2V

M2µs

A CH1

2.5V

T 11%

Figure 34. 0.1 Hz to 10 Hz Output Noise Plot

CLR

Figure 37. Hardware

Rev. F | Page 14 of 28

Data Sheet

AD5024/AD5044/AD5064

10

0.10

0.08

0.06

0.04

0.02

0

CODE = MIDSCALE

= 5V, V = 4.096V

V

DD

REF

0

–10

–20

–30

–40

–0.02

–0.04

–0.06

–0.08

–0.10

CH A

CH B

–50

CH C

CH D

3dB POINT

–60

10

100

1000

10000

–25 –20 –15 –10 –5

0

5

10

15

20

25

30

FREQUENCY (kHz)

I

(mA)

OUT

Figure 41. Typical Current Limiting Plot

Figure 38. Multiplying Bandwidth

5.0

4.5

4.0

3.5

3.0

2.5

T

= 25°C

DD

A

V

= 5V, V

= 4.096V

REF

DAC A 295mV p-p

V

= 5V, V

= 25°C

= 4.096V

DD

REF

T

A

1/4 SCALE TO 3/4 SCALE

3/4 SCALE TO 1/4 SCALE

2.0

1.5

1.0

0.5

0

OUTPUT LOADED WITH 5kΩ

AND 200pF TO GND

0

2

4

6

8

10

12

14

CH1 50mV CH2 5V

M4µs

A CH2

1.2V

T 8.6%

TIME (µs)

Figure 42. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,

No Load

Figure 39. Typical Output Slew Rate

0.0010

0.0008

0.0006

0.0004

0.0002

0

T

V

= 25°C

A

CODE = MIDSCALE

= 5V, V = 4.096V

= 5V, V

= 4.096V

DD

REF

V

DD

REF

DAC A 200mV p-p

–0.0002

–0.0004

–0.0006

–0.0008

SCLK

CH1 50mV CH2 5V

M4µs

A CH2

1.2V

–25 –20 –15 –10 –5

0

5

10

15

20

25

30

T 8.6%

CURRENT (mA)

Figure 43. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,

5 kΩ/200 pF Load

Figure 40. Typical Output Load Regulation

Rev. F | Page 15 of 28

AD5024/AD5044/AD5064

Data Sheet

V

T

= 5V,V = 4.096V

REF

T

V

= 25°C

= 5V, V

DD

= 25°C

A

= 4.096V

REF

A

DD

DAC A 170mV p-p

DAC A 129mV p-p

SCLK

CH1 20mV CH2 5V

M4µs

A CH2

1.2V

CH1 20mV CH2 5V

M4µs

A CH2

1.2V

T 8.6%

Figure 44. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,

No Load

Figure 45. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,

5 kΩ/200 pF Load

Rev. F | Page 16 of 28

Data Sheet

AD5024/AD5044/AD5064

TERMINOLOGY

Relative Accuracy (INL)

DC Power Supply Rejection Ratio (PSRR)

For the DAC, relative accuracy, or integral nonlinearity (INL),

is a measure of the maximum deviation in LSBs from a straight

line passing through the endpoints of the DAC transfer function.

Figure 8, Figure 9, and Figure 10 show plots of typical INL vs.

code.

PSRR indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in V_OUTto

a change in V_DDfor full-scale output of the DAC. It is measured

in decibels. V_REFis held at 2.5 V, and V _DDis varied by 10%.

Measured with V_REF< V_DD

.

Differential Nonlinearity (DNL)

DC Crosstalk

DNL is the difference between the measured change and the

ideal 1 LSB change between any two adjacent codes. A specified

differential nonlinearity of 1 LSB maximum ensures monoto-

nicity. This DAC is guaranteed monotonic by design. Figure 11,

Figure 12, and Figure 13 show plots of typical DNL vs. code.

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is measured

with a full-scale output change on one DAC (or soft power-down

and power-up) while monitoring another DAC kept at midscale.

It is expressed in microvolts.

Offset Error

DC crosstalk due to load current change is a measure of the

impact that a change in load current on one DAC has to another

DAC kept at midscale. It is expressed in microvolts per milliamp.

Offset error is a measure of the difference between the actual

V

_OUTand the ideal V_OUT, expressed in millivolts in the linear

region of the transfer function. Offset error is calculated using

a reduced code range—AD5064/AD5604-1: Code 512 to Code

65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to

Code 4064, with output unloaded. Offset error can be negative or

positive and is expressed in millivolts.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal

at the DAC output to the reference input when the DAC output

is not being updated (that is,

decibels.

LDAC

is high). It is expressed in

Gain Error

Digital Feedthrough

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale range.

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital input pins of the

device, but it is measured when the DAC is not being written

Offset Error Temperature Coefficient

SYNC

to (

held high). It is specified in nanovolt-seconds and

Offset error temperature coefficient is a measure of the change

in offset error with a change in temperature. It is expressed in

microvolts per degree Celsius.

measured with one simultaneous data and clock pulse loaded

to the DAC.

Digital Crosstalk

Gain Temperature Coefficient

Digital crosstalk is the glitch impulse transferred to the output

of one DAC at midscale in response to a full-scale code change

(all 0s to all 1s or vice versa) in the input register of another

DAC. It is measured in standalone mode and is expressed in

nanovolt-seconds.

Gain error drift is a measure of the change in gain error with

changes in temperature. It is expressed in parts per million of

full-scale range per degree Celsius.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code (0xFFFF) is loaded into the DAC register. Ideally, the

output should be V_REF− 1 LSB. Full-scale error is expressed as a

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output

of one DAC due to a change in the output of another DAC. It is

measured by loading one of the input registers with a full-scale

percentage of the full-scale range. Measured with V_REF< V_DD

.

LDAC

code change (all 0s to all 1s or vice versa) while keeping

Digital-to-Analog Glitch Impulse

LDAC

high, and then pulsing

low and monitoring the output of

the DAC whose digital code has not changed. The area of the

glitch is expressed in nanovolt-seconds.

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nanovolt-

seconds and is measured when the digital input code is changed

by 1 LSB at the major carry transition (0x7FFF to 0x8000). See

Figure 31.

Rev. F | Page 17 of 28

AD5024/AD5044/AD5064

Data Sheet

DAC-to-DAC Crosstalk

The multiplying bandwidth, expressed in kilohertz, is the

frequency at which the output amplitude falls to 3 dB below

the input.

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DAC. This includes both digital and

analog crosstalk. It is measured by loading one of the DACs

with a full-scale code change (all 0s to all 1s or vice versa) with

Total Harmonic Distortion (THD)

Total harmonic distortion is the difference between an ideal

sine wave and its attenuated version using the DAC. The sine

wave is used as the reference for the DAC, and the THD is a

measure of the harmonics present on the DAC output. It is

measured in decibels.

LDAC

low and monitoring the output of another DAC. The

energy of the glitch is expressed in nanovolt-seconds.

Multiplying Bandwidth

The multiplying bandwidth is a measure of the finite bandwidth

of the amplifiers within the DAC. A sine wave on the reference

(with full-scale code loaded to the DAC) appears on the output.

Rev. F | Page 18 of 28

Data Sheet

AD5024/AD5044/AD5064

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

OUTPUT AMPLIFIER

The AD5024/AD5044/AD5064/AD5064-1 are single 12-/14-/

16-bit, serial input, voltage output DACs with an individual

reference pin. The AD5064-1 model (see the Ordering Guide)

is a 16-bit, serial input, voltage output DAC that is identical to

other AD5064 models but with a single reference pin for all

DACs. The parts operate from supply voltages of 4.5 V to 5.5 V.

Data is written to the AD5024/AD5044/AD5064/AD5064-1 in a

32-bit word format via a 3-wire serial interface. The AD5024/

AD5044/AD5064/AD5064-1 incorporate a power-on reset circuit

that ensures that the DAC output powers up to a known output

state. The devices also have a software power-down mode that

reduces the typical current consumption to typically 400 nA.

The output buffer amplifier can generate rail-to-rail voltages

on its output, which gives an output range of 0 V to V_DD. The

amplifier is capable of driving a load of 5 kΩ in parallel with

200 pF to GND. The slew rate is 1.5 V/µs with a ¼ to ¾ scale

settling time of 5.8 µs.

SERIAL INTERFACE

The AD5024/AD5044/AD5064/AD5064-1 have a 3-wire serial

SYNC

interface (

, SCLK, and DIN) that is compatible with SPI,

QSPI, and MICROWIRE interface standards as well as most

DSPs. See Figure 4 for a timing diagram of a typical write

sequence. The AD5064-1 model contains an SDO pin to allow

the user to daisy-chain multiple devices together (see the Daisy-

Chaining section).

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

SHIFT REGISTER

D













V_OUT=V_REFIN

×

The AD5024/AD5044/AD5064/AD5064-1 shift register is 32 bits

wide. The first four bits are don’t cares. The next four bits are the

command bits, C3 to C0 (see Table 8), followed by the 4-bit

DAC address bits, A3 to A0 (see Table 9), and finally the bit

data-word. The data-word comprises 12-bit, 14-bit, or 16-bit input

code, followed by eight, six, or four don’t care bits for the AD5024,

AD5044, and AD5064/AD5064-1, respectively (see Figure 47,

Figure 48, and Figure 49). These data bits are transferred to the

DAC register on the 32^ndfalling edge of SCLK. Commands can be

executed on individually selected DAC channels or on all DACs.

2^N

where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register (0 to 65,535 for the 16-bit AD5064).

N is the DAC resolution.

DAC ARCHITECTURE

The DAC architecture of the AD5064 consists of two matched

DAC sections. A simplified circuit diagram is shown in Figure 46.

The four MSBs of the 16-bit data word are decoded to drive

15 switches, E1 to E15. Each of these switches connects one of

15 matched resistors to either GND or the V_REFbuffer output.

The remaining 12 bits of the data-word drive the S0 to S11

switches of a 12-bit voltage mode R-2R ladder network.

Table 8. Command Definitions

Command

C3 C2 C1 C0 Description

0

1

0

1

0

Write to Input Register n

Update DAC Register n

Write to Input Register n, update all

(software LDAC)

V

OUT

2R

E1

2R

E2

2R

S0

2R

S1

2R

E15

S11

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to and update DAC Channel n

Power down/power up DAC

Load clear code register

Load LDAC register

V

REF

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Reset (power-on reset)

Set up DCEN register¹(daisy-chain enable)

Reserved

Figure 46. DAC Ladder Structure

REFERENCE BUFFER

Reserved

The AD5024/AD5044/AD5064/AD5064-1 operate with an exter-

nal reference. For most models, each DAC has a dedicated voltage

reference pin. The AD5064-1 model has a single voltage reference

pin for all DACs. The reference input pin has an input range of

2.2 V to V_DD. This input voltage is then buffered internally to

provide a reference for the DAC core.

¹Available in the AD5064-1 14-lead TSSOP package only.

Table 9. Address Commands

Address (n)

A3

0

A2

0

A1

0

A0

0

1

0

1

Selected DAC Channel

DAC A

DAC B

DAC C

DAC D

All DACs

0

1

Rev. F | Page 19 of 28

AD5024/AD5044/AD5064

Data Sheet

DB31 (MSB)

DB0 (LSB)

X

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DATA BITS

COMMAND BITS

ADDRESS BITS

Figure 47. AD5024 Shift Register Content

DB31 (MSB)

DB0 (LSB)

X

C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DATA BITS

COMMAND BITS

ADDRESS BITS

Figure 48. AD5044 Shift Register Content

DB31 (MSB)

DB0 (LSB)

X

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DATA BITS

COMMAND BITS

ADDRESS BITS

Figure 49. AD5064/AD5064-1 Shift Register Content

SCLK

SYNC

DIN

DB31

DB0

DB31

DB0

INVALID WRITE SEQUENCE:

ND

VALID WRITE SEQUENCE, OUTPUT UPDATES

ND

SYNC HIGH BEFORE 32 FALLING EDGE

ON THE 32 FALLING EDGE

SYNC

Figure 50.

Interrupt Facility

Rev. F | Page 20 of 28

Data Sheet

AD5024/AD5044/AD5064

reserved for this DCEN function (see Table 8). The daisy-chain

mode is enabled by setting Bit DB1 in the DCEN register. The

default setting is standalone mode, where DB1 = 0.

MODES OF OPERATION

There are three main modes of operation: standalone mode

where a single device is used, daisy-chain mode for a system

that contains several DACs, and power-down mode when the

supply current falls to 0.4 µA at 5 V.

Table 10 shows how the state of the bit corresponds to the mode

of operation of the device.

Standalone Mode

Table 10. DCEN (Daisy-Chain Enable) Register

SYNC

The write sequence begins by bringing the

line low. Data

DB1

DB0

Description

from the DIN line is clocked into the 32-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 50 MHz, making the AD5024/AD5044/AD5064/AD5064-1

compatible with high speed DSPs. On the 32^ndfalling clock edge,

the last data bit is clocked in and the programmed function is

0

1

X

Standalone mode (default)

DCEN mode

The SCLK is continuously applied to the shift register when

SYNC

is low. If more than 32 clock pulses are applied, the data

ripples out of the shift register and appears on the SDO line.

This data is clocked out on the rising edge of SCLK and is valid

on the falling edge. By connecting this line to the DIN input on

the next DAC in the chain, a daisy-chain interface is constructed.

Each DAC in the system requires 32 clock pulses; therefore, the

total number of clock cycles must equal 32N, where N is the

total number of devices that are updated. If

at a clock that is not a multiple of 32, it is considered an invalid

frame and the data is discarded.

LDAC

executed, that is, an

-dependent change in DAC register

contents and/or a change in the mode of operation. At this

SYNC

stage, the

line can be kept low or be brought high. In

either case, it must be brought high for a minimum of 3 µs

(single channel, see Table 4, t₈parameter) before the next write

SYNC

sequence so that a falling edge of

can initiate the next

should be idled at rails between write

sequences for even lower power operation of the part.

SYNC

is taken high

SYNC

write sequence.

Interrupt

In a normal write sequence, the

least 32 falling edges of SCLK, and the DAC is updated on the

SYNC

When the serial transfer to all devices is complete,

taken high. This prevents any further data from being clocked

into the shift register.

is

SYNC

line is kept low for at

32^ndfalling edge. However, if

is brought high before the

LDAC

In daisy-chain mode, the

low. The

mode, as shown in Figure 5. The

high after pulsing. This allows all DAC outputs to simulta-

neously update.

pin cannot be tied permanently

32^ndfalling edge, this acts as an interrupt to the write sequence.

The write sequence is seen as invalid. Neither an update of the

DAC register contents nor a change in the operating mode

occurs (see Figure 50).

LDAC

update

pin must be used in asynchronous

LDAC

pin must be brought

Daisy-Chaining

The serial clock can be continuous or a gated clock. A continuous

For systems that contain several DACs the SDO pin can be

used to daisy-chain several devices together and provide serial

readback.

SYNC

SCLK source can be used only if

can be held low for the

correct number of clock cycles. In gated clock mode, a burst

clock containing the exact number of clock cycles must be used,

SYNC

and

must be taken high after the final clock to latch the data.

The daisy-chain mode is enabled through a software executable

daisy-chain enable (DCEN) command. Command 1000 is

Table 11. 32-Bit Shift Register Contents for Daisy-Chain Enable

MSB

LSB

DB31 to DB28

X

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19 to DB2

X

DB1

DB0

1

0

X

1/0

X

Don’t cares

Command bits (C3 to C0)

Address bits (A3 to A0)

Don’t cares

DCEN register

Rev. F | Page 21 of 28

AD5024/AD5044/AD5064

Data Sheet

POWER-ON RESET

Any or all DACs (DAC D to DAC A) can be powered down to

the selected mode by setting the corresponding four bits (DB3,

DB2, DB1, DB0) to 1. See Table 13 for the contents of the shift

register during power-down/power-up operation.

The AD5024/AD5044/AD5064/AD5064-1 contain a power-on

reset circuit that initializes the registers to their default values

and controls the output voltage during power-up. By connecting

the POR pin low, the AD5024/AD5044/AD5064/AD5064-1

output powers up to zero scale. Note that this is outside the

linear region of the DAC; by connecting the POR pin high, the

AD5024/AD5044/AD5064/AD5064-1 output powers up to

midscale. The output remains powered up at this level until a

valid write sequence is made to the DAC. This is useful in

applications where it is important to know the state of the

output of the DAC while it is in the process of powering up.

There is also a software executable reset function that resets the

DAC to the power-on reset code. Command 0111 is designated

When both Bit DB9 and Bit D8 in the shift register are set to 0,

the part works normally with its normal power consumption of

4 mA at 5 V. However, for the three power-down modes, the

supply current falls to 0.4 μA at 5 V. Not only does the supply

current fall, but the output stage is also internally switched from

the output of the amplifier to a resistor network of known values.

This has the advantage that the output impedance of the part is

known while the part is in power-down mode. There are three

different power-down options. The output is connected inter-

nally to GND through either a 1 kΩ or a 100 kΩ resistor, or it is

left open-circuited (three-state). The output stage is illustrated in

Figure 51.

LDAC

for this reset function (see Table 8). Any events on

or

CLR

during power-on reset are ignored. The power-on reset

circuit is triggered when V_DDpasses 2.6 V approximately and

takes 50 µs to complete. No writes to the AD5024/AD5044/

AD5064/AD5064-1 should take place during this time. For

applications which have a slow V_DDramp time (for example,

more than 2 ms to 3ms), it is recommended that a software

reset command is written when the power supplies have

reached their final value.

AMPLIFIER

V

DAC

OUT

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

POWER-DOWN MODES

Figure 51. Output Stage During Power-Down

The AD5024/AD5044/AD5064/AD5064-1 contain three

separate power-down modes. Command 0100 is designated for

the power-down function (see Table 8). These power-down

modes are software-programmable by setting two bits, Bit DB9

and Bit DB8, in the shift register. Table 12 shows how the state of

the bits corresponds to the mode of operation of the device.

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when the power-down

mode is activated. However, the contents of the DAC register

are unaffected when in power-down. The DAC register can be

updated while the device is in power-down mode. The time to

exit power-down is typically 4.5 µs for V_DD= 5 V (see Figure 30).

Table 12. Modes of Operation

DB9 DB8 Operating Mode

0

Normal operation

Power-down modes:

1 kΩ to GND

100 kΩ to GND

Three-state

0

1

0

1

Table 13. 32-Bit Shift Register Contents for Power-Up/Power-Down Function

MSB

LSB

DB31

to

DB19

to

DB7

to

DB28

DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB10

DB9 DB8 DB4

DB3

DB2

DB1

DB0

X

0

1

0

X

PD1

PD0

X

DAC D DAC C DAC B DAC A

Don’t

cares

Command bits (C3 to C0)

Address bits (A3 to A0)—

don’t cares

Don’t

cares

Power-

down mode cares

Don’t

Power-down/power-up channel

selection—set bit to 1 to select

Rev. F | Page 22 of 28

Data Sheet

AD5024/AD5044/AD5064

LDAC

Synchronous

: After new data is read, the DAC registers

CLEAR CODE REGISTER

are updated on the falling edge of the 32^ndSCLK pulse, provided

The AD5024/AD5044/AD5064/AD5064-1 have a hardware

LDAC

is held low.

CLR

pin that is an asynchronous clear input. The

input is

CLR

falling edge sensitive. Bringing the

line low clears the

LDAC

Asynchronous

: The outputs are not updated at the same

LDAC

contents of the input register and the DAC registers to the data

CLR

time that the input registers are written to. When

pulsed low, the DAC registers are updated with the contents of

the input registers.

is

contained in the user-configurable

register and sets the

analog outputs accordingly (see Table 14). This function can be

used in system calibration or reset to load zero scale, midscale,

or full scale to all channels together. Note that zero scale and full

scale are outside the linear region of the DAC. These clear code

values are user-programmable by setting two bits, Bit DB1 and

Bit DB0, in the shift register (see Table 14). The default setting

clears the outputs to 0 V. Command 0101 is designated for

loading the clear code register (see Table 8).

LDAC

Software

Alternatively, the outputs of all DACs can be updated simulta-

LDAC

Function

neously or individually using the software

writing to Input Register n and updating all DAC registers.

LDAC

function by

Command 0010 is reserved for this software

function.

Writing to the DAC using Command 0110 loads the 4-bit

LDAC

is 0; that is, the

register (DB3 to DB0). The default for each channel

Table 14. Clear Code Register

LDAC

pin works normally. Setting the bits to 1

DB1 (CR1)

DB0 (CR0)

Clears to Code

0x0000

0x8000

0xFFFF

No operation

updates the DAC channel regardless of the state of the hardware

pin, so that it effectively sees the hardware

being tied low (see Table 15 for the

operation.) This flexibility is useful in applications where the

user wants to simultaneously update select channels while the

remainder of the channels are synchronously updating.

0

1

0

1

0

1

LDAC

pin as

LDAC

register mode of

The part exits clear code mode on the 32^ndfalling edge of the

CLR

next write to the part. If hardware

write sequence, the write is aborted.

CLR

pin is activated during a

LDAC

Table 15.

Load

Overwrite Definition

Register

LDAC

CLR

pulse activation time, which is the falling edge of

The

to when the output starts to change, is typically 10.6 μs. See

Bits

LDAC

Operation

LDAC

1 or 0

X¹

(DB3 to DB0)

Table 16 for contents of the shift register while loading the clear

code register.

0

1

Determined by the LDAC pin.

DAC channels update, overrides

LDAC FUNCTION

the

LDAC as 0.

pin. DAC channels see

LDAC

Hardware

The outputs of all DACs can be updated simultaneously using

LDAC LDAC

¹X = don’t care.

LDAC

The

over the hardware

bits (DB0 to DB3) to 0 for a DAC channel means that this

LDAC

register gives the user extra flexibility and control

the hardware

permanently low or pulsed. There are two methods of using the

LDAC

pin, as shown in Figure 4.

can be

LDAC LDAC

pin (see Table 17). Setting the

hardware

pin, synchronously and asynchronously.

channel’s update is controlled by the hardware

pin.

Table 16. 32-Bit Shift Register Contents for Clear Code Function

MSB

LSB

DB31 to DB28

X

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19 to DB2

X

DB1

1/0

DB0

0

1

0

1

X

1/0

Don’t cares

Command bits (C3 to C0)

Address bits (A3 to A0)

Don’t cares

Clear code register

(CR1 to CR0)

LDAC

Table 17. 32-Bit Shift Register Contents for

Overwrite Function

MSB

LSB

DB31 to

DB28

DB19

DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 to DB4 DB3

DB2

DB1

DB0

X

0

1

0

X

DAC D

DAC C

DAC B

DAC A

Don’t

cares

Command bits (C3 to C0)

Address bits (A3 to A0)—

don’t cares

Don’t

cares

Setting LDAC bits to 1 overrides LDAC pin

Rev. F | Page 23 of 28

AD5024/AD5044/AD5064

Data Sheet

low effective series inductance (ESI), such as is typical of common

ceramic types of capacitors. This 0.1 µF capacitor provides a low

impedance path to ground for high frequencies caused by

transient currents due to internal logic switching.

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully

consider the power supply and ground return layout on the board.

The printed circuit board (PCB) containing the AD5024/AD5044/

AD5064/AD5064-1 should have separate analog and digital

sections. If the AD5024/AD5044/AD5064/AD5064-1 are in a

system where other devices require an AGND-to-DGND

connection, the connection should be made at one point only.

This ground point should be as close as possible to the

AD5024/AD5044/AD5064/AD5064-1.

The power supply line should have as large a trace as possible to

provide a low impedance path and reduce glitch effects on the

supply line. Clocks and other fast switching digital signals should

be shielded from other parts of the board by digital ground. Avoid

crossover of digital and analog signals, if possible. When traces

cross on opposite sides of the board, ensure that they run at right

angles to each other to reduce feedthrough effects through the

board. The best board layout technique is the microstrip tech-

nique, where the component side of the board is dedicated to the

ground plane only and the signal traces are placed on the solder

side. However, this is not always possible with a 2-layer board.

The power supply to the AD5024/AD5044/AD5064/AD5064-1

should be bypassed with 10 µF and 0.1 µF capacitors. The capaci-

tors should be as physically close as possible to the device, with

the 0.1 µF capacitor ideally right up against the device. The 10 µF

capacitors are the tantalum bead type. It is important that the

0.1 µF capacitor have low effective series resistance (ESR) and

Rev. F | Page 24 of 28

Data Sheet

AD5024/AD5044/AD5064

AD5024/AD5044/AD5064/AD5064-1 to 80C51/80L51

Interface

MICROPROCESSOR INTERFACING

AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-

BF53x Interface

Figure 54 shows a serial interface between the AD5024/AD5044/

AD5064/AD5064-1 and the 80C51/80L51 microcontroller. The

setup for the interface is as follows: TxD of the 80C51/80L51

drives SCLK of the AD5024/AD5044/AD5064/AD5064-1, and

Figure 52 shows a serial interface between the AD5024/AD5044/

AD5064/AD5064-1 and the Blackfin® ADSP-BF53x microproces-

sor. The ADSP-BF53x processor family incorporates two dual-

channel synchronous serial ports, SPORT1 and SPORT0, for

serial and multiprocessor communications. Using SPORT0 to

connect to the AD5024/AD5044/AD5064/AD5064-1, the setup

for the interface is as follows: DT0PRI drives the DIN pin of the

AD5024/AD5044/AD5064/AD5064-1, and TSCLK0 drives the

SYNC

RxD drives the serial data line of the part. The

signal is

again derived from a bit-programmable pin on the port. In this

case, Port Line P3.3 is used. When data is to be transmitted to the

AD5024/AD5044/AD5064/AD5064-1, P3.3 is taken low. The

80C51/80L51 transmit data in 8-bit bytes only; thus, only eight

falling clock edges occur in the transmit cycle. To load data to

the DAC, P3.3 is left low after the first eight bits are transmitted,

and a second write cycle is initiated to transmit the second byte of

data. P3.3 is taken high following the completion of this cycle.

The 80C51/80L51 output the serial data in a format that has the

LSB first. The AD5024/AD5044/AD5064/AD5064-1 must

receive data with the MSB first. The 80C51/80L51 transmit

routine should take this into account.

SYNC

SCLK of the parts. The

pin is driven from TFS0.

ADSP-BF53x*

AD5024/

AD5044/

AD5064/

AD5064-1

*

TFS0

SYNC

DT0PRI

DIN

TSCLK0

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

80C51/80L51*

AD5024/

AD5044/

AD5064/

Figure 52. AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-BF53x

Interface

AD5064-1

*

P3.3

TxD

RxD

SYNC

AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11

Interface

SCLK

DIN

Figure 53 shows a serial interface between the AD5024/AD5044/

AD5064/AD5064-1 and the 68HC11/68L11 microcontroller.

SCK of the 68HC11/68L11 drives the SCLK of the AD5024/

AD5044/AD5064/AD5064-1, and the MOSI output drives the

serial data line of the DAC.

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 54. AD5024/AD5044/AD5064/AD5064-1 to 80C512/80L51 Interface

AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE

Interface

68HC11/68L11*

AD5024/

AD5044/

AD5064/

Figure 55 shows an interface between the AD5024/AD5044/

AD5064/AD5064-1 and any MICROWIRE-compatible device.

Serial data is shifted out on the falling edge of the serial clock and is

clocked into the AD5024/AD5044/AD5064/AD5064-1 on the

rising edge of the SCLK.

AD5064-1

*

PC7

SCK

SYNC

SCLK

DIN

MOSI

MICROWIRE*

AD5024/

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5044/

AD5064/

Figure 53. AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface

AD5064-1

*

CS

SK

SO

SYNC

The

signal is derived from a port line (PC7). The setup

DIN

conditions for correct operation of this interface are as follows:

The 68HC11/68L11 is configured with its CPOL bit as 0, and its

CPHA bit as 1. When data is being transmitted to the DAC, the

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

SYNC

line is taken low (PC7). When the 68HC11/68L11 is

Figure 55. AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE Interface

configured as described previously, data appearing on the MOSI

output is valid on the falling edge of SCK. Serial data from the

68HC11/68L11 is transmitted in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. To load data to the AD5024/AD5044/

AD5064, PC7 is left low after the first eight bits are transferred,

and a second serial write operation is performed to the DAC.

PC7 is taken high at the end of this procedure.

Rev. F | Page 25 of 28

AD5024/AD5044/AD5064

Data Sheet

APPLICATIONS INFORMATION

This is an output voltage range of 5 V, with 0x0000 corre-

sponding to a −5 V output, and 0xFFFF corresponding to a

USING A REFERENCE AS A POWER SUPPLY

Because the supply current required by the AD5024/AD5044/

AD5064/AD5064-1 is extremely low, an alternative option is to

use a voltage reference to supply the required voltage to the parts

(see Figure 56). This is especially useful if the power supply is

quite noisy or if the system supply voltages are at some value

other than 5 V (for example, 15 V). The voltage reference outputs

a steady supply voltage for the AD5024/AD5044/AD5064/

AD5064-1. If the low dropout REF195 is used, it must supply

3 mA of current to the AD5024/AD5044/AD5064/AD5064-1,

with no load on the output of the DAC. When the DAC output is

loaded, the REF195 also needs to supply the current to the load.

The total current required (with a 5 kΩ load on the DAC output) is

+5 V output.

R2 = 10kΩ

+5V

R1 = 10kΩ

AD8638/

AD8639

5V

±5V

V

REF

REFA

V

DD

OUTA

0.1µF

10µF

AD5024/

AD5044/

AD5064/

AD5064-1

–5V

3-WIRE

SERIAL INTERFACE

3 mA + (5 V/5 kΩ) = 4 mA

Figure 57. Bipolar Operation

The load regulation of the REF195 is typically 2 ppm/mA,

which results in a 3 ppm (15 µV) error for the 4 mA current

drawn from it. This corresponds to a 0.196 LSB error.

15V

USING THE AD5024/AD5044/AD5064/AD5064-1

WITH A GALVANICALLY ISOLATED INTERFACE

In process control applications in industrial environments, it

is often necessary to use a galvanically isolated interface to

protect and isolate the controlling circuitry from any hazardous

common-mode voltages that can occur in the area where the

DAC is functioning. iCoupler® provides isolation in excess of

2.5 kV. The AD5024/AD5044/AD5064/AD5064-1 use a 3-wire

serial logic interface, so the ADuM1300 three-channel digital

isolator provides the required isolation (see Figure 58). The

power supply to the part also needs to be isolated, which is done

by using a transformer. On the DAC side of the transformer, a

5 V regulator provides the 5 V supply required for the AD5024/

AD5044/AD5064/AD5064-1.

5V

REF195

V

DD

SYNC

SCLK

DIN

AD5024/

AD5044/

AD5064/

AD5064-1

3-WIRE

SERIAL

INTERFACE

V

= 0V TO 5V

OUT

Figure 56. REF195 as Power Supply to the AD5024/AD5044/AD5064/AD5064-1

BIPOLAR OPERATION

The AD5024/AD5044/AD5064/AD5064-1 have been designed

for single-supply operation, but a bipolar output range is also

possible using the circuit shown in Figure 57. The circuit gives an

output voltage range of 5 V. R a i l-to-rail operation at the

amplifier output is achievable using an AD8638 or an AD8639

as the output amplifier.

5V

REGULATOR

10µF

0.1µF

POWER

V

DD

SCLK

V

SCLK

Assuming V_DD= V_REF, the output voltage for any input code can

be calculated as follows:

IA

OA

AD5024/

AD5044/

AD5064/

AD5064-1

ADuM1300

V









D

65,536

R1 + R2

R1

R2

R1

































SDI

V

x

SYNC

DIN

IB

OUT

OB

V_OUT= V_DD

×

−V

×

DD









where D represents the input code in decimal (0 to 65,535).

V

DATA

OC

IC

GND

With V_DD= 5 V, R1 = R2 = 10 kΩ,

10× D









V_OUT

=

− 5 V

65,536

Figure 58. AD5024/AD5044/AD5064/AD5064-1 with a Galvanically Isolated

Interface





Rev. F | Page 26 of 28

Data Sheet

AD5024/AD5044/AD5064

OUTLINE DIMENSIONS

5.10

5.00

4.90

14

8

7

4.50

4.40

4.30

6.40

BSC

1

PIN 1

0.65 BSC

1.05

1.00

0.80

1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

0.15

0.05

COPLANARITY

0.10

SEATING

PLANE

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 59. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 60. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Rev. F | Page 27 of 28

AD5024/AD5044/AD5064

Data Sheet

ORDERING GUIDE

Model¹

Temperature Range

Accuracy

4 LSB INL

1 LSB INL

0.5 LSB INL

Resolution Package Description

Package Option

RU-14

AD5064ARUZ-1

AD5064ARUZ-1REEL7

AD5064BRUZ-1

AD5064BRUZ-1REEL7

AD5064BRUZ

AD5064BRUZ-REEL7

AD5044BRUZ

AD5044BRUZ-REEL7

AD5024BRUZ

−40°C to +125°C

16 Bits

14 Bits

12 Bits

14-lead TSSOP

16-Lead TSSOP

RU-16

16-Lead TSSOP

RU-16

16-Lead TSSOP

RU-16

AD5024BRUZ-REEL7

EVAL-AD5064-1EBZ

EVAL-AD5064EBZ

14-Lead TSSOP Evaluation Board

16-Lead TSSOP Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D06803-0-6/13(F)

Rev. F | Page 28 of 28


型号：	AD5064BRUZ-1REEL7
厂家：	ADI
描述：	Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP 完全准确， 12位/ 14位/ 16位VOUT属于nanoDAC ，四， SPI接口， 4.5 V至5.5 V的TSSOP 转换器数模转换器光电二极管 PC
文件：	总28页 (文件大小：2828K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5064BRUZ-1REEL7 [ADI]

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