AD5065BRUZ-REEL7 [ADI]
Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP; 完全准确， 12位/ 14位/ 16位，双通道， VOUT属于nanoDAC SPI接口， 4.5 V至5.5 V采用TSSOP
| 型号： | AD5065BRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP |
| 文件： | 总28页 (文件大小：1163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fully Accurate, 12-/14-/16-Bit, Dual, VOUT
nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
AD5025/AD5045/AD5065
ence buffer is provided on chip. The AD5025/AD5045/AD5065
incorporate a power-on reset circuit that ensures the DAC output
FEATURES
Low power dual 12-/14-/16-bit DAC, 1 LSB INL
Individual voltage reference pins
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
Power down to 400 nA @ 5 V
3 power-down functions
Per channel power-down
Low glitch upon power-up
Hardware power-down lockout capability
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
powers up zero scale or midscale and remains there until a valid
write takes place to the device. The AD5025/AD5045/AD5065
contain a power-down feature that reduces the current consump-
tion of the device to typically 400 nA at 5 V and provides software
selectable output loads while in power-down mode. The parts are
put into power-down mode over the serial interface. Total unad-
justed error for the parts is <2.5 mV. The parts exhibit very low
glitch on power-up. The outputs of all DACs can be updated
LDAC
simultaneously using the
functionality of user-selectable DAC channels to simultaneously
CLR
function, with the added
update. There is also an asynchronous
to a software-selectable code—0 V, midscale, or full scale. The
PDL
that clears all DACs
parts also feature a power-down lockout pin,
, which can be
14-lead TSSOP
used to prevent the DAC from entering power-down under any
circumstances over the serial interface.
APPLICATIONS
Process controls
Data acquisition systems
PRODUCT HIGHLIGHTS
1. Dual channel available in a 14-lead TSSOP package with
individual voltage reference pins.
2. 12-/14-/16-bit accurate, 1 LSB INL.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 50 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (zero scale or midscale).
7. Power-down lockout capability.
GENERAL DESCRIPTION
The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit
buffered voltage output nanoDAC® DACs offering relative accuracy
specifications of 1 LSB INL with individual reference pins, and
can operate from a single 4.5 V to 5.5 V supply. The AD5025/
AD5045/AD5065 also offer a differential accuracy specification of
1 LSB. The parts use a versatile 3-wire, low power Schmitt
trigger serial interface that operates at clock rates up to 50 MHz
and is compatible with standard SPI®, QSPI™, MICROWIRE™,
and DSP interface standards. The reference for the AD5025/
AD5045/AD5065 are supplied from an external pin and a refer-
Table 1. Related Devices
Part No.
Description
AD5666
Quad,16-bit buffered DAC, 16 LSB INL, TSSOP
Quad 16-bit nanoDAC, 1 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL, MSOP
16-bit nanoDAC, 4 LSB INL, SOT-23
14-/16-bit nanoDAC, 1 LSB INL, SOT-23
AD5024/AD5044/AD5064
AD5062/AD5063
AD5061
AD5040/AD5060
FUNCTIONAL BLOCK DIAGRAM
V
V
A V
B
POR
DD
REF
REF
LDAC
BUFFER
DAC
INPUT
SCLK
V
V
A
B
DAC A
DAC B
OUT
OUT
REGISTER
REGISTER
SYNC
INTERFACE
LOGIC
DIN
BUFFER
DAC
REGISTER
INPUT
REGISTER
LDAC
POWER-DOWN
LOGIC
SDO
AD5025/AD5045/AD5065
GND
PDL CLR
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD5025/AD5045/AD5065
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Register.............................................................................. 17
Standalone Mode........................................................................ 19
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 17
Digital-to-Analog Converter .................................................... 17
DAC Architecture....................................................................... 17
Reference Buffer ......................................................................... 17
Output Amplifier........................................................................ 17
Serial Interface ............................................................................ 17
Interrupt .......................................................................... 19
SYNC
Daisy-Chaining........................................................................... 19
Power-On Reset and Software Reset ....................................... 20
Power-Down Modes .................................................................. 20
Clear Code Register ................................................................... 21
Function........................................................................... 21
LDAC
Power-Down Lockout................................................................ 22
Power Supply Bypassing and Grounding................................ 22
Microprocessor Interfacing....................................................... 23
Applications Information.............................................................. 24
Using a Reference as a Power Supply for the
AD5025/AD5045/AD5065 ....................................................... 24
Bipolar Operation Using the AD5025/AD5045/AD5065..... 24
Using the AD5025/AD5045/AD5065 with a
Galvanically Isolated Interface ................................................. 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5025/AD5045/AD5065
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to
MAX, unless otherwise noted.
T
Table 2.
B Grade1
Typ
A Grade1, 2
Typ
Parameter
STATIC PERFORMANCE3
Resolution
Min
Max
Min
Max
Unit
Conditions/Comments
AD5065
AD5045
AD5025
16
14
12
16
Bits
Relative Accuracy
AD5065
AD5065
AD5045
AD5045
AD5025
AD5025
Differential Nonlinearity
Total Unadjusted Error
Offset Error
0.4
+0.4
0.1
1
2
0.5
1
0.25
0.5
1
2.5
1.8
0.5
0.5
4
4
LSB
LSB
LSB
TA = −40°C to +105°C
TA = −40°C to +125°C
TA = −40°C to +105°C
TA = −40°C to +125°C
TA = −40°C to +105°C
TA = −40°C to +125°C
0.1
0.05
0.05
0.2
0.2
0.2
0.2
0.2
0.2
1
2.5
1.8
LSB
mV
mV
VREF = 2.5 V; VDD = 5.5 V
Code 512 (AD5065), Code 128 (AD5045),
Code 32 (AD5025) loaded to DAC register
Offset Error Drift4
Full-Scale Error
2
2
μV/°C
0.01
0.005
1
0.07
0.05
0.01
0.005
1
0.07 % FSR
0.05 % FSR
ppm
All 1s loaded to DAC register, VREF < VDD
Gain Error
Gain Temperature Coefficient4
DC Crosstalk4
Of FSR/°C
Due to single channel full-scale output
change, RL = 5 kΩ to GND or VDD
40
40
μV
40
40
40
40
μV/mA Due to load current change
μV
Due to powering down (per channel)
OUTPUT CHARACTERISTICS4
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Normal Mode
0
VDD
1
0
VDD
1
V
nF
RL = 5 kΩ, RL = 100 kΩ, and RL = ∞
0.5
0.5
Ω
Power-Down Mode
Output Connected to
100 kΩ Network
Output Connected to
1 kΩ Network
100
1
100
1
kΩ
kΩ
Output impedance tolerance 400 Ω
Output impedance tolerance 20 Ω
Short-Circuit Current
60
45
4.5
60
45
4.5
mA
mA
μs
DAC = full scale, output shorted to GND
DAC = zero-scale, output shorted to VDD
Time to exit power-down mode to
normal mode of AD5024/AD5044/
AD5064, 32nd clock edge to 90% of DAC
midscale value, output unloaded
Power-Up Time
DC PSRR
−92
−92
dB
VDD 10%, DAC = full scale, VREF < VDD
REFERENCE INPUTS
Reference Input Range
Reference Current
Reference Input Impedance
2.2
VDD
50
2.2
VDD
50
V
μA
kΩ
35
120
35
120
Per DAC channel
Rev. 0 | Page 3 of 28
AD5025/AD5045/AD5065
B Grade1
Typ
A Grade1, 2
Typ
Parameter
Min
Max
Min
Max
Unit
Conditions/Comments
LOGIC INPUTS
Input Current5
1
0.8
1
0.8
μA
V
V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance4
2.2
2.2
4
4
pF
LOGIC OUTPUTS (SDO)3, 4
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage
Current4
0.4
1
0.4
1
V
ISINK = 2 mA
ISOURCE = 2 mA
VDD − 1
VDD − 1
0.002
7
0.002
7
ꢀA
pF
High Impedance Output
Capacitance
POWER REQUIREMENTS
VDD
IDD
4.5
5.5
4.5
5.5
V
6
DAC active, excludes load current
VIH = VDD and VIL = GND
TA = −40°C to +105°C
Normal Mode
All Power-Down Modes7
2.2
0.4
2.7
2
30
2.2
0.4
2.7
2
30
mA
μA
μA
TA = −40°C to +125°C
1 Temperature range is −40°C to +125°C, typical at 25°C.
2 A grade offered in AD5065 only.
3 Linearity calculated using a reduced code range—AD5065: Code 512 to Code 65,024; AD5045: Code 128 to Code 16,256; AD5025: Code 32 to Code 4064. Output
unloaded.
4 Guaranteed by design and characterization; not production tested.
5 Current flowing into or out of individual digital pins.
6 Interface inactive. All DACs active. DAC outputs unloaded.
7 Both DACs powered down.
AC CHARACTERISTICS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
Min
Typ Max Unit
Conditions/Comments2
Output Voltage Settling Time
5.8
8
μs
¼ to ¾ scale settling to 1 LSB, RL = 5 kΩ single-channel update
including DAC calibration sequence
Output Voltage Settling Time
10.7 13
μs
¼ to ¾ scale settling to 1 LSB, RL = 5 kΩ all channel update including
DAC calibration sequence
Slew Rate
1.5
4
V/μs
nV-sec
dB
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kHz
Digital-to-Analog Glitch Impulse3
Reference Feedthrough3
SDO Feedthrough
1 LSB change around major carry
VREF = 3 V 0.86 V p-p, frequency = 100 Hz to 100 kHz
Daisy-chain mode; SDO load is 10 pF
−90
0.07
0.1
1.9
1.2
2.1
340
−80
64
Digital Feedthrough3
Digital Crosstalk3
Analog Crosstalk3
DAC-to-DAC Crosstalk3
Multiplying Bandwidth3
Total Harmonic Distortion3
Output Noise Spectral Density
VREF = 3 V 0.86 V p-p
VREF = 3 V 0.86 V p-p, frequency = 10 kHz
dB
nV/√Hz DAC code = 0x8400, 1 kHz
nV/√Hz DAC code = 0x8400, 10 kHz
60
Output Noise
6
ꢀV p-p
0.1 Hz to 10 Hz
1 Guaranteed by design and characterization; not production tested.
2 Temperature range is −40°C to + 125°C, typical at 25°C.
3 See the Terminology section.
Rev. 0 | Page 4 of 28
AD5025/AD5045/AD5065
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 4. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Symbol
Min
20
10
10
16.5
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns
ns
ns
ns
ns
μs
ns
ns
ns
μs
μs
ns
1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
Data Hold Time
5
0
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single Channel Update)
Minimum SYNC High Time (All Channel Update)
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
30
t8
2
t8
4
t9
17
20
20
10
10
10.6
t10
t11
t12
t13
t14
SCLK Falling Edge to LDAC Rising Edge
CLR Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time
2, 3
SCLK Rising Edge to SDO Valid
SCLK Falling Edge to SYNC Rising Edge
SYNC Rising Edge to SCLK Rising Edge
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update)
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update)
PDL Minimum Pulse Width
t15
22
30
2
t16
5
2
t17
8
2
t18
2
2
t18
4
t19
20
1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2 Daisy-chain mode only.
3 Measured with the load circuit of Figure 2. t15 determines the maximum SCLK frequency in daisy-chain mode.
Circuit and Timing Diagrams
2mA
I
OL
V
(MIN) + V (MAX)
OL
TO OUTPUT
PIN
OH
2
C
L
50pF
2mA
I
OH
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. 0 | Page 5 of 28
AD5025/AD5045/AD5065
t1
t9
SCLK
t2
t8
t7
t3
t4
S YNC
t6
t5
DIN
1
DB31
DB0
t13
t10
LDAC
t11
2
LDAC
CLR
t12
t14
V
OUT
t19
PDL
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 3. Serial Write Operation
SCLK
32
64
t17
t8
t4
t16
SYNC
DIN
t5
t6
DB0
DB31
DB0
DB31
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t15
DB31
DB0
SDO
UNDEFINED
t18
t18
t18
t10
t12
t19
1
LDAC
CLR
PDL
1
IF IN DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY.
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 6 of 28
AD5025/AD5045/AD5065
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUTA or VOUTB to GND
VREFA or VREFB to GND
Operating Temperature Range, Industrial
Storage Temperature Range
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
ESD CAUTION
Junction Temperature (TJ MAX
)
Power Dissipation
θJA Thermal Impedance
(TJ MAX − TA)/θJA
150.4°C/W
Reflow Soldering Peak Temperature
SnPb
Pb-Free
240°C
260°C
Rev. 0 | Page 7 of 28
AD5025/AD5045/AD5065
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC
1
2
3
4
5
6
7
14
SCLK
13 DIN
SYNC
AD5025/
AD5045/
AD5065
TOP VIEW
(Not to Scale)
V
12
11
10
9
PDL
DD
V
A
A
GND
REF
OUT
V
V
V
B
OUT
POR
SDO
B
REF
8
CLR
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows all DAC outputs to simultaneously update. This pin can be tied permanently low in standalone
mode. When daisy-chain mode is enabled, this pin cannot be tied permanently low. The LDAC pin should
be used in asynchronous LDAC update mode, as shown in Figure 3, and the LDAC pin must be brought
high after pulsing. This allows all DAC outputs to simultaneously update.
2
3
SYNC
VDD
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4
5
6
VREF
VOUT
POR
A
A
DAC A Reference Input. This is the reference voltage input pin for DAC A.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Power-On Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up
the part to midscale.
7
8
SDO
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading
back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising
edge of SCLK and is valid on the falling edge of the clock.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
DAC B Reference Input. This is the reference voltage input pin for DAC B.
CLR
9
VREFB
10
11
12
VOUT
GND
PDL
B
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
The PDL pin is used to ensure hardware shutdown lockout of the device under any circumstance. A
Logic 1 at the PLO pin causes the device to behave as normal. The user may successfully enter
software power-down over the serial interface while Logic 1 is applied to the PDL pin.
If a Logic 0 is applied to this pin, it ensures that the device cannot enter software power-down under
any circumstances. If the device had previously been placed in software power-down mode, a high-to-
low transition at the PDL pin causes the DAC(s) to exit power-down and output a voltage corresponding to
the previous code in the DAC register before the device entered software power-down.
13
14
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.
SCLK
Rev. 0 | Page 8 of 28
AD5025/AD5045/AD5065
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.2
0
0.4
0.2
0
–0.2
–0.4
–0.2
–0.4
–0.6
–0.8
–1.0
–0.6
–0.8
–1.0
512
16,640
32,768
48,896
65,024
512
16,640
32,768
48,896
65,024
DAC CODE
DAC CODE
Figure 9. AD5065 DNL
Figure 6. AD5065 INL
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4096
8192
12,288
16,384
0
512
1024
1536
2048
2560
3072
3584
4096
DAC CODE
DAC CODE
Figure 7. AD5045 INL
Figure 10. AD5045 DNL
1.0
0.8
1.00
0.75
0.50
0.25
0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.25
–0.50
–0.75
–1.00
0
512
1024
1536
2048
2560
3072
3584
4096
0
4096
8192
12,288
16,384
DAC CODE
DAC CODE
Figure 8. AD5025 INL
Figure 11. AD5025 DNL
Rev. 0 | Page 9 of 28
AD5025/AD5045/AD5065
0.20
1.2
1.0
T
= 25°C
A
0.15
0.8
0.10
0.05
0.6
0.4
MAX TUE ERROR @ V
= 5.5V
DD
0.2
0
0
MIN TUE ERROR @ V = 5.5V
DD
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–0.05
–0.10
–0.15
–0.20
512
16,640
32,768
48,896
65,024
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
DAC CODE
REFERENCE VOLTAGE (V)
Figure 12. Total Unadjusted Error (TUE) vs. DAC Code
Figure 15. Total Unadjusted Error (TUE) vs. Reference Input Voltage
1.6
1.4
0.015
T
= 25°C
A
1.2
0.010
1.0
DAC A
0.8
0.6
MAX INL ERROR @ V = 5.5V
DD
0.005
0.4
0.2
0
0
DAC B
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
MIN INL ERROR @ V
= 5.5V
DD
–0.005
–0.010
V
V
= 5.5V
DD
= 4.096V
REF
–0.015
120
–60 –40 –20
0
20
40
60
80
100
140
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
Figure 13. INL vs. Reference Input Voltage
Figure 16. Gain Error vs. Temperature
0.6
0.5
1.6
1.4
V
V
= 5.5V
DD
T
= 25°C
A
= 4.096V
REF
1.2
0.4
0.3
0.2
0.1
0
1.0
0.8
0.6
0.4
MAX DNL ERROR @ V
= 5.5V
DD
0.2
DAC B
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
MIN DNL ERROR @ V = 5.5V
DD
–0.1
–0.2
DAC A
–0.3
–0.4
–60 –40 –20
0
20
40
60
80
100 120 140
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (ºC)
REFERENCE VOLTAGE (V)
Figure 17. Offset Error vs. Temperature
Figure 14. DNL vs. Reference Input Voltage
Rev. 0 | Page 10 of 28
AD5025/AD5045/AD5065
0.2
0.1
5.0
4.5
4.0
3.5
3.0
2.5
V
T
= 5V, V = 4.096V
REF
DD
= 25ºC
GAIN ERROR
A
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
OUTPUT LOADED WITH 5kΩ
AND 200pF TO GND
0
2.0
1.5
1.0
0.5
0
FULL-SCALE ERROR
–0.1
–0.2
0
2
4
6
8
10
12
14
4.50
4.75
5.00
(V)
5.25
5.50
V
TIME (µs)
DD
Figure 21. Settling Time and Typical Output Slew Rate
Figure 18. Gain Error and Full-Scale Error vs. Supply Voltage
0.12
POR
0.09
0.06
0.03
0
1
3
V
OUT
4.50
4.75
5.00
(V)
5.25
5.50
CH1 2V
CH3 2V
M2ms
20.4%
A CH1
2.52V
T
V
DD
Figure 19. Offset Error Voltage vs. Supply Voltage
Figure 22. Power-On Reset to 0 V
16
14
12
10
8
1
3
6
4
2
0
CH1 2V
CH3 2V
M2ms
20.4%
A CH1
2.52V
0
1.0
1.1
1.2
1.3
1.4
1.5
T
I
POWER UP (mA)
DD
Figure 23. Power-On Reset to Midscale
Figure 20. IDD Histogram, VDD = 5.0 V
Rev. 0 | Page 11 of 28
AD5025/AD5045/AD5065
7
6
CH1 = SCLK
V
A
= 5V, V = 4.096V
REF
DD
= 25°C
T
5
1
4
3
2
1
CH2 = V
V
= 5V
OUT
DD
POWER-UP TO MIDSCALE
0
–1
–2
–3
–4
2
CH1 5V
CH2 500mV
M2µs
55%
A CH2
1.2V
0
2.5
5.0
7.5
10.0
T
TIME (μs)
Figure 27. DAC-to-DAC Crosstalk
Figure 24. Exiting Power-Down to Midscale
6
5
V
= 5V, V = 4.096V
REF
DD
= 25ºC
T
A
DAC LOADED WITH MIDSCALE
4
3
2
1
0
–1
–2
–3
0
2.5
5.0
7.5
10.0
4s/DIV
TIME (μs)
Figure 28. 0.1 Hz to 10 Hz Output Noise Plot
Figure 25. Digital-to-Analog Glitch Impulse
7
6
0
V
T
= 5V, V = 4.096V
REF
V
T
= 5V,
DD
= 25ºC
DD
= 25ºC
–10
–20
–30
–40
–50
–60
–70
–80
A
A
DAC LOADED WITH MIDSCALE
V
5
= 3.0V ± 200mV p-p
REF
4
3
2
1
0
–1
–2
–3
–4
–90
–100
0
2.5
5.0
7.5
10.0
5
10
20
30
FREQUENCY (kHz)
40
50
55
TIME (μs)
Figure 26. Analog Crosstalk
Figure 29. Total Harmonic Distortion
Rev. 0 | Page 12 of 28
AD5025/AD5045/AD5065
0.0010
0.0008
0.0006
0.0004
0.0002
0
24
22
20
18
16
14
12
10
8
V
T
= 5V, V = 3.0V
REF
CODE = MIDSCALE
= 5V, V = 4.096V
DD
= 25°C
V
DD
REF
A
–0.0002
–0.0004
–0.0006
–0.0008
V
= 5.5V
DD
6
4
0
1
2
3
4
5
6
7
8
9
10
–25 –20 –15 –10 –5
0
5
10
15
20
25
30
CAPACITANCE (nF)
CURRENT (mA)
Figure 30. Settling Time vs. Capacitive Load
Figure 33. Typical Output Load Regulation
0.10
0.08
0.06
0.04
0.02
0
CODE = MIDSCALE
V
= 5V, V = 4.096V
DD
REF
CLR
1
V
OUT
2
–0.02
–0.04
–0.06
–0.08
–0.10
CH1 5V
CH2 2V
M2µs
A CH1
2.5V
–25 –20 –15 –10 –5
0
5
10
15
20
25
30
T 11%
I
(mA)
OUT
Figure 34. Typical Current Limiting Plot
CLR
Figure 31. Hardware
10
0
CH1 295mV p-p
V
OUT
–10
–20
–30
–40
–50
CH A
CH B
CH C
CH D
3dB POINT
SCLK
–60
10
100
1000
10000
CH1 50mV CH2 5V
M4µs
A CH2
1.2V
T 8.6%
FREQUENCY (kHz)
Figure 32. Multiplying Bandwidth
Figure 35. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
No Load
Rev. 0 | Page 13 of 28
AD5025/AD5045/AD5065
CH1 170mV p-p
CH1 200mV p-p
V
OUT
V
OUT
SCLK
SCLK
CH1 50mV CH2 5V
M4µs
A CH2
1.2V
CH1 20mV CH2 5V
M4µs
A CH2
1.2V
T 8.6%
T 8.6%
Figure 36. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
5 kΩ/200 pF Load
Figure 38. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,
5 kΩ/200 pF Load
1
CH1 129mV p-p
V
OUT
PDL
VOUT
2
SCLK
CH1 20mV CH2 5V
M4µs
A CH2
1.2V
CH1 5.00V CH2 1V
M1µs
A CH1
2.5V
T 8.6%
Figure 37. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No
Load
PDL
Figure 39.
Activation Time
Rev. 0 | Page 14 of 28
AD5025/AD5045/AD5065
TERMINOLOGY
Relative Accuracy
Digital-to-Analog Glitch Impulse
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer
function. Figure 6, Figure 7, and Figure 8 show plots of typical
INL vs. code.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nanovolt-
seconds and is measured when the digital input code is changed
by 1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 25.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Figure 9, Figure 10, and Figure 11 show plots of
typical DNL vs. code.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2.5 V, and VDD is varied 10%.
Measured with VREF < VDD
.
Offset Error
DC Crosstalk
Offset error is a measure of the difference between the actual
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
V
OUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
part with Code 512 (AD5065), Code 128 (AD5045), and Code 32
(AD5025) loaded into the DAC register. It can be negative or
positive and is expressed in millivolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Offset Error Drift
Offset error drift is a measure of the change in offset error with
a change in temperature. It is expressed in microvolts per degree
Celsius.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
LDAC
is not being updated (that is,
decibels.
is high). It is expressed in
Digital Feedthrough
Gain Temperature Coefficient
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in parts per million of
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to
full-scale range per degree Celsius. Measured with VREF < VDD
.
SYNC
(
held high). It is specified in nanovolt-seconds. It is
measured with one simultaneous data and clock pulse loaded
to the DAC.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nanovolt-seconds.
Rev. 0 | Page 15 of 28
AD5025/AD5045/AD5065
Analog Crosstalk
Multiplying Bandwidth
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
LDAC
code change (all 0s to all 1s or vice versa) while keeping
LDAC
high, and then pulsing
low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nanovolt-seconds.
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nanovolt-seconds.
Rev. 0 | Page 16 of 28
AD5025/AD5045/AD5065
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
OUTPUT AMPLIFIER
The AD5025/AD5045/AD5065 are single 12-/14-/16-bit, serial
input, voltage output DACs. The parts operate from supply voltages
of 4.5 V to 5.5 V. Data is written to the AD5025/AD5045/AD5065
in a 32-bit word format via a 3-wire serial interface. The AD5025/
AD5045/AD5065 incorporate a power-on reset circuit that ensures
the DAC output powers up to a known output state. The devices
also have a software power-down mode that reduces the typical
current consumption to typically 400 nA.
The on-chip output buffer amplifier can generate rail-to-rail
voltages on its output, which gives an output range of 0 V to
VDD. The amplifier is capable of driving a load of 5 kΩ in
parallel with 200 pF to GND. The slew rate is 1.5 V/μs with a ¼
to ¾ scale settling time of 13 μs.
SERIAL INTERFACE
The AD5025/AD5045/AD5065 have a 3-wire serial interface
SYNC
(
, SCLK, and DIN) that is compatible with SPI, QSPI, and
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
MICROWIRE interface standards as well as most DSPs. See
Figure 3 for a timing diagram of a typical write sequence.
D
INPUT REGISTER
VOUT VREFIN
2N
The AD5025/AD5045/AD5065 input register is 32 bits wide
(see Figure 41). The first four bits are don’t cares. The next four
bits are the command bits, C3 to C0 (see Table 8), followed by
the 4-bit DAC address bits, A3 to A0 (see Table 7) and finally
the data bits. These data bits comprise the 12-bit, 14-bit, or 16-bit
input code, followed by eight, six, or four don’t care bits for the
AD5025/AD5045/AD5065, respectively (see Figure 41, Figure 42,
and Figure 43). These data bits are transferred to the DAC
register on the 32nd falling edge of SCLK.
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535 for the 16-bit AD5065).
N is the DAC resolution.
DAC ARCHITECTURE
The DAC architecture of the AD5025/AD5045/AD5065 consists
of two matched DAC sections. A simplified circuit diagram is
shown in Figure 40. The four MSBs of the 16-bit data-word are
decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either GND or a VREF
buffer output. The remaining 12 bits of the data-word drive
Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder
network.
Table 7. Address Commands
Address (n)
Selected DAC
Channel
A3
0
A2
0
A1
0
A0
0
DAC A
0
0
1
1
DAC B
V
OUT
0
0
1
0
0
1
0
1
1
1
0
1
Reserved
Reserved
Both DACs
2R
2R
S1
2R
2R
E1
2R
E2
2R
2R
S0
E15
S11
V
REF
Table 8. Command Definitions
Command
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
0
1
0
1
0
Write to Input Register n1
Figure 40. DAC Ladder Structure
Update DAC Register n1
REFERENCE BUFFER
Write to Input Register n, update all
(software LDAC)
Write to and update DAC Channel n1
Power down/power up DAC
Load clear code register
Load LDAC register
The AD5025/AD5045/AD5065 operate with an external reference.
Each DAC has a dedicated voltage reference pin and an on-chip
reference buffer. The reference input pin has an input range of
2.5 V to VDD. This input voltage is then used to provide a
buffered reference for the DAC core.
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
Reset (power-on reset)
Set up DCEN register (daisy-chain enable)
Reserved
Reserved
1 See Table 7.
Rev. 0 | Page 17 of 28
AD5025/AD5045/AD5065
DB31 (MSB)
DB0 (LSB)
X
X
X
X
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 41. AD5065 Input Register Content
DB31 (MSB)
DB0 (LSB)
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 42. AD5045 Input Register Content
DB31 (MSB)
DB0 (LSB)
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 43. AD5025 Input Register Content
Rev. 0 | Page 18 of 28
AD5025/AD5045/AD5065
Table 9 shows how the state of the bit corresponds to the mode
of operation of the device.
STANDALONE MODE
SYNC
The write sequence begins by bringing the
line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5025/AD5045/AD5065 compatible
with high speed DSPs. On the 32nd falling clock edge, the last
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
Table 9. DCEN (Daisy-Chain Enable) Register
DB1
DB0
Description
0
1
X
X
Standalone mode (default)
DCEN mode
The SCLK is continuously applied to the input register when
SYNC
is low. If more than 32 clock pulses are applied, the data
SYNC
the mode of operation. The
line must be brought high
ripples out of the input shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next DAC in the chain, a multiDAC interface is
constructed. Each DAC in the system requires 32 clock pulses;
therefore, the total number of clock cycles must equal 32N,
where N is the total number of devices in the chain.
within 30 ns of the 32nd falling edge of SCLK. In either case, it
must be brought high for a minimum of 1.9 μs before the next
SYNC
write sequence so that a falling edge of
can initiate the next
buffer draws more current
SYNC
SYNC
write sequence. Because the
when VIN = VDD than it does when VIN = 0 V,
should be
idled low between write sequences for even lower power
operation of the part. As mentioned previously, however,
SYNC
SYNC
If
part, it is considered an invalid frame and the data is discarded.
SYNC
is taken high before 32N clocks are clocked into the
must be brought high again just before the next write sequence.
INTERRUPT
SYNC
When the serial transfer to all devices is complete,
is
SYNC
In a normal write sequence, the
line is kept low for at
taken high. This prevents any further data from being clocked
into the input register.
least 32 falling edges of SCLK, and the DAC is updated on the
nd
SYNC
32 falling edge. However, if
is brought high before the
The serial clock can be continuous or a gated clock. A continuous
32nd falling edge, this acts as an interrupt to the write sequence.
The input register is reset, and the write sequence is seen as invalid.
Neither an update of the DAC register contents nor a change in
the operating mode occurs (see Figure 44).
SYNC
SCLK source can be used only if
can be held low for the
correct number of clock cycles. In gated clock mode, a burst
clock containing the exact number of clock cycles must be used,
SYNC
and
must be taken high after the final clock to latch the data.
DAISY-CHAINING
LDAC
In daisy-chain mode, the
pin cannot be tied permanently
For systems that contain several DACs, or where the user wishes to
read back the DAC contents for diagnostic purposes, the SDO
pin can be used to daisy-chain several devices together and
provide serial readback.
LDAC
LDAC
update
pin must be brought
low. The
pin must be used in asynchronous
LDAC
mode, as shown in Figure 3. The
high after pulsing. This allows all DAC outputs to simultaneously
update.
The daisy-chain mode is enabled through a software executable
daisy-chain enable (DCEN) command. Command 1000 is
reserved for this DCEN function (see Table 8). The daisy-chain
mode is enabled by setting a bit (DB1) in the DCEN register.
The default setting is standalone mode, where DB1 = 0.
SCLK
SYNC
DB31
DB0
DB31
DB0
DIN
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32 FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ND
ND
ON THE 32 FALLING EDGE
SYNC
Figure 44.
Interrupt Facility
Table 10. 32-Bit Input Register Contents for Daisy-Chain Enable
MSB
LSB
DB0
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2 to DB19
X
DB1
1
0
0
0
X
X
X
X
1/0
X
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
DCEN register
Rev. 0 | Page 19 of 28
AD5025/AD5045/AD5065
current fall, but the output stage is also internally switched from
the output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different options. The output is connected internally to GND
through either a 1 kΩ or a 100 kΩ resistor, or it is left open-
circuited (three-state). The output stage is illustrated in Figure 45.
POWER-ON RESET AND SOFTWARE RESET
The AD5025/AD5045/AD5065 contain a power-on reset (POR)
circuit that controls the output voltage during power-up. By
connecting the POR pin low, the AD5025/AD5045/AD5065
output powers up to zero scale. Note that this is outside the
linear region of the DAC; by connecting the POR pin high, the
AD5025/AD5045/AD5065 output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code selected by the POR pin. Command 0111 is reserved
for this reset function (see Table 8).
AMPLIFIER
V
DAC
OUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
POWER-DOWN MODES
Figure 45. Output Stage During Power-Down
The AD5025/AD5045/AD5065 contain four separate modes
of operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the input register (see
Table 12). Table 11 shows how the state of the bits corresponds
to the mode of operation of the device.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 4.5 μs for VDD = 5 V (see Figure 24).
Either or both DACs (DAC A and DAC B) can be powered down
to the selected mode by setting the corresponding bits (DB3 and
DB0) to 1. See Table 12 for the contents of the input register
during power-down/power-up operation.
Table 11. Modes of Operation
DB9
DB8
Operating Mode
Normal operation, power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
1
1
0
1
0
1
Any combination of DACs can be powered up by setting PD1 = 0
and PD0 = 0 (normal operation). The output powers up to the
LDAC
value in the input register (
low) or to the value in the
LDAC
When both Bit DB9 and Bit DB8 in the input register are set to 0,
the part works normally with its normal power consumption of
2.2 mA at 5 V. However, for the three power-down modes, the
supply current falls to 0.4 μV at 5 V. Not only does the supply
DAC register before powering down (
high).
Table 12. 32-Bit Input Register Contents for Power-Up/Power-Down Function
MSB
LSB
DB31
to
DB10
to
DB4
to
DB28
DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19
DB9
DB8
DB7
DB3
DB2
DB1
DB0
DAC A
X
0
1
0
0
X
X
X
X
X
PD1
PD0
X
DAC
B
DAC
B
DAC
A
Don’t
cares
Command bits (C2 to C0)
Address bits (A3 to A0)—don’t
cares
Don’t
cares
Power-down
mode
Don’t
cares
Power-down/power-up channel
selection—set bits to 1 to select
Rev. 0 | Page 20 of 28
AD5025/AD5045/AD5065
CLEAR CODE REGISTER
FUNCTION
LDAC
CLR
The AD5025/AD5045/AD5065 have a hardware
pin that
LDAC
Hardware
Pin
CLR
is an asynchronous clear input. The
input is falling edge sensi-
line low clears the contents of the input
register and the DAC registers to the data contained in the user-
CLR
The outputs of all DACs can be updated simultaneously using
LDAC LDAC
CLR
tive. Bringing the
the hardware
synchronous or asynchronous mode, as shown in Figure 3.
LDAC LDAC
is held low. After new data is read,
pin. The
pin can be used in
configurable
register, and sets the analog outputs accordingly
Synchronous
:
(see Table 13). This function can be used in system calibration
to load zero scale, midscale, or full scale to all channels together.
These clear code values are user-programmable by setting two
bits, Bit DB1 and Bit DB0, in the input register (see Table 13).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 8).
the DAC registers are updated on the falling edge of the 32nd
LDAC
standalone mode.
daisy-chain mode.
SCLK pulse.
can be permanently low or pulsed in
LDAC
cannot be tied permanently low in
LDAC LDAC
is held high and pulsed. The outputs
Asynchronous
are not updated at the same time that the input registers are
LDAC
:
Table 13. Clear Code Register
written to. When
with the contents of the input register.
LDAC
goes low, the DAC registers are updated
Clear Code Register
DB1 (CR1)
DB0 (CR0)
Clears to Code
0x0000
0x8000
0xFFFF
No operation
Software
Alternatively, the outputs of all DACs can be updated simulta-
LDAC
Function
0
0
1
1
0
1
0
1
neously using the software
Register n (see Table 7) and updating all DAC registers.
LDAC
function by writing to Input
The part exits clear code mode on the 32nd falling edge of the
Command 0010 is reserved for this software
function.
register gives the user extra flexibility and control
LDAC LDAC
CLR
next write to the part. If
the write is aborted.
is activated during a write sequence,
LDAC
The
over the hardware
bit register (DB0 to DB3) to 0 for a DAC channel means that
LDAC
pin (see Table 16). Setting the
CLR
CLR
to when
The
pulse activation time, the falling edge of
the output starts to change, is typically 10.6 μs (see Figure 31).
this channel update is controlled by the hardware
pin.
If DB0 or DB3 is set to 1, this channel updates synchronously.
See Table 14 for contents of the input register during the
loading clear code register operation.
LDAC
The part effectively sees the hardware
pin as being tied
LDAC
low (see Table 15 for the
register mode of operation).
This flexibility is useful in applications where the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
Table 14. 32-Bit Input Register Contents for Clear Code Function
MSB
LSB
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2 to DB19
X
DB1
DB0
0
1
0
1
X
X
X
X
1/0
1/0
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
Clear code register
(CR1 to CR0)
Table 15.
Overwrite Definitions
LDAC
Load DAC Register
LDAC Bits (DB3 and DB0)
LDAC Pin
1, 0
X1
LDAC Operation
0
Determined by LDAC pin.
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
1
1 X = don’t care.
Table 16. 32-Bit Input Register Contents for
Overwrite Function
LDAC
MSB
LSB
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB4 to DB19
X
DB3
DB2
DB1
DB0
DAC A
LDAC
0
1
1
0
X
X
X
X
DAC B
X
X
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)—don’t cares
Don’t cares
LDAC
Set bits to 1 to override
pin
Rev. 0 | Page 21 of 28
AD5025/AD5045/AD5065
The user is recommended to hardwire the pin to a logic high or
low, thereby either enabling or disabling the feature.
POWER-DOWN LOCKOUT
PDL
The AD5025/AD5045/AD5065 contain a digital input pin,
.
POWER SUPPLY BYPASSING AND GROUNDING
PDL
When activated, the power-down lockout pin ( ) disables
software shutdown under any circumstances. The user should
PDL
software power-down) or logic high (the part can be placed in
power-down mode over the serial interface). If the user transitions
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board (PCB) containing the AD5025/AD5045/
AD5065 should have separate analog and digital sections. If the
AD5025/AD5045/AD5065 are in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5025/AD5045/AD5065.
hardwire the
pin to a logic low (thus preventing subsequent
PDL
the
sequence, the device responds immediately and the current
PDL
pin from logic high to a logic low during a valid write
write sequence is aborted. Note the following
During a Write Sequence
features.
PDL
PDL
Bypass the power supply to the AD5025/AD5045/AD5065 with
10 μF and 0.1 μF capacitors. The capacitors should physically be
as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), which is typical of common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
If a
is generated (that is, a high-to-low transition) while a
valid write sequence is ongoing, the write is aborted. The user
must rewrite the current write command again.
While DACs in Power-Down Mode
PDL
PDL
If a
is generated while the DAC(s) are in power-down
mode, the DAC(s) come out of power-down (that is, all power-
down bits are reset to 0000) to the last voltage output correspond-
PDL
ing to the last valid stored DAC value. While
software power-down is disabled.
remains active,
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Shield clocks and other fast switching digital signals
from other parts of the board by digital ground. Avoid crossover
of digital and analog signals if possible. When traces cross on
opposite sides of the board, ensure that they run at right angles
to each other to reduce feedthrough effects through the board.
The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the
ground plane only and the signal traces are placed on the solder
side. However, this is not always possible with a 2-layer board.
Low to High Transition
PDL
PDL
After
is taken from a low to a high state, all DAC channels
remain in normal mode, and the user must reissue a software
power-down command to the control register to power down
the required channels.
PDL
Transitioning
immediately.
from a low to a high disables the feature
CLR
signal
PDL
CLR
are generated at the same time, the
If
and
causes the DAC register to change as per the clear code register,
and the DACs come out of power-down.
PDL CLR
has higher precedence over
LDAC
CLR
If
,
, and
are generated at the same time,
LDAC PDL
and
.
Rev. 0 | Page 22 of 28
AD5025/AD5045/AD5065
AD5025/AD5045/AD5065 to 80C51/80L51 Interface
MICROPROCESSOR INTERFACING
Figure 48 shows a serial interface between the AD5025/AD5045/
AD5065 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5025/AD5045/AD5065, and RxD drives the serial
AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x
Interface
Figure 46 shows a serial interface between the AD5025/AD5045/
AD5065 and the Blackfin® ADSP-BF53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5025/AD5045/AD5065, the setup for the interface is
as follows: DT0PRI drives the DIN pin of the AD5025/AD5045/
SYNC
data line of the part. The
signal is again derived from a
bit-programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5025/AD5045/
AD5065, P3.3 is taken low. The 80C51/80L51 transmits data in
8-bit bytes only; thus, only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is lept low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data in LSB-first format. The AD5025/AD5045/AD5065
must receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
SYNC
AD5065, and TSCLK0 drives the SCLK of the parts. The
driven from TFS0.
is
ADSP-BF53x*
AD5025/
AD5045/
AD5065
*
TFS0
DT0PRI
TSCLK0
SYNC
DIN
80C51/80L51*
AD5025/
AD5045/
SCLK
AD5065
*
*ADDITIONAL PINS OMITTED FOR CLARITY.
P3.3
TxD
RxD
SYNC
Figure 46. AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x Interface
SCLK
DIN
AD5025/AD5045/AD5065 to 68HC11/68L11 Interface
Figure 47 shows a serial interface between the AD5025/AD5045/
AD5065 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5025/AD5045/AD5065,
and the MOSI output drives the serial data line of the DAC.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 48. AD5025/AD5045/AD5065 to 80C51/80L51 Interface
AD5025/AD5045/AD5065 to MICROWIRE Interface
68HC11/68L11*
AD5025/
AD5045/
Figure 49 shows an interface between the AD5025/AD5045/
AD5065 and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked into
the AD5025/AD5045/AD5065 on the rising edge of SCLK.
AD5065
*
PC7
SCK
SYNC
SCLK
DIN
MICROWIRE*
AD5025/
MOSI
AD5045/
AD5065
*
*ADDITIONAL PINS OMITTED FOR CLARITY.
CS
SK
SO
SYNC
Figure 47. AD5025/AD5045/AD5065 to 68HC11/68L11 Interface
DIN
SYNC
The
signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 49. AD5025/AD5045/AD5065 to MICROWIRE Interface
SYNC
line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5025/AD5045/
AD5065, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
Rev. 0 | Page 23 of 28
AD5025/AD5045/AD5065
APPLICATIONS INFORMATION
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5025/AD5045/AD5065
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
Because the supply current required by the AD5025/AD5045/
AD5065 is extremely low, an alternative option is to use a voltage
reference to supply the required voltage to the parts (see Figure 50).
This is especially useful if the power supply is quite noisy or if
the system supply voltages are at some value other than 5 V or
3 V, for example, 15 V. The voltage reference outputs a steady
supply voltage for the AD5025/AD5045/AD5065. If the low
dropout REF195 is used, it must supply 500 μA of current to
the AD5025/AD5045/AD5065 with no load on the output of
the DAC. When the DAC output is loaded, the REF195 also needs
to supply the current to the load. The total current required
(with a 5 kΩ load on the DAC output) is
R2 = 10kΩ
+5V
+5V
R1 = 10kΩ
AD820/
OP295
±5V
V
V
OUT
DD
0.1µF
10µF
AD5025/
AD5045/
AD5065
–5V
3-WIRE
SERIAL INTERFACE
Figure 51. Bipolar Operation with the AD5025/AD5045/AD5065
500 μA + (5 V/5 kΩ) = 1.5 mA
USING THE AD5025/AD5045/AD5065 WITH A
GALVANICALLY ISOLATED INTERFACE
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 μV) error for the 1.5 mA current
drawn from it. This corresponds to a 0.196 LSB error.
15V
In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous common-
mode voltages that can occur in the area where the DAC is
functioning. iCoupler® provides isolation in excess of 2.5 kV.
The AD5025/AD5045/AD5065 use a 3-wire serial logic interface,
so the ADuM1300 three-channel digital isolator provides the
required isolation (see Figure 52). The power supply to the part
also needs to be isolated, which is achieved by using a transformer.
On the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5025/AD5045/AD5065.
5V
REF195
V
DD
SYNC
SCLK
DIN
3-WIRE
SERIAL
INTERFACE
AD5025/
AD5045/
AD5065
V
x = 0V TO 5V
OUT
Figure 50. REF195 as Power Supply to the AD5025/AD5045/AD5065
5V
REGULATOR
BIPOLAR OPERATION USING THE
AD5025/AD5045/AD5065
10µF
0.1µF
POWER
The AD5025/AD5045/AD5065 is designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 51. The circuit gives an output voltage range of
5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
V
DD
SCLK
V
V
V
V
SCLK
IA
IB
IC
OA
AD5025/
AD5045/
AD5065
ADuM1300
The output voltage for any input code can be calculated as
follows:
SDI
V
x
V
SYNC
DIN
OUT
OB
OC
D
65,536
R1 R2
R1
R2
R1
V
DATA
VO V
V
DD
DD
GND
where D represents the input code in decimal (0 to 65,535).
Figure 52. AD5025/AD5045/AD5065 with a Galvanically Isolated Interface
With VDD = 5 V, R1 = R2 = 10 kΩ,
10 D
65,536
V
5 V
O
Rev. 0 | Page 24 of 28
AD5025/AD5045/AD5065
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 53. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
Option
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
Accuracy
0.25 LSB INL
0.25 LSB INL
0.5 LSB INL
0.5 LSB INL
4 LSB INL
Resolution
12 bits
12 bits
14 bits
14 bits
16 bits
16 bits
16 bits
16 bits
AD5025BRUZ1
AD5025BRUZ-REEL71
AD5045BRUZ1
AD5045BRUZ-REEL71
AD5065ARUZ1
AD5065ARUZ-REEL71
AD5065BRUZ1
AD5065BRUZ-REEL71
4 LSB INL
1 LSB INL
1 LSB INL
1 Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
AD5025/AD5045/AD5065
NOTES
Rev. 0 | Page 26 of 28
AD5025/AD5045/AD5065
NOTES
Rev. 0 | Page 27 of 28
AD5025/AD5045/AD5065
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06844-0-10/08(0)
Rev. 0 | Page 28 of 28
相关型号：
AD5066ARUZ-REEL7
Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
ADI
AD5066BRUZ-1REEL7
Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
ADI
©2020 ICPDF网 联系我们和版权申明