AD5111BCPZ10-RL7 [ADI]
Single-Channel, 128-/64-/32-Position, Up/Down, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer; 单通道， 128 / 64 / 32位，上/下，A ± 8 ％电阻容差，非易失性数字电位计
| 型号： | AD5111BCPZ10-RL7 |
| 厂家： | 
ADI |
| 描述： | Single-Channel, 128-/64-/32-Position, Up/Down, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer |
| 文件： | 总24页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Channel, 128-/64-/32-Position, Up/Down, 8%
Resistor Tolerance, Nonvolatile Digital Potentiometer
Data Sheet
AD5111/AD5113/AD5115
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
DD
Nominal resistor tolerance error: 8ꢀ maximum
Wiper current: 6 mA
AD5111/
AD5113/
AD5115
POWER-ON
RESET
Rheostat mode temperature coefficient: 35 ppm/°C
Low power consumption: 2.5mA max @ 2.7 V and 125°C
Wide bandwidth: 4 MHz (5 kΩ option)
Power-on EEPROM refresh time < 50 μs
50-year typical data retention at 125°C
1 million write cycles
A
W
B
CLK
DATA
DATA
EEPROM
EN
UP/DOWN
CONTROL
LOGIC
CS
RDAC
REGISTER
U/D
2.3 V to 5.5 V supply operation
Chip select enable multiple device operation
Wide operating temperature: −40°C to +125°C
Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package
GND
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement
Portable electronics level adjustment
Audio volume control
Table 1. 8% Resistance Tolerance Family
Model
Resistance (kΩ)
Position
128
128
64
Interface
I2C
Up/down
I2C
Up/down
Push-button
I2C
AD5110
AD5111
AD5112
AD5113
AD5116
AD5114
AD5115
10, 80
10, 80
5, 10, 80
5, 10, 80
5, 10, 80
10, 80
Low resolution DAC
LCD panel brightness and contrast control
Programmable voltage to current conversion
Programmable filters, delays, time constants
Feedback resistor programmable power supply
Sensor calibration
64
64
32
10, 80
32
Up/down
GENERAL DESCRIPTION
The AD5111/AD5113/AD5115 provide a nonvolatile solution
for 128-/64-/32-position adjustment applications, offering
guaranteed low resistor tolerance errors of 8% and up to
6 mA current density in the A, B, and W pins. The low resistor
tolerance, low nominal temperature coefficient, and high
bandwidth simplify open-loop applications, as well as tolerance
matching applications.
The new low wiper resistance feature minimizes the wiper
resistance in the extremes of the resistor array to only 45 Ω,
typical.
A simple 3-wire up/down interface allows manual switching
or high speed digital control with clock rates up to 50 MHz.
The AD5111/AD5113/AD5115 are available in a 2 mm × 2 mm
LFCSP package. The parts are guaranteed to operate over the
extended industrial temperature range of −40°C to +125°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
AD5111/AD5113/AD5115
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 17
Theory of Operation ...................................................................... 18
RDAC Register and EEPROM.................................................. 18
Basic Operation .......................................................................... 18
Low Wiper Resistance Feature ................................................. 18
Shutdown Mode ......................................................................... 18
EEPROM Write Operation ....................................................... 18
RDAC Architecture.................................................................... 19
Programming the Variable Resistor......................................... 19
Programming the Potentiometer Divider............................... 20
Terminal Voltage Operating Range ......................................... 20
Power-Up Sequence ................................................................... 21
Layout and Power Supply Biasing............................................ 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—AD5111 .......................................... 3
Electrical Characteristics—AD5113 .......................................... 5
Electrical Characteristics—AD5115 .......................................... 7
Interface Timing Specifications.................................................. 9
Timing Diagram ........................................................................... 9
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 12
REVISION HISTORY
4/12—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Positive Supply Current, Table 2 ................................ 3
Changes to Positive Supply Current, Table 3 ................................ 5
Changes to Positive Supply Current, Table 4 ................................ 7
Updated Outline Dimensions....................................................... 22
10/11—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
AD5111/AD5113/AD5115
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5111
10 kꢀ and 80 kꢀ versions: VDD = 2.3 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
N
R-INL
7
−2.5
−1
−0.5
−1
Bits
LSB
LSB
LSB
LSB
%
ppm/°C
Ω
Ω
Resistor Integral Nonlinearity2
RAB = 10 kΩ, VDD = 2.3 V to 2.7 V
RAB = 10 kΩ, VDD = 2.7 V to 5.5 V
RAB = 80 kΩ
0.5
0.25
0.1
+2.5
+1
+0.5
+1
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance
R-DNL
0.25
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
RBS
RTS
−8
+8
35
70
45
70
Code = zero scale
Code = bottom scale
Code = top scale
140
80
140
Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4
Differential Nonlinearity4
Full-Scale Error
INL
DNL
VWFSE
−0.5
−0.5
−2.5
−1.5
0.15
0.15
+0.5
+0.5
LSB
LSB
RAB = 10 kΩ
RAB = 80 kΩ
LSB
LSB
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 80 kΩ
Code = half scale
1.5
0.5
LSB
LSB
ppm/°C
(ΔVW/VW)/ΔT × 106
10
Voltage Divider Temperature Coefficient3
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW Current3
RAB = 10 kΩ
RAB = 80 kΩ
−6
−1.5
GND
+6
+1.5
VDD
mA
mA
V
Terminal Voltage Range5
Capacitance A, Capacitance B3, 6
CA, CB
CW
f = 1 MHz, measured to GND,
code = half scale
f = 1 MHz, measured to GND,
code = half scale
20
35
15
pF
Capacitance W3, 6
pF
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
VA = VW = VB
−500
2
+500
nA
High
Low
Input Current3
Input Capacitance3
POWER SUPPLIES
Single-Supply Power Range
Positive Supply Current
VINH
VINL
IN
V
V
μA
pF
0.8
1
CIN
5
2.3
5.5
3.5
2.5
2.4
V
IDD
VIH = VDD or VIL = GND, VDD = 5 V
VIH = VDD or VIL = GND, VDD = 2.7 V
VIH = VDD or VIL = GND, VDD = 2.3 V
0.75
mA
mA
mA
mA
μA
μW
EEMEM Store Current3, 7
EEMEM Read Current3, 8
Power Dissipation9
IDD_NVM_STORE
IDD_NVM_READ
PDISS
2
320
5
VIH = VDD or VIL = GND
∆VDD/∆VSS = 5 V 10%
RAB = 10 kΩ
Power Supply Rejection3
PSR
−50
−64
dB
dB
RAB = 80 kΩ
Rev. A | Page 3 of 24
AD5111/AD5113/AD5115
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS3, 10
Bandwidth
BW
Code = half scale, −3 dB
RAB = 10 kΩ
2
200
MHz
kHz
RAB = 80 kΩ
Total Harmonic Distortion
VW Settling Time
THD
ts
VA = VDD/2 + 1 V rms, VB = VDD/
2, f = 1 kHz, code = half scale
RAB = 10 kΩ
RAB = 80 kΩ
VA = 5 V, VB = 0 V, 0.5 LSB
error band
−80
−85
dB
dB
RAB = 10 kΩ
RAB = 80 kΩ
3
12
μs
μs
Resistor Noise Density
eN_WB
Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 10 kΩ
RAB = 80 kΩ
9
20
nV/√Hz
nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance11
TA = 25°C
1
MCycles
kCycles
Years
100
Data Retention12
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step
change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB.
3 Guaranteed by design and characterization; not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other.
6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V.
7 Different from operating current; supply current for NVM program lasts approximately 30 ms.
8 Different from operating current; supply current for NVM read lasts approximately 20 μs.
9 PDISS is calculated from (IDD × VDD).
10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V.
11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev.A | Page 4 of 24
Data Sheet
AD5111/AD5113/AD5115
ELECTRICAL CHARACTERISTICS—AD5113
5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
N
R-INL
6
−2.5
−1
−1
−±.25
−1
Bits
LSB
LSB
LSB
LSB
LSB
%
ppm/°C
Ω
Ω
Resistor Integral Nonlinearity2
RAB = 5 kΩ, VDD = 2.3 V to 2.7 V
RAB = 5 kΩ, VDD = 2.7 V to 5.5 V
RAB = 1± kΩ
±±.5
±±.25 +1
±±.25 +1
±±.1
±±.25 +1
+2.5
RAB = 8± kΩ
+±.25
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance
R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 1±6
RW
RBS
RTS
−8
+8
35
7±
45
7±
Code = zero scale
Code = bottom scale
Code = top scale
14±
8±
14±
Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4
Differential Nonlinearity4
Full-Scale Error
INL
DNL
VWFSE
−±.5
−±.5
−2.5
−1.5
−1
±±.15 +±.5
±±.15 +±.5
LSB
LSB
RAB = 5 kΩ
LSB
LSB
LSB
LSB
RAB =1± kΩ
RAB = 8± kΩ
RAB = 5 kΩ
Zero-Scale Error
VWZSE
1.5
RAB =1± kΩ
RAB = 8± kΩ
Code = half scale
1
±.25
LSB
LSB
ppm/°C
(ΔVW/VW)/ΔT × 1±6
±1±
Voltage Divider Temperature Coefficient3
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW
RAB = 5 kΩ, 1± kΩ
RAB = 8± kΩ
−6
−1.5
GND
+6
+1.5
VDD
mA
mA
V
Current3
Terminal Voltage Range5
Capacitance A, Capacitance B3, 6
CA, CB
CW
f = 1 MHz, measured to GND,
code = half scale
f = 1 MHz, measured to GND,
code = half scale
2±
pF
Capacitance W3, 6
35
pF
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
VA = VW = VB
−5±±
2
±15
+5±±
nA
High
Low
Input Current3
Input Capacitance3
POWER SUPPLIES
Single-Supply Power Range
Positive Supply Current
VINH
VINL
IN
V
V
μA
pF
±.8
±1
CIN
5
2.3
5.5
3.5
2.5
2.4
V
IDD
VIH = VDD or VIL = GND, VDD = 5 V
VIH = VDD or VIL = GND, VDD = 2.7 V
VIH = VDD or VIL = GND, VDD = 2.3 V
±.75
mA
mA
mA
mA
μA
μW
EEMEM Store Current3, 7
EEMEM Read Current3, 8
Power Dissipation9
IDD_NVM_STORE
IDD_NVM_READ
PDISS
2
32±
5
VIH = VDD or VIL = GND
∆VDD/∆VSS = 5 V ± 1±%
RAB = 5 kΩ
RAB =1± kΩ
RAB = 8± kΩ
Power Supply Rejection3
PSR
−43
−5±
−64
dB
dB
dB
Rev. A | Page 5 of 24
AD5111/AD5113/AD5115
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICS3, 10
Bandwidth
BW
Code = half scale, −3 dB
RAB = 5 kΩ
4
2
200
MHz
MHz
kHz
RAB = 10 kΩ
RAB = 80 kΩ
Total Harmonic Distortion
VW Settling Time
THD
VA = VDD/2 + 1 V rms, VB = VDD/2,
f = 1 kHz, code = half scale
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
−75
−80
−85
dB
dB
dB
ts
VA = 5 V, VB = 0 V,
0.5 LSB error band
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
2.5
3
10
μs
μs
μs
Resistor Noise Density
eN_WB
Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
7
9
20
nV/√Hz
nV/√Hz
nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance11
TA = 25°C
1
MCycles
kCycles
Years
100
Data Retention12
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step
change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB.
3 Guaranteed by design and characterization; not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other.
6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V.
7 Different from operating current; supply current for NVM program lasts approximately 30 ms.
8 Different from operating current; supply current for NVM read lasts approximately 20 μs.
9 PDISS is calculated from (IDD × VDD).
10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V.
11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev.A | Page 6 of 24
Data Sheet
AD5111/AD5113/AD5115
ELECTRICAL CHARACTERISTICS—AD5115
10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ1 Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
N
R-INL
R-DNL
5
Bits
LSB
LSB
%
ppm/°C
Ω
Resistor Integral Nonlinearity2
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance
−0.5
−0.25
−8
+0.5
+0.25
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
RBS
RTS
+8
35
Code = zero scale
Code = bottom scale
Code = top scale
70
45
70
140
80
140
Ω
Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4
Differential Nonlinearity4
Full-Scale Error
INL
DNL
VWFSE
−0.25
−0.25
−1
+0.25
+0.25
LSB
LSB
RAB = 10 kΩ
LSB
RAB = 80 kΩ
−0.5
LSB
Zero-Scale Error
VWZSE
RAB = 10 kΩ
1
LSB
RAB = 80 kΩ
Code = half scale
0.25
LSB
ppm/°C
(ΔVW/VW)/ΔT × 106
10
Voltage Divider Temperature Coefficient3
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW Current3
RAB = 10 kΩ
RAB = 80 kΩ
−6
+6
mA
mA
V
−1.5
GND
+1.5
VDD
Terminal Voltage Range5
Capacitance A, Capacitance B3, 6
CA, CB
CW
f = 1 MHz, measured to GND,
code = half scale
f = 1 MHz, measured to GND,
code = half scale
20
35
pF
Capacitance W3, 6
pF
Common-Mode Leakage Current3
DIGITAL INPUTS
Input Logic3
VA = VW = VB
−500
2
15
+500
nA
High
Low
Input Current3
Input Capacitance3
POWER SUPPLIES
Single-Supply Power Range
Positive Supply Current
VINH
VINL
IN
V
V
μA
pF
0.8
1
CIN
5
2.3
5.5
3.5
2.5
2.4
V
IDD
VIH = VDD or VIL = GND, VDD = 5 V
VIH = VDD or VIL = GND, VDD = 2.7 V
VIH = VDD or VIL = GND, VDD = 2.3 V
0.75
mA
mA
mA
mA
μA
μW
EEMEM Store Current3, 7
EEMEM Read Current3, 8
Power Dissipation9
IDD_NVM_STORE
IDD_NVM_READ
PDISS
2
320
5
VIH = VDD or VIL = GND
∆VDD/∆VSS = 5 V 10%
RAB = 10 kΩ
Power Supply Rejection3
PSR
−50
−64
dB
dB
RAB = 80 kΩ
Rev. A | Page 7 of 24
AD5111/AD5113/AD5115
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ1 Max
Unit
DYNAMIC CHARACTERISTICS3, 10
Bandwidth
BW
Code = half scale, −3 dB
RAB = 10 kΩ
2
200
MHz
kHz
RAB = 80 kΩ
Total Harmonic Distortion
VW Settling Time
THD
ts
VA = VDD/2 + 1 V rms, VB = VDD/2,
f = 1 kHz, code = half scale
RAB = 10 kΩ
RAB = 80 kΩ
VA = 5 V, VB = 0 V, 0.5 LSB error
band
−80
−85
dB
dB
RAB = 10 kΩ
RAB = 80 kΩ
μs
μs
2.7
9.5
Resistor Noise Density
eN_WB
Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 10 kΩ
RAB = 80 kΩ
9
20
nV/√Hz
V
FLASH/EE MEMORY RELIABILITY3
Endurance11
TA = 25°C
1
MCycles
kCycles
Years
100
Data Retention12
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step
change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB.
3 Guaranteed by design and characterization; not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on current direction with respect to each other.
6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V.
7 Different from operating current; supply current for NVM program lasts approximately 30 ms.
8 Different from operating current; supply current for NVM read lasts approximately 20 μs.
9 PDISS is calculated from (IDD × VDD).
10 All dynamic characteristics use VDD = 5.5 V and VLOGIC = 5 V.
11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
12 Retention lifetime equivalent at junction temperature (TJ) is 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev.A | Page 8 of 24
Data Sheet
AD5111/AD5113/AD5115
INTERFACE TIMING SPECIFICATIONS
VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter
Test Conditions/Comments Min Typ
Max
50
25
Unit
MHz
MHz
ns
Description
fCLK
VDD ≥ 2.7 V
VDD < 2.7 V
25
Clock frequency
t1
t2
CS setup time
CLK low time
VDD ≥ 2.7 V
VDD < 2.7 V
VDD ≥ 2.7 V
VDD < 2.7 V
10
20
10
20
15
6
ns
ns
ns
t3
CLK high time
ns
ns
t4
t5
t6
U/D setup time
ns
U/D hold time
VDD ≥ 2.7 V
VDD < 2.7 V
20
40
15
12
24
12
1
ns
CS rise to CLK hold time
ns
ns
t7
t8
CS rising edge to next CLK ignored
U/D minimum pulse time
VDD ≥ 2.7 V
VDD < 2.7 V
ns
ns
ns
t9
U/D rise to CLK falling edge
Minimum CS time
t10
µs
1
tEEPROM_PROGRAM
15
50
50
ms
Memory program time
Power-on EEPROM restore time
2
tPOWER_UP
µs
1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
2 Maximum time after VDD is equal to 2.3 V.
TIMING DIAGRAMS
t3
t6
t10
t2
t1
t9
t6
t
1
CS
CS
t7
CLK
U/D
CLK
U/D
t4
t5
R
WB
Figure 4. Shutdown Mode Timing
Figure 2. Increment/Decrement Mode Timing
t
t
t
6
1
8
CS
CLK
tEEPROM_PROGRAM
U/D
DATA
NEW DATA
EEPROM
Figure 3. Storage Mode Timing
Rev.A | Page 9 of 24
AD5111/AD5113/AD5115
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
VDD to GND
VLOGIC to GND
VA, VW, VB to GND
IA, IW, IB
Rating
–0.3 V to +7.0 V
–0.3 V to +7.0 V
GND − 0.3 V to VDD + 0.3 V
Pulsed1
THERMAL RESISTANCE
Frequency > 10 kHz
θJA is defined by JEDEC specification JESD-51, and the value is
dependent on the test board and test environment.
RAW = 5 kΩ and 10 kΩ
RAW = 80 kΩ
±± ꢀA/d2
±1.5 ꢀA/d2
Table 7. Thermal Resistance
Package Type
8-Lead LFCSP
Frequency ≤ 10 kHz
RAW = 5 kΩ and 10 kΩ
RAW = 80 kΩ
±± ꢀA/√d2
±1.5 ꢀA/√d2
θJA
901
θJC
Unit
25
°C/W
Continuous
1 JEDEC 2S2P test board, still air (0 ꢀ/sec air flow).
RAW = 5 kΩ and 10 kΩ
RAW = 80 kΩ
±± ꢀA
±1.5 ꢀA
D CLK
Digital Inputs U/ , , and
CS
−0.3 V to +7 V or VDD + 0.3 V
(whichever is less)
−40°C to +125°C
ESD CAUTION
Operating Teꢀperature Range3
Maxiꢀuꢀ Junction Teꢀperature (TJ Max) 150°C
Storage Teꢀperature Range
Reflow Soldering
−±5°C to +150°C
Peak Teꢀperature
2±0°C
Tiꢀe at Peak Teꢀperature
Package Power Dissipation
20 sec to 40 sec
(TJ ꢀax − TA)/θJA
1 Maxiꢀuꢀ terꢀinal current is bounded by the ꢀaxiꢀuꢀ current handling of
the switches, ꢀaxiꢀuꢀ power dissipation of the package, and ꢀaxiꢀuꢀ
applied voltage across any two of the A, B, and W terꢀinals at a given
resistance.
2 Pulse duty factor.
3 Includes prograꢀꢀing of EEPROM ꢀeꢀory.
Rev.A | Page 10 of 24
Data Sheet
AD5111/AD5113/AD5115
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
8 CS
DD
AD5111/
AD5113/
AD5115
TOP VIEW
(Not to Scale)
A 2
W 3
B 4
7 U/D
6 CLK
5 GND
NOTES
1. THE EXPOSED PAD IS INTERNALLY
FLOATING.
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
VDD
A
W
B
GND
CLK
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC. GND ≤ VA ≤ VDD.
Wiper Terminal of RDAC. GND ≤ VW ≤ VDD.
Terminal B of RDAC. GND ≤ VB ≤ VDD.
Ground Pin, Logic Ground Reference.
Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined
by the state of the U/D pin. CLK is a negative edge trigger. Data can be transferred at rates up to 50 MHz.
7
8
U/D
CS
Up/Down Selection Counter Control.
Chip Select. Active Low.
EPAD
Exposed Pad. The exposed pad is internally floating.
Rev.A | Page 11 of 24
AD5111/AD5113/AD5115
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0.02
0.01
10kΩ, –40°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0.08
0.06
0.04
0.02
0
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.02
–0.04
–0.06
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
CODE (Decimal)
CODE (Decimal)
Figure 6. R-INL vs. Code (AD5111)
Figure 9. R-DNL vs. Code (AD5111)
0.08
0.06
0.04
0.02
0
0.02
5kΩ, –40°C
5kΩ, +25°C
5kΩ, +125°C
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
5kΩ, –40°C
5kΩ, +25°C
–0.02
–0.04
–0.06
5kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
10kΩ, +125°C
80kΩ, +125°C
10kΩ, –40°C
80kΩ, –40°C
10kΩ, +25°C
80kΩ, +25°C
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal)
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal)
Figure 7. R-INL vs. Code (AD5113)
Figure 10. R-DNL vs. Code (AD5113)
0.004
0.002
0.020
0.015
0.010
0.005
0
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0
–0.002
–0.004
–0.006
–0.008
–0.010
–0.012
–0.014
–0.016
–0.018
–0.005
–0.010
–0.015
10kΩ, –40°C
80kΩ, –40°C
10kΩ, +25°C
80kΩ, +25°C
10kΩ, +125°C
80kΩ, +125°C
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 31
CODE (Decimal)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 31
CODE (Decimal)
Figure 11. R-DNL vs. Code (AD5115)
Figure 8. R-INL vs. Code (AD5115)
Rev.A | Page 12 of 24
Data Sheet
AD5111/AD5113/AD5115
0.02
0.08
0.06
0.04
0.02
0
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.02
–0.04
–0.06
–0.08
10kΩ, –40°C
80kΩ, –40°C
10kΩ, +25°C
80kΩ, +25°C
10kΩ, +125°C
80kΩ, +125°C
–0.07
CODE (Decimal)
CODE (Decimal)
Figure 15. DNL vs. Code (AD5111)
Figure 12. INL vs. Code (AD5111)
0.08
0.06
0.04
0.02
0
0.02
0.01
5kΩ, –40°C
5kΩ, +25°C
5kΩ, +125°C
10kΩ, +125°C
5kΩ, –40°C
10kΩ, –40°C
10kΩ, +25°C
5kΩ, +25°C
5kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.02
–0.04
–0.06
–0.08
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal)
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal)
Figure 13. INL vs. Code (AD5113)
Figure 16. DNL vs. Code (AD5113)
0.015
0.004
0.002
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
0.010
0.005
0
0
–0.002
–0.004
–0.006
–0.008
–0.010
–0.012
–0.014
–0.016
–0.005
–0.010
–0.015
–0.020
80kΩ, +25°C
80kΩ, –40°C
80kΩ, +125°C
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 31
CODE (Decimal)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 31
CODE (Decimal)
Figure 14. INL vs. Code (AD5115)
Figure 17. DNL vs. Code (AD5115)
Rev.A | Page 13 of 24
AD5111/AD5113/AD5115
Data Sheet
800
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
V
= 5V
V
V
V
= 2.3V
= 3.3V
= 5V
T = 25°C
A
DD
DD
DD
DD
DD
DD
= 3.3V
= 2.3V
700
600
500
400
300
200
100
0
–100
–40 –25 –10
5
20
35
50
65
80
95 110 125
0.05
0.65
1.25
1.85
2.45
3.05
3.65
4.25
4.85
TEMPERATURE (°C)
DIGITAL INPUT VOLTAGE (V)
Figure 18. Supply Current vs. Temperature
Figure 21. Supply Current (IDD) vs. Digital Input Voltage
200
180
160
140
120
100
80
200
V
= 5V
V
= 5V
DD
DD
10kΩ
80kΩ
5kΩ
10kΩ
80kΩ
5kΩ
180
160
140
120
100
80
60
60
40
40
20
20
0
0
0
0
0
20
10
5
40
20
10
60
30
15
80
40
20
100
50
25
120 AD5111
60 AD5113
30 AD5115
0
0
0
20
10
5
40
20
10
60
30
15
80
40
20
100
50
25
120 AD5111
60 AD5113
30 AD5115
CODE (Decimal)
CODE (Decimal)
Figure 19. Potentiometer Mode Tempco ((ΔVW/VW)/ΔT × 106) vs. Code
Figure 22. Rheostat Mode Tempco ((ΔRWB/RWB)/ΔT × 106) vs. Code
0
0
(0x20) [0x10]
(0x10) [0x08]
0x40
–10 0x20
0x10
0x20
–10
–20
–30
–40
–50
–60
0x10
0x08
0x04
(0x08) [0x04]
(0x04) [0x02]
(0x02) [0x01]
–20
0x08
0x04
–30
0x02
0x01
(0x01) [0x00]
(0x00)
0x02
0x01
–40
0x00
–50
0x00
–60
AD5111 (AD5113) [AD5115]
–70
10k
10k
100k
1M
10M
100M
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 20. 5 kΩ Gain vs. Frequency vs. Code
Figure 23. 10 kΩ Gain vs. Frequency vs. Code
Rev.A | Page 14 of 24
Data Sheet
AD5111/AD5113/AD5115
0
80
70
60
50
40
30
20
10
0
(0x20) [0x10]
5k + 250pF
10k + 75pF
10k + 150pF
10k + 250pF
80k + 0pF
80k + 150pF
80k + 250pF
5k + 0pF
5k + 75pF
5k + 150pF
10k + 0pF
0x40
(0x10) [0x08]
(0x08) [0x04]
–10
–20
–30
–40
–50
–60
–70
–80
0x20
0x10
80k + 75pF
(0x04) [0x02]
(0x02) [0x01]
(0x01) [0x00]
(0x00)
0x08
0x04
0x02
0x01
0x00
AD5111 (AD5113) [AD5115]
10k
0
0
0
10
5
20
10
5
30
15
40
20
10
50
25
60
30
15
AD5111
AD5113
AD5115
100k
1M
FREQUENCY (Hz)
CODE (Decimal)
Figure 24. 80 kΩ Gain vs. Frequency vs. Code
Figure 27. Maximum Bandwidth vs. Code vs. Net Capacitance
150
0
–10
–20
–30
–40
–50
–60
–70
–80
T
= 25°C
5.5V
5V
3.3V
2.7V
2.3V
A
120
90
60
30
0
R
= 10kΩ
AB
FULL SCALE
HALF SCALE
QUARTER SCALE
10k
100k
1M
10M
0
1
2
3
4
5
6
V
(V)
DD
FREQUENCY (Hz)
Figure 25. Normalized Phase Flatness vs. Frequency
Figure 28. Incremental Wiper On Resistance vs. VDD
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
V
V
= 5V
5kΩ
10kΩ
80kΩ
V
V
V
= 5V
5kΩ
10kΩ
80kΩ
DD
A
DD
A
B
= 2.5V + V
= 2.5V
= 2.5V + 1V
= 2.5V
IN
RMS
–10
–20
–30
–40
–50
–60
–70
–80
–90
fINB = 1kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
20
200
2k
20k
200k
0.001
0.01
0.1
1
FREQUENCY (Hz)
AMPLITUDE (V rms)
Figure 29. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude
Figure 26. Total Harmonic Distortion + Noise (THD + N) vs. Frequency
Rev.A | Page 15 of 24
AD5111/AD5113/AD5115
Data Sheet
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
100
80
V
V
= 5V
DD
A
= V
DD
V
= GND
B
60
5kΩ
10kΩ
80kΩ
40
20
0
–20
–40
–60
–80
–100
–120
V
V
V
= 5V
DD
= GND
DD
A
= V
–0.05
–0.10
B
CODE = HALF SCALE
0
0.5 1.0 1.5
2.0
2.5
3.0
3.5
4.0
–1
1
3
5
7
9
TIME (µs)
TIME (µs)
Figure 30. Maximum Transition Glitch
Figure 33. Digital Feedthrough
0.0025
0.0020
0.0015
0.0010
0.0005
0
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–10
–20
–30
–40
–50
–60
–70
5kΩ
10kΩ
80kΩ
–600 –500 –400 –300 –200 –100
0
100 200 300 400 500 600
1k
10k
FREQUENCY (Hz)
1M
10M
RESISTOR DRIFT (ppm)
Figure 31. Resistor Lifetime Drift
Figure 34. Shutdown Isolation vs. Frequency
7
6
5
4
3
2
1
0
–10
–20
–30
–40
–50
–60
–70
10kΩ
5kΩ
10kΩ
80kΩ
V
V
V
= 5V ± 10% AC
= 4V
= GND
DD
80kΩ
5kΩ
A
B
CODE = HALF SCALE
= 25°C
T
A
0
0
0
0
10
100
1k
10k
100k
1M
20
10
5
40
20
10
60
30
15
80
40
20
100
50
25
120 AD5111
60 AD5113
30 AD5115
FREQUENCY (Hz)
CODE (Decimal)
Figure 32. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 35. Theoretical Maximum Current vs. Code
Rev.A | Page 16 of 24
Data Sheet
AD5111/AD5113/AD5115
TEST CIRCUITS
Figure 36 to Figure 41 define the test conditions used in the Specifications section.
NC
DUT
A
I
V
W
A
V+ = V ± 10%
DD
W
∆V
∆V
MS
DD
V
A
B
DD
PSRR (dB) = 20 log
B
W
V+
~
V
MS
∆V
∆V
%
%
MS
DD
PSS (%/%) =
V
MS
NC = NO CONNECT
Figure 36. Resistor Position Nonlinearity Error
(Rheostat Operation: R-INL, R-DNL)
Figure 39. Power Supply Sensitivity (PSS, PSRR)
+15V
A
DUT
A
V+ = V
DD
1LSB = V+/2
W
V
N
IN
DUT
AD8652
B
V
OUT
W
V+
OFFSET
GND
B
V
MS
2.5V
–15V
Figure 37. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 40. Gain and Phase vs. Frequency
GND
V
DD
NC
0.1V
=
R
W
GND
DUT
I
WB
A
B
V
I
A
DD
CM
DUT
W
W
+
B
0.1V
I
GND
WB
–
V
DD
GND TO V
DD
GND
NC = NO CONNECT
V
DD
Figure 41. Common-Mode Leakage Current
Figure 38. Wiper Resistance
Rev.A | Page 17 of 24
AD5111/AD5113/AD5115
Data Sheet
THEORY OF OPERATION
The AD5111/AD5113/AD5115 digital programmable resistors
are designed to operate as true variable resistors for analog
LOW WIPER RESISTANCE FEATURE
The AD5111/AD5113/AD5115 include a new feature to reduce
the resistance between terminals. These extra steps are called
bottom scale and top scale. At bottom scale, the typical wiper
resistance decreases from 70 Ω to 45 Ω. At top scale, the
resistance between Terminal A and Terminal W is decreased by
1 LSB and the total resistance is reduced to 70 Ω. The new extra
steps are loaded automatically in the RDAC register after zero-
scale or full-scale position has been reached.
signals within the terminal voltage range of GND < VTERM
<
VDD. The resistor wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratchpad
register that allows unlimited changes of resistance settings.
The RDAC register can be programmed with any position
setting using the up/down interface. Once a desirable wiper
position is found, this value can be stored in the EEPROM.
Thereafter, the wiper position is always restored to that position
for subsequent power-up. The storing of EEPROM data takes
approximately 30 ms; during this time, the device is locked and
does not accept any new operation, thus preventing any changes
from taking place.
The extra steps are not equal to 1 LSB and are not included in
the INL, DNL, R-INL, and R-DNL specifications.
SHUTDOWN MODE
This feature places Terminal A in open circuit, disconnected
from the internal resistor, and connects Terminal W and
Terminal B. A finite wiper resistance of 45 Ω is present between
these two terminals. The command is sent by a low-to-high
The AD5111/AD5113/AD5115 are designed to allow high
speed digital control with clock rates up to 50 MHz.
RDAC REGISTER AND EEPROM
D
CLK
CLK
CS
transition on the U/ pin, when
is high and
is enabled.
negative edge, as shown
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
0x40 (AD5111), the wiper is connected to midscale of the
variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed.
The command is executed on the
in Figure 4.
The AD5111/AD5113/AD5115 return the wiper to prior
shutdown position if any other operation is performed.
EEPROM WRITE OPERATION
Once a desirable wiper position is found, this value can be
saved into the EEPROM. Thereafter, the wiper position is
always set at that position for any future on-off-on power
supply sequence or recall operation.
The AD5111/AD5113/AD5115 contain an EEPROM that
allows the wiper position storage. Once a desirable wiper
position is found, this value can be saved into the EEPROM.
Thereafter, the wiper position is always set at that position for
any future power-up sequence or a memory recall operation.
BASIC OPERATION
CS
When
achieved by clocking the
and the direction of stepping into the RDAC register is
is pulled low, changing the resistance settings is
During the storage cycle, the device is locked and does not accept
any new operation, thus preventing any changes from taking
place.
CLK
pin. It is negative edge triggered,
D
determined by the state of the U/ input. When a specific state
D
The write cycle is started by applying a pulse in the U/ pin
CS CLK
D
of the U/ remains, the device continues to change in the same
when
is enabled and
remains high, as shown in
direction under consecutive clocks until it comes to the end of
the resistance setting. When the wiper reaches the maximum or
Figure 3. The write cycle takes approximately 20 ms.
CLK
minimum setting, additional
pulses do not change the
wiper setting. Figure 2 shows a typical increment/decrement
operation.
D
CLK
pin
The U/ pin value can be changed only when the
is low.
Rev.A | Page 18 of 24
Data Sheet
AD5111/AD5113/AD5115
PROGRAMMING THE VARIABLE RESISTOR
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5111/AD5113/AD5115
employ a two-stage segmentation approach as shown in
Figure 42. The AD5111/AD5113/AD5115 wiper switch is
designed with the transmission gate CMOS topology and with
the gate voltage derived from VDD.
Rheostat Operation— 8% Resistor Tolerance
The AD5111/AD5113/AD5115 operate in rheostat mode when
only two terminals are used as a variable resistor. The unused
terminal can be floating or tied to the W terminal as shown in
Figure 43.
A
A
A
A
W
W
W
TS
B
B
B
R
R
L
L
Figure 43. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 5 kꢀ, 10 kꢀ, and 80 kꢀ and has 128/64/32
tap points accessed by the wiper terminal. The 5-/6-/7-bit data
in the RDAC latch is decoded to select one of the 128/64/32
possible wiper settings. The general equations for determining
the digitally programmed output resistance between the W
terminal and B terminal are
R
R
S
W
S
5-BIT/6-BIT/7-BIT
ADDRESS
AD5111:
DECODER
R
R
L
L
RWB RBS
Bottom scale (1)
From 0 to 128 (2)
D
128
RWB(D)
RAB RW
BS
AD5113:
RWB RBS
B
Bottom scale (3)
From 0 to 64 (4)
D
64
RWB (D)
RAB RW
Figure 42. AD5111/AD5113/AD5115 Simplified RDAC Circuit
Low Wiper Resistance Feature
AD5115:
RWB RBS
In addition, the AD5111/AD5113/AD5115 include a new
Bottom scale (5)
From 0 to 32 (6)
feature to reduce the resistance between terminals. These extra
steps are called bottom scale and top scale. At bottom scale, the
typical wiper resistance decreases from 70 Ω to 45 Ω. At top
scale, the resistance between Terminal A and Terminal W is
decreased by 1 LSB and the total resistance is reduced to 70 Ω.
The extra steps are not equal to 1 LSB and are not included in
the INL, DNL, R-INL, and R-DNL specifications.
D
32
R
WB (D) RAB RW
where:
D is the decimal equivalent of the binary code in the 5-/6-/7-bit
RDAC register; 128, 64, and 32 refer to the top scale step.
R
AB is the end-to-end resistance.
RW is the wiper resistance.
RBS is the wiper resistance at bottom scale.
Rev.A | Page 19 of 24
AD5111/AD5113/AD5115
Data Sheet
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, RWA
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
.
The digital potentiometer easily generates a voltage divider at
W-to-B and W-to-A that is proportional to the input voltage at
A-to-B, as shown in Figure 44. Unlike the polarity of VDD to
GND, which must be positive, current across A-to-B, W-to-A,
and W-to-B can be in either direction.
RWA starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equations for
this operation are
AD5111:
V
I
RAW = RAB + RW
Bottom scale (7)
From 0 to 127 (8)
Top scale (9)
A
128− D
RAW (D) =
128
W
V
×RAB + RW
×RAB + RW
×RAB + RW
O
B
RAW = RTS
Figure 44. Potentiometer Mode Configuration
AD5113:
If ignoring the effect of the wiper resistance for simplicity,
connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at W to B ranging from 0 V to 5 V.
The general equation defining the output voltage at VW with
respect to ground for any valid input voltage applied to
Terminal A and Terminal B, is
RAW = RAB + RW
Bottom scale (10)
From 0 to 63 (11)
Top scale (12)
64 − D
RAW (D) =
64
RAW = RTS
AD5115:
R
WB(D)
R
AW (D)
RAB
VW (D) =
×VA +
×VB
(16)
RAW = RAB + RW
Bottom scale (13)
From 0 to 31 (14)
Top scale (15)
RAB
32− D
RAW (D) =
32
where:
R
R
WB(D) can be obtained from Equation 1 to Equation 6.
AW(D) can be obtained from Equation 7 to Equation 14.
RAW = RTS
where:
Operation of the digital potentiometer in the divider mode
D is the decimal equivalent of the binary code in the 5-/6-/7-bit
RDAC register; 128, 64, and 32 refer to top scale step.
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly
on the ratio of the internal resistors, RWA and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
RAB is the end-to-end resistance.
RW is the wiper resistance.
RTS is the wiper resistance at top scale.
Regardless of which setting the part is operating in, take care
to limit the current between A to B, W to A, and W to B, to
the maximum continuous current of 6 mA (5 kΩ and 10 kΩ)
or 1.5 mA (80 kΩ), or pulse current specified in Table 6.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
TERMINAL VOLTAGE OPERATING RANGE
The AD5111/AD5113/AD5115 are designed with internal
ESD diodes for protection. These diodes also set the voltage
boundary of the terminal operating voltages. Positive signals
present on the A, B, or W terminals that exceed VDD are
clamped by the forward-biased diode. There is no polarity
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than GND.
Rev.A | Page 20 of 24
Data Sheet
AD5111/AD5113/AD5115
LAYOUT AND POWER SUPPLY BIASING
POWER-UP SEQUENCE
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 46 illustrates the basic supply bypassing configuration
for the AD5111/AD5113/AD5115.
Because of the ESD protection diodes that limit the voltage
compliance at the A, B, and W terminals (see Figure 45), it is
important to power on VDD before applying any voltage to the
A, B, and W terminals. Otherwise, the diodes are forward-
biased such that VDD is powered on unintentionally and can
affect other parts of the circuit. Similarly, VDD should be
powered down last. The ideal power-on sequence is in the
following order: GND, VDD, and VA/VB/VW. The order of
powering VA, VB, VW and the digital inputs is not important as
long as they are powered on after VDD.
AD5111/
AD5113/
AD5115
V
DD
V
V
DD
DD
+
C2
10µF
C1
0.1µF
A
GND
AGND
W
B
Figure 46. Power Supply Bypassing
GND
Figure 45. Maximum Terminal Voltages Set by VDD and GND
Rev.A | Page 21 of 24
AD5111/AD5113/AD5115
OUTLINE DIMENSIONS
Data Sheet
1.70
1.60
1.50
2.00
BSC SQ
0.50 BSC
8
5
0.175 REF
PIN 1 INDEX
AREA
EXPOSED
PAD
1.10
1.00
0.90
0.425
0.350
0.275
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.60
0.55
0.50
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 47. 8-Lead Frame Chip Scale Package [LFCSP_UD]
2 mm × 2 mm Body, Very Thin, Dual Lead (CP-8-10)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Branding
Code
Model1, 2
RAB (kΩ) Resolution
AD5111BCPZ10-RL7
AD5111BCPZ10-500R7
AD5111BCPZ80-RL7
AD5111BCPZ80-500R7
AD5113BCPZ5-RL7
AD5113BCPZ5-500R7
AD5113BCPZ10-RL7
AD5113BCPZ10-500R7
AD5113BCPZ80-RL7
AD5113BCPZ80-500R7
AD5115BCPZ10-RL7
AD5115BCPZ10-500R7
AD5115BCPZ80-RL7
AD5115BCPZ80-500R7
EVAL-AD5111SDZ
10
10
80
80
5
128
128
128
128
64
64
64
64
64
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
Evaluation Board
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
7S
7S
7T
7T
85
85
84
84
86
86
7Y
7Y
7Z
7Z
5
10
10
80
80
10
10
80
80
64
32
32
32
32
1 Z = RoHS Compliant Part.
2 The EVAL-AD5111SDZ has an RAB of 10 kΩ.
Rev. A | Page 22 of 24
Data Sheet
NOTES
AD5111/AD5113/AD5115
Rev. A | Page 23 of 24
AD5111/AD5113/AD5115
NOTES
Data Sheet
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09654-0-4/12(A)
Rev. A | Page 24 of 24
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