AD5112BCPZ80-1-RL7 [ADI]
Single-Channel, 128-/64-/32-Position, I2C, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer; 单通道， 128 / 64 / 32位， I2C ， ± 8 ％电阻容差，非易失性数字电位计
| 型号： | AD5112BCPZ80-1-RL7 |
| 厂家： | 
ADI |
| 描述： | Single-Channel, 128-/64-/32-Position, I2C, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer |
| 文件： | 总28页 (文件大小：517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Channel, 128-/64-/32-Position, I2C, 8%
Resistor Tolerance, Nonvolatile Digital Potentiometer
Data Sheet
AD5110/AD5112/AD5114
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
LOGIC
Single-channel, 128-/64-/32-position resolution
5 kΩ, 10 kΩ, 80 kΩ nominal resistance
Maximum 8ꢀ nominal resistor tolerance error
Low wiper resistance
AD5110/AD5112/AD5114
POWER-ON
RESET
A
6 mA maximum wiper current density
Resistor tolerance stored in EEPROM (0.1ꢀ accuracy)
Rheostat mode temperature coefficient: 35 ppm/°C
Potentiometer mode temperature coefficient: 5 ppm/°C
2.3 V to 5.5 V single-supply operation
1.8 V to 5.5 V logic supply operation
W
B
DATA
DATA
EEPROM
SDA
SCL
2
I C
SERIAL
INTERFACE
RDAC
REGISTER
Power-on EEPROM refresh time < 50 μs
I2C-compatible interface
GND
Figure 1.
Wiper setting and EEPROM readback
50-year typical data retention at 125°C
1 million write cycles
Wide operating temperature: −40°C to +125°C
Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package
APPLICATIONS
Mechanical potentiometer replacement
Portable electronics level adjustment
Audio volume control
Low resolution DAC
LCD panel brightness and contrast control
Programmable voltage to current conversion
Programmable filters, delays, time constants
Feedback resistor programmable power supply
Sensor calibration
GENERAL DESCRIPTION
The AD5110/AD5112/AD5114 provide a nonvolatile solution
for 128-/64-/32-position adjustment applications, offering
guaranteed low resistor tolerance errors of 8% and up to
6 mA current density in the A, B, and W pins. The low resistor
tolerance, low nominal temperature coefficient and high
bandwidth simplify open-loop applications, as well as tolerance
matching applications.
The AD5110/AD5112/AD5114 are available in a 2 mm × 2 mm
LFCSP package. The parts are guaranteed to operate over the
extended industrial temperature range of −40°C to +125°C.
Table 1. 8% Resistance Tolerance Family
Model
Resistance (kΩ)
Position
128
128
64
64
64
Interface
I2C
Up/down
I2C
Up/down
Push-button
I2C
AD5110
AD5111
AD5112
AD5113
AD5116
AD5114
AD5115
10, 80
10, 80
5, 10, 80
5, 10, 80
5, 10, 80
10, 80
The new low wiper resistance feature minimizes the wiper
resistance in the extremes of the resistor array to only 45 Ω,
typical.
The wiper settings are controllable through an I2C-compatible
digital interface that is also used to readback the wiper register
and EEPROM content. Resistor tolerance is stored within
EEPROM, providing an end-to-end tolerance accuracy of 0.1%.
32
32
10, 80
Up/down
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
AD5110/AD5112/AD5114
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 19
RDAC Register and EEPROM.................................................. 19
I2C Serial Data Interface............................................................ 19
Input Shift Register .................................................................... 20
Write Operation.......................................................................... 21
EEPROM Write Acknowlegde Polling .................................... 23
Read Operation........................................................................... 23
Reset............................................................................................. 23
Shutdown Mode ......................................................................... 23
RDAC Architecture.................................................................... 24
Programming the Variable Resistor......................................... 24
Programming the Potentiometer Divider............................... 25
Terminal Voltage Operating Range ......................................... 26
Power-Up Sequence ................................................................... 26
Layout and Power Supply Biasing............................................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—AD5110 .......................................... 3
Electrical Characteristics—AD5112 .......................................... 5
Electrical Characteristics—AD5114 .......................................... 7
Interface Timing Specifications.................................................. 9
Shift Register and Timing Diagram......................................... 10
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 13
Test Circuits..................................................................................... 18
REVISION HISTORY
10/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
AD5110/AD5112/AD5114
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5110
10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
N
R-INL
7
−2.5
−1
−0.5
−1
Bits
LSB
LSB
LSB
LSB
%
ppm/°C
Ω
Ω
Resistor Integral Nonlinearity2
RAB = 10 kΩ, VDD = 2.3 V to 2.7 V
RAB = 10 kΩ, VDD = 2.7 V to 5.5 V
RAB = 80 kΩ
0.5
0.25
0.1
+2.5
+1
+0.5
+1
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance
R-DNL
0.25
ΔRAB/RAB
−8
+8
(ΔRAB/RAB)/ΔT × 106 Code = full scale
35
70
45
70
RW
RBS
RTS
Code = zero scale
Code = bottom scale
Code = top scale
140
80
140
Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4
Differential Nonlinearity4
Full-Scale Error
INL
DNL
VWFSE
−0.5
−0.5
−2.5
−1.5
0.15
0.15
+0.5
+0.5
LSB
LSB
RAB = 10 kΩ
RAB = 80 kΩ
LSB
LSB
Zero-Scale Error
VWZSE
RAB = 10 kΩ
RAB = 80 kΩ
Code = half scale
1.5
0.5
LSB
LSB
ppm/°C
(ΔVW/VW)/ΔT × 106
10
Voltage Divider Temperature Coefficient3
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW
RAB = 10 kΩ
RAB = 80 kΩ
−6
−1.5
GND
+6
+1.5
VDD
mA
mA
V
Current3
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
CW
f = 1 MHz, measured to GND,
code = half scale,
VW = VA = 2.5 V or VW = VB = 2.5 V
f = 1 MHz, measured to GND,
code = half scale, VA = VB = 2.5 V
20
pF
Capacitance W3
35
15
pF
Common-Mode Leakage Current3
VA = VW = VB
−500
+500
nA
DIGITAL INPUTS
Input Logic3
High
VINH
VINL
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
V
V
V
V
Low
0.2 × VLOGIC
0.3 × VLOGIC
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUT (SDA)
Output Low Voltage3
VHYST
IN
0.1 × VLOGIC
V
1
μA
pF
CIN
5
2
VOL
ISINK = 3 mA
ISINK = 6 mA
0.2
0.4
+1
V
V
μA
pF
Three-State Leakage Current
Three-State Output Capacitance3
−1
Rev. 0 | Page 3 of 28
AD5110/AD5112/AD5114
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
Logic Supply Range
Positive Supply Current
EEMEM Store Current3, 6
EEMEM Read Current3, 7
Logic Supply Current
Power Dissipation8
2.3
1.8
5.5
VDD
V
V
IDD
VDD = 5 V
750
2
nA
mA
μA
nA
μW
IDD_NVM_STORE
IDD_NVM_READ
ILOGIC
PDISS
PSR
320
30
5
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
∆VDD/∆VSS = 5 V 10%
RAB = 10 kΩ
Power Supply Rejection3
−50
−64
dB
dB
RAB = 80 kΩ
DYNAMIC CHARACTERISTICS3, 9
Bandwidth
BW
Code = half scale, −3 dB
RAB = 10 kΩ
2
MHz
kHz
RAB = 80 kΩ
200
Total Harmonic Distortion
VW Settling Time
THD
VA = VDD/2 +1 V rms, VB = VDD/2,
f = 1 kHz, code = half scale
RAB = 10 kΩ
RAB = 80 kΩ
VA = 5 V, VB = 0 V,
0.5 LSB error band
−80
−85
dB
dB
ts
RAB = 10 kΩ
RAB = 80 kΩ
3
μs
μs
12
Resistor Noise Density
eN_WB
Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 10 kΩ
RAB = 80 kΩ
9
20
nV/√Hz
nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance10
TA = 25°C
1
MCycles
kCycles
Years
100
Data Retention11
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.
7 Different from operating current; supply current for NVM read lasts approximately 20 μs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V.
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev. 0 | Page 4 of 28
Data Sheet
AD5110/AD5112/AD5114
ELECTRICAL CHARACTERISTICS—AD5112
5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
N
R-INL
6
−2.5
−1
−1
−0.25
+1
Bits
LSB
LSB
LSB
LSB
LSB
%
ppm/°C
Ω
Ω
Resistor Integral Nonlinearity2
RAB = 5 kΩ, VDD = 2.3 V to 2.7 V
RAB = 5 kΩ, VDD = 2.7 V to 5.5 V
RAB = 10 kΩ
0.5
+2.5
+1
+1
+0.25
+1
0.25
0.25
0.1
RAB = 80 kΩ
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance
R-DNL
0.25
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
RBS
RTS
−8
+8
Code = full scale
Code = zero scale
Code = bottom scale
Code = top scale
35
70
45
70
140
80
140
Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4
Differential Nonlinearity4
Full-Scale Error
INL
DNL
VWFSE
−0.5
−0.5
−2.5
−1.5
−1
0.15
0.15
+0.5
+0.5
LSB
LSB
RAB = 5 kΩ
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
RAB =10 kΩ
RAB = 80 kΩ
RAB = 5 kΩ
RAB =10 kΩ
RAB = 80 kΩ
Code = half scale
Zero-Scale Error
VWZSE
1.5
1
0.25
(ΔVW/VW)/ΔT × 106
10
Voltage Divider Temperature Coefficient3
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW
RAB = 5 kΩ, 10 kΩ
RAB = 80 kΩ
−6
−1.5
GND
+6
+1.5
VDD
mA
mA
V
Current3
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
CW
f = 1 MHz, measured to GND,
code = half scale, VW = VA =
2.5 V or VW = VB = 2.5 V
f = 1 MHz, measured to GND,
code = half scale,
VA = VB = 2.5 V
VA = VW = VB
20
35
15
pF
Capacitance W3
pF
Common-Mode Leakage Current3
−500
+500
nA
DIGITAL INPUTS
Input Logic3
High
VINH
VINL
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
V
V
V
V
Low
0.2 × VLOGIC
0.3 × VLOGIC
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUT (SDA)
Output Low Voltage3
VHYST
IN
0.1 × VLOGIC
V
1
μA
pF
CIN
5
2
VOL
ISINK = 3 mA
ISINK = 6 mA
0.2
0.4
+1
V
V
μA
pF
Three-State Leakage Current
Three-State Output Capacitance3
−1
Rev. 0 | Page 5 of 28
AD5110/AD5112/AD5114
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ1
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
Logic Supply Range
Positive Supply Current
EEMEM Store Current3, 6
EEMEM Read Current3, 7
Logic Supply Current
Power Dissipation8
2.3
1.8
5.5
VDD
V
V
IDD
VDD = 5 V
750
2
nA
mA
μA
nA
μW
IDD_NVM_STORE
IDD_NVM_READ
ILOGIC
PDISS
PSR
320
30
5
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
∆VDD/∆VSS = 5 V 10%
RAB = 5 kΩ
RAB =10 kΩ
RAB = 80 kΩ
Power Supply Rejection3
−43
−50
−64
dB
dB
dB
DYNAMIC CHARACTERISTICS3, 9
Bandwidth
BW
Code = half scale − 3 dB
RAB = 5 kΩ
4
2
200
MHz
MHz
kHz
RAB = 10 kΩ
RAB = 80 kΩ
Total Harmonic Distortion
THD
VA = VDD/2 + 1 V rms,
VB = VDD/2, f = 1 kHz,
code = half scale
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
VA = 5 V, VB = 0 V,
0.5 LSB error band
−75
−80
−85
dB
dB
dB
μs
VW Settling Time
ts
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
2.5
3
10
μs
μs
μs
Resistor Noise Density
eN_WB
Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 5 kΩ
RAB = 10 kΩ
RAB = 80 kΩ
7
9
20
nV/√Hz
nV/√Hz
nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance10
TA = 25°C
1
MCycles
kCycles
Years
100
Data Retention11
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.
7 Different from operating current; supply current for NVM read lasts approximately 20 μs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V.
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev. 0 | Page 6 of 28
Data Sheet
AD5110/AD5112/AD5114
ELECTRICAL CHARACTERISTICS—AD5114
10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ1 Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
N
R-INL
R-DNL
5
Bits
LSB
LSB
%
ppm/°C
Ω
Resistor Integral Nonlinearity2
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance
−0.5
−0.25
−8
+0.5
+0.25
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
RBS
RTS
+8
35
Code = full scale
Code = zero scale
Code = bottom scale
Code = top scale
70
45
70
140
80
140
Ω
Ω
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity4
Differential Nonlinearity4
Full-Scale Error
INL
DNL
VWFSE
−0.25
−0.25
−1
+0.25
+0.25
LSB
LSB
RAB = 10 kΩ
LSB
RAB = 80 kΩ
−0.5
LSB
Zero-Scale Error
VWZSE
RAB = 10 kΩ
1
LSB
RAB = 80 kΩ
Code = half scale
0.25
LSB
ppm/°C
(ΔVW/VW)/ΔT × 106
10
Voltage Divider Temperature Coefficient3
RESISTOR TERMINALS
Maximum Continuous IA, IB, and IW
RAB = 10 kΩ
RAB = 80 kΩ
−6
−1.5
GND
+6
+1.5
VDD
mA
mA
V
Current3
Terminal Voltage Range5
Capacitance A, Capacitance B3
CA, CB
CW
f = 1 MHz, measured to GND,
code = half scale, VW = VA =
2.5 V or VW = VB = 2.5 V
f = 1 MHz, measured to
GND, code = half scale, VA =
VB = 2.5 V
20
35
pF
Capacitance W3
pF
Common-Mode Leakage Current3
VA = VW = VB
−500
15
+500
nA
DIGITAL INPUTS
Input Logic3
High
VINH
VINL
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
VLOGIC = 1.8 V to 2.3 V
VLOGIC = 2.3 V to 5.5 V
0.8 × VLOGIC
0.7 × VLOGIC
V
V
V
V
Low
0.2 × VLOGIC
0.3 × VLOGIC
Input Hysteresis3
Input Current3
Input Capacitance3
DIGITAL OUTPUT (SDA)
Output Low Voltage3
VHYST
IN
0.1 × VLOGIC
V
1
μA
pF
CIN
5
2
VOL
ISINK = 3 mA
ISINK = 6 mA
0.2
0.4
+1
V
V
μA
pF
Three-State Leakage Current
Three-State Output Capacitance3
−1
Rev. 0 | Page 7 of 28
AD5110/AD5112/AD5114
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ1 Max
Unit
POWER SUPPLIES
Single-Supply Power Range
Logic Supply Range
Positive Supply Current
EEMEM Store Current3, 6
EEMEM Read Current3,7
Logic Supply Current
Power Dissipation8
2.3
1.8
5.5
VDD
V
V
IDD
VDD = 5 V
750
2
nA
mA
μA
nA
μW
IDD_NVM_STORE
IDD_NVM_READ
ILOGIC
PDISS
PSR
320
30
5
VIH = VLOGIC or VIL = GND
VIH = VLOGIC or VIL = GND
∆VDD/∆VSS = 5 V 10%
RAB = 10 kΩ
Power Supply Rejection3
−50
−64
dB
dB
RAB = 80 kΩ
DYNAMIC CHARACTERISTICS3, 9
Bandwidth
BW
Code = half scale, −3 dB
RAB = 10 kΩ
2
200
MHz
kHz
RAB = 80 kΩ
Total Harmonic Distortion
THD
VA = VDD/2 + 1 V rms,
VB = VDD/2, f = 1 kHz,
code = half scale
RAB = 10 kΩ
RAB = 80 kΩ
−80
−85
dB
dB
VW Settling Time
ts
VA = 5 V, VB = 0 V, 0.5 LSB
error band
RAB = 10 kΩ
RAB = 80 kΩ
μs
μs
2.7
9.5
Resistor Noise Density
eN_WB
Code = half scale, TA = 25°C,
f = 100 kHz
RAB = 10 kΩ
RAB = 80 kΩ
9
20
nV/√Hz
nV/√Hz
FLASH/EE MEMORY RELIABILITY3
Endurance10
TA = 25°C
1
MCycles
kCycles
Years
100
Data Retention11
50
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × VDD/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Different from operating current; supply current for NVM program lasts approximately 30 ms.
7 Different from operating current; supply current for NVM read lasts approximately 20 μs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V.
10 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
Rev. 0 | Page 8 of 28
Data Sheet
AD5110/AD5112/AD5114
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Test Conditions/
Comments
Parameter1
Min
Typ
Max
100
400
Unit
kHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
µs
Description
2
fSCL
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Serial clock frequency
t1
t2
t3
t4
t5
t6
t7
4.0
0.6
4.7
1.3
250
100
0
tHIGH, SCL high time
tLOW, SCL low time
tSU;DAT, data setup time
3.45
0.9
tHD;DAT, data hold time
0
4.7
0.6
4
0.6
4.7
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time (repeated) start condition
tBUF, bus free time between a stop and a start
condition
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Fast mode
1.3
4
0.6
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
µs
t8
tSU;STO, setup time for stop condition
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
t9
1000
300
300
300
1000
300
1000
300
300
300
50
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
20 + 0.1 CL
t10
t11
t11A
t12
tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit.
tFCL, fall time of SCL signal
20 + 0.1 CL
0
3
tSP
Pulse width of suppressed spike
Memory program time
4
tEEPROM_PROGRAM
15
50
5
tPOWER_UP
tRESET
50
25
Power-on EEPROM restore time
Reset EEPROM restore time
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.
4 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
5 Maximum time after VDD is equal to 2.3 V.
Rev. 0 | Page 9 of 28
AD5110/AD5112/AD5114
Data Sheet
SHIFT REGISTER AND TIMING DIAGRAM
DB7 (MSB)
D7
DB0 (LSB)
D0
D1
C1
C0
D6
D5
D4
D3
0
0
0
0
0
C2
D2
DATA BITS
CONTROL BITS
Figure 2. Input Register Content
t11
t12
t6
t2
t6
SCL
SDA
t1
t5
t10
t8
t4
t3
t9
t7
P
S
S
P
Figure 3. 2-Wire Serial Interface Timing Diagram
Rev. 0 | Page 10 of 28
Data Sheet
AD5110/AD5112/AD5114
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
VDD to GND
VLOGIC to GND
VA, VW, VB to GND
IA, IW, IB
Rating
–0.3 V to +7.0 V
–0.3 V to +7.0 V
GND − 0.3 V to VDD + 0.3 V
Pulsed1
THERMAL RESISTANCE
Frequency > 10 kHz
θJA is defined by JEDEC specification JESD-51, and the value is
dependent on the test board and test environment.
RAW = 5 kΩ and 10 kΩ
RAW = 80 kΩ
6 mA/d2
1.5 mA/d2
Table 7. Thermal Resistance
Package Type
Frequency ≤ 10 kHz
RAW = 5 kΩ and 10 kΩ
RAW = 80 kΩ
6 mA/√d2
1.5 mA/√d2
θJA
θJC
Unit
8-Lead LFCSP
901
25
°C/W
Continuous
1 JEDEC 2S2P test board, still air (0 m/sec air flow).
RAW = 5 kΩ and 10 kΩ
RAW = 80 kΩ
Digital Inputs SDA and SCL
6 mA
1.5 mA
ESD CAUTION
−0.3 V to +7 V or VLOGIC + 0.3 V
(whichever is less)
−40°C to +125°C
Operating Temperature Range3
Maximum Junction Temperature (TJ Max) 150°C
Storage Temperature Range
Reflow Soldering
−65°C to +150°C
Peak Temperature
260°C
Time at Peak Temperature
Package Power Dissipation
20 sec to 40 sec
(TJ max − TA)/θJA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Pulse duty factor.
3 Includes programming of EEPROM memory.
Rev. 0 | Page 11 of 28
AD5110/AD5112/AD5114
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
6
5
V
LOGIC
DD
AD5110/
AD5112/
AD5114
A
SDA
SCL
GND
W
B
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD IS INTERNALLY FLOATING.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD
Positive Power Supply; 2.3 V to 5.5 V. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF
capacitors.
2
3
4
5
6
A
W
B
GND
SCL
Terminal A of RDAC. GND ≤ VA ≤ VDD.
Wiper Terminal of RDAC. GND ≤ VW ≤ VDD.
Terminal B of RDAC. GND ≤ VB ≤ VDD.
Ground Pin, Logic Ground Reference.
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit input
registers.
7
8
SDA
Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input
registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up
resistor.
Logic Power Supply; 1.8 V to VDD. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF
capacitors.
VLOGIC
EPAD
Exposed Pad. The exposed pad is internally floating.
Rev. 0 | Page 12 of 28
Data Sheet
AD5110/AD5112/AD5114
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0.02
0.01
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0.08
0.06
0.04
0.02
0
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.02
–0.04
–0.06
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
CODE (Decimal)
CODE (Decimal)
Figure 5. R-INL vs. Code (AD5110)
Figure 8. R-DNL vs. Code (AD5110)
0.08
0.06
0.04
0.02
0
0.02
5kΩ, –40°C
5kΩ, +25°C
5kΩ, +125°C
5kΩ, –40°C
5kΩ, +25°C
0.01
0
5kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.02
–0.04
–0.06
10kΩ, +125°C
80kΩ, +125°C
10kΩ, –40°C
80kΩ, –40°C
10kΩ, +25°C
80kΩ, +25°C
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal)
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal)
Figure 6. R-INL vs. Code (AD5112)
Figure 9. R-DNL vs. Code (AD5112)
0.020
0.015
0.010
0.005
0
0.004
0.002
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0
–0.002
–0.004
–0.006
–0.008
–0.010
–0.012
–0.014
–0.016
–0.018
–0.005
–0.010
–0.015
10kΩ, –40°C
80kΩ, –40°C
10kΩ, +25°C
80kΩ, +25°C
10kΩ, +125°C
80kΩ, +125°C
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 31
CODE (Decimal)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 31
CODE (Decimal)
Figure 10. R-DNL vs. Code (AD5114)
Figure 7. R-INL vs. Code (AD5114)
Rev. 0 | Page 13 of 28
AD5110/AD5112/AD5114
Data Sheet
0.08
0.06
0.04
0.02
0
0.02
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.02
–0.04
–0.06
–0.08
10kΩ, –40°C
80kΩ, –40°C
10kΩ, +25°C
80kΩ, +25°C
10kΩ, +125°C
80kΩ, +125°C
–0.07
CODE (Decimal)
CODE (Decimal)
Figure 11. INL vs. Code (AD5110)
Figure 14. DNL vs. Code (AD5110)
0.08
0.06
0.04
0.02
0
0.02
5kΩ, –40°C
5kΩ, +25°C
5kΩ, +125°C
10kΩ, +125°C
5kΩ, –40°C
10kΩ, –40°C
10kΩ, +25°C
5kΩ, +25°C
0.01
0
5kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.02
–0.04
–0.06
–0.08
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal)
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
CODE (Decimal)
Figure 12. INL vs. Code (AD5112)
Figure 15. DNL vs. Code (AD5112)
0.004
0.002
0.015
0.010
0.005
0
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
80kΩ, –40°C
80kΩ, +25°C
80kΩ, +125°C
0
–0.002
–0.004
–0.006
–0.008
–0.010
–0.012
–0.014
–0.016
–0.005
–0.010
–0.015
–0.020
80kΩ, +25°C
80kΩ, –40°C
80kΩ, +125°C
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 31
CODE (Decimal)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 31
CODE (Decimal)
Figure 13. INL vs. Code (AD5114)
Figure 16. DNL vs. Code (AD5114)
Rev. 0 | Page 14 of 28
Data Sheet
AD5110/AD5112/AD5114
0.12
0.10
0.08
0.06
0.04
0.02
0
800
700
600
500
400
300
V
V
V
V
= 5.0V
= 3.3V
= 2.3V
= 1.8V
LOGIC
LOGIC
LOGIC
LOGIC
200
100
0
2.3V AVERAGE OF I
2.3V AVERAGE OF I
3.3V AVERAGE OF I
3.3V AVERAGE OF I
5.0V AVERAGE OF I
5.0V AVERAGE OF I
DD
LOGIC
DD
LOGIC
DD
LOGIC
–100
–40 –25 –10
–0.02
5
20
35
50
65
80
95 110 125
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TEMPERATURE (°C)
DIGITAL INPUT VOLTAGE (V)
Figure 17. Supply Current vs. Temperature
Figure 20. Supply Current (ILOGIC) vs. Digital Input Voltage
200
200
180
160
140
120
100
80
V
= 5V
V
= 5V
DD
DD
180
160
140
120
100
80
10kΩ
80kΩ
5kΩ
10kΩ
80kΩ
5kΩ
60
60
40
40
20
20
0
0
0
0
0
20
10
5
40
20
10
60
30
15
80
40
20
100
50
25
120 AD5110
60 AD5112
30 AD5114
0
0
0
20
10
5
40
20
10
60
30
15
80
40
20
100
50
25
120 AD5110
60 AD5112
30 AD5114
CODE (Decimal)
CODE (Decimal)
Figure 18. Potentiometer Mode Tempco ((ΔVW/VW)/ΔT × 106) vs. Code
Figure 21. Rheostat Mode Tempco ((ΔRWB/RWB)/ΔT × 106) vs. Code
0
0
(0x20) [0x10]
(0x10) [0x08]
0x40
–10 0x20
0x10
0x20
–10
–20
–30
–40
–50
–60
0x10
0x08
(0x08) [0x04]
(0x04) [0x02]
(0x02) [0x01]
–20
0x08
0x04
0x02
0x01
0x04
–30
(0x01) [0x00]
(0x00)
0x02
0x01
–40
0x00
–50
0x00
–60
AD5110 (AD5112) [AD5114]
–70
10k
10k
100k
1M
10M
100M
100k
FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 22. 10 kΩ Gain vs. Frequency vs. Code
Figure 19. 5 kΩ Gain vs. Frequency vs. Code
Rev. 0 | Page 15 of 28
AD5110/AD5112/AD5114
Data Sheet
0
80
70
60
50
40
30
20
10
0
(0x20) [0x10]
0x40
5k + 250pF
10k + 75pF
10k + 150pF
10k + 250pF
80k + 0pF
80k + 150pF
80k + 250pF
5k + 0pF
(0x10) [0x08]
(0x08) [0x04]
–10
–20
–30
–40
–50
–60
–70
–80
0x20
0x10
5k + 75pF
5k + 150pF
10k + 0pF
80k + 75pF
(0x04) [0x02]
(0x02) [0x01]
(0x01) [0x00]
(0x00)
0x08
0x04
0x02
0x01
0x00
AD5110 (AD5112) [AD5114]
10k
0
0
0
10
5
20
10
5
30
15
40
20
10
50
25
60
30
15
AD5110
AD5112
AD5114
100k
1M
FREQUENCY (Hz)
CODE (Decimal)
Figure 23. 80 kΩ Gain vs. Frequency vs. Code
Figure 26. Maximum Bandwidth vs. Code vs. Net Capacitance
150
0
–10
–20
–30
–40
–50
–60
–70
–80
5.5V
5V
3.3V
2.7V
2.3V
TEMPERATURE = 25°C
120
90
60
30
0
AD5110
= 10kΩ
R
AB
FULL SCALE
HALF SCALE
QUARTER SCALE
10k
100k
1M
10M
0
1
2
3
4
5
6
FREQUENCY (Hz)
V
(V)
DD
Figure 24. Normalized Phase Flatness vs. Frequency
Figure 27. Incremental Wiper On Resistance vs. VDD
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
V
V
= 5V,
V
V
V
= 5V,
5kΩ
10kΩ
80kΩ
5kΩ
10kΩ
80kΩ
DD
A
B
DD
A
= 2.5V + 1V
= 2.5V
= 2.5V + V
= 2.5V
RMS
IN
–10
–20
–30
–40
–50
–60
–70
–80
–90
fINB = 1kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
20
200
2k
20k
200k
0.001
0.01
0.1
1
FREQUENCY (Hz)
AMPLITUDE (V rms)
Figure 28. Total Harmonic Distortion + Noise (THD + N) vs. Amplitude
Figure 25. Total Harmonic Distortion + Noise (THD + N) vs. Frequency
Rev. 0 | Page 16 of 28
Data Sheet
AD5110/AD5112/AD5114
0.4
0.3
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
V
V
= 5V
V
V
V
= 5V
DD
DD
A
= V
= V
DD
A
DD
= GND
= GND
B
B
5kΩ
10kΩ
80kΩ
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
10kΩ
80kΩ
5kΩ
–0.05
–0.10
–1
0
0.6
1.2
1.8
2.5
1
3
5
7
9
TIME (µs)
TIME (µs)
Figure 29. Maximum Transition Glitch
Figure 32. Digital Feedthrough
0.0025
0.0020
0.0015
0.0010
0.0005
0
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–10
–20
–30
–40
–50
–60
–70
5kΩ
10kΩ
80kΩ
–600 –500 –400 –300 –200 –100
0
100 200 300 400 500 600
1k
10k
FREQUENCY (Hz)
1M
10M
RESISTOR DRIFT (ppm)
Figure 30. Resistor Lifetime Drift
Figure 33. Shutdown Isolation vs. Frequency
7
6
5
4
3
2
1
0
0
5kΩ
10kΩ
80kΩ
10kΩ
80kΩ
5kΩ
–10
–20
–30
–40
–50
–60
–70
V
V
V
= 5V ± 10% AC
= GND
DD
= 4V
A
B
HALF SCALE
T
= 25°C
A
10
100
1k
10k
100k
1M
0
0
0
20
10
5
40
20
10
60
30
15
80
40
20
100
50
25
120 AD5110
60 AD5112
30 AD5114
FREQUENCY (Hz)
CODE (Decimal)
Figure 34. Theoretical Maximum Current vs. Code
Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency
Rev. 0 | Page 17 of 28
AD5110/AD5112/AD5114
Data Sheet
TEST CIRCUITS
Figure 35 to Figure 40 define the test conditions used in the Specifications section.
NC
DUT
A
I
V
W
A
V+ = V ± 10%
DD
W
ΔV
ΔV
MS
DD
V
A
B
DD
PSRR (dB) = 20 log
B
W
V+
~
V
ΔV
ΔV
%
%
MS
MS
DD
PSS (%/%) =
V
MS
NC = NO CONNECT
Figure 35. Resistor Position Nonlinearity Error
(Rheostat Operation: R-INL, R-DNL)
Figure 38. Power Supply Sensitivity (PSS, PSRR)
+15V
A
DUT
A
V+ = V
DD
1LSB = V+/2
W
V
N
IN
DUT
AD8652
V
OUT
W
B
V+
OFFSET
GND
B
V
MS
2.5V
–15V
Figure 36. Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 39. Gain and Phase vs. Frequency
GND
V
DD
NC
0.1V
=
R
W
DUT
GND
I
WB
A
A
B
V
I
DD
CM
W
DUT
W
+
B
0.1V
I
WB
GND
–
V
DD
GND TO V
DD
NC = NO CONNECT
GND
V
DD
Figure 37. Wiper Resistance
Figure 40. Common-Mode Leakage Current
Rev. 0 | Page 18 of 28
Data Sheet
AD5110/AD5112/AD5114
THEORY OF OPERATION
I2C SERIAL DATA INTERFACE
The AD5110/AD5112/AD5114 digital programmable resistors
are designed to operate as true variable resistors for analog
The AD5110/AD5112/AD5114 have 2-wire I2C-compatible
serial interfaces. These devices can be connected to an I2C bus
as a slave device under the control of a master device. See
Figure 3 for a timing diagram of a typical write sequence.
signals within the terminal voltage range of GND < VTERM
<
VDD. The resistor wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratchpad
register that allows unlimited changes of resistance settings.
The AD5110/AD5112/AD5114 support standard (100 kHz) and
fast (400 kHz) data transfer modes. Support is not provided for
10-bit addressing and general call addressing.
The RDAC register can be programmed with any position
setting using the I2C interface. Once a desirable wiper position
is found, this value can be stored in the EEPROM memory.
Thereafter, the wiper position is always restored to that position
for subsequent power-up. The storing of EEPROM data takes
approximately 18 ms; during this time, the device is locked and
does not acknowledge any new command, thus preventing any
changes from taking place.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
and an R/W bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is termed the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x3F (128-taps), the wiper is connected to full scale
of the variable resistor. The RDAC register is a standard logic
register; there is no restriction on the number of changes
allowed.
W
2. If the R/ bit is set high, the master reads from the slave
W
device. However, if the R/ bit is set low, the master writes
It is possible to both write to and read from the RDAC register
using the I2C interface (see Table 10).
to the slave device.
3. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
4. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish
a stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master brings the SDA line low before
the 10th clock pulse, and high during the 10th clock pulse to
establish a stop condition.
The contents of the RDAC register can be stored to the
EEPROM using Command 1 (Table 10). Thereafter, the
RDAC register is always set at that position for any future
on-off-on power supply sequence. It is possible to read back
the data saved into the EEPROM with Command 6 in Table 10.
In addition, the resistor tolerance error is saved within the
EEPROM; this can be read back and used to calculate the end-
to-end tolerance, providing an accuracy of 0.1%.
Low Wiper Resistance Feature
The AD5110/AD5112/AD5114 include extra steps to achieve a
minimum resistance between Terminal W and Terminal A or
Terminal B. These extra steps are called bottom scale and top
scale. At bottom scale, the typical wiper resistance decreases
from 70 Ω to 45 Ω. At top scale, the resistance between
Terminal A and Terminal W is decreased by 1 LSB, and the
total resistance is reduced to 70 Ω. The extra steps are not equal
to 1 LSB and are not included in the INL, DNL, R-INL, and
R-DNL specifications.
I2C Address
The AD5110/AD5112/AD5114 each have two different slave
address options available. See Table 9 for a list of slave addresses.
Table 9. Device Address Selection
Model
AD511X1 BCPZ Y2
AD511X1 BCPZ Y2-1
7-Bit I2C Device Address
0101111
0101100
1 Model.
2 Resistance.
Rev. 0 | Page 19 of 28
AD5110/AD5112/AD5114
Data Sheet
INPUT SHIFT REGISTER
For the AD5110/AD5112/AD5114, the input shift register is
16 bits wide (see Figure 2). The 16-bit word consists of five
unused bits (should be set to zero), followed by three control
bits, and eight RDAC data bits. If the RDAC register is read from
or written to in the AD5112, Bit DB0 is a don’t care. The RDAC
register is read from or written to in the AD5114, Bit DB0 and
DB1 are don’t cares. Data is loaded MSB first (Bit DB15).
The three control bits determine the function of the software
command (Table 10). Figure 3 shows a timing diagram of a
typical AD5110/AD5112/AD5114 write sequence.
The command bits (Cx) control the operation of the digital
potentiometer and the internal EEPROM. The data bits (Dx)
are the values that are loaded into the decoded register.
Table 10. Command Operation Truth Table
Command
Data1
DB10 DB8 DB7
DB0
Command
Number
C2
0
0
C1 C0
D7
X
X
D6 D5 D4 D3 D2 D1 D0
Operation
0
1
2
0
0
1
0
1
0
X
X
6
X
X
5
X
X
4
X
X
3
X
X
2
X
X
12
X
X
02, 3
LSB
No operation
Write contents of RDAC register to EEPROM
Write contents of serial register data to RDAC
0
7
MSB
1
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
A0
Top scale
Bottom scale
Software shutdown
0: shutdown off
1: shutdown on
3
0
1
1
4
5
6
1
1
1
0
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Software reset: refresh RDAC register with EEPROM
Read contents of RDAC register
Read contents of EEPROM
A1 A0
A1
0
0
A0
0
1
Data
Wiper position saved
Resistor tolerance
1 X is don’t care.
2 In the AD5114, this bit is a don’t care.
3 In the AD5112, this bit is a don’t care.
Rev. 0 | Page 20 of 28
Data Sheet
AD5110/AD5112/AD5114
WRITE OPERATION
When writing to the AD5110/AD5112/AD5114, the user
must begin with a start command followed by an address
these data bytes are acknowledged by the AD5110/AD5112/
AD5114. A stop condition follows. The write operations for
the AD5110/AD5112/AD5114 are shown in Figure 41,
Figure 42, and Figure 43.
W
byte (R/ = 0), after which the AD5110/AD5112/AD5114
acknowledge that it is prepared to receive data by pulling
SDA low.
A repeated write function gives the user flexibility to update
the device a number of times after addressing the part only
once, as shown in Figure 44.
Two bytes of data are then written to the DAC, the most
significant byte, followed by the least significant byte. Both of
1
9
1
9
SCL
1
0
0
1
1
A1
A0
R/W
0
0
0
0
0
C1
C0
SDA
START BY
C2
ACK. BY
AD5110
ACK. BY
AD5110
MASTER
FRAME 2
FRAME 1
MOST SIGNIFICANT DATA BYTE
SERIAL BUS ADDRESS BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY STOP BY
MASTER
AD5110
FRAME 3
LEAST SIGNIFICANT DATA BYTE
Figure 41. AD5110 Interface Write Command
1
9
1
0
9
SCL
SDA
1
0
0
1
1
A1
A0
R/W
0
0
0
0
C1
C0
C2
ACK. BY
AD5112
ACK. BY
AD5112
START BY
MASTER
FRAME 2
FRAME 1
MOST SIGNIFICANT DATA BYTE
SERIAL BUS ADDRESS BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D6
D5
D4
D3
D2
D1
D0
0
ACK. BY STOP BY
MASTER
AD5112
FRAME 3
LEAST SIGNIFICANT DATA BYTE
Figure 42. AD5112 Interface Write Command
Rev. 0 | Page 21 of 28
AD5110/AD5112/AD5114
Data Sheet
1
9
1
0
9
SCL
1
0
0
1
1
A1
A0
R/W
0
0
0
0
C1
C0
SDA
START BY
C2
ACK. BY
AD5114
ACK. BY
AD5114
MASTER
FRAME 2
FRAME 1
MOST SIGNIFICANT DATA BYTE
SERIAL BUS ADDRESS BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D5
D4
D3
D2
D1
D0
0
0
ACK. BY STOP BY
MASTER
AD5114
FRAME 3
LEAST SIGNIFICANT DATA BYTE
Figure 43. AD5114 Interface Write Command
1
9
1
0
9
SCL
SDA
1
0
0
1
1
A1
A0
R/W
0
0
0
0
C2
C1
C0
START BY
MASTER
ACK. BY
AD5110
ACK. BY
AD5110
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
AD5110
FRAME 3
LEAST SIGNIFICANT DATA BYTE
9
1
0
9
SCL (CONTINUED)
SDA (CONTINUED)
0
0
0
0
C2
C1
C0
ACK. BY
AD5110
FRAME 4
MOST SIGNIFICANT DATA BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY STOP BY
AD5110 MASTER
FRAME 5
LEAST SIGNIFICANT DATA BYTE
Figure 44. AD5110 Interface Multiple Write
Rev. 0 | Page 22 of 28
Data Sheet
AD5110/AD5112/AD5114
the RDAC register, EEPROM memory. The user can then read
back the data. This begins with a start command followed by an
EEPROM WRITE ACKNOWLEGDE POLLING
After each write operation to the EEPROM, an internal write
cycle begins. The I2C interface of the device is disabled. To
determine if the internal write cycle is complete and the I2C
interface is enabled, interface polling can be executed. I2C
interface polling can be conducted by sending a start condition,
followed by the slave address and the write bit. If the I2C
interface responds with an acknowledge, the write cycle is
complete, and the interface is ready to proceed with further
operations. Otherwise, I2C interface polling can be repeated
until it succeeds.
W
address byte (R/ = 1), after which the device acknowledges
that it is prepared to transmit data by pulling SDA low. Two
bytes of data are then read from the device, which are both
acknowledged by the master, as shown in Figure 45. A stop
condition follows. If the master does not acknowledge the first
byte, then the second byte is not transmitted by the AD5110/
AD5112/AD5114.
The AD5110/AD5112/AD5114 does not support repeat
readback.
RESET
READ OPERATION
The AD5110/AD5112/AD5114 can be reset by executing
Command 4 (see Table 10). The reset command loads the
RDAC register with the contents of the EEPROM and takes
approximately 25 µs. EEPROM is pre-loaded to midscale at the
factory, and initial power-up is, accordingly, at midscale.
The AD5110/AD5112/AD5114 allow read back of the contents
of the RDAC register and EEPROM memory through the I2C
interface by using Command 6 (see Table 10).
When reading data back from the AD5110/AD5112/AD5114,
the user must first issue a readback command to the device.
This begins with a start command, followed by an address
SHUTDOWN MODE
W
byte (R/ = 0), after which the AD5110/AD5112/AD5114
The AD5110/AD5112/AD5114 can be shut down by executing
the software shutdown command, Command 3 (see Table 10).
This feature places the RDAC in a zero-power-consumption
state where Terminal A is open-circuited and the wiper,
Terminal W is connected to Terminal B but a finite wiper
resistance of 45 Ω is present. The part can be taken out of
shutdown mode by executing Command 3 (see Table 10)
and setting Bit DB0 to 0.
acknowledges that it is prepared to receive data by pulling
SDA low.
Two bytes of data are then written to the AD5110/AD5112/
AD5114, the most significant byte followed by the least
significant byte. Both of these data bytes are acknowledged by
the AD5110/AD5112/AD5114. A stop condition follows. These
bytes contain the read instruction, which enables readback of
1
9
1
0
9
SCL
1
0
0
1
1
A1
A0
R/W
0
0
0
0
C1
C0
SDA
START BY
C2
ACK. BY
AD5110
ACK. BY
AD5110
MASTER
FRAME 2
FRAME 1
MOST SIGNIFICANT DATA BYTE
SERIAL BUS ADDRESS BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY STOP BY
MASTER
AD5110
FRAME 3
LEAST SIGNIFICANT DATA BYTE
1
9
1
0
9
SCL
SDA
1
0
0
1
1
A1
A0
R/W
0
0
0
0
C1
C0
C2
ACK. BY
AD5110
NO ACK.
BY MASTER MASTER
STOP BY
START BY
MASTER
FRAME 2
MOST SIGNIFICANT DATA BYTE
FRAME 1
SERIAL BUS ADDRESS BYTE
Figure 45. AD5110 Interface Read Command
Rev. 0 | Page 23 of 28
AD5110/AD5112/AD5114
Data Sheet
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation— 8% Resistor Tolerance
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5110/AD5112/AD5114
employ a two-stage segmentation approach as shown in
Figure 46. The AD5110/AD5112/AD5114 wiper switch is
designed with the transmission gate CMOS topology and with
the gate voltage derived from VDD.
The AD5110/AD5112/AD5114 operate in rheostat mode when
only two terminals are used as a variable resistor. The unused
terminal can be floating or tied to the Terminal W as shown in
Figure 47.
A
A
A
A
W
W
W
TS
B
B
B
R
R
L
Figure 47. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
AB, is available in 5 kꢀ, 10 kꢀ, and 80 kꢀ and has 32/64/128
L
R
tap points accessed by the wiper terminal. The 5-/6-/7-bit data
in the RDAC latch is decoded to select one of the 32/64/128
possible wiper settings. The general equations for determining
the digitally programmed output resistance between the W
terminal and B terminal are
R
R
S
S
W
6-BIT/7-BIT/8-BIT
ADDRESS
AD5110:
DECODER
R
R
RWB RBS
Bottom scale (0xFF) (1)
From 0x00 to 0x80 (2)
L
D
128
R
WB (D)
RAB RW
L
BS
AD5112:
RWB RBS
Bottom scale (0xFF) (3)
From 0x00 to 0x40 (4)
B
D
64
R
WB (D)
RAB RW
Figure 46. AD5110/AD5112/AD5114 Simplified RDAC Circuit
AD5114:
WB RBS
Top Scale/Bottom Scale Architecture
R
Bottom scale (0xFF) (5)
From 0x00 to 0x20 (6)
In addition, the AD5110/AD5112/AD5114 include a new
D
32
R
WB (D) RAB RW
feature to reduce the resistance between terminals. These extra
steps are called bottom scale and top scale. At bottom scale, the
typical wiper resistance decreases from 70 Ω to 45 Ω. At top
scale, the resistance between Terminal A and Terminal W is
decreased by 1 LSB, and the total resistance is reduced to 70 Ω.
The extra steps are not equal to 1 LSB and are not included in
the INL, DNL, R-INL, and R-DNL specifications.
where:
D is the decimal equivalent of the binary code in the 5-/6-/7-bit
RDAC register.
R
AB is the end-to-end resistance.
RW is the wiper resistance.
RBS is the wiper resistance at bottom scale
Rev. 0 | Page 24 of 28
Data Sheet
AD5110/AD5112/AD5114
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, RWA
Table 11. Tolerance Format
Data Byte
.
DB7 DB6 DB5 DB4 DB3
DB2 DB1 DB0
2-1 2-2 2-3
Sign 24
23
22
21
RWA also gives a maximum of 8% absolute resistance error. RWA
.
starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equations for
this operation are
For example, if RAB = 10 kΩ and the data readback shows
01010010, the end-to-end resistance can be calculated as,
if,
AD5110:
DB[7] is 0 = negative
DB[6:3] is 1010 = 10
DB[2:0] is 010 = 2 × 2−3 = 0.25
RAW = RAB + RW
Bottom scale (0xFF) (7)
From 0x00 to 0x7F (8)
Top scale (0x80) (9)
128 − D
128
R
AW (D) =
×RAB + RW
×RAB + RW
×RAB + RW
then,
tolerance = −10.25% and, therefore, RAB = 8.975 kΩ
RAW = RTS
AD5112:
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
RAW = RAB + RW
Bottom scale (0xFF) (10)
From 0x00 to 0x3F (11)
Top scale (0x40) (12)
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input
voltage at A to B, as shown in Figure 48. Unlike the polarity of
64 − D
64
R
AW (D) =
VDD to GND, which must be positive, voltage across A-to-B, W-
to-A, and W-to-B can be at either polarity.
RAW = RTS
AD5114:
V
I
A
B
RAW = RAB + RW
Bottom scale (0xFF) (13)
From 0x00 to 0x1F (14)
Top scale (0x20) (15)
W
V
O
32 − D
32
R
AW (D) =
RAW = RTS
where:
Figure 48. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to Terminal A and Terminal B, is:
D is the decimal equivalent of the binary code in the 5-/6-/7-bit
RDAC register.
R
R
R
AB is the end-to-end resistance.
W is the wiper resistance.
TS is the wiper resistance at top scale.
R
WB(D)
RAB
RAW (D)
RAB
In the bottom-scale condition or top-scale condition, a finite
total wiper resistance of 45 Ω is present. Regardless of which
setting the part is operating in, take care to limit the current
between Terminal A to Terminal B, Terminal W to Terminal A,
and Terminal W to Terminal B, to the maximum continuous
current of 6 mA or to the pulse current specified in Table 6.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
VW (D) =
×VA +
×VB
(16)
where:
R
R
WB(D) can be obtained from Equation 1 to Equation 6.
AW(D) can be obtained from Equation 7 to Equation 15.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RAW and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
Calculating the Actual End-to-End Resistance
The resistance tolerance is stored in the internal memory
during factory testing. The actual end-to-end resistance can,
therefore, be calculated, which is valuable for calibration,
tolerance matching, and precision applications.
The resistance tolerance in percentage is stored in fixed-point
format, using an 8-bit sign magnitude binary. The data can be
read back by executing Command 6 and setting Bit DB0 (A0).
The MSB is the sign bit (0 = − and 1 = +) and the next four bits
are the integer part, the fractional part is represented by the
three LSBs, as shown in Table 11.
Rev. 0 | Page 25 of 28
AD5110/AD5112/AD5114
Data Sheet
of powering VA, VB, VW, and digital inputs is not important as
long as they are powered after VDD and VLOGIC. Regardless of the
power-up sequence and the ramp rates of the power supplies,
once VLOGIC is powered, the power-on preset activates, which
restores EEPROM values to the RDAC registers.
TERMINAL VOLTAGE OPERATING RANGE
The AD5110/AD5112/AD5114 are designed with internal
ESD diodes for protection. These diodes also set the voltage
boundary of the terminal operating voltages. Positive signals
present on Terminal A, Terminal B, or Terminal W that
exceed VDD are clamped by the forward-biased diode. There
is no polarity constraint between VA, VW, and VB, but they
cannot be higher than VDD or lower than GND.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low equivalent series resistance (ESR) 1 μF to 10 μF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and to filter low frequency
ripple. Figure 50 illustrates the basic supply bypassing
V
DD
A
W
B
configuration for the AD5110/AD5112/AD5114.
GND
Figure 49. Maximum Terminal Voltages Set by VDD and GND
AD5110/
AD5112/
AD5114
POWER-UP SEQUENCE
V
V
LOGIC
V
V
LOGIC
DD
DD
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (Figure 49), it is
important to power VDD first before applying any voltage
to Terminal A, Terminal B, and Terminal W. Otherwise,
the diode is forward-biased such that VDD is powered
unintentionally. The ideal power-up sequence is GND,
VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order
+
+
C2
10µF
C1
0.1µF
C3
0.1µF
C4
10µF
GND
Figure 50. Power Supply Bypassing
Rev. 0 | Page 26 of 28
Data Sheet
AD5110/AD5112/AD5114
OUTLINE DIMENSIONS
1.70
1.60
1.50
2.00
BSC SQ
0.50 BSC
8
5
PIN 1 INDEX
EXPOSED
PAD
1.10
1.00
0.90
AREA
0.425
0.350
0.275
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.60
0.55
0.50
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 51. 8-Lead Frame Chip Scale Package[LFCSP_UD]
2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead
(CP-8-10)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
RAB (kΩ) Resolution Range
Package
Description
Package
Option
Model1
I2C Address
0101111
0101111
0101100
0101111
0101111
0101100
0101111
0101111
0101100
0101111
0101111
0101100
0101111
0101111
0101100
0101111
0101111
0101100
0101111
0101111
0101100
Branding
4J
4J
4H
4L
4L
AD5110BCPZ10-RL7
AD5110BCPZ10-500R7
AD5110BCPZ10-1-RL7
AD5110BCPZ80-RL7
AD5110BCPZ80-500R7
AD5110BCPZ80-1-RL7
AD5112BCPZ5-RL7
AD5112BCPZ5-500R7
AD5112BCPZ5-1-RL7
AD5112BCPZ10-RL7
AD5112BCPZ10-500R7
AD5112BCPZ10-1-RL7
AD5112BCPZ80-RL7
AD5112BCPZ80-500R7
AD5112BCPZ80-1-RL7
AD5114BCPZ10-RL7
AD5114BCPZ10-500R7
AD5114BCPZ10-1-RL7
AD5114BCPZ80-RL7
AD5114BCPZ80-500R7
AD5114BCPZ80-1-RL7
EVAL-AD5110SDZ
10
10
10
80
80
80
5
128
128
128
128
128
128
64
64
64
64
64
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_UD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
Evaluation Board
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
CP-8-10
4K
7P
7P
7N
7L
7L
7K
7R
7R
7Q
81
5
5
10
10
10
80
80
80
10
10
10
80
80
80
64
64
64
64
32
32
32
32
32
32
81
80
83
83
82
1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
AD5110/AD5112/AD5114
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09582-0-10/11(0)
Rev. 0 | Page 28 of 28
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明