AD5161BRM100 [ADI]
256-Position SPI/I2C Selectable Digital Potentiometer; 256位SPI / I2C可选的数字电位计
| 型号： | AD5161BRM100 |
| 厂家： | 
ADI |
| 描述： | 256-Position SPI/I2C Selectable Digital Potentiometer |
| 文件： | 总20页 (文件大小：927K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256-Position SPI/I2C Selectable
Digital Potentiometer
AD5161
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
SDO/NC
DD
256-position
SDI/SDA
CLK/SCL
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Pin selectable SPI/I2C compatible interface
Extra package address decode pin AD0
Full read/write of wiper register
A
2
SPI OR I C
INTERFACE
DIS
W
B
CS/AD0
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
WIPER
REGISTER
Low temperature coefficient 45 ppm/°C
Low power, IDD = 8 µA
GND
Wide operating temperature –40°C to +125°C
SDO output allows multiple device daisy-chaining
Evaluation board available
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement in new designs
PIN CONFIGURATION
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
1
2
3
4
5
10
9
8
7
6
A
B
W
V
DIS
GND
CLK/SCL
AD5161
DD
CS/ADO
SDO/NC
SDI/SDA
TOP VIEW
(Not to Scale)
Figure 2.
GENERAL OVERVIEW
The AD5161 provides a compact 3 mm × 4.9 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.
The wiper settings are controllable through a pin selectable SPI
or I2C compatible digital interface, which can also be used to
read back the wiper register content. When the SPI mode is
used, the device can be daisy-chained (SDO to SDI), allowing
several parts to share the same control lines. In the I2C mode,
address pin AD0 can be used to place up to two devices on the
same bus. In this same mode, command bits are available to
reset the wiper position to midscale or to shut down the device
into a state of zero power consumption.
Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed
Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 µA allows for usage in portable battery-operated
applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD5161
TABLE OF CONTENTS
Electrical Characteristics—5 kΩ Version ...................................... 3
Level Shifting for Bidirectional Interface................................ 17
ESD Protection ........................................................................... 17
Terminal Voltage Operating Range.......................................... 17
Power-Up Sequence ................................................................... 17
Layout and Power Supply Bypassing ....................................... 17
Pin Configuration and Function Descriptions........................... 18
Pin Configuration ...................................................................... 18
Pin Function Descriptions ........................................................ 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
ESD Caution................................................................................ 19
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4
Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions 5
Absolute Maximum Ratings1 .......................................................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 11
SPI Interface .................................................................................... 12
I2C Interface..................................................................................... 13
Operation......................................................................................... 14
Programming the Variable Resistor ......................................... 14
Programming the Potentiometer Divider............................... 15
Pin Selectable Digital Interface................................................. 15
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5161
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
(VDD = 5 V 10%, or 3 V 10%ꢀ VA = +VDDꢀ VB = 0 Vꢀ –40°C < TA < +125°Cꢀ unless otherwise noted.)
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB
∆RAB/∆T
RW
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
–1.5
–4
–30
0.1
0.ꢀ5 +4
+1.5
LSB
LSB
%
ppm/°C
Ω
+30
VAB = VDD, Wiper = no connect
45
50
120
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
∆VW/∆T
VWFSE
VWZSE
–1.5
–1.5
0.1
0.ꢁ
15
–2.5
+2
+1.5
+1.5
LSB
LSB
ppm/°C
LSB
LSB
Code = 0x80
Code = 0xFF
Code = 0x00
–ꢁ
0
0
+ꢁ
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
VA,B,W
CA,B
GND
VDD
V
pF
Capacitanceꢁ A, B
f = 1 MHz, measured to GND,
Code = 0x80
f = 1 MHz, measured to GND,
Code = 0x80
45
ꢁ0
Capacitanceꢁ W
CW
pF
Shutdown Supply Currentꢀ
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
IDD_SD
ICM
VDD = 5.5 V
VA = VB = VDD/2
0.01
1
1
µA
nA
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
µA
pF
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitanceꢁ
0.8
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
0.ꢁ
1
CIL
5
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation8
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
8
0.2
V
µA
mW
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
3
Power Supply Sensitivity
PSS
∆VDD = +5 V 10%,
Code = Midscale
0.02
0.05 %/%
DYNAMIC CHARACTERISTICSꢁ, 9
Bandwidth –3dB
BW_5K
THDW
tS
RAB = 5 kΩ, Code = 0x80
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA= 5 V, VB = 0 V, 1 LSB error
band
1.2
0.05
1
MHz
%
µs
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage Density
eN_WB
RWB = 2.5 kΩ, RS = 0
ꢁ
nV/√Hz
Rev. 0 | Page 3 of 20
AD5161
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = 5 V 10%, or 3 V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ –40°C < TA < +125°Cꢀ unless otherwise noted.)
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
VAB = VDD,
Wiper = no connect
–1
–2
–30
0.1
0.25
+1
+2
+30
LSB
LSB
%
∆RAB/∆T
45
50
ppm/°C
Wiper Resistance
RW
VDD = 5 V
120
Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
∆VW/∆T
VWFSE
VWZSE
–1
–1
0.1
0.3
15
–1
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
Code = 0x80
Code = 0xFF
Code = 0x00
–3
0
0
3
Zero-Scale Error
1
RESISTOR TERMINALS
Voltage Range5
VA,B,W
CA,B
GND
VDD
V
pF
Capacitanceꢁ A, B
f = 1 MHz, measured to
GND, Code = 0x80
f = 1 MHz, measured to
GND, Code = 0x80
45
ꢁ0
Capacitanceꢁ W
CW
pF
Shutdown Supply Currentꢀ
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
IDD_SD
ICM
VDD = 5.5 V
VA = VB = VDD/2
0.01
1
1
µA
nA
VIH
VIL
VIH
VIL
IIL
2.4
2.1
V
V
V
V
µA
pF
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitanceꢁ
0.8
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
0.ꢁ
1
CIL
5
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation8
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
8
0.2
V
µA
mW
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V,
3
V
DD = 5 V
Power Supply Sensitivity
PSS
∆VDD = +5 V 10%,
Code = Midscale
0.02
0.05 %/%
DYNAMIC CHARACTERISTICSꢁ, 9
Bandwidth –3dB
BW
RAB = 10 kΩ/50 kΩ/100 kΩ,
Code = 0x80
VA =1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
VA = 5 V, VB = 0 V,
1 LSB error band
RWB = 5 kΩ, RS = 0
ꢁ00/100/40
kHz
%
Total Harmonic Distortion
THDW
tS
0.05
2
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density
µs
eN_WB
9
nV/√Hz
Rev. 0 | Page 4 of 20
AD5161
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
(VDD = +5V 10%, or +3V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ –40°C < TA < +125°Cꢀ unless otherwise noted.)
Table 3.
Parameter
Symbol
Conditions
Min Typ1 Max Unit
SPI INTERFACE TIMING CHARACTERISTICSꢁ, 10 (Specifications Apply to All Parts)
Clock Frequency
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
fCLK
tCH, tCL
tDS
25
MHz
ns
ns
Clock level high or low
20
5
5
tDH
ns
CS
tCSS
15
40
0
ns
Setup Time
CS
tCSW
tCSH0
tCSH1
tCS1
ns
High Pulsewidth
CS
CS
ns
CLK Fall to
CLK Fall to
CS
Fall Hold Time
Rise Hold Time
0
ns
10
ns
Rise to Clock Rise Setup
I2C INTERFACE TIMING CHARACTERISTICSꢁ, 11 (Specifications Apply to All Parts)
SCL Clock Frequency
tBUF Bus Free Time between STOP and START
tHD;STA Hold Time (Repeated START)
fSCL
t1
t2
400
kHz
µs
µs
1.3
0.ꢁ
After this period, the first clock pulse is
generated.
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated START Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
t3
t4
t5
tꢁ
tꢀ
t8
t9
t10
1.3
0.ꢁ
0.ꢁ
µs
µs
µs
µs
ns
ns
ns
µs
50
0.9
100
0.ꢁ
300
300
NOTES
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
ꢁ Guaranteed by design and not subject to production test.
ꢀ Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V.
10 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
11 See timing diagrams for locations of measured values.
Rev. 0 | Page 5 of 20
AD5161
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C, unless otherwise noted.)
Table 4
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Value
VDD to GND
–0.3 V to +ꢀ V
VDD
VA, VB, VW to GND
1
IMAX
20 mA
Digital Inputs and Output Voltage to GND 0 V to +ꢀ V
Operating Temperature Range
Maximum Junction Temperature (TJMAX
Storage Temperature
–40°C to +125°C
)
150°C
–ꢁ5°C to +150°C
300°C
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2 θJA: MSOP-10
200°C/W
NOTES
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA
.
Rev. 0 | Page ꢁ of 20
AD5161
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
5V
3V
–40°C
+25°C
+85°C
+125°C
0.8
0.6
0.6
0.4
0.2
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 6. DNL vs. Code, VDD = 5 V
Figure 3. R-INL vs. Code vs. Supply Voltages
1.0
0.8
1.0
0.8
5V
3V
5V
3V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 7. INL vs. Code vs. Supply Voltages
Figure 4. R-DNL vs. Code vs. Supply Voltages
1.0
0.8
1.0
0.8
_
40°C
5V
3V
+25°C
+85°C
0.6
0.6
+125°C
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
256
CODE (Decimal)
CODE (Decimal)
Figure 5. INL vs. Code, VDD = 5 V
Figure 8. DNL vs. Code vs. Supply Voltages
Rev. 0 | Page ꢀ of 20
AD5161
1.0
0.8
2.5
2.0
1.5
1.0
0.5
–40
°C
+25°C
+85°C
0.6
+125°C
0.4
V
V
= 5.5V
= 2.7V
DD
DD
0.2
0
–0.2
–0.4
–0.6
–0.8
0
–1.0
0
–40
0
40
80
120
32
64
96
128
160
192
224
256
TEMPERATURE (°C)
CODE (Decimal)
Figure 12. Zero-Scale Error vs. Temperature
Figure 9. R-INL vs. Code, VDD = 5 V
1.0
0.8
10
_
40°C
+25°C
+85°C
0.6
+125°C
0.4
0.2
V
= 5.5V
= 2.7V
DD
0
1
–0.2
–0.4
–0.6
–0.8
–1.0
V
DD
0.1
0
32
64
96
128
160
192
224
256
–40
0
40
80
120
CODE (Decimal)
TEMPERATURE (°C)
Figure 10. R-DNL vs. Code, VDD = 5 V
Figure 13. Supply Current vs. Temperature
2.5
2.0
1.5
1.0
70
60
50
40
30
20
10
0
V
V
= 2.7V
DD
DD
= 5.5V
V
= 5V
DD
0.5
0
–40
0
40
80
120
–40
0
40
80
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Full-Scale Error vs. Temperature
Figure 14. Shutdown Current vs. Temperature
Rev. 0 | Page 8 of 20
AD5161
REF LEVEL
0.000dB
0
/DIV
MARKER 510 634.725Hz
MAG (A/R) –9.049dB
6.000dB
200
0x80
–6
0x40
–12
150
100
50
0x20
0x10
–18
–24
–30
–36
–42
–48
–54
–60
0x08
0x04
0x02
0x01
0
–50
1k
START 1 000.000Hz
10k
100k
1M
0
32
64
96
128
160
192
224
256
STOP 1 000 000.000Hz
CODE (Decimal)
Figure 15. Rheostat Mode Tempco ∆RWB/∆T vs. Code
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 kΩ
REF LEVEL
0.000dB
0
/DIV
MARKER 100 885.289Hz
MAG (A/R) –9.014dB
6.000dB
160
140
120
100
80
0x80
–6
0x40
0x20
0x10
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x08
60
0x04
0x02
0x01
40
20
0
–20
0
32
64
96
128
160
192
224
256
1k
START 1 000.000Hz
10k
100k
1M
CODE (Decimal)
STOP 1 000 000.000Hz
Figure 16. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 kΩ
REF LEVEL
0.000dB
0
/DIV
MARKER 54 089.173Hz
MAG (A/R) –9.052dB
REF LEVEL
0.000dB
0
/DIV
MARKER 1 000 000.000Hz
MAG (A/R) –8.918dB
6.000dB
6.000dB
0x80
–6
0x80
–6
0x40
0x20
–12
0x40
0x20
–12
–18
–24
–30
–36
–42
–48
–54
–60
–18
–24
–30
–36
–42
–48
–54
–60
0x10
0x10
0x08
0x04
0x02
0x01
0x08
0x04
0x02
0x01
1k
START 1 000.000Hz
10k
100k
1M
1k
START 1 000.000Hz
10k
100k
1M
STOP 1 000 000.000Hz
STOP 1 000 000.000Hz
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Figure 17. Gain vs. Frequency vs. Code, RAB = 5 kΩ
Rev. 0 | Page 9 of 20
AD5161
REF LEVEL
–5.000dB
/DIV
0.500dB
–5.5
5kΩ – 1.026 MHz
10kΩ – 511 MHz
50kΩ – 101 MHz
100kΩ – 54 MHz
–6.0
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
–10.0
–10.5
1
VW
CLK
R = 50kΩ
R = 5kΩ
2
R = 10kΩ
R = 100kΩ
Ch 1 200mV
B
Ch 2 5.00 V
B
M 100ns A CH2 3.00 V
W
W
Figure 24. Digital Feedthrough
10k
START 1 000.000Hz
100k
1M
10M
STOP 1 000 000.000Hz
Figure 21. –3 dB Bandwidth @ Code = 0x80
60
40
20
0
CODE = 0x80, V = V , V = 0V
A
DD
B
V
V
= 5V
= 0V
A
B
1
VW
CS
PSRR @ V = 3V DC ± 10% p-p AC
DD
2
Ch 1 100mV
B
Ch 2 5.00 V
B
M 200ns A CH1 152mV
W
W
PSRR @ V = 5V DC ± 10% p-p AC
DD
Figure 25. Midscale Glitch, Code 0x80–0x7F
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 22. PSRR vs. Frequency
900
V
= 5V
DD
800
700
600
500
400
300
V
V
= 5V
= 0V
A
B
1
VW
CS
CODE = 0x55
CODE = 0xFF
2
200
100
0
Ch 1
5.00V
B
Ch 2 5.00 V
B
M 200ns A CH1 3.00 V
W
W
Figure 26. Large Signal Settling Time, Code 0xFF–0x00
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 23. IDD vs. Frequency
Rev. 0 | Page 10 of 20
AD5161
TEST CIRCUITS
Figure 27 to Figure 35 illustrate the test circuits that define the
test conditions used in the product specification tables.
5V
OP279
V
DUT
A
V+ = V
DD
OUT
N
V
1LSB = V+/2
IN
W
W
V+
OFFSET
GND
B
A
DUT
B
V
MS
OFFSET
BIAS
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 32. Test Circuit for Noninverting Gain
NO CONNECT
DUT
A
+15V
I
W
W
A
V
DUT
IN
W
AD8610
–15V
V
OUT
OFFSET
GND
B
B
V
MS
2.5V
Figure 33. Test Circuit for Gain vs. Frequency
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
0.1V
SW
R
=
SW
I
DUT
DUT
CODE = 0x00
I
= V /R
NOMINAL
DD
W
W
A
V
W
W
V
MS2
B
0.1V
I
SW
B
V
R
= [V
– V
]/I
MS2
W
MS1
W
MS1
V
TO V
DD
SS
Figure 29. Test Circuit for Wiper Resistance
Figure 34. Test Circuit for Incremental ON Resistance
V
A
NC
V+ = V
PSRR (dB) = 20 LOG
10%
DD
∆V
∆V
MS
DD
(
)
V
DD
A
I
V
A
B
%
CM
∆V
∆V
DUT
GND
DD
MS
W
V+
W
PSS (%/%) =
%
DD
B
V
SS
V
V
MS
CM
NC NC = NO CONNECT
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
Figure 35. Test Circuit for Common-Mode Leakage current
A
B
DUT
5V
W
V
IN
OP279
V
OUT
OFFSET
GND
OFFSET
BIAS
Figure 31. Test Circuit for Inverting Gain
Rev. 0 | Page 11 of 20
AD5161
SPI INTERFACE
1
0
1
Table 5. AD5161 Serial Data-Word Format
D7
D6
D5
D4
D3
D2
D1
D0
SDI
CLK
CS
B7
Dꢀ
MSB
2ꢀ
B6 B5 B4 B3 B2 B1 B0
Dꢁ D5 D4 D3 D2 D1 D0
0
1
RDAC REGISTER LOAD
LSB
20
0
1
0
VOUT
Figure 36. AD5161 SPI Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = VOUT
)
1
SDI
(DATA IN)
0
Dx
Dx
tDS
tCH
tCS1
tCH
1
CLK
0
tCSH1
tCL
tCSHO
tCSS
1
CS
tCSW
tS
0
VDD
VOUT
0
±1LSB
Figure 37. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT
)
Rev. 0 | Page 12 of 20
AD5161
I2C INTERFACE
Table 6. Write Mode
S
0
1
0
1
1
0
AD0 W
A
X
R
RS SD
X
X
X
X
X
A
Dꢀ Dꢁ D5 D4 D3 D2 D1 D0
Data Byte
A
P
Slave Address Byte
Instruction Byte
Table 7. Read Mode
S
0
1
0
1
1
0
AD0
A
Dꢀ Dꢁ D5 D4 D3 D2 D1 D0
Data Byte
A
P
Slave Address Byte
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
R = Read
RS = Reset wiper to Midscale 80H
SD = Shutdown connects wiper to B terminal and open
circuits A terminal. It does not change contents of wiper
register.
W
= Write
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits
t2
t8
t9
SCL
SDA
t6
t7
t5
t10
t2
t3
t4
t9
t8
t1
P
S
S
P
Figure 38. I2C Interface Detailed Timing Diagram
1
9
1
9
1
9
SCL
X
RS
SD
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
AD0 R/W
SDA
ACK BY
AD5161
ACK BY
AD5161
ACK BY
AD5161
FRAME 1
FRAME 2
INSTRUCTION BYTE
FRAME 3
STOP BY
START BY
MASTER
SLAVE ADDRESS BYTE
DATA BYTE
MASTER
Figure 39. Writing to the RDAC Register
1
9
1
9
SCL
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
AD0 R/W
SDA
ACK BY
AD5161
NO ACK
BY MASTER
FRAME 1
FRAME 2
RDAC REGISTER
START BY
MASTER
STOP BY
MASTER
SLAVE ADDRESS BYTE
Figure 40. Reading Data from a Previously Selected RDAC Register in Write Mode
Rev. 0 | Page 13 of 20
AD5161
OPERATION
The AD5161 is a 256-position digitally controlled variable
resistor (VR) device.
The general equation determining the digitally programmed
output resistance between W and B is
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
D
256
RWB (D) =
×RAB +RW
(1)
where D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register, RAB is the end-to-end resistance, and
RW is the wiper resistance contributed by the on resistance of
the internal switch.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two
or three digits of the part number determine the nominal
resistance value, e.g., 10 kΩ = 10ꢀ 50 kΩ = 50. The nominal
resistance (RAB) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings. Assume a 10 kΩ part is used, the wiper’s first
connection starts at the B terminal for data 0x00. Since there is a
60 Ω wiper contact resistance, such connection yields a
minimum of 60 Ω resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
99 Ω (RWB = RAB/256 + RW = 39 Ω + 60 Ω) for data 0x01.
The third connection is the next tap point, representing 177 Ω
(2 × 39 Ω + 60 Ω) for data 0x02, and so on. Each LSB data value
increase moves the wiper up the resistor ladder until the last tap
point is reached at 9961 Ω (RAB – 1 LSB + RW). Figure 41 shows
a simplified diagram of the equivalent RDAC circuit where the
last resistor string will not be accessedꢀ therefore, there is 1 LSB
less of the nominal resistance at full scale in addition to the
wiper resistance.
In summary, if RAB = 10 kΩ and the A terminal is open
circuited, the following output resistance RWB will be set for the
indicated RDAC latch codes.
Table 8. Codes and Corresponding RWB Resistance
D (Dec.)
RWB (Ω)
9,9ꢁ1
5,0ꢁ0
99
Output State
255
128
1
Full Scale (RAB – 1 LSB + RW)
Midscale
1 LSB
0
ꢁ0
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
60 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
A
SD BIT
RS
D7
D6
256 − D
256
RWA (D) =
×RAB + RW
(2)
RS
D5
D4
D3
D2
RS
D1
For RAB = 10 kΩ and the B terminal open circuited, the
following output resistance RWA will be set for the indicated
RDAC latch codes.
D0
W
RDAC
Table 9. Codes and Corresponding RWA Resistance
LATCH
RS
DECODER
AND
D (Dec.)
RWA (Ω)
Output State
Full Scale
Midscale
1 LSB
B
255
128
1
99
5,0ꢁ0
9,9ꢁ1
10,0ꢁ0
Figure 41. AD5161 Equivalent RDAC Circuit
0
Zero Scale
Typical device to device matching is process lot dependent and
may vary by up to 30%. Since the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 45 ppm/°C temperature coefficient.
Rev. 0 | Page 14 of 20
AD5161
CS
internal RDAC register when the
Extra MSB bits are ignored.
line returns to logic high.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
Daisy-Chain Operation
The serial data output (SDO) pin contains an open-drain
N-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. This allows for
daisy-chaining several RDACs from a single processor serial
data line. The pull-up resistor termination voltage can be larger
than the VDD supply voltage. It is recommended to increase the
clock period when using a pull-up resistor to the SDI pin of the
following device because capacitive loading at the daisy-chain
node SDO-SDI between devices may induce time delay to
subsequent devices. Users should be aware of this potential
problem to achieve data transfer successfully (see Figure 42). If
two AD5161s are daisy-chained, a total of at least 16 bits of data
is required. The first eight bits, complying with the format
shown in Table 5, go to U2 and the second eight bits with the
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
D
256
256 − D
256
VW (D) =
VA
+
VB
(3)
CS
same format go to U1.
clocked into their respective serial registers. After this,
pulled high to complete the operation and load the RDAC latch.
CS
should be kept low until all 16 bits are
For a more accurate calculation, which includes the effect of
wiper resistance, VW, can be found as
CS
is
If the data word during the
low period is greater than 16
RWB (D)
256
RWA (D)
256
VW (D) =
VA
+
VB
(4)
bits, any additional MSBs will be discarded.
VDD
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
AD5161
RP
AD5161
µC
MOSI
CLK SC
U1
U2
2.2k
Ω
SDI
CS
SDO
CLK
SDI
SDO
CLK
CS
PIN SELECTABLE DIGITAL INTERFACE
The AD5161 provides the flexibility of a selectable interface.
When the digital interface select (DIS) pin is tied low, the SPI
mode is engaged. When the DIS pin is tied high, the I2C mode is
engaged.
Figure 42. Daisy-Chain Configuration
I2C Compatible 2-Wire Serial Bus (DIS = 1)
SPI Compatible 3-Wire Serial Bus (DIS = 0)
The AD5161 can also be controlled via an I2C compatible serial
bus with DIS tied high. The RDACs are connected to this bus as
slave devices.
The AD5161 contains a 3-wire SPI compatible digital interface
CS
(SDI, , and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table 5.
The first byte of the AD5161 is a slave address byte (see Table 6
and Table 7). It has a 7-bit slave address and a R/ bit. The six
MSBs of the slave address are 010110, and the following bit is
determined by the state of the AD0 pin of the device. AD0
allows the user to place up to two of the I2C compatible devices
on one bus.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
W
CS
flip-flop or other suitable means. When
is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 36).
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 39). The
following byte is the slave address byte, which consists of
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5161 uses an
8-bit serial input data register word that is transferred to the
Rev. 0 | Page 15 of 20
AD5161
W
5. When all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 39). In read mode, the master will
issue a No Acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse which goes high
to establish a STOP condition (see Figure 40).
the 7-bit slave address followed by an R/ bit (this bit
determines whether data will be read from or written to
the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/ bit is high, the master will read
from the slave device. On the other hand, if the R/ bit is
W
W
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
low, the master will write to the slave device.
2. A write operation contains an extra instruction byte that a
read operation does not contain. Such an instruction byte
in write mode follows the slave address byte. The first bit
(MSB) of the instruction byte is a don’t care.
instructing the part only once. During the write cycle, each data
byte will update the RDAC output. For example, after the RDAC
has acknowledged its slave address and instruction bytes, the
RDAC output will update after these two bytes. If another byte
is written to the RDAC while it is still addressed to a specific
slave device with the same instruction, this byte will update the
output of the selected slave device. If different instructions are
needed, the write mode has to start again with a new slave
address, instruction, and data byte. Similarly, a repeated read
function of the RDAC is also allowed.
The second MSB, RS, is the midscale reset. A logic high on
this bit moves the wiper to the center tap where RWA = RWB
This feature effectively writes over the contents of the
register, and thus, when taken out of reset mode, the RDAC
will remain at midscale.
.
The third MSB, SD, is a shutdown bit. A logic high causes
an open circuit at terminal A while shorting the wiper to
terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to note
that the shutdown operation does not disturb the contents
of the register. When brought out of shutdown, the
previous setting will be applied to the RDAC. Also, during
shutdown, new settings can be programmed. When the
part is returned from shutdown, the corresponding VR
setting will be applied to the RDAC.
Readback RDAC Value
The AD5161 allows the user to read back the RDAC values in
the read mode. Refer to Table 6 and Table 7 for the
programming format.
Multiple Devices on One Bus
Figure 43 shows two AD5161 devices on the same serial bus.
Each has a different slave address since the states of their AD0
pins are different. This allows each RDAC within each device to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully I2C
compatible interface.
The remainder of the bits in the instruction byte are don’t
cares (see Table 6).
3. After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Table 6).
+5V
RP
RP
SDA
SCL
MASTER
+5V
4. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, where there
are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 40).
SDA SCL
SDA SCL
AD0
AD0
AD5161
AD5161
Figure 43. Multiple AD5161 Devices on One I2C Bus
Rev. 0 | Page 1ꢁ of 20
AD5161
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
TERMINAL VOLTAGE OPERATING RANGE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 3.3 V
E2PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional
The AD5161 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed VDD or GND will be clamped by the internal forward
biased diodes (see Figure 47).
V
DD
communication so that the setting of the digital potentiometer
can be stored to and retrieved from the E2PROM. Figure 44
shows one of the implementations. M1 and M2 can be any
N-channel signal FETs, or if VDD falls below 2.5 V, low threshold
FETs such as the FDV301N.
A
W
B
V
= 3.3V
V
= 5V
DD2
DD1
V
R
R
R
R
P
SS
P
P
P
G
Figure 47. Maximum Terminal Voltages Set by VDD and VSS
S
D
SDA2
SCL2
SDA1
SCL1
G
POWER-UP SEQUENCE
M1
S
D
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 47), it is important to power
VDD/GND before applying any voltage to terminals A, B, and Wꢀ
otherwise, the diode will be forward biased such that VDD will be
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA/B/W. The relative order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after VDD/GND.
M2
3.3V
5V
2
AD5161
E PROM
Figure 44. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 45 and Figure 46.
This applies to the digital input pins SDI/SDA, CLK/SCL, and
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
CS
/AD0.
340Ω
LOGIC
V
ss
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disc or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 48). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
Figure 45. ESD Protection of Digital Pins
A,B,W
VSS
Figure 46. ESD Protection of Resistor Terminals
V
V
DD
DD
+
10
C3
C1
µ
F
0.1µF
AD5161
GND
Figure 48. Power Supply Bypassing
Rev. 0 | Page 1ꢀ of 20
AD5161
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
1
2
3
4
5
10
9
8
7
6
Table 10.
Pin Name
A
B
W
V
DIS
GND
CLK/SCL
AD5161
DD
Description
A Terminal.
B Terminal.
CS/ADO
SDO/NC
SDI/SDA
TOP VIEW
1
2
3
A
(Not to Scale)
B
CS
CS
CS
: Chip Select Input, Active Low. When
/AD0
Figure 49.
returns high, data will be loaded into the DAC
register.
AD0: Programmable address bit 0 for multiple
package decoding.
4
5
SDO/NC SDO: Serial Data Output. Open-drain transistor
requires pull-up resistor.
NC: No Connect.
SDI/SDA SDI: Serial Data Input.
SDA: Serial Data Input/Output.
ꢁ
ꢀ
8
CLK/SCL Serial Clock Input. Positive edge triggered.
GND
DIS
Digital Ground.
Digital Interface Select (SPI/I2C Select).
SPI when DIS = 0, I2C when DIS = 1.
9
VDD
W
Positive Power Supply.
W Terminal.
10
Rev. 0 | Page 18 of 20
AD5161
OUTLINE DIMENSIONS
3.00 BSC
10
6
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.23
0.20
0.17
0.80
0.40
8°
0°
0.15
0.00
0.27
0.17
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 50. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD51ꢁ1BRM5
RAB (Ω)
Temperature
Package Description
MSOP-10
Package Option
RM-10
Branding
5k
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
D0C
D0C
D0D
D0D
D0E
D0E
D0F
D0F
AD51ꢁ1BRM5-RLꢀ
AD51ꢁ1BRM10
AD51ꢁ1BRM10-RLꢀ
AD51ꢁ1BRM50
AD51ꢁ1BRM50-RLꢀ
AD51ꢁ1BRM100
AD51ꢁ1BRM100-RLꢀ
AD51ꢁ1EVAL
5k
MSOP-10
RM-10
10k
MSOP-10
RM-10
10k
MSOP-10
RM-10
50k
MSOP-10
RM-10
50k
MSOP-10
RM-10
100k
100k
See Note 1
MSOP-10
RM-10
MSOP-10
RM-10
Evaluation Board
1The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
The AD5161 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2358 sq. mil.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 19 of 20
AD5161
NOTES
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
C03435–0–5/03(0)
Rev. 0 | Page 20 of 20
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