AD5172BRM10-R2_技术文档

256-Position One-Time Programmable

Dual-Channel I²C Digital Potentiometer

Preliminary Technical Data

AD5172/AD5173

The AD5172/73 are programmed using a 2-wire I²C compatible

digital control. They allow unlimited adjustments before

permanently setting the resistance value. During the OTP

FEATURES

2-Channel, 256-position

OTP(One-Time Programmable) Set-and-Forget Resistance

Setting — low cost alternative over EEMEM

Unlimited adjustments prior to OTP activation

OTP overwriting function allows temporary adjustments¹

End-to-end resistance 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ

Compact MSOP-10 (3 mm × 4.9 mm) Package

Low tempco 5 ppm/^oC in potentiometer mode

Low tempco 35 ppm/°C in rheostat mode

activation, a permanent fuse blown command is sent after the

final value is determined; therefore freezing the wiper position

at a given setting (analogous to placing epoxy on a mechanical

trimmer). Unlike other OTP digital potentiometers in the same

family, AD5172/73 have unique temporary OTP overwriting

feature that new adjustments if desired but the OTP setting is

restored during subsequent power up conditions. To verify the

success of permanent programming, Analog Devices patterned

the OTP validation such that the fuse status can be discerned

from two validation bits in read mode.

Fast Settling Time: t_S= 5µs Typ in Power-Up

Full read/write of wiper register

Power-on preset to midscale¹

For applications that program AD5172/73 in the factories,

Analog Devices offers a device programming software, which

operates across Windows® 95 to XP® platforms including

Windows NT®. This software application effectively replaces the

need for external I²C controllers or host processors and

therefore significantly reduces users’ development time.

Extra package address decode pins AD0 and AD1(AD5173)

Computer Software Replaces µC in Factory Programming

Applications

6 V one-time programming voltage

Single supply 2.7 V to 5.5 V

Low power, I_DD= 5 µA

Wide operating temperature –40°C to +125°C

An AD5172/73 evaluation kit is available, which include the

software, connector, and cable that can be converted for the

factory programming applications.

APPLICATIONS

The AD5172/73 are available in a MSOP-10 package. All parts

are guaranteed to operate over the automotive temperature

range of −40°C to +125°C. Besides their unique OTP features,

the AD5172/73 lend themselves well to other general-purpose

digital potentiometer applications due to their programmable

preset, superior temperature stability, and small form factor.

Systems Calibrations

Mechanical Potentiometers and Trimmers^®Replacements

Transducer adjustment

RF amplifier biasing

Automotive electronics adjustment

Gain control and offset adjustment

Electronics Level Settings

FUNCTIONAL BLOCK DIAGRAMS

A1 W1

B1

W2

A2

B2

GENERAL OVERVIEW

FUSE

The AD5172/73 are dual channel 256-position, one-time

programmable (OTP) digital potentiometers², which employ

fuse link technology to achieve the memory retention of

resistance setting function. OTP is a cost-effective alternative

over the EEMEM approach for users who do not need to

program the digital potentiometer setting in memory for more

than once. These devices perform the same electronic

adjustment functions like most mechanical trimmers and

variable resistors do but offer enhanced resolution, solid-state

reliability, and superior low temperature coefficient

performance.

V_DD

LINKS

1

2

RDAC

REGISTER 1

REGISTER 2

GND

8

SDA

SCL

SERIAL INPUT

REGISTER

Figure 1. AD5172

Rev. PrF 8/14/03

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD5172/AD5173

Preliminary Technical Data

Figure 2. AD5173

W1

B1

W2

B2

Note:

1. New adjustments are allowed even after OTP is achieved but the

permanent setting will always be restored during subsequent power up

cycles. This feature allows users to use these digital potentiometers as volatile

pots with programmable preset.

FUSE

V_DD

LINKS

2

1

RDAC

REGISTER 2

REGISTER 1

GND

2. The terms digital potentiometer, VR, and RDAC are used interchangeably.

AD0

ADDRESS

DECODE

Purchase of licensed I²C components of Analog Devices or one of its sublicensed

Associated Companies conveys a license for the purchaser under the Philips I²C

Patent Rights to use these components in an I²C system, provided that the system

conforms to the I²C Standard Specification as defined by Philips.

AD1

8

SDA

SCL

SERIAL INPUT

REGISTER

Rev. PrF 8/14/03 | Page 2 of 19

AD5172/AD5173

Preliminary Technical Data

TABLE OF CONTENTS

Electrical Characteristics—2.5 kΩ Version....................................4

ESD Protection.........................Error! Bookmark not defined.

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions........5

Terminal Voltage Operating Range .......Error! Bookmark not

defined.

Timing Characteristics—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions

..............................................................................................................6

Power-Up Sequence.................Error! Bookmark not defined.

Absolute Maximum Ratings¹...........................................................7

Typical Performance Characteristics..............................................8

Test Circuits .....................................................................................18

I²C Interface .......................................................................................8

Operation ...........................................................................................9

POWER supply Considerations.............Error! Bookmark not

defined.

Layout and Power Supply Bypassing........................................11

Pin Configuration and Function Descriptions ...........................18

Pin Configuration.........................................................................7

Pin Function Descriptions...........................................................7

Outline Dimensions........................................................................19

Ordering Guide ...........................................................................19

ESD Caution ................................................................................19

Programming the Variable Resistor.......Error! Bookmark not

defined.

Programming the Potentiometer Divider....Error! Bookmark

not defined.

I²C Compatible 2-Wire Serial Bus ............................................13

Level Shifting for Bidirectional Interface.....Error! Bookmark

not defined.

REVISION HISTORY

Revision Pr F: Initial Version

Rev. PrF 8/14/03 | Page 3 of 19

AD5172/AD5173

Preliminary Technical Data

ELECTRICAL CHARACTERISTICS—2.5 kΩ VERSION

(V_DD= 5 V 10%, or 3 V 10%; V_A= +V_DD; V_B= 0 V; –40°C < T_A< +125°C; unless otherwise noted.)

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

Wiper Resistance

R-DNL

R-INL

∆R_AB/R_AB

R_WB, V_A= no connect

T_A= 25°C

–1.5

–4

–30

0.1

0.ꢀ5 +4

+1.5

LSB

%

ppm/°C

Ω

+30

(∆R_AB/R_AB)/∆T V_AB= V_DD, Wiper = no connect

R_W

35

50

120

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all RDACs)

Resolution

N

8

Bits

Differential Nonlinearity⁴

Integral Nonlinearity⁴

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

(∆V_W/V_W)/∆T

V_WFSE

V_WZSE

–1.5

0.1

0.ꢁ

15

–2.5

+2

+1.5

LSB

ppm/°C

LSB

Code = 0x80

Code = 0xFF

Code = 0x00

–ꢁ

0

+ꢁ

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁵

V_A,B,W

C_A,B

GND

V_DD

V

pF

Capacitance^ꢁA, B

f = 1 MHz, measured to GND,

Code = 0x80

f = 1 MHz, measured to GND,

Code = 0x80

45

ꢁ0

Capacitance^ꢁW

C_W

pF

Shutdown Supply Current^ꢀ

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

I_{DD_SD}

I_CM

V_DD= 5.5 V

V_A= V_B= V_DD/2

0.01

1

µA

nA

V_IH

V_IL

V_IH

V_IL

I_IL

2.4

2.1

V

µA

pF

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance^ꢁ

0.8

V_DD= 3 V

V_IN= 0 V or 5 V

0.ꢁ

1

C_IL

5

POWER SUPPLIES

Normal Operating Supply Voltage

OTP Supply Voltage⁸

Supply Current

OTP Supply Current⁹

Power Dissipation¹⁰

Power Supply Sensitivity

V_DD

V_{DD_OTP}

I_DD

I_{DD_OTP}

P_DISS

PSS

2.ꢀ

5.5

5

V

T_A= 25°C

V_IH= 5 V or V_IL= 0 V

V_{DD_OTP}=ꢁV, T_A= 25°C

V_IH= 5 V or V_IL= 0 V, V_DD= 5 V

∆V_DD= +5 V 10%,

Code = Midscale

3

µA

mA

mW

100

0.2

0.05 %/%

0.02

DYNAMIC CHARACTERISTICS^{ꢁ, 10, 11}

Bandwidth –3dB

BW_2.5K

THD_W

t_S

R_AB= 2.5 kΩ, Code = 0x80

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= 5 V, V_B= 0 V, 1 LSB error

band, R_WB= 2.5 kΩ

2.4

0.05

1

MHz

%

µs

Total Harmonic Distortion

V_WSettling Time

Resistor Noise Voltage Density

e_{N_WB}

R_WB= 2.5 kΩ, RS = 0

4.5

nV/√Hz

Rev. PrF 8/14/03 | Page 4 of 19

AD5172/AD5173

Preliminary Technical Data

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(V_DD= 5 V 10%, or 3 V 10%; V_A= V_DD; V_B= 0 V; –40°C < T_A< +125°C; unless otherwise noted.)

Table 2.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

R-DNL

R-INL

∆R_AB/R_AB

R_WB, A = no connect

T_A= 25°C

–1

–2

–30

0.1

0.25

+1

+2

+30

LSB

%

(∆R_AB/R_AB)/∆T V_AB= V_DD,

Wiper = no connect

V_DD= 5 V

35

50

ppm/°C

Wiper Resistance

R_W

120

Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)

Resolution

N

8

Bits

Differential Nonlinearity⁴

Integral Nonlinearity⁴

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

(∆V_W/V_W)/∆T

V_WFSE

V_WZSE

R_WB, A = no connect

Code = 0x80

Code = 0xFF

Code = 0x00

–1

0.1

0.3

15

–1

+1

LSB

ppm/°C

LSB

–3

0

+3

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁵

V_A,B,W

C_A,B

GND

V_DD

V

pF

Capacitance^ꢁA, B

f = 1 MHz, measured to

GND, Code = 0x80

f = 1 MHz, measured to

GND, Code = 0x80

45

ꢁ0

Capacitance^ꢁW

C_W

pF

Shutdown Supply Current^ꢀ

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

I_{DD_SD}

I_CM

V_DD= 5.5 V

V_A= V_B= V_DD/2

0.01

1

µA

nA

V_IH

V_IL

V_IH

V_IL

I_IL

2.4

2.1

V

µA

pF

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance^ꢁ

0.8

V_DD= 3 V

V_IN= 0 V or 5 V

0.ꢁ

1

C_IL

5

POWER SUPPLIES

Normal Operating Supply Voltage

OTP Supply Voltage⁸

Supply Current

OTP Supply Current⁹

Power Dissipation¹⁰

V_DD

2.ꢀ

ꢁ

5.5

ꢁ.5

5

V

µA

mA

mW

V_{DD_OTP}

I_DD

I_{DD_OTP}

P_DISS

T_A= 25°C

V_IH= 5 V or V_IL= 0 V

V_{DD_OTP}=ꢁV, T_A= 25°C

V_IH= 5 V or V_IL= 0 V,

3

100

0.2

V

_DD= 5 V

Power Supply Sensitivity

PSS

∆V_DD= +5 V 10%,

Code = Midscale

0.02

0.05 %/%

DYNAMIC CHARACTERISTICS^{ꢁ, 10, 11}

Bandwidth –3dB

BW

R_AB= 10 kΩ/50 kΩ/100 kΩ,

Code = 0x80

V_A=1 V rms, V_B= 0 V,

f = 1 kHz, R_AB= 10 kΩ

V_A= 5 V, V_B= 0 V, 1 LSB

error band, R_WB= 5 kΩ

R_WB= 5 kΩ, RS = 0

ꢁ00/100/40

kHz

%

Total Harmonic Distortion

THD_W

t_S

0.05

2

V_WSettling Time (10 kΩ/50 kΩ/100 kΩ)

Resistor Noise Voltage Density

µs

e_{N_WB}

9

nV/√Hz

Rev. PrF 8/14/03 | Page 5 of 19

AD5172/AD5173

Preliminary Technical Data

TIMING CHARACTERISTICS—2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(V_DD= +5V 10%, or +3V 10%; V_A= V_DD; V_B= 0 V; –40°C < T_A< +125°C; unless otherwise noted.)

Table 3.

Parameter

Symbol

Conditions

Min Typ¹Max Unit

I²C INTERFACE TIMING CHARACTERISTICS^{ꢁ, 11}(Specifications Apply to All Parts)

SCL Clock Frequency

t_BUFBus Free Time between STOP and START

t_HD;STAHold Time (Repeated START)

f_SCL

t₁

t₂

400

kHz

µs

1.3

0.ꢁ

After this period, the first clock pulse is

generated.

t_LOWLow Period of SCL Clock

t_HIGHHigh Period of SCL Clock

t_SU;STASetup Time for Repeated START Condition

t_HD;DATData Hold Time

t_SU;DATData Setup Time

t_FFall Time of Both SDA and SCL Signals

t_RRise Time of Both SDA and SCL Signals

t_SU;STOSetup Time for STOP Condition

t₃

t₄

t₅

t_ꢁ

t_ꢀ

t₈

t₉

t₁₀

1.3

0.ꢁ

µs

ns

µs

50

0.9

100

0.ꢁ

300

NOTES

¹Typical specifications represent average readings at +25°C and V_DD= 5 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

³V_AB= V_DD, Wiper (V_W) = no connect.

⁴INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

⁵Resistor terminals A, B, W have no limitations on polarity with respect to each other.

^ꢁGuaranteed by design and not subject to production test.

^ꢀMeasured at the A terminal. The A terminal is open circuited in shutdown mode.

⁸Different from operating power supply, power supply for OTP is used one-time only.

⁹Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only.

¹⁰Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value result in the minimum overall power consumption.

¹¹All dynamic characteristics use V_DD= 5 V.

¹²Different from settling time after fuse is blown. The OTP settling time occurs once only

t₂

t₈

t₉

SCL

SDA

t₆

t₇

t₅

t₁₀

t₂

t₃

t₄

t₉

t₈

t₁

P

S

P

Figure 3. I²C Interface Detailed Timing Diagram

Rev. PrF 8/14/03 | Page ꢁ of 19

AD5172/AD5173

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS¹

(T_A= +25°C, unless otherwise noted.)

Table 4.

Parameter

Value

V_DDto GND

–0.3 V to +ꢀ V

V_DD

V_A, V_B, V_Wto GND

1

I_MAX

20 mA

Digital Inputs and Output Voltage to GND 0 V to +ꢀ V

Operating Temperature Range

Maximum Junction Temperature (T_JMAX

Storage Temperature

–40°C to +125°C

)

150°C

–ꢁ5°C to +150°C

300°C

Lead Temperature (Soldering, 10 sec)

Thermal Resistance²θ_JA: MSOP-10

230°C/W

NOTES

¹Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage

across any two of the A, B, and W terminals at a given resistance.

²Package power dissipation = (T_JMAX– T_A)/θ_JA.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is

not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

driving capability.

Serial Clock Input. Positive edge triggered.

Requires pull-up resistor

PIN CONFIGURATION

ꢁ

SCL

ꢀ

SDA

Serial Data Input/Output. Requires pull-up

resistor

1

2

3

4

5

B1

A1

W1

B2

10

9

8

A2

B2

A2 Terminal. GND ≤ V_A2≤ V_DD

B2 Terminal. GND ≤ V_B2≤ V_DD

W1 Terminal. GND ≤ V_W1≤ V_DD

8

W2

GND

A2

SDA

SCL

7

9

V_DD

6

10

W1

Figure 4.- AD5172 Pin Configuration

Table 6.

Pin Name Description

1

2

B1

B1 Terminal. GND ≤ V_B1≤ V_DD

1

2

3

4

5

B1

W1

B2

10

9

AD0

Programmable address bit 0 for multiple

package decoding. AD0 and AD1 allow

maximum of four AD51ꢀ3s to be addressed

8

W2

GND

AD1

SDA

SCL

7

3

4

W2

W2 Terminal. GND ≤ V_W2≤ V_DD

Digital Ground.

Positive Power Supply. Specified for operation

from 2.ꢀ V to 5.5 V. For OTP programming, V_DD

needs to be a minimum of ꢁ V and 100 mA

driving capability.

V_DD

6

GND

Figure 5. – AD5173 Pin Configuration

5

V_DD

PIN FUNCTION DESCRIPTIONS

ꢁ

ꢀ

8

SCL

Serial Clock Input. Positive edge triggered.

Requires pull-up resistor

Table 5.

Pin Name Description

SDA

AD1

Serial Data Input/Output. Requires pull-up

resistor

1

2

3

4

B1

B1 Terminal. GND ≤ V_B1≤ V_DD

A1 Terminal. GND ≤ V_A1≤ V_DD

W2 Terminal. GND ≤ V_W2≤ V_DD

Digital Ground.

A1

Programmable address bit 1 for multiple

package decoding. AD0 and AD1 allow

maximum of four AD51ꢀ3s to be addressed

W2

GND

9

B2

B2 Terminal. GND ≤ V_B2≤ V_DD

W1 Terminal. GND ≤ V_W1≤ V_DD

Positive Power Supply. Specified for operation

from 2.ꢀ V to 5.5 V. For OTP programming, V_DD

needs to be a minimum of ꢁ V and 100 mA

5

V_DD

10

W1

Rev. PrF 8/14/03 | Page ꢀ of 19

AD5172/AD5173

Preliminary Technical Data

TYPICAL PERFORMANCE

CHARACTERISTICS

Figures 6 to 25

Rev. PrF 8/14/03 | Page 8 of 19

Preliminary Technical Data

AD5172/AD5173

THEORY OF OPERATION

The AD5172/73 allow unlimited 8-bit adjustments, except for

one-time programmable, set-and-forget resistance setting. OTP

technology is a proven cost-effective alternative over EEMEM

in one-time memory programming applications. AD5172/73

employ fuse link technology to achieve the memory retention of

the resistance setting function. It comprises eight data fuses,

which control the address decoder for programming the RDAC,

one user mode test fuse for checking setup error, and one

programming lock fuse for disabling any further programming

once the data fuses are blown.

A

SCL

SDA

DECODER

MUX

DAC

2

I

C INTERFACE

REG.

W

B

COMPARATOR

ONE-TIME

FUSES

EN

FUSE

REG.

PROGRAM/TEST

CONTROL BLOCK

ONE-TIME PROGRAMMING (OTP)

Figure26. Detailed Functional Block Diagram

Prior to OTP activation, the AD5172/73 preset to midscale

during power on. After the wiper is set at the desired position,

the resistance can be permanently set by programming the T bit

to high along with the proper coding (Tables 10 and 11).

DETERMINING THE VARIABLE RESISTANCE AND

VOLTAGE

Rheostat Mode Operation

The device control circuit has two validation bits, E1 and E0,

that can be read back in the read mode for checking the

programming status as shown in Table 7.

If only the W-to-B or W-to-A (AD5172 only) terminals are used

as variable resistors, the unused terminal can be opened or

shorted with W. This operation is called rheostat mode

(Figure27).

Table 7. Validation Status

E1

E0

Status

A

0

1

Ready for Programming

W

Test Fuse Not Blown Successfully. (For factory

setup checking purpose only. Users should not

see these combinations.)

B

1

0

1

Error. Some fuses are not blown. Try again.

Successful. No further programming is possible.

Figure27. Rheostat Mode Configuration

The nominal resistance (R_AB) of the RDAC has 256 contact

points accessed by the wiper terminal, plus the B terminal

contact if R_WBis considered. The 8-bit data in the RDAC latch is

decoded to select one of the 256 settings. Assuming that a 10 kΩ

part is used, the wiper’s first connection starts at the B terminal

for data 0x00. Such connection yields a minimum of 60 Ω

resistance between terminals W and B because of the 60 Ω

wiper contact resistance. The second connection is the first tap

point, which corresponds to 219 Ω (R_WB= (1) × R_AB/256 + R_W)

for data 0x01, and so on. Each LSB data value increase moves

the wiper up the resistor ladder until the last tap point is

reached at 10060 Ω ((256) × R_AB/256 + R_W). Figure 28 shows a

simplified diagram of the equivalent RDAC circuit. The general

equation determining R_WBis

When the OTP T bit is set, the internal clock is enabled. The

program will attempt to blow a test fuse. The operation stops if

this fuse is not blown properly. The validation Bits E1 and E0

show 01, and the users should check the setup. If the test fuse is

blown successfully, the data fuses will be programmed next. The

eight data fuses will be programmed in eight clock cycles. The

output of the fuses is compared with the code stored in the

DAC register. If they do not match, E1 and E0 = 10 is issued as a

error and the operation stops. Users may retry with the same

codes. If the output and stored code match, the programming

lock fuse will be blown so that no further programming is

possible. In the meantime, E1 and E0 will issue 11 indicating the

lock fuse is blown successfully. All the fuse latches are enabled at

power-on and therefore the output corresponds to the stored

setting from this point on. Figure26 shows a detailed functional

block diagram.

D

R_WB(D) =

R_AB+ R_W

(1)

256

where:

D is the decimal equivalent of the 8-bit binary code.

R

_ABis the end-to-end resistance.

_Wis the wiper resistance contributed by the on-resistance of

the internal switch.

Rev. PrF 8/14/03 | Page 9 of 19

AD5172/AD5173

Preliminary Technical Data

Table 8. R_WBvs. Codes; R_AB= 10 kΩ and

the A Terminal Is Opened

potentiometer mode. The most common configuration is the

voltage divider operation (Figure 29).

D (Dec)

R_WB(Ω)

9,9ꢁ1

5,0ꢁ0

99

Output State

255

128

1

Full Scale (R_AB– 1 LSB + R_W)

Midscale

1 LSB

V

I

A

B

W

V

O

0

ꢁ0

Zero Scale (Wiper Contact Resistance)

Since a finite wiper resistance of 60 Ω is present in the zero-

scale condition, care should be taken to limit the current flow

between W and B in this state to a maximum pulse current of

no more than 20 mA. Otherwise, degradation or possible

destruction of the internal switch contact can occur.

Figure 29. Potentiometer Mode Configuration

The transfer function can be found as

D

256

R_AB+ 2R_W

R_AB+ R_W

Similar to the mechanical potentiometer, the resistance of the

RDAC between the wiper W and terminal A also produces a

complementary resistance R_WA(AD5172 only). When these

terminals are used, the B terminal can be opened or shorted to

W. Setting the resistance value for R_WAstarts at a maximum

value of resistance and decreases as the data loaded in the latch

increases in value. The general equation for this operation is

V_W(D) =

V_A

(AD5172 only) (3)

If we ignore the effect of the wiper resistance, the transfer

function is simply

D

256

256 − D

V_W(D) =

V_A

(AD5172 only)

(4)

R_WA(D) =

R_AB+ R_W(AD5172 only) (2)

256

Table 9. R_WAvs. Codes; R_AB=10 kΩ and

Unlike in rheostat mode operation where the absolute tolerance

is high, potentiometer mode operation yields an almost ratio-

metric function of D/256 with a relatively small error

contributed by the R_Wterms, and therefore the tolerance effect is

almost cancelled. Although the thin film step resistor R_Sand CMOS

switches resistance R_Whave very different temperature coefficients,

the ratio-metric adjustment also reduces the overall temperature

coefficient effect to 5 ppm/^oC, except at low value codes where R_W

dominates.

B Terminal Is Opened

D (Dec)

R_WA(Ω)

Output State

Full Scale

Midscale

1 LSB

255

128

1

99

5,0ꢁ0

9,9ꢁ1

10,0ꢁ0

0

Zero Scale

The typical distribution of the resistance tolerance from device

to device is process lot dependent, and it is possible to have

30% tolerance.

Potentiometer mode operations include others such as op amp

input, feedback resistor networks, and other voltage scaling

applications. A, W, and B terminals can in fact be input or output

terminals provided that |V_AB|, |V_WA|, and |V_WB| do not exceed

A

V_DDto GND.

SD BIT

R_S

ESD PROTECTION

D7

D6

Digital inputs SDA and SCL are protected with a series input

resistor and parallel Zener ESD structures (Figure30).

R_S

D5

D4

D3

D2

R_S

D1

340Ω

D0

W

LOGIC

RDAC

LATCH

R_S

Figure30. ESD Protection of Digital Pins

AND

B

DECODER

TERMINAL VOLTAGE OPERATING RANGE

Figure 28. Equivalent RDAC Circuit (A terminal for AD5172 only)

There are also ESD protection diodes between V_DDand the

RDAC terminals. The V_DDof AD5172/73 therefore defines their

voltage boundary conditions, see Figure31. Supply signals

Potentiometer Mode Operation (AD5172 only)

If all three terminals are used, the operation is called the

Rev. PrF 8/14/03 | Page 10 of 19

AD5172/AD5173

Preliminary Technical Data

Figure 32. Power Supply Requirement

present on terminals A, B, and W that exceed V_DDwill be

clamped by the internal forward-biased diodes and should be

avoided.

An alternate approach in 3.5V to 5.5V systems adds a signal

diode between the system supply and the OTP supply for

isolation as shown in Figure 33.

V

DD

A (AD5172 only)

W

B

GND

Figure31. Maximum Terminal Voltages Set by V_DD

POWER-UP/POWER-DOWN SEQUENCES

Similarly, because of the ESD protection diodes, it is important

to power V_DDfirst before applying any voltages to terminals A,

B, and W. Otherwise, the diode will be forward-biased such that

Figure 33. Isolate 6 V OTP supply from 3.5V-5.5V normal operating supply.

The 6V supply must be removed once OTP is completed

V_DDwill be powered unintentionally and may affect the rest of

the users’ circuits. The ideal power-up sequence is in the

following order: GND, V_DD, digital inputs, and V_A/V_B/V_W. The

order of powering V_A, V_B, V_W, and digital inputs is not

important as long as they are powered after V_DD. Similarly, V_DD

should be powered down last.

POWER SUPPLY CONSIDERATIONS

To minimize the package pin count, both the one-time

programming and normal operating voltages are applied to the

same V_DDterminal of the AD5172/73. The AD5172/73 employs

fuse link technology that requires 6V to blow the internal fuses

to achieve a given setting. On the other hand, it operates at

2.7V-5.5V once the programming is completed. Such dual

voltage requirement requires isolation between the supplies.

The fuse programming supply (either an on-board regulator or

rack-mount power supply) must be rated at 6 V and be able to

handle 400 ms and 100 mA of transient current for one-time

programming. Once programming completes, the 6 V, supply

must be removed to allow normal operation at 2.7 V to 5.5 V.

Figure 32 shows the simplest implementation using a jumper.

This approach saves one voltage supply but draws additional

current and requires manual configuration.

Figure 34. Isolate 6 V OTP Supply from 2.7V normal operating supply. The 6V

supply must be removed once OTP is completed

For users who operate their systems at 2.7V, it is recommended

to use the bi-directional low-threshold P-Ch MOSFETs for the

supplies isolation. As shown in Figure 34, assumes the 2.7V

system voltage is applied first but not the 6V, the gates of P1 and

P2 are pulled to ground thus turns on P1 and subsequently P2.

As a result, V_DDof AD5172/73 becomes 2.7V minus few tenths

of mV drop across P1 and P2. When the AD5172/73 setting is

found, the factory tester applies the 6V to V_DDand also the gates

of P1 and P2 to turn them off. While the OTP command is

executed at this time to program AD5172/73, the 2.7V source is

therefore protected. Once the OTP is completed, the tester

withdraws the 6V and AD5172/73’s setting is permanently

fixed.

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

Rev. PrF 8/14/03 | Page 11 of 19

AD5172/AD5173

Preliminary Technical Data

Similarly, it is also a good practice to bypass the power supplies

with quality capacitors for optimum stability. Supply leads to the

device should be bypassed with disc or chip ceramic capacitors

of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or

electrolytic capacitors should also be applied at the supplies to

minimize any transient disturbance and low frequency ripple

(see Figure 35). Note that the digital ground should also be

joined remotely to the analog ground at one point to minimize

the ground bounce.

V

DD

+

10 F

C3

C1

0.1 F

µ

AD5172/

AD5173

GND

Figure 35. Power Supply Bypassing

Rev. PrF 8/14/03 | Page 12 of 19

AD5172/AD5173

Preliminary Technical Data

FIGURE 36. AD5172/73 COMPUTER SOFTWARE INTERFACE

data to the device is shown in Error! Reference source not

found.. Once the desirable setting is found, the user may press

the Program Permanent button to blow the internal fuse links

for permanent setting. The user may also set the programming

bit pattern in the upper screen and press the Run button to

achieve the same result.

CONTROLLING THE AD5172/73

There are two ways of controlling the AD5172/73. Users can

either program the devices with computer software or external

I²C controllers.

Read

Software Programming

To read the validation bits and data out from the device, the

user may simply press the Read button. The user may also set

the bit pattern in the upper screen and press the Run button.

The format of reading data out from the device is shown in

Error! Reference source not found..

Due to the advantage of the one-time programmable feature,

users may consider programming the device in the factory

before shipping to end users. ADI offers a device programming

software, which can be implemented in the factory on PCs that

run Windows 95 to XP platforms. As a result, external control-

lers are not required, which significantly reduces development

time. The program is an executable file that does not require

any programming languages or user programming skills. It is

easy to set up and use. Figure 36 shows the software interface.

The software can be downloaded from www.analog.com.

To apply the device programming software in the factory, users

need to modify a parallel port cable and configure Pins 2, 3, 15,

and 25 for SDA_write, SCL, SDA_read, and DGND, respectively

for the control signals (Figure 37). Users should also layout the

PCB of the AD5172/73 with SCL and SDA pads, as shown in

Figure 38, such that pogo pins can be inserted for the factory

programming.

Write

The AD5172/73 start at midscale after power-up prior to the

OPT programming. To increment or decrement the resistance,

the user may simply move the scrollbar on the left. To write any

specific values, the user should use the bit pattern control in the

upper screen and press the Run button. The format of writing

Rev. PrF 8/14/03 | Page 13 of 19

AD5172/AD5173

Preliminary Technical Data

Figure 37. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL,

Pin 15 = SDA_read, and Pin 25 = DGND.

13

25

12

24

11

23

AD5172

AD5173

B1

A1

W1

B2

B1

AD0

W2

GND

VDD

W1

B2

10

W2

GND

VDD

A2

AD1

SDA

SCL

22

SDA

SCL

9

21

8

20

7

19

6

Figure 38. Recommended AD5172/73 PCB Layout. The SCL and SDA pads

allow pogo pins to be inserted so that signals can be communicated through

the parallel port for programming (Figure 37).

18

5

17

4

16

3

R3

100Ω

R2

SCL

SDA

READ

100Ω

15

2

R1

100Ω

WRITE

14

1

Rev. PrF 8/14/03 | Page 14 of 19

AD5172/AD5173

Preliminary Technical Data

I²C INTERFACE

Table 10. Write Mode

AD5172

S

0

1

0

1

W

A

A0 SD

T

0

OW

X

A

Dꢀ Dꢁ D5 D4 D3 D2 D1 D0

Data Byte

A

P

Slave Address Byte

Instruction Byte

AD5173

S

0

1

AD1 AD0 W

A

T

0

OW

X

Dꢀ Dꢁ D5 D4 D3 D2 D1 D0

Data Byte

Slave Address Byte

Instruction Byte

Table 11. Read Mode

AD5172

S

0

1

0

1

R

A

Dꢀ Dꢁ D5 D4 D3 D2 D1 D0

Instruction Byte

A

E1 E0

X

A

P

Slave Address Byte

Data Byte

AD5173

S

0

1

0

1

AD1 AD0

R

A

Dꢀ Dꢁ D5 D4 D3 D2 D1 D0

Instruction Byte

X

Slave Address Byte

Data Byte

S = Start Condition

P = Stop Condition

A = Acknowledge

X = Don’t Care

OW = Overwrite fuse setting and program digital pot to

different setting. Note that upon power up, digital pot will

preset to either midscale or fuse setting depending on whether

or not the fuse link has been blown.

D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits

E1, E0 = OTP Validation Bits

W

= Write

0 , 0 = Ready to program

R = Read

0 , 1 = Test fuse not blown successfully(check setup)

1 , 0 = Fatal error. Retry.

A0 = RDAC sub address select bit

SD = Shutdown connects wiper to B terminal and open

circuits A terminal. It does not change contents of wiper

register.

1 , 1 =Programmed Successfully. No further

adjustments possible.

T = OTP Programming Bit. Logic 1 programs wiper

permanently.

Rev. PrF 8/14/03 | Page 15 of 19

AD5172/AD5173

Preliminary Technical Data

1

9

1

9

1

9

SCL

0

1

0

1

R/W

A0

SD

T

0

OW

X

D7

D6

D5

D4

D3

D2

D1

D0

SDA

ACK BY

AD5172

ACK BY

AD5172

ACK BY

AD5172

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

STOP BY

START BY

MASTER

DATA BYTE

MASTER

Figure 39. Writing to the RDAC Register – AD5172

1

9

1

9

1

9

SCL

SDA

0

1

0

1

AD1 AD0 R/W

A0

SD

T

0

OW

X

D7

D6

D5

D4

D3

D2

D1

D0

ACK BY

AD5173

ACK BY

AD5173

ACK BY

AD5173

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

STOP BY

START BY

MASTER

DATA BYTE

MASTER

Figure 40. Writing to the RDAC Register – AD5173

1

9

1

9

1

9

SCL

SDA

0

1

0

1

R/W

D7

D6

D5

D4

D3

D2

D1

D0

E1

E0

X

ACK BY

AD5172

ACK BY

NO ACK

MASTER

BY MASTER

STOP BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

FRAME 3

VERIFICATION BYTE

START BY

MASTER

DATA BYTE

Figure 41. Reading Data from a Previously Selected RDAC Register in Write Mode – AD5172

1

9

1

9

1

9

SCL

SDA

0

1

0

1

AD1 AD0 R/W

D7

D6

D5

D4

D3

D2

D1

D0

E1

E0

X

ACK BY

AD5173

ACK BY

NO ACK

MASTER

BY MASTER

STOP BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

FRAME 3

VERIFICATION BYTE

START BY

MASTER

DATA BYTE

Figure 42 Reading Data from a Previously Selected RDAC Register in Write Mode – AD5173

2. In the write mode, the second byte is the instruction byte.

The first bit (MSB) of the instruction byte is the RDAC sub

address select bit. A logic low will select channel-1 and a

logic high will select channel-2.

I²C COMPATIBLE 2-WIRE SERIAL BUS

The 2-wire I²C serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see Figure 399 and 40).

The following byte is the slave address byte, which consists

The second MSB, SD, is a shutdown bit. A logic high

causes an open circuit at terminal A while shorting the

wiper to terminal B. This operation yields almost 0 Ω in

rheostat mode or 0 V in potentiometer mode. It is

important to note that the shutdown operation does not

disturb the contents of the register. When brought out of

shutdown, the previous setting will be applied to the

RDAC. Also, during shutdown, new settings can be

programmed. When the part is returned from shutdown,

the corresponding VR setting will be applied to the RDAC.

W

of the slave address followed by an R/ bit (this bit

determines whether data will be read from or written to

the slave device). The AD5172 has a fixed slave address

byte whereas the AD5173 has two configurable address bits

AD0 and AD1 (see Table 10).

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

The third MSB, T, is the OTP(One Time Programmable)

programming bit. A logic high blows the poly fuses and

programs the resistor setting permanently.

W

The fourth MSB must always be at a logic zero.

its serial register. If the R/ bit is high, the master will read

W

from the slave device. On the other hand, if the R/ bit is

low, the master will write to the slave device.

The fifth MSB, OW, is an overwrite bit. When raised to a

logic high, this bit allows the RDAC setting to be changed

Rev. PrF 8/14/03 | Page 1ꢁ of 19

AD5172/AD5173

Preliminary Technical Data

even after the internal fuses have been blown. However,

once the OW bit is returned to a logic zero, the position of

the RDAC will return to the setting prior to overwrite.

Because OW is not static, if the device is powered off and

on, the RDAC will preset to midscale or to the setting at

which the fuses were blown depending on whether or not

the fuses have been permanently set already.

instructing the part only once. For example, after the RDAC has

acknowledged its slave address and instruction bytes in the

write mode, the RDAC output will update on each successive

byte. If different instructions are needed, the write/read mode

has to start again with a new slave address, instruction, and data

byte. Similarly, a repeated read function of the RDAC is also

allowed.

The remainder of the bits in the instruction byte are don’t

cares(see Table 10).

Table 12. Validation Status

After acknowledging the instruction byte, the last byte in

write mode is the data byte. Data is transmitted over the

serial bus in sequences of nine clock pulses (eight data bits

followed by an acknowledge bit). The transitions on the

SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see Figures

39 and 40).

E1

0

E0

0

Status

Ready for Programming

0

1

Test Fuse Not Blown Successfully

(Check Setup)

1

0

1

Fatal Error. Some Fuses are not

Blown. Retry Again

3. In the read mode, the data byte follows immediately after

the acknowledgment of the slave address byte. Data is

transmitted over the serial bus in sequences of nine clock

pulses(a slight difference with the write mode, where there

are eight data bits followed by an acknowledge bit).

Similarly, the transitions on the SDA line must occur

during the low period of SCL and remain stable during the

high period of SCL (see Figure 41 and Figure 42).

Successful. No Further

Programming is Possible

Multiple Devices on One Bus( AD5173 only)

Figure 44 shows four AD5173 devices on the same serial bus.

Each has a different slave address since the states of their AD0

and AD1 pins are different. This allows each device on the bus

to be written to or read from independently. The master device

output bus line drivers are open-drain pull-downs in a fully I²C

compatible interface.

Note that the channel of interest is the one that is

previously selected in the Write Mode. In the case where

users need to read the RDAC values of both channels, they

need to program the first channel in the Write Mode and

then change to the Read Mode to read the first channel

value. After that, they need to change back to the Write

Mode with the second channel selected and read the

second channel value in the Read Mode again. It is not

necessary for users to issue the Frame 3 data byte in the

write mode for subsequent readback operation. Users

should refer to Figure 41 for the programming format.

+5V

Rp

SDA

SCL

MASTER

+5 V

D

+5V

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

AD0

Following the data byte, the validation byte contains two

validation bits, E0 and E1. These bits signify the status of

the One Time Programming (see Table ).

AD5173

Figure 44. Multiple AD5173 Devices on One I²C Bus

4. After all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In write mode, the master will pull the SDA

line high during the tenth clock pulse to establish a STOP

condition (see Figure 39) In read mode, the master will

issue a No Acknowledge for the ninth clock pulse (i.e., the

SDA line remains high). The master will then bring the

SDA line low before the tenth clock pulse which goes high

to establish a STOP condition (see Figure 41).

A repeated write function gives the user flexibility to update the

RDAC output a number of times after addressing and

Rev. PrF 8/14/03 | Page 1ꢀ of 19

AD5172/AD5173

TEST CIRCUITS

Preliminary Technical Data

5V

Figure 4 5 to Figure 53 illustrate the test circuits that define the

test conditions used in the product specification tables.

OP279

V

OUT

V

IN

W

DUT

A

V+ = V

DD

OFFSET

GND

N

1LSB = V+/2

A

DUT

B

W

V+

OFFSET

BIAS

B

V

MS

Figure 50. Test Circuit for Noninverting Gain

Figure 4 5. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)

A

+15V

W

NO CONNECT

DUT

V

DUT

IN

AD8610

–15V

V

OUT

OFFSET

GND

I

W

A

B

W

2.5V

B

V

MS

Figure 51. Test Circuit for Gain vs. Frequency

Figure 46. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

0.1V

SW

CODE = 0x00

R

=

SW

I

DUT

W

DUT

B

0.1V

I

SW

I

= V /R

NOMINAL

DD

W

A

V

W

V

MS2

V

TO V

DD

SS

B

V

R

= [V

– V

]/I

MS2

W

MS1

W

MS1

Figure 52. Test Circuit for Incremental ON Resistance

Figure 47. Test Circuit for Wiper Resistance

NC

V

A

I

V

A

B

CM

DUT

GND

DD

V+ = V

PSRR (dB) = 20 LOG

10%

DD

W

∆V

MS

DD

(

)

V

SS

DD

A

V

CM

%

∆V

MS

W

V+

PSS (%/%) =

%

DD

B

NC NC = NO CONNECT

V

MS

Figure 53. Test Circuit for Common-Mode Leakage current

Figure 48. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

A

B

DUT

5V

W

V

IN

OP279

V

OUT

OFFSET

GND

OFFSET

BIAS

Figure 49. Test Circuit for Inverting Gain

Rev. PrF 8/14/03 | Page 18 of 19

Preliminary Technical Data

AD5172/AD5173

OUTLINE DIMENSIONS

3.00 BSC

10

6

4.90 BSC

3.00 BSC

PIN 1

1

5

0.50 BSC

0.95

0.85

0.75

1.10 MAX

0.23

0.20

0.17

0.80

0.40

8°

0°

0.15

0.00

0.27

0.17

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 54. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model

R_AB(Ω)

2.5k

Temperature

Package Description

MSOP-10

Package Option

Branding

D0U

D0V

AD51ꢀ2BRM2.5-R2

AD51ꢀ2BRM2.5-RLꢀ

AD51ꢀ2BRM10-R2

AD51ꢀ2BRM10-RLꢀ

AD51ꢀ2BRM50-R2

AD51ꢀ2BRM50-RLꢀ

AD51ꢀ2BRM100-R2

AD51ꢀ2BRM100-RLꢀ

AD51ꢀ2EVAL

–40°C to +125°C

RM-10

2.5k

MSOP-10

10k

MSOP-10

10k

MSOP-10

D0V

50k

MSOP-10

D10

50k

MSOP-10

D10

100k

See Note 1

MSOP-10

D11

MSOP-10

D11

Evaluation Board

Model

R_AB(Ω)

2.5k

Temperature

Package Description

MSOP-10

Package Option

RM-10

Branding

D1K

AD51ꢀ3BRM2.5-R2

AD51ꢀ3BRM2.5-RLꢀ

AD51ꢀ3BRM10-R2

AD51ꢀ3BRM10-RLꢀ

AD51ꢀ3BRM50-R2

AD51ꢀ3BRM50-RLꢀ

AD51ꢀ3BRM100-R2

AD51ꢀ3BRM100-RLꢀ

AD51ꢀ3EVAL

–40°C to +125°C

2.5k

MSOP-10

RM-10

D1K

10k

MSOP-10

RM-10

D1L

10k

MSOP-10

RM-10

D1L

50k

MSOP-10

RM-10

D1M

D1N

50k

MSOP-10

RM-10

100k

See Note 1

MSOP-10

RM-10

MSOP-10

RM-10

D1N

Evaluation Board

¹The evaluation board is shipped with the 10 kΩ R_ABresistor option; however, the board is compatible with all available resistor value options.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

NOTES

Rev. PrF 8/14/03 | Page 19 of 19


型号：	AD5172BRM10-R2
厂家：	ADI
描述：	IC DUAL 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer 光电二极管
文件：	总19页 (文件大小：315K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5172BRM10-R2 [ADI]

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