AD5233BRU10 [ADI]
Nonvolatile Memory Digital Potentiometers; 非易失性存储器数字电位器
| 型号： | AD5233BRU10 |
| 厂家： | 
ADI |
| 描述： | Nonvolatile Memory Digital Potentiometers |
| 文件： | 总14页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory
a
Digital Potentiometers
AD5231/AD5232/AD5233
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Nonvolatile Memory Preset Maintains Wiper Settings
AD5231 Single, 1024 Position Resolution
AD5232 Dual, 256 Position Resolution
AD5233 Quad, 64 Position Resolution
10K, 50K, 100K Ohm Terminal Resistance
Linear or Log taper Settings
Increment/Decrement Commands, Push Button Command
SPI Compatible Serial Data Input with Readback Function
+3 to +5V Single Supply or 2.5V Dual Supply Operation
User EEMEM nonvolatile memory for constant storage
AD5231
C S
VD D
AD DR
D ECO D E
R D AC 1
REGISTER
C LK
SDI
R D AC 1
SDI
A1
W 1
B1
SERIAL
EEMEM1
INTERFACE
SDO
G ND
SDO
W P
D IG ITAL 2
REGISTER
O1
O2
D IG ITAL
O UTPU T
BUFFER
2
EEMEM
C ON TR O L
R D Y
PR
APPLICATIONS
EEMEM2
VSS
28 BYTES
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
DIP Switch Setting
USER EEM EM
AD5232
C S
VDD
ADDR
DECODE
R DAC1
R DAC1
C LK
SDI
R EG ISTER
A1
W 1
B1
SDI
SER IAL
G ND
EEM EM 1
IN TERFAC E
SDO
GENERAL DESCRIPTION
The AD5231/AD5232/AD5233 family provides a single-
/dual-/quad-channel, digitally controlled variable resistor (VR)
with resolutions of 1024/256/64 positions respectively. These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. The AD523X’s versatile
programming via a Micro Controller allows multiple modes of
operation and adjustment.
R DAC2
SDO
W P
R DAC2
R EG ISTER
A2
W 2
B2
EEM EM
C ON TR O L
R DY
PR
EEM EM 2
14 BY T ES
VSS
U S ER E EM E M
AD5233
C S
In the direct program mode a predetermined setting of the
RDAC register can be loaded directly from the micro controller.
Another key mode of operation allows the RDAC register to be
refreshed with the setting previously stored in the EEMEM
register. When changes are made to the RDAC register to
establish a new wiper position, the value of the setting can be
saved into the EEMEM by executing an EEMEM save
operation. Once the settings are saved in the EEMEM register
these values will be transferred automatically to the RDAC
register to set the wiper position at system power ON. Such
operation is enabled by the internal preset strobe and the preset
can also be accessed externally.
VDD
ADDR
DECODE
R DAC1
R DAC1
C LK
SDI
R EG ISTER
A1
W 1
B1
SDI
SER IAL
EEM EM 1
IN TERFAC E
SDO
R DAC2
SDO
W P
R DAC2
R EG ISTER
A2
W 2
B2
EEM EM
C ON TR O L
R DY
G ND
EEM EM 2
11 BY T ES
U S ER E EM E M
The basic mode of adjustment is the increment and decrement
command controlling the present setting of the Wiper position
setting (RDAC) register. An internal scratch pad RDAC register
can be moved UP or DOWN, one step of the nominal terminal
resistance between terminals A-and-B. This linearly changes the
wiper to B terminal resistance (RWB) by one position segment of
the device's end-to-end resistance (RAB). For
exponential/logarithmic changes in wiper setting, a left/right
shift command adjusts levels in +/-6dB steps, which can be
useful for sound and light alarm applications.
R DAC3
R DAC3
R EG ISTER
O1
O2
A3
W 3
B3
D IGITAL
O UTPU T
BUFFER
EEM EM 3
2
R DAC4
D IGITAL 5
R EG ISTER
R DAC4
A4
R EG ISTER
W 4
PR
B4
EEM EM 5
EEM EM 4
VSS
The AD523X are available in the thin TSSOP package. All
parts are guaranteed to operate over the extended industrial
temperature range of -40°C to +85°C.
REV PrF, 22 MAR '01
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use; nor for any infringements of patents
or other rights of third parties, which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
Fax:617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
PRELIMINARY TECHNICAL DATA
AD5231/AD5232/AD5233 - SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS (VDD = +3V 10% or +5V 10% and VSS=0V,
VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential Nonlinearity2
R-DNL
R-INL
RWB, VA=NC
RWB, VA=NC
-1
-1
-30
±1/4
±1/2
+1
+1
30
LSB
%FS
Resistor Nonlinearity2
Nominal resistor tolerance
∆R
TA = 25°C, VAB = VDD,Wiper (VW) = No connect
%
Resistance Temperature Coefficent
RAB/∆T
V
= V , Wiper (VW) = No Connect
500
50
200
ppm/°C
AB DD
Wiper Resistance
Wiper Resistance
RW
RW
IW = 1 V/R, VDD = +5V
IW = 1 V/R, VDD = +3V
100
Ω
Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution
N
AD5231/AD5232/AD5233
10 / 8 / 6
–1
Bits
Integral Nonlinearity3
INL
±1/2
+1
+1
%FS
Differential Nonlinearity3
Voltage Divider Temperature Coefficent
Full-Scale Error
DNL
–1
±1/4
LSB
ppm/°C
%FS
∆VW/∆T
VWFSE
Code = Half-scale
Code = Full-scale
Code = Zero-scale
15
–3
0
+0
+3
Zero-Scale Error
VWZSE
%FS
RESISTOR TERMINALS
Voltage Range4
VA,B,W
CA,B
CW
VSS
VDD
V
pF
pF
µA
5
Capacitance Ax, Bx
f = 1 MHz, measured to GND, Code = Half-scale
f = 1 MHz, measured to GND, Code = Half-scale
VA = VB = VDD/2
45
60
0.01
5
Capacitance Wx
Common-mode Leakage Current6
ICM
1
DIGITAL INPUTS & OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic High
Output Logic Low
Input Current
VIH
VIL
with respect to GND, VDD = 5V
with respect to GND, VDD = 5V
with respect to GND, VDD = 3V
with respect to GND, VDD = 3V
RPULL-UP = 2.2KΩ to +5V
IOH = 40µA, VLOGIC = +5V
IOL = 1.6mA, VLOGIC = +5V
VIN = 0V or VDD
2.4
2.1
V
V
0.8
0.6
VIH
VIL
V
V
VOH
VOH
VOL
IIL
4.9
4
V
V
0.4
±1
V
µA
pF
Input Capacitance5
CIL
5
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0V
2.7
5.5
V
Dual-Supply Power Range
VDD/VSS
±2.25
±2.75
V
Positive Supply Current
IDD
VIH = VDD or VIL = GND
2
20
µA
Programming Mode Current
IDD(PG)
IDD(READ)
ISS
PDISS
PSS
VIH = VDD or VIL = GND
35
mA
mA
µA
mW
%/%
13
Read Mode Current
VIH = VDD or VIL = GND
0.9
9
10
0.1
0.01
Negative Supply Current
VIH = VDD or VIL = GND, VDD = 2.5V, VSS = -2.5V
VIH = VDD or VIL = GND
Power Dissipation7
Power Supply Sensitivity
∆VDD = +5V ±10%
0.002
DYNAMIC CHARACTERISTICS5, 8
Bandwidth –3dB
BW_10K
THDW
tS
R = 10KΩ
600
KHz
%
Total Harmonic Distortion
VA =1Vrms, VB = 0V, f=1KHz
0.003
VW Settling Time
VA= VDD, VB=0V, 50% of final value
For RAB = 10K/50K/100K
1 / 3 / 6
9
µs
Resistor Noise Voltage
eN_WB
CT
RWB = 5KΩ, f = 1KHz
nV√Hz
Crosstalk (CW1/CW2
)
VA = VDD, VB = 0V, Measure VW with adjacent
VR making full scale change
-65
dB
NOTES: See bottom of table next page.
REV PrF
2
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
AD5231/AD5232/AD5233 - SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS (VDD = +3V 10% to +5V 10% and VSS=0V,
VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)
Parameter
Symbol Conditions
Min
Typ1
Max
Units
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 9)
Clock Cycle Time
t 1
20
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ms
ns
ns
us
Input Clock Pulse Width
CS Setup Time
t 2 , t 3
t 4
Clock level high or low
Data Setup Time
Data Hold Time
t 5
From Positive CLK transition
From Positive CLK transition
t 6
5
CLK Shutdown Time
CS Rise to Clock Rise Setup
CS High Pulse Width
CLK to SDO Propagation Delay10
t 7
0
t 8
10
10
1
t 9
t 10
RP = 1KΩ, CL < 20pF
Applies to Command 2H, 3H, 9H
25
25
Store to Nonvolatile EEMEM Save Time11 t 12
CS to SDO - SPI line acquire
CS to SDO - SPI line release
RDY Rise to CS Fall
t13
t14
t15
Startup Time
t16
CLK Setup Time
t17
For 1 CLK period (t4 - t3 = 1 CLK period)
Preset Pulse Width (Asynchronous)
Preset Response Time
tPR
50
tPRESP
PR pulsed low then high
70
NOTES:
1.
2.
Typicals represent average readings at +25°C and VDD = +5V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+3V or VDD=+5V.
3.
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = VSS
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
.
4.
5.
6.
7.
8.
9.
Common mode leakage current is a measure of the DC leakage from any terminal A, B, W to a common mode bias level of VDD / 2.
PDISS is calculated from (IDD x VDD) + (ISS X VSS).
All dynamic characteristics use VDD = +5V.
See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching
characteristics are measured using both VDD = +3V or +5V.
10. Propagation delay depends on value of VDD, RPULL_UP, and CL see applications text.
11. Low only for instruction commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.12ms; CMD_2,3 ~20ms
12. Dual Supply Operation primarily affects the POT terminals.
13. Read Mode current is not continuous.
Timing Diagram
CLK
t17
t1
t3
t2
t7
t8
t4
CS
t9
t5
t6
SDI
M SB
LSB
t13
t10
t14
SDO1
SDO2
M SB
LSB
M SB
LSB
t15
t16
t12
RDY
SDO1 CLK IDLES LOW
SDO2 CLK IDLES HIGH
Figure 1. Timing Diagram
REV PrF
3
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Digital Inputs & Output Voltage to GND .................. 0V, +7V
Operating Temperature Range ........................ -40°C to +85°C
Maximum Junction Temperature (TJ MAX) ..................+150°C
Absolute Maximum Rating (TA = +25°C, unless
otherwise noted)
V
DD to GND..............................................................-0.3, +7V
Storage Temperature ..................................... -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .........................+300°C
Package Power Dissipation ........................ (TJMAX - TA) / θJA
VSS to GND .................................................................0V, -7V
VDD to VSS .........................................................................+7V
VA, VB, VW to GND..................................................VSS, VDD
A
X – BX, AX – WX, BX – WX
Intermittent ................................................... 20mA
Continuous................................................... 1.3mA
Thermal Resistance θJA,
TSSOP-16 ..................................................... 150°C/W
TSSOP-24 ..................................................... 128°C/W
Ox to GND.................................................................. 0V, VDD
Ordering Guide
Number of
Channels
End to End
R (k Ohm)
Temp
Range
Package
Description
Package #Devices
Option per Container
Top Mark
Model
AD5231BRU10
X1
X1
X1
X1
X1
X1
10
-40/+85°C
-40/+85°C
-40/+85°C
-40/+85°C
-40/+85°C
-40/+85°C
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
RU-16
AD5231BRU10-REEL7
AD5231BRU50
10
50
RU-16
RU-16
RU-16
RU-16
RU-16
1,000
1,000
1,000
AD5231BRU50-REEL7
AD5231BRU100
50
100
100
AD5231BRU100-REEL7
AD5232BRU10
AD5232BRU10-REEL7
AD5232BRU50
X2
X2
X2
X2
X2
X2
10
10
-40/+85°C
-40/+85°C
-40/+85°C
-40/+85°C
-40/+85°C
-40/+85°C
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
TSSOP-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
1,000
1,000
1,000
50
AD5232BRU50-REEL7
AD5232BRU100
50
100
100
AD5232BRU100-REEL7
AD5233BRU10
X4
X4
X4
X4
X4
X4
10
-40/+85°C
-40/+85°C
-40/+85°C
-40/+85°C
-40/+85°C
-40/+85°C
TSSOP-24
TSSOP-24
TSSOP-24
TSSOP-24
TSSOP-24
TSSOP-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
AD5233BRU10-REEL7
AD5233BRU50
10
50
AD5233BRU50-REEL7
AD5233BRU100
AD5233BRU100-REEL7
50
100
100
The AD5231/AD5232/AD5233 contains 9,646 transistors.
Die size: 69 mil x 115 mil, 7,993 sq. mil
REV PrF
4
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
AD5231 PIN CONFIGURATION
AD5232 PIN CONFIGURATION
O1
CLK
SDI
SDO
GND
VSS
1
2
3
4
5
6
7
8
16 O2
CLK
SDI
SDO
GND
VSS
1
2
3
4
5
6
7
8
16 RDY
15
14
13
12
11
10
9
RDY
CS
15
14
13
12
11
10
9
CS
PR
PR
WP
VDD
A2
W2
B2
WP
VDD
A1
A1
T1
W1
W1
B1
B1
AD5231 PIN FUNCTION DESCRIPTION
AD5232 PIN FUNCTION DESCRIPTION
#
Name
Description
#
Name
Description
1
O1
Non-Volatile Digital Output #1, ADDR(O1) =
1H, data bit position D0
1
CLK
Serial Input Register clock pin. Shifts in one
bit at a time on positive clock edges.
2
CLK
Serial Input Register clock pin. Shifts in one
bit at a time on positive clock CLK edges.
2
3
SDI
Serial Data Input Pin. Shifts in one bit at a
time on positive clock CLK edges.
3
4
SDI
Serial Data Input Pin.
SDO
Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 16 clock pulses. This allows daisy-chain
operation of multiple packages.
SDO
Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 24 clock pulses. This allows daisy-chain
operation of multiple packages.
4
5
GND
VSS
Ground pin, logic ground reference
5
6
GND
VSS
Ground pin, logic ground reference.
Negative Supply. Connect to zero volts for
single supply applications.
Negative Supply. Connect to zero volts for
single supply applications.
6
7
A1
A terminal of RDAC1.
7
T1
Used as digital input during factory test mode.
Leave pin floating or connect to VDD or VSS.
W1
Wiper terminal of RDAC1,
ADDR(RDAC1) = 0H.
8
9
B1
B terminal of RDAC1.
8
B1
B2
W2
B terminal of RDAC1.
B terminal of RDAC2.
W1
Wiper terminal of RDAC1,
ADDR(RDAC1) = 0H
9
10
Wiper terminal of RDAC2,
ADDR(RDAC2) = 1H.
10
11
A1
A terminal of RDAC1.
VDD
Positive Power Supply Pin. Should be ≥ the
input-logic HIGH voltage.
11
12
A2
A terminal of RDAC2.
VDD
Positive Power Supply Pin. Should be ≥ the
input-logic HIGH voltage.
12
WP
PR
Write Protect Pin. When active low WP
prevents any changes to the present contents
except retrieving EEMEM contents and
RESET.
13
WP
PR
Write Protect Pin. When active low, WP
prevents any changes to the present contents,
except retrieving EEMEM content and
RESET.
13
Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 200H until EEMEM loaded with a
new value by the user (PR is activated at the
rising logic high transition)
14
Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 80H until EEMEM loaded with a new
value by the user (PR is activated at the logic
high transition).
14
15
16
CS
Serial Register chip select active low. Serial
register operation takes place when CS returns
to logic high.
15
16
CS
Serial Register chip select active low. Serial
register operation takes place when CS returns
to logic high.
RDY
O2
Ready. Active-high open drain output.
Identifies completion of commands 2, 3, 8, 9,
10.
RDY
Ready. Active-high open drain output.
Identifies completion of commands 2, 3, 8, 9,
10.
Non-Volatile Digital Output #2, ADDR(O2) =
1H, data bit position D1.
REV PrF
5
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
AD5233 PIN CONFIGURATION
O1
CLK
SDI
SDO
GND
VSS
1
2
3
4
5
6
7
8
9
24 O2
23 RDY
22 CS
PR
21
20
19
18
17
16
15
14
13
WP
VDD
A4
W4
B4
A3
W3
B3
A1
W1
B1
A2 10
W2 11
B2 12
AD5233 PIN FUNCTION DESCRIPTION
#
1
2
3
4
Name
O1
Description
Non-Volatile Digital Output #1, ADDR(O1) = 4H, data bit position D0.
Serial Input Register clock pin. Shifts in one bit at a time on positive clock CLK edges.
Serial Data Input Pin.
CLK
SDI
SDO
Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 & 10 activate the SDO output.
See Instruction operation Truth Table. Other commands shift out the previously loaded bit pattern delayed by 16 clock
pulses. This allows daisy-chain operation of multiple packages.
5
GND
VSS
A1
Ground pin, logic ground reference
Negative Supply. Connect to zero volts for single supply applications.
A terminal of RDAC1.
6
7
8
W1
B1
Wiper terminal of RDAC1, ADDR(RDAC1) = 0H.
B terminal of RDAC1.
9
10
11
12
13
14
15
16
17
18
19
20
A2
A terminal of RDAC2.
W2
B2
Wiper terminal of RDAC2, ADDR(RDAC2) = 1H.
B terminal of RDAC2.
B3
B terminal of RDAC3.
W3
A3
Wiper terminal of RDAC3, ADDR(RDAC3) = 2H.
A terminal of RDAC3.
B4
B terminal of RDAC4.
W4
A4
Wiper terminal of RDAC4, ADDR(RDAC4) = 3H.
A terminal of RDAC4.
VDD
WP
Positive Power Supply Pin. Should be ≥ the input-logic HIGH voltage.
Write Protect Pin. When active low, WP prevents any changes to the present contents, except retrieving EEMEM content
and RESET.
21
PR
Hardware over ride preset pin. Refreshes the scratch pad register with current contents of the EEMEM register. Factory
default loads midscale 20H until EEMEM loaded with a new value by the user (PR is activated at the logic high
transition).
22
23
24
CS
Serial Register chip select active low. Serial register operation takes place when CS returns to logic high.
Ready. Active-high open drain output. Identifies completion of commands 2, 3, 8, 9, 10.
Non-Volatile Digital Output #2, ADDR(O2) = 4H, data bit position D1.
RDY
O2
REV PrF
6
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
SERIAL DATA INTERFACE
OPERATIONAL OVERVIEW
The AD523X family contains a four-wire SPI compatible digital
interface (SDI, SDO, CS, and CLK). Key features of this
interface include:
The AD5231/32/33 digital potentiometer family is designed to
operate as a true variable resistor replacement device for analog
signals that remain within the terminal voltage range of
VSS<VTERM<VDD. The basic voltage range is limited to a |VDD
VSS| < 5.5V.
-
•
•
Independently Programmable Read & Write to all registers
Direct parallel refresh of all RDAC wiper registers from
corresponding internal EEMEM registers
Increment & Decrement instructions for each RDAC wiper
register
Left & right Bit Shift of all RDAC wiper registers to
achieve 6dB level changes
Nonvolatile storage of the present scratch pad RDAC
register values into the corresponding EEMEM register
Extra bytes of user addressable electrical-erasable memory
Control of the digital potentiometer allows both scratch pad
register (RDAC register) changes to be made, as well as,
100,000 nonvolatile electrically erasable memory (EEMEM)
register operations. The EEMEM update process takes
approximately 20.2ms, during this time the shift register is
locked preventing any changes from taking place. The RDY pin
flags the completion of this EEMEM save. The EEMEM
retention is designed to last 15 years at 85°C, which is
equivalent to 90 years at 55°C, without refresh.
•
•
•
•
The serial interface contains three different word formats to
support the single AD5231, dual AD5232, and the quad
AD5233 digital potentiometer devices. The AD5232 and
AD5233 use a 16-bit serial data word loaded MSB first, while
the AD5231 uses a 24-bit serial word loaded MSB first. The
format of the SPI compatible word is shown in Table 1 and 2.
The Command Bits (Cx) control the operation of the digital
potentiometer according to the command instructions shown in
Table 3, 4, and 5. The Address Bits (Ax) determine which
register is activated. The Data Bits (Dx) are the values that are
loaded into the decoded register. The last instruction executed
prior to a period of no programming activity should be the No
OPeration (NOP) instruction. This will place the internal logic
circuitry in a minimum power dissipation state.
The scratch pad register can be changed incrementally by using
the software controlled Increment/Decrement instruction or the
Shift Left/Right instruction command. Once an Increment,
Decrement or Shift command has been loaded into the shift
register subsequent CS strobes will repeat this command. This is
useful for push button control applications. Alternately the
scratch pad register can be programmed with any position value
using the standard SPI serial interface mode by loading the
representative data word. The scratch pad register can be loaded
with the current contents of the nonvolatile EEMEM register
under program control. At system power ON, the default value
of the scratch pad memory is the value previously saved in the
EEMEM register. The factory EEMEM preset value is midscale.
The scratch pad (wiper) register can be loaded with the current
contents of the nonvolatile EEMEM register under hardware
control by pulsing the PR pin. Beware that the PR pulse first sets
the wiper at midscale when brought to logic zero, and then on
the positive transition to logic high, it reloads the DAC wiper
register with the contents of EEMEM. Similarly, the saved
EEMEM value will automatically be retrieved to the scratch pad
register during system power ON.
PR
VALID
COMMAND
COMMAND
+5V
PROCESSOR
& ADDRESS
DECODE
COUNTER
R PULLUP
CLK
SERIAL
REGISTER
A serial data output pin is available for daisy chaining and for
readout of the internal register contents. The serial input data
register uses a 16 or 24-bit instruction/address/data WORD.
Write protect (WP) disables any changes of current content in
the scratch pad register regardless of the commands, except that
EEMEM setting can be retrieved using commands 1 and 9.
Therefore, write-protect (WP) pin provides hardware EEMEM
protection feature.
SDO
GND
CS
SDI
Figure 2. Equivalent Digital Input-Output Logic
The equivalent serial data input and output logic is shown in
figure 2. The open drain output SDO is disabled whenever chip
select CS is logic high. The SPI interface can be used in two
slave modes CPHA=1, CPOL=1 and CPHA=0, CPOL=0. CPHA
and CPOL refer to the control bits, which dictate SPI timing in
the following microprocessors/Micro Converters:
DIGITAL INPUT/OUTPUT CONFIGURATION
All digital inputs are ESD protected high input impedance that
can be driven directly from most digital sources. For PR and WP,
which are active at logic low, can be tied directly to VDD if they
are not being used.
ADuC812/824, M68HC11, and MC68HC16R1/916R1.
The SDO and RDY pins are open drain digital outputs where
pull-up resistors are needed only if using these functions. A
resistor value in the range of 1k to 10k ohm optimizes the power
and switching speed trade off.
REV PrF
7
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Table 1. AD5232 & AD5233 16-bit Serial Data Word
MSB
LSB
D0
AD5232
AD5233
C3
C2
C2
C1
C1
C0
C0
A3
A3
A2
A2
A1
A1
A0
A0
D7
X
D6
X
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
C3
D0
Table 2. AD5231 24-bit Serial Data Word
M
S
B
L
S
B
D
0
AD5231
C
3
C
2
C
1
C
0
A3 A2 A1 A0
X
X
X
X
X
X
D
9
D
D
7
D
D
5
D
4
D
3
D
2
D
1
8
6
Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in tables 3, 4, & 5.
REV PrF
8
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Table 3. AD5231 Instruction/Operation Truth Table
Inst Instruction Byte 1
No.
Data Byte 1
B15 •••• B8
Data Byte 0
B7 ••• B0
Operation
B15 •••••••••••••••• B8
C3 C2 C1 C0 A3 A2 A1 A0
X ••• D9 D8 D7 ••• D0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X ••• X
X ••• X
X ••• X
X
X
X
X
X
X
••• X
••• X
••• X
No Operation (NOP): Do nothing
1
<< ADDR >>
<< ADDR >>
<< ADDR >>
<< ADDR >>
Write contents of EEMEM(ADDR) to RDAC(ADDR)
Register
2
SAVE WIPER SETTING: Write contents of
RDAC(ADDR) to EEMEM(ADDR)
3
X ••• D9 D8 D7 ••• D0
Write contents of Serial Register Data Byte 0 & 1 to
EEMEM(ADDR)
4
X ••• X
X ••• X
X ••• X
X ••• X
X ••• X
X ••• X
X ••• X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
••• X
••• X
••• X
••• X
••• X
••• X
••• X
Decrement 6dB: Right Shift contents of
RDAC(ADDR), stops at all "Zeros".
5
X
X
X
X
Decrement All 6dB: Right Shift contents of all
RDAC Registers, stops at all "Zeros".
6
<< ADDR >>
Decrement contents of RDAC(ADDR) by "One",
stops at all "Zeros".
7
X
0
X
0
X
0
X
0
Decrement contents of RDAC Register by "One",
stops at all "Zeros".
8
RESET: Load all RDACs with their corresponding
EEMEM previously-saved values
9
<< ADDR >>
<< ADDR >>
<< ADDR >>
<< ADDR >>
Write contents of EEMEM(ADDR) to Serial Register
Data Byte 0 & 1
10
11
12
13
14
15
Write contents of RDAC(ADDR) to Serial Register
Data Byte 0 & 1
X ••• D9 D8 D7 ••• D0
Write contents of Serial Register Data Byte 0 &1 to
RDAC(ADDR)
X ••• X
X ••• X
X ••• X
X ••• X
X
X
X
X
X
X
X
X
••• X
••• X
••• X
••• X
Increment 6dB: Left Shift contents of
RDAC(ADDR), stops at all "Ones".
X
X
X
X
Increment All 6dB: Left Shift contents of all RDAC
Registers, stops at all "Ones".
<< ADDR >>
Increment contents of RDAC(ADDR) by "One",
stops at all "Ones".
X
X
X
X
Increment contents of RDAC Register by "One",
stops at all "Ones".
NOTES:
1. The SDO output shifts-out the last 16-bits of data clocked into the serial register for daisy chain operation. Exception:
following Instruction #9 or #10 the selected internal register data will be present in data byte 0 & 1. Instructions
following #9 & #10 must be a full 24-bit data word to completely clock out the contents of the serial register.
2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile
EEMEM register.
3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high.
REV PrF
9
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Table 4. AD5232 Instruction/Operation Truth Table
Inst Instruction Byte 1
No.
Data Byte 0
B7 ••••••••••••••••• B0
Operation
B15 •••••••••••••••• B8
C3 C2 C1 C0 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No Operation (NOP): Do nothing
1
<< ADDR >>
<< ADDR >>
<< ADDR >>
<< ADDR >>
Write contents of EEMEM(ADDR) to RDAC(ADDR)
Register
2
SAVE WIPER SETTING: Write contents of
RDAC(ADDR) to EEMEM(ADDR)
3
D7 D6 D5 D4 D3 D2 D1 D0
Write contents of Serial Register Data Byte 0 to
EEMEM(ADDR)
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Decrement 6dB: Right Shift contents of
RDAC(ADDR) , stops at all "Zeros".
5
X
X
X
X
Decrement All 6dB: Right Shift contents of all
RDAC Registers, stops at all "Zeros".
6
<< ADDR >>
Decrement contents of RDAC(ADDR) by "One",
stops at all "Zeros".
7
X
0
X
0
X
0
X
0
Decrement contents of all RDAC Registers by
"One", stops at all "Zeros".
8
RESET: Load all RDACs with their corresponding
EEMEM previously-saved values
9
<< ADDR >>
<< ADDR >>
<< ADDR >>
<< ADDR >>
Write contents of EEMEM(ADDR) to Serial Register
Data Byte 0
10
11
12
13
14
15
Write contents of RDAC(ADDR) to Serial Register
Data Byte 0
D7 D6 D5 D4 D3 D2 D1 D0
Write contents of Serial Register Data Byte 0 to
RDAC(ADDR)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Increment 6dB: Left Shift contents of
RDAC(ADDR), stops at all "Ones".
X
X
X
X
Increment All 6dB: Left Shift contents of all RDAC
Registers, stops at all "Ones".
<< ADDR >>
Increment contents of RDAC(ADDR) by "One",
stops at all "Ones".
X
X
X
X
Increment contents of all RDAC Registers "One",
stops at all "Ones".
NOTES:
1. The SDO output shifts-out the last 8-bits of data clocked into the serial register for daisy chain operation. Exception:
following Instruction #9 or #10 the selected internal register data will be present in data byte 0. Instructions following #9
& #10 must be a full 16-bit data word to completely clock out the contents of the serial register.
2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile
EEMEM register.
3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high.
REV PrF
10
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Table 5. AD5233 Instruction/Operation Truth Table
Inst Instruction Byte 1
No.
Data Byte 0
B7 ••••••••••••••••• B0
Operation
B15 •••••••••••••••• B8
C3 C2 C1 C0 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No Operation (NOP): Do nothing
1
<< ADDR >>
<< ADDR >>
<< ADDR >>
<< ADDR >>
Write contents of EEMEM(ADDR) to RDAC(ADDR)
Register
2
SAVE WIPER SETTING: Write contents of
RDAC(ADDR) to EEMEM(ADDR)
3
D7 D6 D5 D4 D3 D2 D1 D0
Write contents of Serial Register Data Byte 0 to
EEMEM(ADDR)
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Decrement 6dB: Right Shift contents of
RDAC(ADDR), stops at all "Zeros".
5
X
X
X
X
Decrement All 6dB: Right Shift contents of all
RDAC Registers, stops at all "Zeros".
6
<< ADDR >>
Decrement contents of RDAC(ADDR) by "One",
stops at all "Zeros".
7
X
0
X
0
X
0
X
0
Decrement contents of all RDAC Registers by
"One", stops at all "Zeros".
8
RESET: Load all RDACs with their corresponding
EEMEM previously-saved values
9
<< ADDR >>
<< ADDR >>
<< ADDR >>
<< ADDR >>
Write contents of EEMEM(ADDR) to Serial Register
Data Byte 0
10
11
12
13
14
15
Write contents of RDAC(ADDR) to Serial Register
Data Byte 0
D7 D6 D5 D4 D3 D2 D1 D0
Write contents of Serial Register Data Byte 0 to
RDAC(ADDR)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Increment 6dB: Left Shift contents of
RDAC(ADDR), stops at all "Ones".
X
X
X
X
Increment All 6dB: Left Shift contents of all RDAC
Registers, stops at all "Ones".
<< ADDR >>
Increment contents of RDAC(ADDR) by "One",
stops at all "Ones".
X
X
X
X
Increment contents of all RDAC Registers by
"One", stops at all "Ones".
NOTES:
1. The SDO output shifts-out the last 8-bits of data clocked into the serial register for daisy chain operation. Exception:
following Instruction #9 or #10 the selected internal register data will be present in data byte 0. Instructions following #9
& #10 must be a full 16-bit data word to completely clock out the contents of the serial register. The wiper only has 64
positions that correspond to the lower 6-bits of register data.
2. The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding non-volatile
EEMEM register.
3. The increment, decrement and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high.
REV PrF
11
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Latched Digital Outputs
A pair of digital outputs, O1 & O2, is available on the AD5231,
Detail Programmable Potentiometer Operation
and the AD5233 parts that provide a nonvolatile logic 0 or logic
1 setting. O1 & O2 are standard CMOS logic outputs shown in
figure 2A. These outputs are ideal to replace functions often
provided by DIP switches. In addition, they can be used to drive
other standard CMOS logic controlled parts that need an
occasional setting change.
The actual structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. The RDAC
contains a string of connected resistor segments, with an array of
analog switches that act as the wiper connection to several
points along the resistor array. The number of points is the
resolution of the device. For example, the AD5232 has 256
connection points allowing it to provide better than 0.5% set-
ability resolution. Figure 3 provides an equivalent diagram of
the connections between the three terminals that make up one
channel of the RDAC. The SWA and SWB will always be ON
while one of the switches SW(0) to SW(2N-1) will be ON one at
a time depending upon the resistance step decoded from the
Data Bits. Note there are two 50 ohm wiper resistances, RW. The
resistance contributed by RW must be accounted for in the output
resistance. At terminals A-to-wiper, RW is the sum of the
resistances of SWA and SWX. Similarly, RW is the sum of the
resistances SWB and SWX at terminals B-to-Wiper.
VD D
OUTPUTS
O1 & O2
PINS
GND
Figure 2A. Logic Outputs O1 & O2.
SW A
AX
Using Additional internal Nonvolatile EEMEM
The AD523x family of devices contains additional internal user
storage registers (EEMEM) for saving constants and other 8-bit
data. Table 6 provides an address map of the internal storage
registers shown in the functional block diagrams as EEMEM1,
EEMEM2, … EEMEMn, and bytes of USER EEMEM.
SW (2N-1)
RDAC
W X
RS
W IPER
REGISTER
&
SW (2N-2)
Table 6: EEMEM Address Map
DECODER
EEMEM
Address
(ADDR)
EEMEM Contents of each device
EEMEM(ADDR)
RS
SW (1)
SW (0)
SW B
AD5231 (16B)
AD5232
(8B)
AD5233
RS
(8B)
RS = RAB / N
0000
0001
0010
0011
0100
0101
***
RDAC
RDAC1
RDAC2
USER 1
USER 2
USER 3
USER 4
***
RDAC1
RDAC2
RDAC3
RDAC4
O1 & O2
USER 1
***
DIG ITAL
CIRCUITRY
O1 & O2
USER 1
USER 2
USER 3
USER 4
***
BX
O MITTED FO R
CLARITY
Figure 3. Equivalent RDAC structure
TEST CIRCUITS
Figures X7 to X15 define the test conditions used in the product
specification's table.
1111
NOTES:
USER 14
USER 14
USER 11
1. RDAC data stored in EEMEM locations are transferred to
their corresponding RDAC REGISTER at Power ON, or
when the following instructions are executed Inst#1 and
Inst#8.
2. O1 & O2 data stored in EEMEM locations are transferred
to their corresponding DIGITAL REGISTER at Power ON,
or when the following instructions are executed Inst#1 and
Inst#8.
Figure X7. Potentiometer Divider Nonlinearity error test circuit
(INL, DNL)
3. USER data are internal nonvolatile EEMEM registers
available to store and retrieve constants using Inst#3 and
Inst#9 respectively.
4. AD5231 EEMEM locations are 2 bytes each (16-bits) of
data, while the AD5232 & AD5233 are 1 byte each (8-bits).
REV PrF
12
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
Figure X8. Resistor Position Nonlinearity Error (Rheostat
Figure X14. Incremental ON Resistance Test Circuit
Operation; R-INL, R-DNL)
Figure X15. Common Mode Leakage current test circuit
Figure X9. Wiper Resistance test Circuit
TYPICAL PERFORMANCE GRAPHS
TBD
Figure X10. Power supply sensitivity test circuit (PSS, PSSR)
Figure X11. Inverting Gain test Circuit
Figure X12. Non-Inverting Gain test circuit
Figure X13. Gain Vs Frequency test circuit
REV PrF
13
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers AD5231/AD5232/AD5233
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
REV PrF
14
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
相关型号：
AD5235BRU25
DUAL 25K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO16, MO-153AB, TSSOP-16
ROCHESTER
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