AD5247 [ADI]
128-Position I2C Compatible Digital Potentiometer; 128位I2C兼容数字电位计
| 型号： | AD5247 |
| 厂家： | 
ADI |
| 描述： | 128-Position I2C Compatible Digital Potentiometer |
| 文件： | 总20页 (文件大小：1011K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128-Position I2C Compatible
Digital Potentiometer
AD5247
FEATURES
128-position
FUNCTIONAL BLOCK DIAGRAM
V
DD
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Ultracompact SC70-6 (2 mm × 2.1 mm) package
I2C® compatible interface
A
SDA
SCL
2
I C INTERFACE
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, IDD = 3 µA typical
Wide operating temperature –40°C to +125°C
Evaluation board available
W
WIPER
REGISTER
B
GND
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
1 Note: The terms digital potentiometer, VR, and RDAC are used
interchangeably in this document.
RF amplifier biasing
LCD brightness and contrast adjustment
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW
The AD5247 provides a compact 2 mm × 2.1 mm packaged
solution for 128-position adjustment applications. This device
performs the same electronic adjustment function as a
mechanical potentiometer or a variable resistor. Available in
four different end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ,
100 kΩ), these low temperature coefficient devices are ideal for
high accuracy and stability variable resistance adjustments.
The wiper settings are controllable through the I2C compatible
digital interface, which can also be used to read back the present
wiper register control word. The resistance between the wiper
and either end point of the fixed resistor varies linearly with
respect to the digital code transferred into the RDAC1 latch.
Operating from a 2.7 V to 5.5 V power supply and consuming
3 µA allows for usage in portable battery-operated applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD5247
TABLE OF CONTENTS
Electrical Characteristics—5 kΩ Version ...................................... 3
Level Shifting for Bidirectional Interface................................ 15
ESD Protection ........................................................................... 15
Terminal Voltage Operating Range.......................................... 15
Maximum Operating Current .................................................. 15
Power-Up Sequence ................................................................... 15
Layout and Power Supply Bypassing ....................................... 16
Constant Bias to Retain Resistance Setting............................. 16
Evaluation Board........................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4
Timing Characteristics
5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions........................................ 5
Absolute Maximum Ratings............................................................ 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 11
I2C Interface..................................................................................... 12
Operation......................................................................................... 13
Programming the Variable Resistor ......................................... 13
Programming the Potentiometer Divider............................... 14
I2C Compatible 2-Wire Serial Bus............................................ 14
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5247
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
Table 1. VDD = 5 V 1ꢀ0 or 3 V 1ꢀ0; VA = +VDD; –4ꢀ°C < TA < +125°C; unless otherwise noted
Parameter
Symbol Conditions
Min Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB
R-DNL
R-INL
∆RAB
∆RAB/∆T
RWB
RWB, VA = No Connect
RWB, VA = No Connect
–1.5
–4
–30
0.1
0.ꢀ5
+1.5
+4
+30
LSB
LSB
%
ppm/°C
Ω
VA = VDD, Wiper = No Connect
Code = 0x00
45
ꢀ5
300
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
∆VW/∆T
VWFSE
VWZSE
–1
–1
0.1
0.2
15
–2
+1
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
Code = 0x40
Code = 0xꢀF
Code = 0x00
–3
0
0
+2
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range5
VB, W
CA
GND
VDD
V
Capacitance6 A
f = 1 MHz, Measured to GND,
Code = 0x40
f = 1 MHz, Measured to GND,
Code = 0x40
45
pF
Capacitance6 W
CW
ICM
60
1
pF
nA
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
VA = VDD/2
VIH
VIL
VIH
VIL
IIL
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
2.4
2.1
V
V
V
V
µA
pF
0.8
0.6
1
VIN = 0 V or 5 V
CIL
5
3
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipationꢀ
VDD RANGE
IDD
PDISS
2.ꢀ
5.5
8
40
V
µA
µW
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
Power Supply Sensitivity
PSSR
VDD = +5 V 10%,
Code = Midscale
0.003
0.05 %/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
Total Harmonic Distortion
BW_5K
THDW
RAB = 5 kΩ, Code = 0x40
VA = 1 V rms, VB = 0 V,
f = 1 kHz
VA = 5 V, 1 LSB Error Band
RWB = 2.5 kΩ, RS = 0 Ω
1.2
MHz
0.05
1
%
µs
nV/√Hz
VW Settling Time
Resistor Noise Voltage Density
tS
eN_WB
6
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
ꢀ PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
Rev. 0 | Page 3 of 20
AD5247
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 2. VDD = 5 V ꢀ10 or 3 V ꢀ10; VA = VDD; –41°C < TA < +ꢀ25°C; unless otherwise noted
Parameter
Symbol Conditions
Min Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB
R-DNL
R-INL
∆RAB
RWB, VA = No Connect
RWB, VA = No Connect
–1
–2
–20
0.1
0.2ꢀ
+1
+2
+20
LSB
LSB
%
ppm/°C
Ω
∆RAB/∆T VA = VDD, Wiper = No Connect
RWB
4ꢀ
7ꢀ
Code = 0x00
300
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error (ꢀ0 kΩ, 100 kΩ)
Zero-Scale Error (ꢀ0 kΩ, 100 kΩ)
Full-Scale Error (10 kΩ)
DNL
INL
–1
–1
0.1
0.2
1ꢀ
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
∆VW/∆T
VWFSE
VWZSE
VWFSE
VWZSE
Code = 0x40
Code = 0x7F
Code = 0x00
Code = 0x7F
Code = 0x00
–1
0
–2
0
–1
0
+1
0
+0.4
–0.ꢀ
+0.ꢀ
LSB
LSB
Zero-Scale Error (10 kΩ)
+1
RESISTOR TERMINALS
Voltage Rangeꢀ
VA, W
CA
GND
VDD
V
Capacitance6 A
f = 1 MHz, Measured to GND,
Code = 0x40
f = 1 MHz, Measured to GND,
Code = 0x40
4ꢀ
pF
Capacitance6 W
CW
ICM
60
1
pF
nA
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
VA = VDD/2
VIH
VIL
VIH
VIL
IIL
VDD = ꢀV
VDD = ꢀ V
VDD = 3 V
VDD = 3 V
2.4
2.1
V
V
V
V
µA
pF
0.8
0.6
1
VIN = 0 V or ꢀ V
CIL
ꢀ
3
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
VDD RANGE
IDD
PDISS
2.7
ꢀ.ꢀ
8
40
V
µA
µW
VIH = ꢀ V or VIL = 0 V
VIH = ꢀ V or VIL = 0 V, VDD = ꢀ V
VDD = +ꢀ V 10%, Code = Midscale
PSSR
0.01
0.02 %/%
BW
RAB = 10 kΩ/ꢀ0 kΩ/100 kΩ,
Code = 0x40
VA =1 V rms, f = 1 kHz, RAB = 10 kΩ
VA = ꢀ V 1 LSB Error Band
RWB = ꢀ kΩ, RS = 0
600/100/40
0.0ꢀ
2
kHz
%
µs
Total Harmonic Distortion
VW Settling Time (10 kΩ/ꢀ0 kΩ/100 kΩ)
Resistor Noise Voltage Density
THDW
tS
eN_WB
9
nV/√Hz
1 Typical specifications represent average readings at 2ꢀ°C and VDD = ꢀ V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VA = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
ꢀ Resistor terminals A and W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = ꢀ V.
Rev. 0 | Page 4 of 20
AD5247
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 3. VDD = 5 V 1ꢀ0 or 3 V 1ꢀ0; VA = VDD; –4ꢀ°C < TA < +125°C; unless otherwise noted
Parameter
Symbol
Conditions
Min Typ1 Max Unit
I2C INTERFACE TIMING CHARACTERISTICS2, 3
(Specifications Apply to All Parts)
SCL Clock Frequency
tBUF Bus Free Time between STOP and START
tHD;STA Hold Time (Repeated START)
fSCL
t1
t2
400
kHz
µs
1.3
After this period, the first clock pulse is
generated.
0.6
1.3
0.6
0.6
µs
µs
µs
µs
µs
ns
ns
ns
µs
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated START Condition
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
t3
t4
t5
t6
tꢀ
t8
t9
t10
50
0.9
100
0.6
300
300
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 See timing diagrams (Figure 31, Figure 32, Figure 33) for locations of measured values.
Rev. 0 | Page 5 of 20
AD5247
ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25°C, unless otherwise noted1
Parameter
Value
1 Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
VDD to GND
VA, VW to GND
Terminal Current, Ax–Bx, Ax–Wx, Bx–Wx
Pulsed2
Continuous
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance3 θJA: SC70-6
–0.3 V to +7 V
VDD
±20 mA
±± mA
2 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
0 V to VDD + 0.3 V
–40°C to +12±°C
1±0°C
–6±°C to +1±0°C
300°C
3 Package power dissipation = (TJMAX – TA)/θJA.
)
340°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20
AD5247
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.25
0.20
0.15
0.10
0.05
0
V
= 2.7V
T
= 25°C
DD
A
–40°C
+25°C
+85°C
+125°C
0.8
0.6
R
= 10kΩ
R
= 10kΩ
AB
AB
V
= 2.7V
DD
0.4
0.2
T
= –40°C, +25°C, +85°C, +125°C
A
0
V
= 5.5V
DD
–0.05
–0.2
–0.10
–0.15
–0.20
–0.25
–0.4
–0.6
–0.8
–1.0
0
16
32
48
64
80
96
112
128
0
16
32
48
64
80
96
112
128
CODE (Decimal)
CODE (Decimal)
Figure 2. R-INL vs. Code vs. Supply Voltages
Figure 5. DNL vs. Code vs. Temperature
0.25
0.20
0.15
0.5
T
= 25°C
A
T
= 25°C
A
0.4
0.3
0.2
R
= 10kΩ
AB
R
= 10kΩ
AB
0.10
0.05
V
= 2.7V
DD
V
= 2.7V
DD
0.1
0
0
V
= 5.5V
–0.1
–0.2
–0.05
DD
64
V
= 5.5V
DD
–0.10
–0.15
–0.20
–0.3
–0.4
–0.25
–0.5
0
16
32
48
80
96
112
128
0
16
32
48
64
80
96
112
128
CODE (Decimal)
CODE (Decimal)
Figure 6. INL vs. Code vs. Supply Voltages
Figure 3. R-DNL vs. Code vs. Supply Voltages
0.25
0.20
0.15
0.25
0.20
T
= 25°C
V
R
= 2.7V
T
T
T
T
= –40°C
= +25°C
= +85°C
= +125°C
A
DD
AB
A
A
A
A
V
V
= 2.7V
= 5.5V
DD
R
= 10kΩ
= 10kΩ
AB
DD
0.15
T
= +25°C, +85°C, +125°C
0.10
0.05
0.10
0.05
A
V
= 2.7V
DD
0
0
–0.05
–0.05
T
= –40°C
V
= 5.5V
A
DD
80
–0.10
–0.15
–0.20
–0.10
–0.15
–0.20
–0.25
–0.25
0
16
32
48
64
96
112
128
0
16
32
48
64
80
96
112
128
CODE (Decimal)
CODE (Decimal)
Figure 4. INL vs. Code vs. Temperature
Figure 7. DNL vs. Code vs. Supply Voltages
Rev. 0 | Page ꢀ of 20
AD5247
1.50
1.0
0.8
T
= –40°C
A
1.25
1.00
0.75
T
= +85°C
A
0.6
0.4
0.2
V
= 5.5V, V = 5.5V
A
DD
T
= +25°C
0
A
T
= +125°C
A
–0.2
0.50
–0.4
–0.6
T
T
T
T
= –40°C
= +25°C
= +85°C
= +125°C
A
A
A
A
0.25
0
V
= 2.7V, V = 2.7V
A
DD
–0.8
–1.0
0
–40 –25 –10
5
20
35
50
65 80
95 110 125
16
32
48
64
80
96
112
128
TEMPERATURE (°C)
CODE (Decimal)
Figure 8. R-INL vs. Code vs. Temperature
Figure 11. Zero-Scale Error vs. Temperature
0.5
0.4
0.3
0.2
0.1
0
100
10
1
V
= 2.7V
DD
–40°C
+25°C
+85°C
+125°C
DIGITAL INPUTS = 0V
CODE = 0x40
R
= 10kΩ
AB
T
= –40°C, +25°C, +85°C, +125°C
A
V
= 5.5V
DD
–0.1
V
= 2.7V
–0.2
–0.3
–0.4
DD
0.1
–0.5
0
0.01
16
32
48
64
80
96
112
128
–40 –25 –10
5
20
35 50
65
)
80
95 110 125
CODE (Decimal)
TEMPERATURE (°C
Figure 9. R-DNL vs. Code vs. Temperature
Figure 12. Supply Current vs. Temperature
0
–0.5
–1.0
–1.5
–2.0
500
400
300
200
100
0
V
= 2.7V
DD
R
= 10kΩ
AB
V
= 5.5V, V = 5.5V
T = –40°C to +85°C
A
DD
A
–100
–200
–300
–400
–500
V
= 2.7V, V = 2.7V
A
DD
65
T
= –40°C to +125°C
A
–2.5
–3.0
–40 –25 –10
5
20 35
50
80
95 110 125
0
16
32
48
64
80
96
112
128
TEMPERATURE (°C)
CODE (Decimal)
Figure 13. Rheostat Mode Tempco ∆RWB/∆T vs. Code
Figure 10. Full-Scale Error vs. Temperature
Rev. 0 | Page 8 of 20
AD5247
30
0
–6
0x40
0x20
V
= 2.7V
DD
25
20
R
= 10kΩ
AB
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x10
0x08
0x04
0x02
0x01
15
10
5
T
= –40°C TO +85°C
A
0
–5
T
= –40°C TO +125°C
A
–10
0
16
32
48
64
80
96
112
128
10M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
CODE (Decimal)
Figure 14. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
Figure 17. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
0
–6
0x40
0x40
0x20
0x10
0x08
0x04
0x02
0x01
–6
0x20
–12
–18
–24
–30
–36
–42
–48
–54
–60
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x10
0x08
0x04
0x02
0x01
1k
10k
100k
FREQUENCY (Hz)
1M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 15. Gain vs. Frequency vs. Code, RAB = 5 kΩ
Figure 18. Gain vs. Frequency vs. Code, RAB = 100 kΩ
0
–6
0
–6
0x40
0x20
5kΩ
–12
–18
–24
–30
–36
–42
–48
–54
–60
–12
–18
–24
–30
–36
–42
–48
–54
–60
10kΩ
0x10
0x08
0x04
100kΩ
50kΩ
0x02
0x01
1k
10k
100k
FREQUENCY (Hz)
1M
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 16. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 19. –3 dB Bandwidth @ Code = 0x80
Rev. 0 | Page 9 of 20
AD5247
0.30
0.25
0.20
0.15
0.10
0.05
T
= 25°C
A - V = 5.5V
DD
A
V
V
V
= 5.5V
DD
T
= 25°C
A
CODE = 0x55
= 5.0V
= 0V
A
B
R
= 10kΩ
AB
B - V = 5.5V
DD
CODE 0x40 to 0x3F
CODE = 0x7F
C - V = 2.7V
DD
CODE = 0x55
D - V = 2.7V
DD
CODE = 0x7F
V
W
A
B
C
D
0
1k
10k
FREQUENCY (Hz)
100k
1M
200ns/DIV
Figure 20. IDD vs. Frequency
Figure 23. Midscale Glitch, Code 0x40 to 0x3F
150
125
100
75
T
= 25°C
= 50k
A
V
V
V
= 5.5V
T = 25°C
A
R
Ω
DD
A
B
AB
= 5.0V
= 0V
R
= 10kΩ
AB
CODE 0x00 to 0x7F
V
= 2.7V
DD
V
W
50
25
V
= 5.5V
64
DD
0
0
16
32
48
80
96
112
128
4µs/DIV
CODE (Decimal)
Figure 21. Wiper Resistance vs. Code vs. VDD
Figure 24. Large Signal Settling Time
T
= 25°C
= 10kΩ
V
V
V
= 5.5V
A
DD
A
B
R
F
= 5.0V
= 0V
AB
= 100kHz
CLK
V
W
5V
0V
CLK
1µs/DIV
Figure 22. Digital Feedthrough
Rev. 0 | Page 10 of 20
AD5247
TEST CIRCUITS
Figure 25 to Figure 30 define the test conditions used in the
product Specification tables.
V
A
V+ = V
10%
PSRR (dB) = 20 LOG
DD
DUT
∆V
∆V
MS
DD
DUT
A
V+ = V
DD
1LSB = V+/2
(
)
N
V
DD
A
%
∆V
∆V
MS
W
V+
W
PSS (%/%) =
V+
%
DD
B
B
V
MS
V
MS
Figure 28. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
Figure 25. Test Circuit for Potentiometer Divider
Nonlinearity Error (INL, DNL)
NO CONNECT
DUT
DUT
+15V
A
W
I
V
W
IN
A
W
OP27
–15V
V
OUT
B
B
V
MS
Figure 29. Test Circuit for Gain vs. Frequency
Figure 26. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
NC
DUT
I
= V /R
NOMINAL
DD
DUT
W
A
V
W
W
V
DD
V
I
A
B
MS2
CM
W
B
V
R
= [V
– V
]/I
W
MS2
MS1
W
MS1
GND
V
CM
NC
Figure 27. Test Circuit for Wiper Resistance
Figure 30. Test Circuit for Common-Mode Leakage Current
Rev. 0 | Page 11 of 20
AD5247
I2C INTERFACE
Table 5. Write Mode
S
0
1
0
1
1
1
1
0
0
W
R
A
A
X
0
D6
D5
D5
D4
D3
D2
D2
D1
D1
D0
D0
A
A
P
P
Slave Address Byte
Data Byte
Table 6. Read Mode
S
0
1
0
1
1
D6
D4
D3
Slave Address Byte
Data Byte
S = Start Condition.
P = Stop Condition.
A = Acknowledge.
X = Don’t Care.
= Write.
W
R = Read.
D6, D5, D4, D3, D2, D1, D0 = Data Bits.
t2
t8
t9
SCL
SDA
t6
t7
t5
t10
t2
t3
t4
t9
t8
t1
P
S
S
P
Figure 31. I2C Interface, Detailed Timing Diagram
1
0
9
1
9
1
SCL
SDA
X
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
0
R/W
ACK BY
AD5247
ACK BY
AD5247
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
STOP BY
MASTER
START BY
MASTER
DATA BYTE
Figure 32. Writing to the RDAC Register
1
9
1
9
SCL
0
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
R/W
SDA
ACK BY
AD5247
NO ACK
BY MASTER
STOP BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
RDAC REGISTER
START BY
MASTER
Figure 33. Reading from the RDAC Register
Rev. 0 | Page 12 of 20
AD5247
OPERATION
The AD5247 is a 128-position, digitally controlled variable
resistor (VR) device. An internal power-on preset places the
wiper at midscale during power-on, which simplifies the default
condition recovery at power-up.
The general equation determining the digitally programmed
output resistance between W and B is
D
128
RWB(D) =
×RAB +2×RW
(1)
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
where D is the decimal equivalent of the binary code loaded in
the 7-bit RDAC register, RAB is the end-to-end resistance, and
RW is the wiper resistance contributed by the on resistance of
the internal switch. In summary, if RAB = 10 kΩ and the A
terminal is open-circuited, the output resistance RWB shown in
Table 7 will be set for the indicated RDAC latch codes.
The nominal resistance of the RDAC between terminals A and
B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two
or three digits of the part number determine the nominal
resistance value, e.g., 10 kΩ = 10, 50 kΩ = 50. The nominal
resistance (RAB) of the VR has 128 contact points accessed by
the wiper terminal, plus the B terminal contact. The 7-bit data
in the RDAC latch is decoded to select one of the 128 possible
settings.
Table 7. Codes and Corresponding RWB Resistance
D (Dec.)
RWB (Ω)
10,100
5,100
1ꢀ8
Output State
12ꢀ
64
1
Full Scale (RAB + 2 × RW)
Midscale
1 LSB
Assuming a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for data 0x00. Since there is a 50 Ω wiper
contact resistance, such a connection yields a minimum of
100 Ω (2 × 50 Ω) resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
178 Ω (RWB = RAB/128+ RW = 78 Ω + 2 × 50 Ω) for data 0x01.
The third connection is the next tap point, representing 256 Ω
(2 × 78 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the
last tap point is reached at 10,100 Ω (RAB + 2 × RW).
0
100
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition, a finite resistance of
100 Ω between terminals W and B is present. Care should be
taken to limit the current flow between W and B in this state to
a maximum pulse current of no more than 20 mA. Otherwise,
degradation or possible destruction of the internal switch
contact can occur.
Figure 34 shows a simplified diagram of the equivalent RDAC
circuit where the last resistor string will not be accessed.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
Ax
D6
RS
D5
D4
D3
128– D
128
D2
RS
RWA(D) =
×RAB + 2×RW
(2)
D1
Wx
Bx
D0
For RAB = 10 kΩ and the B terminal open circuited, the output
resistance RWA shown in Table 8 will be set for the indicated
RDAC latch codes.
RDAC
LATCH
AND
RS
DECODER
Table 8. Codes and Corresponding RWA Resistance
D (Dec.)
RWA (Ω)
Output State
Full Scale
Midscale
1 LSB
Figure 34. AD5247 Equivalent RDAC Circuit
12ꢀ
64
1
1ꢀ8
5,100
9,961
10,100
0
Zero Scale
Typical device-to-device matching is process lot dependent and
may vary by up to 30ꢀ. Since the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 45 ppm/°C temperature coefficient.
Rev. 0 | Page 13 of 20
AD5247
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A–B, W–A, and W–B can be at either
polarity.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/ bit is high, the master will read
from the slave device. On the other hand, if the R/ bit is
W
low, the master will write to the slave device.
W
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 128 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
2. In write mode, after acknowledgement of the slave address
byte, the next byte is the data byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (eight data
bits followed by an acknowledge bit). The transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Table 5).
D
128
VW(D) =
VA
(3)
3. In read mode, after acknowledgment of the slave address
byte, data is received over the serial bus in sequences of
nine clock pulses (a slight difference from write mode,
where eight data bits are followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 33).
For a more accurate calculation, which includes the effect of
wiper resistance, VW, can be found as
RWB(D)
RAB
VW(D) =
VA
(4)
Operation of the digital potentiometer in the divider mode
4. When all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 32). In read mode, the master will
issue a No Acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse, which goes high
to establish a STOP condition (see Figure 33).
results in a more accurate operation over temperature. Unlike in
rheostat mode, the output voltage in divider mode is dependent
mainly on the ratio of internal resistors RWA and RWB and not
the absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
I2C COMPATIBLE 2-WIRE SERIAL BUS
The first byte of the AD5247 is a slave address byte (see Table 5
and Table 6). It has a 7-bit slave address and a R/ bit. The
W
seven MSBs of the slave address are 0101110 followed by 0 for a
write command or 1 to place the device in read mode.
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing the part only
once. For example, after the RDAC has acknowledged its slave
address in the write mode, the RDAC output will update on
each successive byte. If different instructions are needed, the
write/read mode has to start again with a new slave address and
data byte. Similarly, a repeated read function of the RDAC is
also allowed.
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 32). The
following byte is the slave address byte, which consists of
the 7-bit slave address followed by an R/ bit (this bit
W
determines whether data will be read from or written to
the slave device).
Rev. 0 | Page 14 of 20
AD5247
V
DD
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 3.3 V
E2PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional communi-
cation so that the setting of the digital potentiometer can be
stored to and retrieved from the E2PROM. Figure 35 shows one
of the implementations. M1 and M2 can be any N channel
signal FETs, or if VDD falls below 2.5 V, M1 and M2 can be low
threshold FETs such as the FDV301N.
A
W
GND
Figure 38. Maximum Terminal Voltages Set by VDD and GND
MAXIMUM OPERATING CURRENT
At low code values, the user should be aware that due to low
resistance values, the current through the RDAC may exceed
the 5 mA limit. In Figure 39, a 5 V supply is placed on the wiper,
and the current through terminals W and B is plotted with
respect to code. A line is also drawn denoting the 5 mA current
limit. Note that at low code values (particularly for the 5 kΩ and
10 kΩ options), the current level increases significantly. Care
should be taken to limit the current flow between W and B in
this state to a maximum continuous current of 5 mA and a
maximum pulse current of no more than 20 mA. Otherwise,
degradation or possible destruction of the internal switch
contacts can occur.
V
= 3.3V
V
= 5V
DD1
DD2
R
R
R
R
P
P
P
P
G
S
D
SDA2
SCL2
SDA1
SCL1
G
M1
S
D
M2
3.3V
5V
2
AD5247
E PROM
Figure 35. Level Shifting for Operation at Different Potentials
100.00
ESD PROTECTION
10.00
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 36 and Figure 37.
This applies to the digital input pins SDA and SCL.
5mA CURRENT LIMIT
R
= 5kΩ
AB
1.00
R
= 10kΩ
AB
340Ω
LOGIC
R
= 50kΩ
AB
0.10
0.01
R
= 100k
96
Ω
AB
GND
Figure 36. ESD Protection of Digital Pins
64
80
112
128
0
16
32
48
CODE (Decimal)
A,W
Figure 39. Maximum Operating Current
POWER-UP SEQUENCE
GND
Since the ESD protection diodes limit the voltage compliance at
terminals A and W (see Figure 38), it is important to power
VDD/GND before applying any voltage to terminals A and W;
otherwise, the diode will be forward biased such that VDD will be
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA/VW. The relative order of
powering VA and VW and the digital inputs is not important as
long as they are powered after VDD/GND.
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5247 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A and W that
exceed VDD or GND will be clamped by the internal forward
biased diodes (see Figure 38).
Rev. 0 | Page 15 of 20
AD5247
110%
108%
106%
104%
102%
100%
98%
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ a compact, minimum lead-length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
T
= 25°C
A
Similarly, it is a good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disc or chip
ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electro-
lytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 40). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
96%
94%
92%
90%
0
5
10
15
DAYS
20
25
30
Figure 41. Battery Operating Life Depletion
This demonstrates that constantly biasing the pot is not an
impractical approach. Most portable devices do not require the
removal of batteries for the purpose of charging. Although the
resistance setting of the AD5247 will be lost when the battery
needs replacement, such events occur rather infrequently such
that this inconvenience is justified by the lower cost and smaller
size offered by the AD5247. If and when total power is lost, the
user should be provided with a means to adjust the setting
accordingly.
V
V
DD
DD
+
10µF
C3
C1
0.1µF
AD5247
GND
Figure 40. Power Supply Bypassing
EVALUATION BOARD
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
An evaluation board, along with all necessary software, is
available to program the AD5247 from any PC running
Windows® 98, Windows 2000®, or Windows XP®. The graphical
user interface, as shown in Figure 42, is straightforward and
easy to use. More detailed information is available in the user
manual, which comes with the board.
For users who desire nonvolatility but cannot justify the
additional cost for the EEMEM, the AD5247 may be considered
as a low cost alternative by maintaining a constant bias to retain
the wiper setting. The AD5247 was designed specifically with
low power in mind, which allows low power consumption even
in battery-operated systems. The graph in Figure 41
demonstrates the power consumption from a 3.4 V 450 mAhr
Li-ion cell phone battery, which is connected to the AD5247.
The measurement over time shows that the device draws
approximately 1.3 µA and consumes negligible power. Over a
course of 30 days, the battery was depleted by less than 2ꢀ, the
majority of which is due to the intrinsic leakage current of the
battery itself.
Figure 42. AD5247 Evaluation Board Software
Rev. 0 | Page 16 of 20
AD5247
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
6
5
4
V
GND
SCL
A
W
SDA
AD5247
TOP VIEW
(Not to Scale)
DD
Figure 43. Pin Configuration (6-Lead SC70)
Table 9. AD5247 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
VDD
GND
SCL
SDA
W
Positive Power Supply.
Digital Ground and B Termination Voltage.
Serial Clock Input. Positive edge triggered.
Serial Data Input/Output.
W Terminal.
A
A Terminal.
Rev. 0 | Page 1ꢀ of 20
AD5247
OUTLINE DIMENSIONS
2.00 BSC
6
5
2
4
3
2.10 BSC
1.25 BSC
1
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
1.10 MAX
0.22
0.08
0.46
0.36
0.26
8°
4°
0°
0.30
0.15
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AB
Figure 44. 6-Lead Thin Shrink Small Outline Transistor [SC70]
(KS-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model
RAB (kΩ)
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
6-lead SCꢀ0
6-lead SCꢀ0
6-lead SCꢀ0
6-lead SCꢀ0
6-lead SCꢀ0
6-lead SCꢀ0
6-lead SCꢀ0
6-lead SCꢀ0
Package Option
Branding
D1E
D1E
D19
D19
D18
D18
D1ꢀ
D1ꢀ
AD524ꢀBKS5-R2
AD524ꢀBKS5-RLꢀ
AD524ꢀBKS10-R2
AD524ꢀBKS10-RLꢀ
AD524ꢀBKS50-R2
AD524ꢀBKS50-RLꢀ
AD524ꢀBKS100-R2
AD524ꢀBKS100-RLꢀ
AD524ꢀEVAL
5
5
10
10
50
50
100
100
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
See Note 1
Evaluation Board
1 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. 0 | Page 18 of 20
AD5247
NOTES
Rev. 0 | Page 19 of 20
AD5247
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the
purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C
Standard Specification as defined by Philips.
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03876–0–9/03(0)
Rev. 0 | Page 20 of 20
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