AD5258 [ADI]
Nonvolatile, I2C-Compatible 64-Position, Digital Potentiometer; 非易失， I2C兼容64位，数字电位器
| 型号： | AD5258 |
| 厂家： | 
ADI |
| 描述： | Nonvolatile, I2C-Compatible 64-Position, Digital Potentiometer |
| 文件： | 总24页 (文件大小：1241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nonvolatile, I2C-Compatible
64-Position, Digital Potentiometer
AD5258
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Nonvolatile memory maintains wiper settings
64-position
Compact MSOP-10 (3 mm × 4.9 mm) package
I2C®-compatible interface
VLOGIC pin provides increased interface flexibility
End-to-end resistance 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time <1 ms
Software write protect command
RDAC
V
DD
A
RDAC
V
RDAC
LOGIC
EEPROM
W
REGISTER
GND
B
6
6
DATA
CONTROL
SCL
SDA
2
I C
SERIAL
INTERFACE
AD0
AD1
COMMAND
DECODE LOGIC
AD5258
ADDRESS
DECODE LOGIC
POWER-
ON RESET
Three-state Address Decode Pins AD0 and AD1 allow
9 packages per bus
CONTROL LOGIC
100-year typical data retention at 55°C
Wide operating temperature −40°C to +85°C
3 V to 5 V single supply
Figure 1. Block Diagram
V
V
DD
LOGIC
A
EEPROM
APPLICATIONS
SCL
SDA
AD0
AD1
RDAC
REGISTER
AND
2
I C
LCD panel VCOM adjustment
SERIAL
INTERFACE
LEVEL
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
SHIFTER
W
COMMAND
DECODE LOGIC
ADDRESS
DECODE LOGIC
CONTROL
LOGIC
GND
B
Figure 2. Block Diagram Showing Level Shifters
Electronics level settings
GENERAL DESCRIPTION
CONNECTION DIAGRAM
The AD5258 provides a compact, nonvolatile 3 mm × 4.9 mm
packaged solution for 64-position adjustment applications.
These devices perform the same electronic adjustment function
as mechanical potentiometers1 or variable resistors, but with
enhanced resolution and solid-state reliability.
W
AD0
AD1
SDA
SCL
1
2
3
4
5
10
9
A
B
V
AD5258
8
TOP VIEW
DD
(Not to Scale)
7
GND
6
V
LOGIC
Figure 3. Pinout
The wiper settings are controllable through an I2C-compatible
digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM providing an end-to-end tolerance accuracy of 0.1%.
There is also a software write protection function that ensures
data cannot be written to the EEPROM register.
1 The terms digital potentiometer, VR (variable resistor), and RDAC are used
interchangeably.
A separate VLOGIC pin delivers increased interface flexibility. For
users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to nine devices on the same bus.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD5258
TABLE OF CONTENTS
Specifications..................................................................................... 3
Write Modes ................................................................................ 17
Read Modes................................................................................. 17
Store/Restore Modes .................................................................. 17
Tolerance Readback Modes ...................................................... 18
ESD Protection of Digital Pins and Resistor Terminals........ 19
Power-Up Sequence ................................................................... 19
Layout and Power Supply Bypassing ....................................... 19
Multiple Devices on One Bus ................................................... 19
Evaluation Board........................................................................ 19
Display Applications ...................................................................... 20
Circuitry ...................................................................................... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Electrical Characteristics............................................................. 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 13
Theory of Operation ...................................................................... 14
Programming the Variable Resistor......................................... 14
Programming the Potentiometer Divider............................... 14
I2C Interface..................................................................................... 15
I2C Byte Formats............................................................................. 16
Generic Interface ........................................................................ 16
REVISION HISTORY
3/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD5258
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = VLOGIC = 5 V 10%, or 3 V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ −40°C < TA < +85°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS: RHEOSTAT MODE
Resistor Differential Nonlinearity
1 kΩ
R-DNL
RWB, VA = no connect
LSB
−1.5
−0.25
0.3
0.1
+1.5
+0.25
10 kΩ/50 kΩ/100 kΩ
Resistor Integral Nonlinearity
1 kΩ
10 kΩ/100 kΩ
50 kΩ
R-INL
RWB, VA = no connect
TA = 25°C, VDD = 5.5 V
LSB
−5
−0.5
−0.25
0.5
0.1
0.1
+5
+0.5
+0.25
Nominal Resistor Tolerance
1 kΩ
RAB
0.9
1.5
kΩ
10 kΩ/50 kΩ/100 kΩ
Resistance Temperature Coefficient
Total Wiper Resistance
∆RAB
−30
+30
%
(∆RAB × 106)/(RAB × ∆T) Code = 0x00/0x20
200/15
75
ppm/°C
Ω
RWB
Code = 0x00
350
DC CHARACTERISTICS:
POTENTIOMETER DIVIDER MODE
Differential Nonlinearity
1 kΩ
10 kΩ/50 kΩ/100 kΩ
Integral Nonlinearity
1 kΩ
10 kΩ/50 kΩ/100 kΩ
Full-Scale Error
1 kΩ
DNL
LSB
LSB
LSB
−1
−0.25
0.3
0.1
+1
+0.25
INL
−1
−0.25
0.3
0.1
+1
+0.25
VWFSE
Code = 0x3F
−6
−1
−1
−3
−0.3
−0.1
0
0
0
10 kΩ
50 kΩ/100 kΩ
Zero-Scale Error
1 kΩ
10 kΩ
50 kΩ/100 kΩ
VWZSE
Code = 0x00
LSB
0
0
0
3
5
1
0.5
0.3
0.1
120/15
Voltage Divider Temperature
Coefficient
(∆VW × 106)/(VW × ∆T)
Code = 0x00/0x20
ppm/°C
RESISTOR TERMINALS
Voltage Range
VA, B, W
CA, B
GND
VDD
V
pF
Capacitance A, B
f = 1 MHz, measured to GND,
code = 0x20
f = 1 MHz, measured to GND,
code = 0x20
45
60
10
Capacitance W
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
VA = VB = VDD/2
nA
VIH
VIL
IIL
0.7 × VL
−0.5
VL + 0.5
0.3 × VL
V
V
µA
Input Logic Low
Leakage Current
SDA, AD0, AD1
SCL – Logic High
SCL – Logic Low
VIN = 0 V or 5 V
VIN = 0 V
VIN = 5 V
0.01
−1.4
0.01
5
1
+1
1
−2.5
Input Capacitance
CIL
pF
Rev. 0 | Page 3 of 24
AD5258
Parameter
Symbol
Conditions
Min
2.7
Typ1
Max
Unit
POWER SUPPLIES
Power Supply Range
Positive Supply Current
Logic Supply
VDD
IDD
VLOGIC
ILOGIC
5.5
2
5.5
6
V
µA
V
µA
mA
µW
%/%
0.5
2.7
Logic Supply Current
Programming Mode Current (EEPROM) ILOGIC(PROG)
Power Dissipation
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = +5 V 10%, Code = 0x20
3.5
35
20
PDISS
PSRR
40
0.06
Power Supply Rejection Ratio
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB
0.01
BW
Code = 0x20
RAB = 1 kΩ
RAB = 10 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
RAB = 10 kΩ, VA = 1 V rms, VB = 0,
f = 1 kHz
RAB = 10 kΩ, VAB = 5 V,
1 LSB error band
18000
1000
190
100
0.1
kHz
kHz
kHz
kHz
%
Total Harmonic Distortion
VW Settling Time
THDW
tS
500
9
ns
Resistor Noise Voltage Density
eN_WB
RWB = 5 kΩ, f = 1 kHz
nV/√Hz
1
Typical values represent average readings at 25°C and VDD = 5 V.
Rev. 0 | Page 4 of 24
AD5258
TIMING CHARACTERISTICS
VDD = VLOGIC = 5 V 10%, or 3 V 10%ꢀ VA = VDDꢀ VB = 0 Vꢀ −40°C < TA < +85°C, unless otherwise noted.
Table 2.
Parameter
I2C INTERFACE TIMING CHARACTERISTICS
Symbol
Conditions
Min Typ Max Unit
SCL Clock Frequency
tBUF Bus Free Time between STOP and START
tHD;STA Hold Time (Repeated START)
fSCL
t1
t2
0
1.3
0.6
400
kHz
µs
µs
After this period, the first clock pulse is
generated.
tLOW Low Period of SCL Clock
tHIGH High Period of SCL Clock
tSU;STA Setup Time for Repeated START
Condition
t3
t4
t5
1.3
0.6
0.6
µs
µs
µs
tHD;DAT Data Hold Time
tSU;DAT Data Setup Time
t6
t7
t8
t9
0
100
0.9
µs
ns
ns
ns
µs
ms
µs
tF Fall Time of Both SDA and SCL Signals
tR Rise Time of Both SDA and SCL Signals
tSU;STO Setup Time for STOP Condition
EEPROM Data Storing Time
300
300
t10
0.6
tEEMEM_STORE
26
300
EEPROM Data Restoring Time at Power On1
tEEMEM_RESTORE1 VDD rise time dependant. Measure
without decoupling capacitors at VDD and
GND.
EEPROM Data Restoring Time upon Restore
Command1
tEEMEM_RESTORE2 VDD = 5 V.
300
540
µs
µs
EEPROM Data Rewritable Time2
FLASH/EE MEMORY RELIABILITY
Endurance3
tEEMEM_REWRITE
100 700
100
kCycles
Years
Data Retention4
1 During power-up, the output is momentarily preset to midscale before restoring EEPROM content.
2 Delay time after power-on PRESET prior to writing new EEPROM data.
3 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
4 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates
with junction temperature.
t6
t8
t9
SCL
t10
t5
t7
t4
t2
t3
t9
t8
t1
SDA
P
S
P
Figure 4. I2C Interface Timing Diagram
Rev. 0 | Page 5 of 24
AD5258
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating onlyꢀ functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Value
−0.3 V to +7 V
GND − 0.3 V, VDD + 0.3 V
VDD to GND
VA, VB, VW to GND
IMAX
Pulsed1
20 mA
5 mA
Continuous
Digital Inputs and Output Voltage to GND 0 V to +7 V
−40°C to +85°C
150°C
Operating Temperature Range
Maximum Junction Temperature (TJMAX
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance2 θJA: MSOP − 10
)
−65°C to +150°C
300°C
200°C/W
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA
.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 24
AD5258
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W
AD0
AD1
SDA
SCL
1
2
3
4
5
10
9
A
B
V
AD5258
8
TOP VIEW
DD
(Not to Scale)
7
GND
6
V
LOGIC
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
W Terminal, GND ≤ VW ≤ VDD.
Programmable Three-State Address Bit 0 for Multiple Package Decoding. State is registered on
power-up.
1
2
W
ADO
3
AD1
Programmable Three-State Address Bit 1 for Multiple Package Decoding. State is registered on
power-up.
4
5
6
7
8
9
10
SDA
SCL
VLOGIC
GND
VDD
B
Serial Data Input/Output.
Serial Clock Input. Positive edge triggered.
Logic Power Supply.
Digital Ground.
Positive Power Supply.
B Terminal, GND ≤ VB ≤ VDD.
A Terminal, GND ≤ VA ≤ VDD.
A
Rev. 0 | Page 7 of 24
AD5258
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = VLOGIC = 5.5 V, RAB = 10 kΩ, TA = 25°C, unless otherwise noted.
0.5
0.4
0.3
0.2
0.10
0.08
0.06
0.04
0.02
0
2.7V
0.1
0
5.5V
–0.1
–0.02
–0.04
–0.06
–0.08
–0.10
–40°C
+85°C
+25°C
–0.2
–0.3
–0.4
–0.5
0
8
16
24
65
40
48
56
64
0
8
16
24
65
40
48
56
64
CODE (Decimal)
CODE (Decimal)
Figure 6. R-INL vs. Code vs. Supply Voltage
Figure 9. DNL vs. Code vs. Temperature
0.25
0.20
0.15
0.10
0.05
0
0.10
0.08
0.06
0.04
0.02
0
2.7V
5.5V
–0.05
–0.10
–0.15
–0.20
–0.25
–0.02
–0.04
–0.06
–0.08
–0.10
5.5V
2.7V
0
8
16
24
65
40
48
56
64
0
8
16
24
65
40
48
56
64
CODE (Decimal)
CODE (Decimal)
Figure 7. R-DNL vs. Code vs. Supply Voltages
Figure 10. INL vs. Supply Voltages
0.10
0.08
0.06
0.04
0.02
0
0.10
0.08
0.06
0.04
0.02
0
2.7V
+85°C
–0.02
–0.04
–0.06
–0.08
–0.10
–0.02
–0.04
–0.06
–0.08
–0.10
+25°C
–40°C
5.5V
0
8
16
24
65
40
48
56
64
0
8
16
24
65
40
48
56
64
CODE (Decimal)
CODE (Decimal)
Figure 8. INL vs. Code vs. Temperature
Figure 11. DNL vs. Code vs. Supply Voltages
Rev. 0 | Page 8 of 24
AD5258
0.25
0.20
0.15
0.10
0.05
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
ZSE @ V = 2.7V
DD
ZSE @ V = 5.5V
DD
–40°C
+85°C
+25°C
–0.05
–0.10
–0.15
–0.20
–0.25
0
8
16
24
65
40
48
56
64
–40
–20
0
20
40
60
80
CODE (Decimal)
TEMPERATURE (°C)
Figure 12. R-INL vs. Code vs. Temperature
Figure 15. Zero-Scale Error vs. Temperature
1
0.25
0.20
0.15
0.10
0.05
0
+85°C
–40°C
V
= 5.5V
DD
+25°C
–0.05
–0.10
–0.15
–0.20
–0.25
0.1
–40
–20
0
20
40
60
80
0
8
16
24
65
40
48
56
64
TEMPERATURE (°C)
CODE (Decimal)
Figure 13. R-DNL vs. Code vs. Temperature
Figure 16. Supply Current vs. Temperature
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
6
5
4
3
2
1
V
= 5.5V
DD
FSE @ V = 5.5V
DD
FSE @ V = 2.7V
DD
V
= 2.7V
20
DD
0
–40
–40
–20
0
20
40
60
80
–20
0
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Full-Scale Error vs. Temperature
Figure 17. Logic Supply Current vs. Temperature vs. VDD
Rev. 0 | Page 9 of 24
AD5258
250
200
150
100
50
120
100
80
60
40
20
0
100k Rt @ V = 5.5V
DD
1k
50k
50k Rt @ V = 5.5V
DD
10k
0
10k Rt @ V = 5.5V
DD
–50
–100
1k Rt @ V = 5.5V
DD
100k
–150
0
–40
–20
0
20
40
60
80
8
16
24
65
40
48
56
64
TEMPERATURE (°C)
CODE (Decimal)
Figure 18. Rheostat Mode Tempco (ΔRAB ×106)/( RAB × ∆T) vs. Code
Figure 21. Total Resistance vs. Temperature
120
0
–6
20
H
100
10
08
H
H
1k
–12
–18
–24
–30
–36
–42
–48
–54
–60
80
60
04
02
H
H
01
H
40
50k
20
0
10k
100k
–20
0
8
16
24
65
40
48
56
64
10k
100k
1M
10M
100M
CODE (Decimal)
FREQUENCY (Hz)
Figure 19. Potentiometer Mode Tempco (ΔVW × 106)/( VW × ΔT) vs. Code
Figure 22. Gain vs. Frequency vs. Code, RAB = 1 kΩ
350
300
0
–6
20
10
08
H
H
–12
–18
–24
–30
–36
–42
–48
–54
–60
R
@ V = 2.7V
DD
H
H
WB
250
200
150
100
50
04
02
01
H
H
R
@ V = 5.5V
DD
WB
0
–40
–20
0
20
40
60
80
1k
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 20. RWB vs. Temperature
Figure 23. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Rev. 0 | Page 10 of 24
AD5258
0
–6
80
60
40
20
0
CODE = MIDSCALE, V = V
, V = 0V
B
20
10
A
LOGIC
H
H
–12
–18
–24
–30
–36
–42
–48
–54
–60
PSRR @ V
= 5V DC ± 10% p-p AC
LOGIC
08
04
02
01
H
H
H
H
PSRR @ V
= 3V DC ± 10% p-p AC
LOGIC
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27. PSRR vs. Frequency
Figure 24. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
–6
20
10
08
04
02
01
H
H
H
H
H
H
–12
–18
–24
–30
–36
–42
–48
–54
–60
V
W
1
SCL
2
400ns/DIV
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 28. Digital Feedthrough
Figure 25. Gain vs. Frequency vs. Code, RAB = 100 kΩ
10k
1k
V
= V = 5V
LOGIC
DD
V
W
1
V
= V
= 3V
LOGIC
DD
100
10
1µs/DIV
0
1
2
3
4
5
V
(V)
IH
Figure 29. Midscale Glitch, Code 0×7F to 0×80
Figure 26. Logic Supply Current vs. Input Voltage
Rev. 0 | Page 11 of 24
AD5258
V
W
1
SCL
2
200ns/DIV
Figure 30. Large Signal Settling Time
Rev. 0 | Page 12 of 24
AD5258
TEST CIRCUITS
Figure 31 through Figure 36 illustrate the test circuits that
define the test conditions used in the product specification
tables.
V
V+ = V
1LSB = V+/2
A
V+ = V
±
10%
DUT
W
DD
DD
N
∆V
∆V
MS
)
A
B
DUT
W
PSRR (dB) = 20 LOG
(
%
%
DD
∆V
∆V
A
B
V+
MS
∆V
PSS (%/%) =
DD
DD
V+
V
MS
V
MS
Figure 31. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
Figure 34. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
NO CONNECT
DUT
DUT
+5V
A
W
V
I
IN
W
A
W
AD8610
–5V
V
OUT
B
OFFSET
GND
B
+2.5V
V
MS
Figure 32. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
Figure 35. Test Circuit for Gain vs. Frequency
0.1V
R
=
SW
I
SW
DUT
DUT
I
= V /R
DD NOMINAL
CODE = 0x00
W
A
B
W
V
W
W
V
MS2
I
SW
0.1V
R
= [V
– V
]/I
W
MS1
MS2 W
B
V
MS1
GND TO V
DD
Figure 33. Test Circuit for Wiper Resistance
Figure 36. Test Circuit for Common-Mode Leakage Current
Rev. 0 | Page 13 of 24
AD5258
THEORY OF OPERATION
The AD5258 is a 64-position digitally controlled variable
resistor (VR) device. The wiper’s default value, prior to
programming the EEPROM, is midscale.
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A produces a digitally
controlled complementary resistance, RWA. The resistance value
setting for RWA starts at a maximum value of resistance and
decreases as the data loaded in the latch increases in value. The
general equation for this operation is
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance (RAB) of the RDAC between Terminal A
and Terminal B is available in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance of the VR has 64 contact points
accessed by the wiper terminal. The 6-bit data in the RDAC
latch is decoded to select one of 64 possible settings.
64 − D
64
(2)
RWA (D) =
× RAB + 2 × RW
Typical device-to-device matching is process lot dependent and
may vary by up to 30%. For this reason, resistance tolerance is
stored in the EEPROM such that the user will know the actual
A
A
A
R
AB within 0.1%.
W
W
W
PROGRAMMING THE POTENTIOMETER DIVIDER
B
B
B
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
Wiper W-to-Terminal B and Wiper W-to-Terminal A propor-
tional to the input voltage at Terminal A to Terminal B. Unlike
the polarity of VDD to GND, which must be positive, voltage
across Terminal A to Terminal B, Wiper W to Terminal A, and
Wiper W to Terminal B can be at either polarity.
Figure 37. Rheostat Mode Configuration
The general equation determining the digitally programmed
output resistance between Wiper W and Terminal B is
D
(1)
RWB
(
D
)
=
× RAB + 2 × RW
64
V
I
A
where:
D is the decimal equivalent of the binary code loaded in the
6-bit RDAC register.
W
V
O
R
R
AB is the end-to-end resistance.
W is the wiper resistance contributed by the on resistance of
B
each internal switch.
Figure 39. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at Wiper W-to-Terminal B starting
at 0 V up to 1 LSB less than 5 V. The general equation defining
the output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
A
R
S
D5
D4
D3
D2
D1
D0
R
R
S
S
W
D
VW (D) = VA +
64
64 − D
64
(3)
VB
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
R
RDAC
S
R
WB (D)
RAB
RWA(D)
RAB
LATCH
AND
DECODER
(4)
VW (D) =
VA +
VB
B
Figure 38. AD5258 Equivalent RDAC Circuit
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the Internal Resistors, RWA and RWB, and not the
absolute values.
Note that in the zero-scale condition, there is a relatively low
value finite wiper resistance. Care should be taken to limit the
current flow between Wiper W and Terminal B in this state to a
maximum pulse current of no more than 20 mA. Otherwise,
degradation or destruction of the internal switch contact can
occur.
Rev. 0 | Page 14 of 24
AD5258
I2C INTERFACE
(store), or from EEPROM to RDAC (restore). The final five
bits are all zeros (see Table 13 to Table 14).
Note that the wiper’s default value, prior to programming the
EEPROM, is midscale.
4. Reading: Assuming the register of interest was not just
written to, it is necessary to write a dummy address and
instruction byte. The instruction byte will vary depending
on whether the data that is wanted is the RDAC register,
EEPROM register, or tolerance register (see Table 11 to
Table 16).
1. The master initiates data transfer by establishing a START
condition when a high-to-low transition on the SDA line
occurs while SCL is high (see Figure 4). The next byte is
the slave address byte, which consists of the slave address
(first 7 bits) followed by an R/ bit (see Table 6). When the
W
R/ bit is high, the master reads from the slave device.
W
When the R/ bit is low, the master writes to the slave
W
device.
After the dummy address and instruction bytes are sent, a
repeat start is necessary. After the repeat start, another
address byte is needed, except this time the R/ bit is logic
W
The slave address of the part is determined by two three-
state-configurable Address Pins AD0 and AD1. The state of
these two pins is registered upon power-up and decoded
into a corresponding I2C 7-bit address (see Table 5). The
slave address corresponding to the transmitted address bits
responds by pulling the SDA line low during the ninth
clock pulse (this is termed the slave acknowledge bit).
high. Following this address byte is the readback byte
containing the information requested in the instruction
byte. Read bits appear on the negative edges of the clock.
Don’t cares may either be in a high or low state.
The tolerance register can be read back individually (see
Table 15) or consecutively (see Table 16). Refer to the Read
Modes section for detailed information on the interpreta-
tion of the tolerance bytes.
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its serial register.
5. After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the tenth clock pulse to establish a STOP
condition (see Figure 45). In read mode, the master issues a
no acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master then brings the SDA line
low before the tenth clock pulse, and then raises SDA high
to establish a STOP condition (see Figure 46).
2. Writing: In the write mode, the last bit (R/ ) of the slave
W
address byte is logic low. The second byte is the instruction
byte. The first three bits of the instruction byte are the
command bits (see Table 6). The user must choose whether
to write to the RDAC register, EEPROM register, or
activate the software write protect (see Table 7 to Table 10).
The final five bits are all zeros (see Table 13 to Table 14).
The slave again responds by pulling the SDA line low during
the ninth clock pulse.
A repeated write function gives the user flexibility to
update the RDAC output a number of times after
addressing and instructing the part only once. For
example, after the RDAC has acknowledged its slave
address and instruction bytes in the write mode, the RDAC
output is updated on each successive byte until a STOP
condition is received. If different instructions are needed,
the write/read mode has to start again with a new slave
address, instruction, and data byte. Similarly, a repeated
read function of the RDAC is also allowed.
The final byte is the data byte MSB first. Don’t cares can be
left either high or low. In the case of the write protect
mode, data is not storedꢀ rather, a logic high in the LSB
enables write protect. Likewise, a logic low will disable
write protect. The slave again responds by pulling the SDA
line low during the ninth clock pulse.
3. Storing/Restoring: In this mode, only the address and
instruction bytes are necessary. The last bit (R/ ) of the
W
address byte is logic low. The first three bits of the
instruction byte are the command bits (see Table 6). The
two choices are transfer data from RDAC to EEPROM
Rev. 0 | Page 15 of 24
AD5258
I2C BYTE FORMATS
Table 5. Device Address Lookup
The following generic, write, read, and store/restore control
registers for the AD5258 all refer to the device addresses listed
in Table 5, and the mode/condition reference key (S, P, SA, MA,
AD1 and AD0 are three-state address pins.
Device Address
0011000
0011001
0011010
0101001
0101010
0101011
1001100
1001101
1001110
AD1
0
NC
1
0
NC
1
0
NC
1
AD0
0
0
W
NA, , R, and X) listed below.
S = Start Condition
0
P = Stop Condition
NC
NC
NC
1
1
1
SA = Slave Acknowledge
MA = Master Acknowledge
NA = No Acknowledge
W
= Write
R = Read
X = Don’t Care
GENERIC INTERFACE
Table 6. Generic Interface Format
7-Bit Device Address
R/W
S
(See Table 5)
SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA
Instruction Byte Data Byte
P
Slave Address Byte
Table 7. RDAC-to-EEPROM Interface Command Descriptions
C2
C1
C0
Command Description
Operation between I2C and RDAC
Operation between I2C and EEPROM
0
0
0
0
0
1
0
1
0
Operation between I 2C and Write Protection
Register. See Table 10.
1
1
1
0
0
1
0
1
0
NOP
Restore EEPROM to RDAC
Store RDAC to EEPROM
Rev. 0 | Page 16 of 24
AD5258
WRITE MODES
Table 8. Writing to RDAC Register
7-Bit Device Address
S
(See Table 5)
0
SA
SA
0
0
0
0
0
0
0
0
0
0
0
0
SA
SA
X
X
X
X
D5 D4 D3 D2 D1 D0 SA
P
P
Slave Address Byte
Instruction Byte
Data Byte
Table 9. Writing to EEPROM Register
7-Bit Device Address
S
(See Table 5)
0
1
0
0
0
D5 D4 D3 D2 D1 D0 SA
Data Byte
Slave Address Byte
Instruction Byte
The wiper’s default value, prior to programming the EEPROM, is midscale.
Table 10. Activating/Deactivating Software Write Protect
7-Bit Device Address
S
(See Table 5)
0
SA
0
1
0
0
0
0
0
0
SA
0
0
0
0
0
0
0
WP SA
P
Slave Address Byte
Instruction Byte
Data Byte
In order to activate the write protection mode, the WP bit in Table 10 must be logic high. In order to deactivate the write protection, the
command must be sent again except with the WP in logic zero state.
READ MODES
written to. For example, if the EEPROM was just written to,
Read modes are referred to as traditional because the first two
then the user can skip the two dummy bytes and proceed
bytes for all three cases are “dummy” bytes which function to
directly to the slave address byte followed by the EEPROM
readback data.
place the pointer towards the correct register. This is the reason
for the repeat start. In theory, this step can be avoided if the
user is interested in reading a register that was previously
Table 11. Traditional Readback of RDAC Register Value
7-Bit Device Address
(See Table 5)
7-Bit Device Address
(See Table 5)
S
0
SA
0
0
0
0
0
0
0
0
SA
S
1
SA
X
X
D5 D4 D3 D2 D1 D0 NA P
Read Back Data
Slave Address Byte
Instruction Byte
Slave Address Byte
↑
Repeat start
Table 12. Traditional Readback of Stored EEPROM Value
7-Bit Device Address
7-Bit Device Address
S
(See Table 5)
(See Table 5)
0
SA
0
0
1
0
0
0
0
0
SA
S
1
SA
X
X
D5 D4 D3 D2 D1 D0 NA P
Read Back Data
Slave Address Byte
Instruction Byte
Slave Address Byte
↑
Repeat start
STORE/RESTORE MODES
Table 13. Storing RDAC Value to EEPROM
7-Bit Device Address
S
(See Table 5)
0 SA 1 1 0 0 0 0 0 0 SA P
Instruction Byte
Slave Address Byte
Table 14. Restoring EEPROM to RDAC
7-Bit Device Address
S
(See Table 5)
0 SA 1 0 1 0 0 0 0 0 SA P
Instruction Byte
Slave Address Byte
Rev. 0 | Page 17 of 24
AD5258
TOLERANCE READBACK MODES
Table 15. Traditional Readback of Tolerance (Individually)
7-Bit Device Address
(See Table 5)
7-Bit Device Address
(See Table 5)
S
0 SA 0 0 1 1 1 1 1 0 SA S
Instruction Byte
1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Sign + Integer Byte
Slave Address Byte
Slave Address Byte
↑
Repeat start
7-Bit Device Address
(See Table 5)
7-Bit Device Address
(See Table 5)
S
0 SA 0 0 1 1 1 1 1 1 SA S
Instruction Byte
1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Decimal Byte
Slave Address Byte
Slave Address Byte
↑
Repeat start
Table 16.Traditional Readback of Tolerance (Consecutively)
7-Bit Device Address
(See Table 5)
7-Bit Device Address
S
0 SA 0 0 1 1 1 1 1 0 SA S
Instruction Byte
(See Table 5)
1 SA D7 D6 D5 D4 D3 D2 D1 D0 MA D7 D6 D5 D4 D3 D2 D1 D0 NA P
Slave Address Byte
Slave Address Byte
Sign + Integer Byte
Decimal Byte
↑
Repeat start
Calculating RAB Tolerance Stored in Read-Only Memory
A
A
A
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
–6
D1
–7
D0
–8
6
5
4
3
2
1
0
–1
2
–2
2
–3
2
–4
2
–5
2
SIGN
2
2
2
2
2
2
2
2
2
2
SIGN
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
Figure 40. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions.
(Unit is Percent. Only Data Bytes are Shown.)
the second EEPROM location (increments from 11110 to
11111) if read consecutively.
The AD5258 features a patented RAB tolerance storage in the
nonvolatile memory. The tolerance is stored in the memory
during factory production and can be read by users at any time.
The knowledge of stored tolerance allows users to accurately
calculate RAB. This feature is valuable for precision, rheostat
mode, and open-loop applications where knowledge of absolute
resistance is critical.
In the first memory location, the MSB is designated for the sign
(0 = + and 1= –) and the seven LSBs are designated for the integer
portion of the tolerance. In the second memory location, all eight
data bits are designated for the decimal portion of tolerance. Note
that the decimal portion has a limited accuracy of only 0.1%. For
example, if the rated RAB = 10 kΩ and the data readback from
Address 11110 shows 0001 1100, and Address 11111 shows
0000 1111, then the tolerance can be calculated as
The stored tolerance resides in the read-only memory and is
expressed as a percentage. The tolerance is stored in two memory
location bytes in sign magnitude binary form (see Figure 40).
The two EEPROM address bytes are 11110 (sign + integer) and
11111 (decimal number). The two bytes can be individually
accessed with two separate commands (see Table 15). Alternatively,
readback of the first byte followed by the second byte can be
done in one command (see Table 16). In the latter case, the
memory pointer will automatically increment from the first to
MSB: 0 = +
Next 7 MSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2–8 = 0.06
Tolerance = +28.06%
Rounded Tolerance = +28.1% and therefore,
RAB_ACTUAL = 12.810 kΩ
Rev. 0 | Page 18 of 24
AD5258
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic
capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 43). The digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
ESD PROTECTION OF DIGITAL PINS AND
RESISTOR TERMINALS
The AD5258 VDD, VLOGIC, and GND power supplies define the
boundary conditions for proper 3-terminal and digital input
operation. Supply signals present on Terminal A, Terminal B,
and Terminal W that exceed VDD or GND are clamped by the
internal forward biased ESD protection diodes (see Figure 41).
Digital Input SCL and Digital Input SDA are clamped by ESD
protection diodes with respect to VLOGIC and GND as shown in
Figure 42.
V
V
DD
DD
+
V
DD
C2
C1
10µF
0.1µF
AD5258
A
W
B
GND
GND
Figure 43. Power Supply Bypassing
Figure 41. Maximum Terminal Voltages Set by VDD and GND
MULTIPLE DEVICES ON ONE BUS
V
LOGIC
The AD5258 has two three-state configurable Address Pins
AD0 and AD1. The state of these two pins is registered upon
power-up and decoded into a corresponding I2C 7-bit address
(see Table 5). This allows up to nine devices on the bus to be
written to, or read from, independently. In the case that the pin
is assigned to be floated, the static voltage will be VLOGIC/2.
SCL
SDA
GND
Figure 42. Maximum Terminal Voltages Set by VLOGIC and GND
EVALUATION BOARD
An evaluation board, along with all necessary software, is
available to program the AD5258 from any PC running
Windows® 98/2000/XP. The graphical user interface, as shown
in Figure 44, is straightforward and easy to use. More detailed
information is available in the user manual that comes with the
board.
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 41), it is
important to power GND/VDD/VLOGIC before applying any
voltage to Terminal A, Terminal B, and Terminal Wꢀ otherwise,
the diode is forward biased such that VDD and VLOGIC are
powered unintentionally and may affect the user’s circuit. The
ideal power-up sequence is in the following order: GND, VDD
,
VLOGIC, digital inputs, and then VA, VB, VW. The relative order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after GND/VDD/VLOGIC
.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with minimum conductor length. Ground paths should
have low resistance and low inductance.
Figure 44. AD5258 Evaluation Board Software
Rev. 0 | Page 19 of 24
AD5258
DISPLAY APPLICATIONS
VDD will not affect that node’s bias because it is only on the
order of microamps. VLOGIC is tied to the MCU’s 3.3 V digital
supply because VLOGIC will draw the 35 mA which is needed
when writing to the EEPROM. It would be impractical to try
and source 35 mA through the 70 kΩ resistor, therefore, VLOGIC
CIRCUITRY
A special feature of the AD5258 is its unique separation of the
VLOGIC and VDD supply pins. The reason for doing this is to
provide greater flexibility in applications that do not always
provide needed supply voltages.
is not connected to the same node as VDD
.
In particular, LCD panels often require a VCOM voltage in the
range of 3 V to 5 V. The circuit in Figure 45 is the rare exception
in which a 5 V supply is available to power the digital
potentiometer.
For this reason, VLOGIC and VDD are provided as two separate
supply pins that can either be tied together or treated inde-
pendentlyꢀ VLOGIC supplying the logic/EEPROM with power,
and VDD biasing up the A, B, and W terminals for added
flexibility.
VCC (~3.3V)
14.4V
SUPPLIES POWER
TO BOTH THE
MICRO AND THE
LOGIC SUPPLY OF
THE DIGITAL POT
VCC (~3.3V)
5V
14.4V
R1
70kΩ
R1
70kΩ
C1
1µF
AD5258
C1
1µF
AD5258
R6
R5
–
V
V
R6
R5
DD
10kΩ 10kΩ
–
V
V
DD
10kΩ 10kΩ
U1
AD8565
LOGIC
U1
AD8565
R2
10kΩ
LOGIC
A
B
R2
10kΩ
A
B
3.5V < V
COM
< 4.5V
SCL
SDA
GND
+
3.5V < V
< 4.5V
COM
SCL
SDA
GND
MCU
W
+
MCU
W
R3
25kΩ
R3
25kΩ
Figure 46. Circuitry When a Separate Supply is Not Available for VDD
Figure 45. VCOM Adjustment Application
For a more detailed look at this application, refer to the article,
“Simple VCOM Adjustment uses any Logic Supply Voltage” in
the September 30, 2004, issue of EDN magazine.
In the more common case shown in Figure 46, only analog 14.4 V
and digital logic 3.3 V supplies are available. By placing discrete
resistors above and below the digital pot, VDD can now be tapped
off the resistor string itself. Based on the chosen resistor values,
the voltage at VDD in this case equals 4.8 V, allowing the wiper to
be safely operated all the way up to 4.8 V. The current draw of
Rev. 0 | Page 20 of 24
AD5258
OUTLINE DIMENSIONS
3.00 BSC
10
6
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 47. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
RAB (Ω)
Temperature
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
AD5258BRMZ11
AD5258BRMZ1-R71
AD5258BRMZ101
AD5258BRMZ10-R71
AD5258BRMZ501
AD5258BRMZ50-R71
AD5258BRMZ1001
AD5258BRMZ100-R71
AD5258EVAL2
1 k
1 k
D4K
D4K
D4L
D4L
D4M
D4M
D4N
D4N
10 k
10 k
50 k
50 k
100 k
100 k
Evaluation Board
1 Z = Pb-free part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. 0 | Page 21 of 24
AD5258
NOTES
Rev. 0 | Page 22 of 24
AD5258
NOTES
Rev. 0 | Page 23 of 24
AD5258
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05029–0–3/05(0)
Rev. 0 | Page 24 of 24
相关型号：
AD5258BRMZ100-RL7
IC 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO10, LEAD FREE, MO-187-BA, MSOP-10, Digital Potentiometer
ADI
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