AD5292SRU-20-EP [ADI]
Single Channel, 1024-Position, 1% R-Tol, Digital Potentiometer with 20-Times Programmable Memory;
| 型号： | AD5292SRU-20-EP |
| 厂家： | 
ADI |
| 描述： | Single Channel, 1024-Position, 1% R-Tol, Digital Potentiometer with 20-Times Programmable Memory 光电二极管 转换器 电阻器 |
| 文件： | 总30页 (文件大小：897K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256-/1024-Position, Digital Potentiometers with
Maximum 1ꢀ ꢁ-ꢂoleranꢃe ꢄrror anꢅ 20-ꢂP Memorꢆ
Data Sheet
AD5291/AD5292
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
RESET
DD
Single-channel, 256-/1024-position resolution
20 kΩ, 50 kΩ, and 100 kΩ nominal resistance
Maximum 1ꢀ nominal resistor tolerance error (resistor
performance mode)
20-times programmable wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C
Voltage divider temperature coefficient: 5 ppm/°C
+9 V to +33 V single-supply operation
9 V to 16.5 V dual-supply operation
SPI-compatible serial interface
POWER-ON
RESET
AD5291/
AD5292
V
LOGIC
RDAC
REGISTER
SCLK
SYNC
A
DATA
SERIAL
INTERFACE
W
OTP
MEMORY
BLOCK
DIN
B
Wiper setting readback
SDO
Power-on refreshed from 20-TP memory
RDY
APPLICATIONS
V
EXT_CAP
GND
SS
Mechanical potentiometer replacement
Instrumentation: gain and offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, and time constants
Programmable power supply
Figure 1.
Low resolution DAC replacement
Sensor calibration
GENERAL DESCRIPTION
The AD5291 and AD5292 are single-channel, 256-/1024-
position digital potentiometers1 that combine industry leading
variable resistor performance with nonvolatile memory (NVM)
in a compact package. These devices are capable of operating
across a wide voltage range, supporting both dual supply operation
at 10.5 V to 16.5 V and single supply operation at +21 V to
+33 V, while ensuring less than 1% end-to-end resistor tolerance
error and offering 20-time programmable (20-TP) memory.
The AD5291 and AD5292 device wiper settings are controllable
through the SPI digital interface. Unlimited adjustments are
allowed before programming the resistance value into the
20-TP memory. The AD5291 and AD5292 do not require any
external voltage supply to facilitate fuse blow, and there are 20
opportunities for permanent programming. During 20-TP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
The guaranteed industry leading low resistor tolerance error
feature simplifies open-loop applications as well as precision
calibration and tolerance matching applications.
The AD5291 and AD5292 are available in a compact 14-lead
TSSOP package. The part is guaranteed to operate over the
extended industrial temperature range of −40°C to +105°C.
1 The terms digital potentiometer and RDAC are used interchangeably.
Rev. F
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5291/AD5292
Data Sheet
ꢂABLꢄ OF CONꢂꢄNꢂS
Features .............................................................................................. 1
20-TP Memory ........................................................................... 23
Write Protection ......................................................................... 23
Basic Operation .......................................................................... 24
20-TP Readback and Spare Memory Status ........................... 24
Shutdown Mode ......................................................................... 24
Resistor Performance Mode...................................................... 25
Reset............................................................................................. 25
SDO Pin and Daisy-Chain Operation..................................... 25
RDAC Architecture.................................................................... 25
Programming the Variable Resistor......................................... 26
Programming the Potentiometer Divider............................... 26
EXT_CAP Capacitor.................................................................. 27
Terminal Voltage Operating Range ......................................... 27
Applications Information.............................................................. 28
High Voltage DAC...................................................................... 28
Programmable Voltage Source with Boosted Output ........... 28
High Accuracy DAC .................................................................. 28
Variable Gain Instrumentation Amplifier .............................. 28
Audio Volume Control .............................................................. 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—AD5291 .......................................... 3
Resistor Performance Mode Code Range ................................. 4
Electrical Characteristics—AD5292 .......................................... 6
Resistor Performance Mode Code Range ................................. 7
Interface Timing Specifications.................................................. 8
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 12
Test Circuits..................................................................................... 21
Theory of Operation ...................................................................... 22
Serial Data Interface................................................................... 22
Shift Register ............................................................................... 22
RDAC Register............................................................................ 22
REVISION HISTORY
11/2019—Rev. E to Rev. F
12/2009—Rev. 0 to Rev. A
Change to Ordering Guide............................................................ 30
Added 50 kΩ and 100 kΩ specifications.........................Universal
Changes to Features Section ............................................................1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Added Table 3 ....................................................................................5
Changes to Table 4.............................................................................6
Changes to Table 5.............................................................................7
Added Table 6 ....................................................................................8
Change to Table 7 ..............................................................................8
Changes to Absolute Maximum Rating Section ........................ 10
Changes Table 9 .............................................................................. 11
Changes to Typical Performance Characteristics Section ........ 12
Changes to Ordering Guide.......................................................... 30
12/2014—Rev. D to Rev. E
Changes to Shift Register Section and Table 11 ......................... 22
9/2010—Rev. C to Rev. D
Changes to SDO Pin and Daisy-Chain Operation Section....... 25
3/2010—Rev. B to Rev. C
Changes to Revision History........................................................... 2
Changes to Figure 3 and Figure 4 Captions .................................. 9
3/2010—Rev. A to Rev. B
Changes to Data Sheet Title ............................................................ 1
Changes to General Description Section ...................................... 1
Changes to Theory of Operation Section.................................... 22
4/2009—Revision 0: Initial Version
Rev. F | Page 2 of 30
Data Sheet
AD5291/AD5292
SPꢄCIFICAꢂIONS
ELECTRICAL CHARACTERISTICS—AD5291
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS,
−40°C < TA < +105°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
N
8
Bits
LSB
LSB
%
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance (R-Perf Mode)3
Nominal Resistor Tolerance (Normal Mode)
Resistance Temperature Coefficient4
Wiper Resistance
R-DNL
RWB, VA = NC
−1
−1
−1
+1
+1
+1
R-INL
∆RAB/RAB
∆RAB/RAB
(∆RAB/RAB)/∆T × 106
RW
See Table 2, Table 3
±0.ꢀ
±±
%
Code = full-scale; See Figure 38
Code= zero scale
3ꢀ
ppm/°C
Ω
60
100
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Resolution
N
8
Bits
Differential Nonlinearityꢀ
Integral Nonlinearityꢀ
Voltage Divider Temperature Coefficient4
Full-Scale Error
DNL
−0.ꢀ
−0.ꢀ
+0.ꢀ
+0.ꢀ
LSB
INL
LSB
(∆VW/VW)/∆T × 106
Code = half-scale; See Figure 41
Code = full scale
1.ꢀ
ppm/°C
LSB
VWFSE
VWZSE
−2
0
+0.2ꢀ
2
Zero-Scale Error
Code = zero scale
LSB
RESISTOR TERMINALS
Terminal Voltage Range6
Capacitance A, Capacitance B4
VA, VB, VW
CA, CB
VSS
VDD
V
f = 1 MHz, measured to GND,
code = half-scale
8ꢀ
6ꢀ
±1
pF
Capacitance W4
CW
ICM
f = 1 MHz, measured to GND,
code = half-scale
pF
Common-Mode Leakage Current4
DIGITAL INPUTS
Input Logic High4
VA = VB = VW
nA
JEDEC compliant
VLOGIC = 2.± V to ꢀ.ꢀ V
VLOGIC = 2.± V to ꢀ.ꢀ V
VIN = 0 V or VLOGIC
VIH
VIL
IIL
2.0
V
Input Logic Low4
0.8
±1
V
Input Current
Input Capacitance4
μA
pF
CIL
ꢀ
ꢀ
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage4
Output Low Voltage4
Three-State Leakage Current
Output Capacitance4
POWER SUPPLIES
VOH
VOL
RPULL_UP = 2.2 kΩ to VLOGIC
RPULL_UP = 2.2 kΩ to VLOGIC
VLOGIC − 0.4
−1
V
GND + 0.4 V
+1
V
μA
pF
COL
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Logic Supply Range
VDD
VSS = 0 V
9
33
V
VDD/VSS
IDD
±9
±16.ꢀ
2
V
VDD/VSS = ±16.ꢀ V
VDD/VSS = ±16.ꢀ V
0.1
μA
μA
V
ISS
−2
−0.1
VLOGIC
ILOGIC
2.±
ꢀ.ꢀ
10
Logic Supply Current
OTP Store Current4, ±
OTP Read Current4, 8
VLOGIC = ꢀ V; VIH = ꢀ V or VIL = GND
VIH = ꢀ V or VIL = GND
VIH = ꢀ V or VIL = GND
VIH = ꢀ V or VIL = GND
∆VDD/∆VSS = ±1ꢀ V ± 10%
RAB = 20 kΩ
1
μA
mA
mA
μW
%/%
ILOGIC_PROG
ILOGIC_FUSE_READ
PDISS
2ꢀ
2ꢀ
8
Power Dissipation9
110
Power Supply Rejection Ratio
PSRR
0.103
0.039
0.021
RAB = ꢀ0 kΩ
RAB = 100 kΩ
Rev. F | Page 3 of 30
AD5291/AD5292
Data Sheet
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICSꢀ, 10
Bandwidth
BW
−3 dB, code = half-scale
RAB = 20 kΩ
kHz
ꢀ20
210
10ꢀ
RAB = ꢀ0 kΩ
RAB = 100 kΩ
Total Harmonic Distortion
VW Settling Time
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
RAB = 20 kΩ
dB
−93
RAB = ꢀ0 kΩ
−101
−106
RAB = 100 kΩ
tS
VA = 30 V, VB = 0 V, ±0.ꢀ LSB error
band, initial code = zero scale,
board capacitance = 1±0 pF
Code = full-scale, normal mode
Code = full-scale, R-Perf mode
Code = half-scale, normal mode
RAB = 20 kΩ
±ꢀ0
2.ꢀ
ns
μs
μs
2.ꢀ
±
RAB = ꢀ0 kΩ
RAB = 100 kΩ
14
Code = half-scale, R-Perf mode
RAB = 20 kΩ
μs
ꢀ
RAB = ꢀ0 kΩ
9
RAB = 100 kΩ
16
Resistor Noise Density
eN_WB
Code = half-scale, TA = 2ꢀ°C, 0 kHz
to 200 kHz
nV/√Hz
RAB = 20 kΩ
RAB = ꢀ0 kΩ
RAB = 100 kΩ
10
18
2±
1 Typical values represent average readings at 2ꢀ°C, VDD = 1ꢀ V, VSS = −1ꢀ V, and VLOGIC = ꢀ V.
2 Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x02 to code 0xFF or between RWA at code 0xFD to
code 0x00. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with
a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3 Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.
4 Guaranteed by design and characterization, not subject to production test.
ꢀ INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
± Different from operating current; supply current for fuse program lasts approximately ꢀꢀ0 μs.
8 Different from operating current; supply current for fuse read lasts approximately ꢀꢀ0 μs.
9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10 All dynamic characteristics use VDD = 1ꢀ V, VSS = −1ꢀ V, and VLOGIC = ꢀ V.
RESISTOR PERFORMANCE MODE CODE RANGE
Table 2.
RAB = 20 kΩ
|VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V
Resistor
Tolerance per
Code
|VDD − VSS| = 30 V to 33 V
|VDD − VSS| = 21 V to 22 V
RWB
RWA
RWB
RWA
RWB
RWA
RWB
RWA
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
From 0xꢀA
to 0xFF
From 0x23
to 0xFF
From 0x1E
to 0xFF
From 0x00
to 0xAꢀ
From 0x00
to 0xDC
From 0x00
to 0xE1
From 0x±D
to 0xFF
From 0x2D
to 0xFF
From 0x19
to 0xFF
From 0x00
to 0x82
From 0x00
to 0xD2
From 0x00
to 0xE6
From 0x±D
to 0xFF
From 0x23
to 0xFF
From 0x1±
to 0xFF
From 0x00
to 0x82
From 0x00
to 0xDC
From 0x00
to 0xE8
N/A
N/A
From 0x23
to 0xFF
From 0x1±
to 0xFF
From 0x00
to 0xDC
From 0x00
to 0xE8
Rev. F | Page 4 of 30
Data Sheet
AD5291/AD5292
Table 3.
RAB = 50 kΩ
|VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V
RAB = 100 kΩ
|VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V
Resistor Tolerance
per Code
RWB
RWA
RWB
RWA
RWB
RWA
RWB
RWA
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
From 0x2A
to 0xFF
From 0x11
to 0xFF
From 0x0A
to 0xFF
From 0x00
to 0xDꢀ
From 0x00
to 0xEE
From 0x00
to 0xFꢀ
From 0x3±
to 0xFF
From 0x16
to 0xFF
From 0x0D
to 0xFF
From 0x00
to 0xC8
From 0x00
to 0xE9
From 0x00
to 0xF2
From 0x1E
to 0xFF
From 0x0A
to 0xFF
From 0x0±
to 0xFF
From 0x00
to 0xE1
From 0x00
to 0xFꢀ
From 0x00
to 0xF8
From 0x14
to 0xFF
From 0x0A
to 0xFF
From 0x0±
to 0xFF
From 0x00
to 0xEB
From 0x00
to 0xFꢀ
From 0x00
to 0xF8
Rev. F | Page ꢀ of 30
AD5291/AD5292
Data Sheet
ELECTRICAL CHARACTERISTICS—AD5291
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS,
−40°C < TA < +105°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
N
10
−1
−2
−2
−3
−1
Bits
LSB
LSB
LSB
LSB
%
R-DNL
R-INL
R-INL
R-INL
∆RAB/RAB
∆RAB/RAB
RWB, VA = NC
+1
+2
+2
+3
+1
RAB =ꢀ0 kΩ, 100 kΩ
RAB =20 kΩ , |VDD − VSS| = 26 V to 33 V
RAB =20 kΩ , |VDD − VSS| = 21 V to 26 V
See Table ꢀ and Table 6
Nominal Resistor Tolerance (R-Perf Mode)3
±0.ꢀ
±±
Nominal Resistor Tolerance (Normal
Mode)4
%
Resistance Temperature Coefficient
Wiper Resistance
(∆RAB/RAB)/∆T × 106
RW
Code = full scale; See Figure 38
Code= zero scale
3ꢀ
60
ppm/°C
Ω
100
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Resolution
N
10
Bits
Differential Nonlinearityꢀ
Integral Nonlinearityꢀ
Voltage Divider Temperature Coefficient4
Full-Scale Error
DNL
−1
+1
LSB
INL
−1.ꢀ
+1.ꢀ
LSB
(∆VW/VW)/∆T × 106
Code = half scale; See Figure 41
Code = full scale
ꢀ
ppm/°C
LSB
VWFSE
VWZSE
−8
0
+1
8
Zero-Scale Error
Code = zero scale
LSB
RESISTOR TERMINALS
Terminal Voltage Range4
Capacitance A, Capacitance B6
VA, VB, VW
CA, CB
VSS
VDD
V
f = 1 MHz, measured to GND,
code = half scale
8ꢀ
6ꢀ
±1
pF
Capacitance Wꢀ
CW
ICM
f = 1 MHz, measured to GND,
code = half scale
pF
Common-Mode Leakage Current4
DIGITAL INPUTS
Input Logic High4
VA = VB = VW
nA
JEDEC compliant
VLOGIC = 2.± V to ꢀ.ꢀ V
VLOGIC = 2.± V to ꢀ.ꢀ V
VIN = 0 V or VLOGIC
VIH
VIL
IIL
2.0
V
Input Logic Low4
0.8
±1
V
Input Current
Input Capacitance4
μA
pF
CIL
ꢀ
ꢀ
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage4
Output Low Voltage4
Three-State Leakage Current
Output Capacitance4
POWER SUPPLIES
VOH
VOL
RPULL_UP = 2.2 kΩ to VLOGIC
RPULL_UP = 2.2 kΩ to VLOGIC
VLOGIC − 0.4
−1
V
GND + 0.4
+1
V
μA
pF
COL
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Logic Supply Range
VDD
VSS = 0 V
9
33
V
VDD/VSS
IDD
±9
±16.ꢀ
2
V
VDD/VSS = ±16.ꢀ V
VDD/VSS = ±16.ꢀ V
0.1
μA
μA
V
ISS
−2
−0.1
VLOGIC
ILOGIC
2.±
ꢀ.ꢀ
10
Logic Supply Current
OTP Store Current6, ±
OTP Read Current6, 8
Power Dissipation9
Power Supply Rejection Ratio6
VLOGIC = ꢀ V; VIH = ꢀ V or VIL = GND
VIH = ꢀ V or VIL = GND
VIH = ꢀ V or VIL = GND
VIH = ꢀ V or VIL = GND
∆VDD/∆VSS = ±1ꢀ V ± 10%
RAB = 20 kΩ
1
μA
mA
mA
μW
%/%
ILOGIC_PROG
ILOGIC_FUSE_READ
PDISS
2ꢀ
2ꢀ
8
110
PSSR
0.103
0.039
0.021
RAB = ꢀ0 kΩ
RAB = 100 kΩ
Rev. F | Page 6 of 30
Data Sheet
AD5291/AD5292
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DYNAMIC CHARACTERISTICSꢀ, 10
Bandwidth
BW
−3 dB
kHz
RAB = 20 kΩ
RAB = ꢀ0 kΩ
RAB = 100 kΩ
ꢀ20
210
10ꢀ
Total Harmonic Distortion
VW Settling Time
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
RAB = 20 kΩ
dB
−93
RAB = ꢀ0 kΩ
−101
−106
RAB = 100 kΩ
tS
VA = 30 V, VB = 0 V, ±0.ꢀ LSB error
band, initial code = zero scale, board
capacitance = 1±0 pF
Code = full-scale, normal mode
Code = full-scale, R-Perf mode
Code = half-scale, normal mode
RAB = 20 kΩ
±ꢀ0
2.ꢀ
ns
μs
μs
2.ꢀ
±
RAB = ꢀ0 kΩ
RAB = 100 kΩ
14
Code = half-scale, R-Perf mode
RAB = 20 kΩ
μs
ꢀ
RAB = ꢀ0 kΩ
9
RAB = 100 kΩ
16
Resistor Noise Density
eN_WB
Code = half-scale, TA = 2ꢀ°C, 0 kHz to
200 kHz
nV/√Hz
RAB = 20 kΩ
RAB = ꢀ0 kΩ
RAB = 100 kΩ
10
18
2±
1 Typical values represent average readings at 2ꢀ°C, VDD = 1ꢀ V, VSS = −1ꢀ V, and VLOGIC = ꢀ V.
2 Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x00B to code 0x3FF or between RWA at code 0x3F3 to
code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with
a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3 Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.
4 Guaranteed by design and characterization, not subject to production test.
ꢀ INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
± Different from operating current; supply current for fuse program lasts approximately ꢀꢀ0 μs.
8 Different from operating current; supply current for fuse read lasts approximately ꢀꢀ0 μs.
9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10 All dynamic characteristics use VDD = 1ꢀ V, VSS = −1ꢀ V, and VLOGIC = ꢀ V.
RESISTOR PERFORMANCE MODE CODE RANGE
Table 5.
RAB = 20 kΩ
|VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V
RWB RWA RWB RWA
From 0x1F4 From 0x000 From 0x1F4 From 0x000 N/A
Resistor
Tolerance per
Code
|VDD − VSS| = 30 V to 33 V
|VDD − VSS| = 21 V to 22 V
RWB
RWA
RWB
RWA
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
From 0x1ꢀE From 0x000
N/A
to 0x3FF
to 0x2A1
to 0x3FF
From 0xB4
to 0x3FF
From 0x64
to 0x3FF
to 0x20B
From 0x000 From 0xFA
to 0x34B to 0x3FF
From 0x000 From 0x±8
to 0x39B to 0x3FF
to 0x3FF
to 0x20B
From 0x000 From 0xFA
to 0x30ꢀ
From 0x000 From 0x±8
to 0x38± to 0x3FF
From 0x8C
to 0x3FF
From 0x000
to 0x3±3
From 0x000
to 0x30ꢀ
From 0x000
to 0x38±
to 0x3FF
From 0xꢀA
to 0x3FF
From 0x000
to 0x3Aꢀ
Rev. F | Page ± of 30
AD5291/AD5292
Data Sheet
Table 6.
R
AB = 50 kΩ
|VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V
RWB RWA RWB RWA
From 0x08C From 0x000 From 0x0B4 From 0x000
to 0x3FF to 0x3ꢀF to 0x3FF to 0x31E
From 0X03C From 0x000 From 0x0ꢀ0 From 0x000
to 0x3FF to 0x3C3 to 0x3FF to 0x3AF
From 0X028 From 0x000 From 0x032 From 0x000
to 0x3FF to 0x3D± to 0x3FF to 0x3CD
RAB = 100 kΩ
|VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V
RWB RWA RWB RWA
From 0x04B From 0x000 From 0x064 From 0x000
to 0x3FF to 0x3B4 to 0x3FF to 0x39B
From 0x028 From 0x000 From 0x028 From 0x000
to 0x3FF to 0x3D± to 0x3FF to 0x3D±
From 0x019 From 0x000 From 0x019 From 0x000
to 0x3FF to 0x3E6 to 0x3FF to 0x3E6
Resistor
Tolerance per
Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
INTERFACE TIMING SPECIFICATIONS
VDD/VSS
= 15 V, VLOGIC = 2.7 V to 5.5 V, −40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter
Limit1
20
10
10
10
ꢀ
ꢀ
1
4003
14
1
Unit
Description
2
t1
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
t2
t3
t4
tꢀ
t6
t±
t8
t9
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
RDY rising edge to SYNC falling edge
SYNC rising edge to RDY fall time
4
t10
4
t11
40
4
t12
2.4
410
8
μs max
ns max
ms max
ms min
ns max
ms max
ns max
ns min
ms max
RDY low time, RDAC register write command execute time (R-Perf mode)
RDY low time, RDAC register write command execute time (normal mode)
RDY low time, memory program execute time
Software/hardware reset
4
t12
4
t12
4
t12
1.ꢀ
4ꢀ0
1.3
4ꢀ0
20
4
t13
RDY low time, RDAC register readback execute time
RDY low time, memory readback execute time
SCLK rising edge to SDO valid
4
t13
4
t14
tRESET
Minimum RESET pulse width (asynchronous)
Power-on OTP restore time
ꢀ
tPOWER-UP
2
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is ꢀ0 MHz.
3 Refer to t12 and t13 for RDAC register and memory commands operations.
4 RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF.
ꢀ Maximum time after VLOGIC is equal to 2.ꢀ V.
DB9 (MSB)
DB0 (LSB)
C3
C1
C0
D9
D7
D6
D5
D4
D3
D0
0
0
C2
D8
D2
D1
DATA BITS
CONTROL BITS
Figure 2. Shift Register Content
Rev. F | Page 8 of 30
Data Sheet
Timing Diagrams
t4
AD5291/AD5292
t7
t2
t1
SCLK
t9
t3
t8
SYNC
t5
t6
D7
DIN
D6
D2
X
X
C3
C2
D1
D0
SDO
t11
t10
t12
RDY
tRESET
RESET
Figure 3. Write Timing Diagram, CPOL = 0, CPHA = 1
SCLK
SYNC
t9
DIN
X
X
X
C3
D0
X
D0
C3
D1
D0
t14
C3
SDO
RDY
X
X
D1
D0
t11
t13
Figure 4. Read Timing Diagram, CPOL = 0, CPHA = 1
Rev. F | Page 9 of 30
AD5291/AD5292
Data Sheet
ABSOLUꢂꢄ MAXIMUM ꢁAꢂINGS
TA = 25°C, unless otherwise noted.
Table 8.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
VDD to GND
VSS to GND
VLOGIC to GND
VDD to VSS
−0.3 V to +3ꢀ V
+0.3 V to − 2ꢀ V
−0.3 V to + ± V
3ꢀ V
VSS − 0.3 V, VDD+ 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to +± V
VA, VB, VW to GND
Digital Input and Output Voltage to GND
EXT_CAP Voltage to GND
IA, IB, IW
THERMAL RESISTANCE
θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.
Continuous
RAB = 20 kΩ
RAB = ꢀ0 kΩ, 100 kΩ
Pulsed1
Frequency > 10 kHz
Frequency ≤ 10 kHz
Operating Temperature Range4
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Reflow Soldering
±3 mA
±2mA
Table 9. Thermal Resistance
Package Type
θJA
931
θJC
Unit
14-Lead TSSOP
20
°C/W
MCC2/d3
MCC2/√d3
−40°C to +10ꢀ°C
1ꢀ0°C
−6ꢀ°C to +1ꢀ0°C
1 JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec airflow).
ESD CAUTION
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given resistance.
2 Maximum continuous current.
3 Pulse duty factor.
4 Includes programming of OTP memory.
Rev. F | Page 10 of 30
Data Sheet
AD5291/AD5292
PIN CONFIGUꢁAꢂION AND FUNCꢂION DꢄSCꢁIPꢂIONS
RESET
1
2
3
4
5
6
7
14 RDY
V
13
SDO
SS
AD5291/
AD5292
A
W
B
12
SYNC
11 SCLK
10 DIN
TOP VIEW
Not to Scale
V
9
8
GND
DD
EXT_CAP
V
LOGIC
Figure 5. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Description
1
RESET
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory
default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the
logic high transition. Tie RESET to VLOGIC if not used.
2
VSS
Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF
ceramic capacitors and 10 μF capacitors.
3
4
ꢀ
6
±
8
A
W
B
VDD
EXT_CAP
VLOGIC
Terminal A of RDAC. VSS ≤ VA ≤ VDD
Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD
Terminal B of RDAC. VSS ≤ VB ≤ VDD
Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥± V.
.
.
.
Logic Power Supply; 2.± V to ꢀ.ꢀ V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
9
10
GND
DIN
Ground Pin, Logic Ground Reference.
Serial Data Input. The ADꢀ291 and ADꢀ292 have a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
11
12
SCLK
SYNC
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be
transferred at rates up to ꢀ0 MHz.
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The
selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high
before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by
the DAC.
13
14
SDO
RDY
Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data
from the shift register in daisy-chain mode or in readback mode.
Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from
the RDAC register or memory.
Rev. F | Page 11 of 30
AD5291/AD5292
Data Sheet
ꢂYPICAL PꢄꢁFOꢁMANCꢄ CHAꢁACꢂꢄꢁISꢂICS
1.0
1.0
0.8
–40°C
20kꢀ
50kꢀ
100kꢀ
TEMPERATURE = 25°C
+25°C
0.8
+105°C
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
R
= 20kΩ
AB
0
128
256
384
512
640
768
896
1023
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
CODE (Decimal)
Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5292)
Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
0.6
0.6
TEMPERATURE = 25°C
R
= 20kΩ
AB
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.1
–0.2
–0.3
20kꢀ
–0.2
50kꢀ
100kꢀ
+105°C
768
+25°C
512
CODE (Decimal)
–40°C
–0.3
0
128
256
384
512
640
768
896
1023
0
128
256 384
640
896
1023
CODE (Decimal)
Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)
1.0
1.0
20kꢀ
50kꢀ
100kꢀ
TEMPERATURE = 25°C
R
= 20kΩ
AB
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
+105°C
768
+25°C
512
CODE (Decimal)
–40°C
0
128
256 384
640
896
1023
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
Figure 8. R-INL in Normal Mode vs. Code vs. Temperature (AD5292)
Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
Rev. F | Page 12 of 30
Data Sheet
AD5291/AD5292
0.15
0.15
0.10
0.05
0
20kꢀ
50kꢀ
100kꢀ
TEMPERATURE = 25°C
R
= 20kꢀ
AB
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
+105°C
768
+25°C
512
CODE (Decimal)
–40°C
0
128
256 384
640
896
1023
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5292)
Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
0.8
1.5
TEMPERATURE = 25°C
R
= 20kꢀ
AB
0.6
0.2
0
1.0
0.5
0
–0.2
–0.5
–1.0
–1.5
–0.6
20kꢀ
50kꢀ
100kꢀ
+105°C
768
+25°C
512
CODE (Decimal)
–40°C
–0.8
0
128
256
384
512
640
768
896
1023
0
128
256 384
640
896
1023
CODE (Decimal)
Figure 16. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
Figure 13. INL in R-Perf Mode vs. Code vs. Temperature (AD5292)
0.6
0.6
TEMPERATURE = 25°C
R
= 20kꢀ
AB
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
–0.1
20kꢀ
–0.1
–0.2
–0.2
50kꢀ
100kꢀ
+105°C
768
+25°C
512
CODE (Decimal)
–40°C
–0.3
0
128
256
384
512
640
768
896
1023
0
128
256 384
640
896
1023
CODE (Decimal)
Figure 17. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
Figure 14. DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)
Rev. F | Page 13 of 30
AD5291/AD5292
Data Sheet
0.8
0.8
0.6
–40°C
+25°C
+105°C
20kꢀ
50kꢀ
100kꢀ
TEMPERATURE = 25°C
R
= 20kꢀ
AB
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
0
128
256
384
512
640
768
896
1023
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
CODE (Decimal)
Figure 18. INL in Normal Mode vs. Code vs. Temperature (AD5292)
Figure 21. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
0.10
0.08
–40°C
20kꢀ
50kꢀ
100kꢀ
+25°C
+105°C
0.05
0
0.04
0
–0.05
–0.10
–0.15
–0.20
–0.04
–0.08
–0.12
TEMPERATURE = 25°C
–0.16
R
= 20kꢀ
AB
0
128
256
384
512
640
768
896
1023
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
CODE (Decimal)
Figure 19. DNL in Normal Mode vs. Code vs. Temperature (AD5292)
Figure 22. DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
0.30
0.30
TEMPERATURE = 25°C
20kꢀ
+105°C
+25°C
–40°C
50kꢀ
0.25
0.25
0.20
0.15
0.10
0.05
0
100kꢀ
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
R
= 20kꢀ
AB
0
32
64
96
128
160
192
224
255
0
32
64
96
128
160
192
224
255
CODE (Decimal)
CODE (Decimal)
Figure 23. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
Figure 20. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5291)
Rev. F | Page 14 of 30
Data Sheet
AD5291/AD5292
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
0.14
TEMPERATURE = 25°C
R
= 20kꢀ
AB
0.12
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.02
–0.04
–0.06
20kꢀ
50kꢀ
100kꢀ
+105°C
192
+25°C
128
CODE (Decimal)
–40°C
64
0
32
64
96
128
160
192
224
255
0
32
96
160
224
255
CODE (Decimal)
Figure 27. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
Figure 24. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.25
0.25
20kꢀ
50kꢀ
100kꢀ
TEMPERATURE = 25°C
+105°C
+25°C
–40°C
0.20
0.15
0.10
0.05
0
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.05
–0.10
R
= 20kꢀ
AB
0
32
64
96
128
160
192
224
255
0
32
64
96
128
160
192
224
255
CODE (Decimal)
CODE (Decimal)
Figure 28. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
Figure 25. R-INL in Normal Mode vs. Code vs. Temperature (AD5291)
0.03
0.03
20kꢀ
50kꢀ
100kꢀ
TEMPERATURE = 25°C
+105°C
+25°C
–40°C
0.02
0.01
0.02
0.01
0
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.01
–0.02
–0.03
–0.04
–0.05
R
= 20kꢀ
AB
0
32
64
96
128
160
192
224
255
0
32
64
96
128
160
192
224
255
CODE (Decimal)
CODE (Decimal)
Figure 29. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
Figure 26. R-DNL in Normal Mode vs. Code vs. Temperature (AD5291)
Rev. F | Page 1ꢀ of 30
AD5291/AD5292
Data Sheet
0.25
0.20
0.15
0.10
0.05
0
0.25
TEMPERATURE = 25°C
+105°C
+25°C
–40°C
0.20
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.05
–0.10
–0.15
–0.20
20kꢀ
50kꢀ
100kꢀ
R
= 20kꢀ
AB
–0.25
0
32
64
96
128
160
192
224
255
0
32
64
96
128
160
192
224
255
CODE (Decimal)
CODE (Decimal)
Figure 30. INL in R-Perf Mode vs. Code vs. Temperature (AD5291)
Figure 33. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
0.14
0.14
+105°C
TEMPERATURE = 25°C
+25°C
–40°C
0.12
0.10
0.08
0.06
0.04
0.02
0
0.12
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.02
–0.04
–0.06
20kꢀ
–0.04
50kꢀ
R
= 20kꢀ
100kꢀ
AB
–0.06
0
32
64
96
128
160
192
224
255
0
32
64
96
128
160
192
224
255
CODE (Decimal)
CODE (Decimal)
Figure 31. DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)
Figure 34. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
0.20
0.20
+105°C
+25°C
–40°C
20kꢀ
50kꢀ
100kꢀ
TEMPERATURE = 25°C
0.15
0.10
0.05
0
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
0
32
64
96
128
160
192
224
256
0
32
64
96
128
160
192
224
255
CODE (Decimal)
CODE (Decimal)
Figure 32. INL in Normal Mode vs. Code vs. Temperature (AD5291)
Figure 35. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
Rev. F | Page 16 of 30
Data Sheet
AD5291/AD5292
0.03
0.03
0.02
+105°C
+25°C
–40°C
TEMPERATURE = 25°C
0.02
0.01
0.01
0
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.01
–0.02
–0.03
–0.04
–0.05
20kꢀ
50kꢀ
100kꢀ
R
AB
= 20kꢀ
0
32
64
96
128
160
192
224
255
0
32
64
96
128
160
192
224
255
CODE (Decimal)
CODE (Decimal)
Figure 39. DNL in Normal Mode vs. Code vs. Temperature (AD5291)
Figure 36. DNL in Normal Mode vs. Code vs. Temperature (AD5291)
0.20
450
V
V
/V = ±15V
DD SS
V
= ±15V
DD
= +5V
0.18
0.16
0.14
0.12
0.1
LOGIC
400
350
300
250
200
150
100
50
I
LOGIC
0.08
0.06
0.04
0.02
0
I
DD
0
I
SS
–50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
DIGITAL INPUT VOLTAGE (V)
Figure 40. Supply Current ILOGIC vs. Digital Input Voltage
Figure 37. Supply Current (IDD, ISS, ILOGIC) vs. Temperature
700
700
600
500
400
300
200
100
0
V
V
= 30V
V
V
= 30V,
DD
= 0V
DD
= 0V
SS
SS
600
500
400
300
200
100
0
20kꢀ
20kꢀ
50kꢀ
100kꢀ
50kꢀ
100kꢀ
0
0
256
64
512
128
768
192
1023 AD5292
255 AD5291
0
0
256
64
512
128
768
192
1023 AD5292
255 AD5291
CODE (Decimal)
CODE (Decimal)
Figure 41. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code
Figure 38. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
Rev. F | Page 1± of 30
AD5291/AD5292
Data Sheet
0
–5
0
AD5292 (AD5291)
AD5292 (AD5291)
0x200 (0x80)
0x100 (0x40)
0x200 (0x80)
–5
–10
–10
–15
–20
–25
–30
–35
–40
–45
–50
0x100 (0x40)
–15
–20
0x080 (0x20)
0x040 (0x10)
0x020 ( 0x08)
0x080 (0x20)
0x040 (0x10)
–25
–30
–35
–40
–45
–50
–55
0x010 (0x04)
0x008 (0x02)
0x020 ( 0x08)
0x010 (0x04)
0x008 (0x02)
0x004 (0x01)
0x002
0x001
0x004 (0x01)
–60
0x002
0x001
–65
–67.5
10
100
1k
10k
100k
1M
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 42. 20 kΩ Gain vs. Frequency vs. Code
Figure 45. 100 kΩ Gain vs. Frequency vs. Code
0
0
–10
–20
–30
–40
–50
–60
–70
100kꢀ
20kꢀ
50kꢀ
AD5292 (AD5291)
0x200 (0x80)
–10
–20
–30
–40
–50
–60
0x100 (0x40)
0x080 (0x20)
0x040 (0x10)
0x020 ( 0x08)
0x010 (0x04)
0x008 (0x02)
0x004 (0x01)
0x002
0x001
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 46. Power Supply Rejection Ratio vs. Frequency
Figure 43. 50 kΩ Gain vs. Frequency vs. Code
0
–20
0
–15
V
/V = ±15V,
DD SS
V
/V = ±15V
DD SS
CODE = HALF SCALE
fIN = 1kHz
NOISE BW = 22kHz
20kꢀ
CODE = HALF SCALE
= 1V rms
V
IN
Noise BW = 22kHz
20kꢀ
50kꢀ
100kꢀ
–40
50kꢀ
100kꢀ
–30
–45
–60
–60
–80
–75
–100
–120
–140
–90
–105
–120
0.001
0.01
0.1
AMPLITUDE (V rms)
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 44. THD + Noise vs. Frequency
Figure 47. THD + Noise vs. Amplitude
Rev. F | Page 18 of 30
Data Sheet
AD5291/AD5292
1,000,000
900,000
800,000
700,000
600,000
500,000
400,000
300,000
200,000
100,000
0
8
7
6
5
4
3
2
1
0
20k – 0pF
50k – 150pF
50k – 250pF
100k – 0pF
100k – 75pF
100k – 150pF
100k – 250pF
V
V
V
/V = 30V/0V
DD SS
20k – 75pF
20k – 150pF
20k – 250pF
50k – 0pF
= V
= V
A
B
DD
SS
50k – 75pF
20kꢀ
50kꢀ
100kꢀ
0
0
8
16
32
16
CODE (Decimal)
64
128
256
64
512 AD5292
128 AD5291
0
0
256
64
512
128
768
192
1023 AD5292
255 AD5291
8
32
CODE (Decimal)
Figure 48. Bandwidth vs. Code vs Net Capacitance
Figure 51. Theoretical Maximum Current vs. Code
35
1.2
1.0
V
V
V
V
/V = ±15V
DD SS
30
25
20
15
10
5
= +5V
LOGIC
= V
= V
A
B
DD
SS
0.8
20kꢀ
0.6
50kꢀ
100kꢀ
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0
–5
–0.4
–0.2
0
0.2
0.4
TIME (ms)
0.6
0.8
1.0
1.2
–2
0
2
4
6
8
10
12
14
16
TIME (µs)
Figure 52. Maximum Transition Glitch
Figure 49. IDD Waveform While Blowing/Reading Fuse
40
32
24
16
8
35
V
, CODE: FULL SCALE,
NORMAL MODE
V
V
V
/V = ±15V
DD SS
WB
= V
A
DD
30
25
20
15
10
5
= V
B
SS
V
V
V
V
/V = 30V/0V
DD SS
CODE = HALF CODE
= 5V
LOGIC
= V
= V
A
B
DD
SS
V
, CODE: FULL SCALE,
WB
R-PERF MODE
0
–8
SYNC
–16
20kꢀ
50kꢀ
100kꢀ
20kꢀ
50kꢀ
100kꢀ
V
, CODE: HALF-SCALE,
NORMAL MODE
–24
–32
WB
0
V
, CODE: HALF-SCALE,
WB
R-PERF MODE
–40
–0.5
–5
0
5
10
15
20
25
30
35
40
45
TIME (µs)
TIME (µs)
Figure 53. Digital Feedthrough
Figure 50. 20 kΩ Large-Signal Settling Time from Code Zero Scale
Rev. F | Page 19 of 30
AD5291/AD5292
Data Sheet
6
75.0
62.5
50.0
37.5
25.0
12.5
0
300
250
200
150
100
50
V
V
/V = ±15V
DD SS
V
/V = ±15V
DD SS
= +5V
LOGIC
20kꢀ
50kꢀ
100kꢀ
5
4
3
2
1
0
–1
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
TIME (ms)
Figure 54. VEXT_CAP Waveform While Reading Fuse or Calibration
Figure 56. Code Range > 1% R-Tolerance Error vs. Temperature
8
20.0
80
70
60
50
40
30
20
10
0
V
V
/V = ±15V
DD SS
V
V
= V
= V
20kꢀ
50kꢀ
100kꢀ
A
B
DD
= +5V
LOGIC
SS
17.5
15.0
12.5
10.0
7.5
TEMPERATURE = 25°C
6
3
2
5.0
0
2.5
–2
0
21
26
30
33
VOLTAGE V /V
DD SS
TIME (ms)
Figure 57. Code Range > 1% R-Tolerance Error vs. Voltage
Figure 55. VEXT_CAP Waveform While Writing Fuse
Rev. F | Page 20 of 30
Data Sheet
AD5291/AD5292
ꢂꢄSꢂ CIꢁCUIꢂS
Figure 58 to Figure 63 define the test conditions used in the Specifications section.
NC
DUT
A
I
W
V
A
V+ = V ± 10%
W
DD
∆V
∆V
MS
DD
V
A
B
DD
PSRR (dB) = 20 log
B
W
V+
~
V
MS
∆V
∆V
%
%
MS
DD
PSS (%/%) =
V
MS
NC = NO CONNECT
Figure 58. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
Figure 61. Power Supply Sensitivity (PSS, PSRR)
+15V
A
DUT
A
V+ = V
DD
W
V
IN
N
DUT
1LSB = V+/2
OP42
–15V
V
OUT
W
B
OFFSET
GND
V+
B
2.5V
V
MS
Figure 59. Potentiometer Divider Nonlinearity Error
(INL, DNL)
Figure 62. Gain vs. Frequency
+15V
NC
–15V
GND
GND
0.1V
R
=
=
A
WB
V
DUT
I
DD
CM
I
DUT
B
WB
+15V
–15V
W
R
CODE = 0x00
WB
2
R
W
W
V
+
–
GND
SS
B
0.1V
GND
I
WB
NC
+15V
GND
V
TO V
DD
SS
A = NC
NC = NO CONNECT
–15V
Figure 63. Common-Mode Leakage Current
Figure 60. Wiper Resistance
Rev. F | Page 21 of 30
AD5291/AD5292
Data Sheet
ꢂHꢄOꢁY OF OPꢄꢁAꢂION
The AD5291 and AD5292 digital potentiometers are designed
to operate as true variable resistors for analog signals that
remain within the terminal voltage range of VSS < VTERM <
VDD. The patented 1% resistor tolerance feature helps to
minimize the total RDAC resistance error, which reduces the
overall system error by offering better absolute matching and
improved open-loop performance. The digital potentiometer
wiper position is determined by the RDAC register contents.
The RDAC register acts as a scratchpad register, allowing as
many value changes as necessary to place the potentiometer
wiper in the correct position. The RDAC register can be
programmed with any position setting using the standard SPI
interface by loading the 16-bit data-word. Once a desirable
position is found, this value can be stored in a 20-TP memory
register. Thereafter, the wiper position is always restored to that
position for subsequent power-up. The storing of 20-TP data
takes approximately 6 ms; during this time, the shift register is
locked, preventing any changes from taking place. The RDY pin
identifies the completion of this 20-TP storage.
the lower two RDAC data bits are don’t cares if the RDAC register
is read from or written to. Data is loaded MSB first (Bit DB15).
The four control bits determine the function of the software
command (see Table 11). Figure 3 shows a timing diagram of a
typical AD5291 and AD5292 write sequence.
SYNC
The write sequence begins by bringing the
line low. The
SYNC
pin must be held low until the complete data-word is
SYNC
loaded from the DIN pin. When
returns high, the serial
data-word is decoded according to the commands in Table 11.
The command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5291 and AD5292 have an
internal counter that counts a multiple of 16 bits (a frame) for
proper operation. For example, AD5291 and AD5292 work with
a 32-bit word but does not work properly with a 31-bit or 33-bit
word. The AD5291 and AD5292 do not require a continuous
SYNC
SCLK, when
is high, and all serial interface pins should
be operated at close to the VLOGIC supply rails to minimize
power consumption in the digital input buffers.
SERIAL DATA INTERFACE
RDAC REGISTER
The AD5291 and AD5292 contain a serial interface (
,
SYNC
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with all zeros, the wiper is connected to Terminal B of
the variable resistor. The RDAC register is a standard logic
register; there is no restriction on the number of changes allowed.
SCLK, DIN and SDO) that is compatible with SPI interface
standards, as well as most DSPs. The part allows writing of data
via the serial interface to every register.
SHIFT REGISTER
The AD5291 and AD5292 shift register is 16 bits wide (see
Figure 2). The 16-bit input word consists of two zeros, followed
by four control bits, and 10 RDAC data bits. For the AD5291,
Table 11. Command Operation Truth Table
Command
Bits[DB13:DB10]
Data Bits[DB9:DB0]1
D9 D8 D7 D6 D5 D4 D3 D2 D1
Command DB15 DB14 C3
C2
0
C1
0
C0
0
D0
Operation
0
1
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
NOP command: do nothing.
0
0
1
D9 D8 D± D6 Dꢀ D4 D3 D2 D12 D02 Write contents of serial data to
RDAC.
2
3
4
ꢀ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read RDAC wiper setting from the
SDO output in the next frame.
X
Store wiper setting: store RDAC
setting to 20-TP memory.
X
Reset: refresh RDAC with 20-TP
stored value.
D4 D3 D2 D1
D0
Read contents of 20-TP memory,
or status of 20-TP memory, from
the SDO output in the next frame.
6
±
8
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D3 D2 D1
D0
X
Write contents of serial data to
control register.
X
X
X
X
X
X
Read control register from the
SDO output in the next frame.
D0
Software shutdown.
D0 = 0 (normal mode).
D0 = 1 (device placed in shutdown
mode).
1 X = don’t care.
2 In the ADꢀ291, this bit is a don’t care.
Rev. F | Page 22 of 30
Data Sheet
AD5291/AD5292
20-TP MEMORY
WRITE PROTECTION
Once a desirable wiper position is found, the contents of the
RDAC register can be saved into a 20-TP memory register
(see Table 12). Thereafter, the wiper position is always set at that
position for any future on-off-on power supply sequence. The
AD5291 and AD5292 have an array of 20 one-time programmable
(OTP) memory registers. When the desired word is programmed
to 20-TP memory, the device automatically verifies that the
program command was successful. The verification process
includes margin testing. Bit C3 of the control register can be
polled to verify that the fuse program command was successful.
Programming data to 20-TP memory consumes approximately
25 mA for 550 μs and takes approximately 8 ms to complete.
During this time, the shift register is locked, preventing any
changes from taking place. The RDY pin can be used to monitor
the completion of the 20-TP memory program and verification.
No change in supply voltage is required to program the 20-TP
memory. However, a 1 μF capacitor on the EXT_CAP pin is
required (see Figure 68). Prior to 20-TP activation, the AD5291
and AD5292 preset to midscale on power-up.
On power-up, the shift register write commands for both the
RDAC register and the 20-TP memory register are disabled.
The RDAC write protect bit, C1 of the control register (see
Table 13 and Table 14), is set to 0 by default. This disables any
change of the RDAC register content regardless of the software
commands, except that the RDAC register can be refreshed
from the 20-TP memory using the software reset command
RESET
(Command 4) or through hardware by the
pin. To enable
programming of the variable resistor wiper position (program-
ming the RDAC register), the write protect bit, C1 of the control
register, must first be programmed. This is accomplished by
loading the shift register with Command 6 (see Table 11). To
enable programming of the 20-TP memory block bit, C0 of the
control register (set to 0 by default) must first be set to 1.
Table 12. Write and Read to RDAC and 20-TP Memory
DIN
SDO
Action
0x1803
0x0ꢀ00
0x0800
0x0C00
0xXXXX
0x1803
0x0ꢀ00
0x0100
Enable update of wiper position and 20-TP memory contents through digital interface.
Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position.
Prepare data read from the RDAC register.
Stores RDAC register content into 20-TP memory. The 16-bit word appears out of SDO, where the last 10 bits
contain the contents of the RDAC register (0x100).
0x1C00
0x0000
0x0C00
0x000X
Prepare data read from the control register.
NOP Instruction 0 sends 16-bit word out of SDO, where the last four bits contain the contents of the control
register. If Bit C3 = 1, the fuse program command is successful.
Table 13. Control Register Bit Map1
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
X
X
X
X
C3
C2
C1
C0
1 X = don’t care.
Table 14. Control Register Function
Bit Name
Description
C0
20-TP program enable
0 = 20-TP program disabled (default)
1 = enable device for 20-TP program
RDAC register write protect
0 = wiper position frozen to value in memory (default)1
1 = allow update of wiper position through digital Interface
Calibration enable
C1
C2
C3
0 = resistor performance mode enabled (default)
1 = normal mode enabled
20-TP memory program success
0 = fuse program command unsuccessful (default)
1 = fuse program command successful
1 Wiper position frozen to value last programmed in 20-TP memory. Wiper is frozen to midscale if 20-TP memory has not been previously programmed.
Rev. F | Page 23 of 30
AD5291/AD5292
Data Sheet
read-only Memory Address 0x14 and Memory Address 0x15
using Command 5. The data bytes read back from Memory
Address 0x014 and Memory Address 0x015 are thermometer
encoded versions of the address of the last programmed
memory location.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the RDAC register) is accomplished by loading
the shift register with Command 1 (see Table 11) and the desired
wiper position data. When the desired wiper position is deter-
mined, the user can load the shift register with Command 3
(see Table 11), which stores the wiper position data in the 20-TP
memory register. After 6 ms, the wiper position is permanently
stored in the 20-TP memory. The RDY pin can be used to moni-
tor the completion of this 20-TP program. Table 12 provides a
programming example, listing the sequence of serial data input
(DIN) words with the serial data output appearing at the SDO pin
in hexadecimal format.
For the example outlined in Table 15, the address of the last
programmed location is calculated as
(Number of Bits = 1 in Memory Address 0x14) + (Number
of Bits = 1 in Memory Address 0x15) − 1 = 10 + 8 − 1 = 17
(0x10)
If no memory location has been programmed, then the address
generated is −1.
SHUTDOWN MODE
20-TP READBACK AND SPARE MEMORY STATUS
The AD5291 and AD5292 can be placed in shutdown mode by
executing the software shutdown command, Command 8 (see
Table 11), and setting the LSB, D0, to 1. This feature places the
RDAC in a special state in which Terminal A is open-circuited,
and Wiper W is connected to Terminal B. The contents of the
RDAC register are unchanged by entering shutdown mode.
However, all commands listed in Table 11 are supported while
in shutdown mode. Execute Command 8 (see Table 11), and set
the LSB, D0, to 0 to exit shutdown mode.
It is possible to read back the contents of any of the 20-TP
memory registers through SDO by using Command 5 (see
Table 11). The lower five LSB bits (D0 to D4) of the data byte
select which memory location is to be read back (see Table 16).
Data from the selected memory location are clocked out of the
SDO pin during the next SPI operation, where the last 10 bits
contain the contents of the specified memory location.
It is also possible to calculate the address of the most recently
programmed memory location by reading back the contents of
Table 15. Example 20-TP Memory Readback
DIN
SDO
Action
0x1414 0xXXXX Prepares data read from Memory Address 0x14.
0x141ꢀ 0x03FF
Prepares data read from Memory Address 0x1ꢀ. Sends 16-bit word out of SDO, where the last 10 bits contain the
contents of Memory Address 0x14.
0x0000 0x00FF
0x1410 0x0000
NOP Command 0 sends 16-bit word out of SDO, where last 10-bits contain the contents of Memory Address 0x1ꢀ.
Prepares data read from memory location 0x10.
0x0000 0xXXXX NOP Instruction 0 sends 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Address 0x10 (1±).
Table 16. Memory Map of Command 5
Data Bits[DB9:DB0]1
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Register Contents
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
0
0
0
0
0
…
0
0
1
1
1
0
0
0
0
0
…
1
1
0
0
0
0
0
0
0
1
…
0
1
0
1
1
0
0
1
1
0
…
0
1
1
0
0
0
1
0
1
0
…
1
0
1
0
1
1st programmed wiper location (0x00)
2nd programmed wiper location (0x01)
3rd programmed wiper location (0x02)
4th programmed wiper location (0x03)
ꢀth programmed wiper location (0x04)
…
10th programmed wiper location (0x09)
1ꢀth programmed wiper location (0x0E)
20th programmed wiper location (0x13)
Programmed memory status (thermometer encoded)2 (0x14)
Programmed memory status (thermometer encoded)2 (0x1ꢀ)
1 X = don’t care.
2 Allows the user to calculate the remaining spare memory locations.
Rev. F | Page 24 of 30
Data Sheet
AD5291/AD5292
SYNC
Keep the
pin low until all 32 bits are clocked into their
RESISTOR PERFORMANCE MODE
SYNC
respective serial registers. The
complete the operation.
pin is then pulled high to
This mode activates a new, patented 1% end-to-end resistor
tolerance that ensures a 1% resistor tolerance on each code,
that is, code = half scale, RWB = 10 kΩ 100 Ω. See Table 2
(AD5291) or Table 5 (AD5292) to check which codes achieve
1% resistor tolerance. The resistor performance mode is
activated by programming Bit C2 of the control register (see
Table 13 and Table 14). The typical settling time is shown in
Figure 50.
V
LOGIC
R
AD5291/
AD5292
AD5291/
AD5292
P
2.2kꢀ
MOSI
DIN
SDO
DIN
U1 SDO
U2
MICRO-
CONTROLLER
SCLK
SS
SYNC
SCLK
SYNC
SCLK
RESET
Figure 64. Daisy-Chain Configuration Using SDO
RESET
A low-to-high transition of the hardware
pin loads the
RDAC register with the contents of the most recently programmed
20-TP memory location. The AD5291 and AD5292 can also be
reset through software by executing Command 4 (see Table 11).
If no 20-TP memory location is programmed, then the RDAC
register loads with midscale upon reset. The control register is
restored with default bits; see Table 14.
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented
the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5291 and AD5292 employ
a three-stage segmentation approach, as shown in Figure 65.
The AD5291 and AD5292 wiper switches are designed with the
transmission gate CMOS topology and with the gate voltages
derived from VDD and VSS.
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting, 50-TP values and
control register using Command 2, Command 5 and Command 7,
respectively (see Table 11) or the SDO pin can be used in daisy-
chain mode. Data is clocked out of SDO on the rising edge of
SCLK. The SDO pin contains an open-drain N-channel FET
that requires a pull-up resistor if this pin is used. To place the
pin in high impedance and minimize the power dissipation
when the pin is used, the 0x8001 data word followed by
Command 0 should be sent to the part. Table 17 provides a
sample listing for the sequence of the serial data input (DIN).
Daisy chaining minimizes the number of port pins required
from the controlling IC. As shown in Figure 64, users need to
tie the SDO pin of one package to the DIN pin of the next
package. Users may need to increase the clock period, because
the pull-up resistor and the capacitive loading at the SDO-to-
DIN interface may require additional time delay between
subsequent devices.
A
R
R
L
L
R
M
S
W
R
M
R
R
W
W
W
8-/10-BIT
ADDRESS
DECODER
R
M
R
L
R
M
R
L
B
When two AD5291 and AD5292 devices are daisy-chained, 32
bits of data are required. The first 16 bits go to U2, and the
SYNC
second 16 bits go to U1. Hold the
pin low until all 32 bits
SYNC
are clocked into their respective shift registers. The
then pulled high to complete the operation.
pin is
Figure 65. Simplified RDAC Circuit
Table 17. Minimize Power Dissipation at SDO Pin
DIN
SDO1
Action
0xXXXX
0x8001
0x0000
0xXXXX
0xXXXX
High impedance
Last user command sent to the digipot
Prepares the SDO pin to be placed in high impedance mode
The SDO pin is placed in high impedance
1 X is don’t care.
Rev. F | Page 2ꢀ of 30
AD5291/AD5292
Data Sheet
where:
PROGRAMMING THE VARIABLE RESISTOR
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
Rheostat Operation—1% Resistor Tolerance
The AD5291 and AD5292 operate in rheostat mode when only
two terminals are used as a variable resistor. The unused
terminal can be left floating or tied to the W terminal, as shown in
Figure 66.
R
AB is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of 120 Ω
is present. Regardless of which setting the part is operating in,
take care to limit the current between Terminal A and Terminal B,
between Terminal W and Terminal A, and between Terminal W
and Terminal B, to the maximum continuous current of 3 mA or
to the pulse current specified in Table 8. Otherwise, degradation
or possible destruction of the internal resistors may occur.
A
A
A
W
W
W
B
B
B
Figure 66. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 20 kΩ, 50 kΩ, and 100 kΩ, and 256 or 1024
tap points accessed by the wiper terminal. The 8-/10-bit data in
the RDAC latch is decoded to select one of the 256/1024
possible wiper settings. The AD5291 and AD5292 contain an
internal 1% resistor performance mode that can be disabled or
enabled (this is enabled by default), by programming Bit C2 of
the control register (see Table 13 and Table 14). The digitally
programmed output resistance between the W terminal and the
A terminal, RWA, and between the W terminal and B terminal,
RWB, is internally calibrated to give a maximum of 1% absolute
resistance error across a wide code range. As a result, the
general equations for determining the digitally programmed
output resistance between the W terminal and B terminal are
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
the wiper to B and at the wiper to A that is proportional to the
input voltage at A to B, as shown in Figure 67. Unlike the polarity
of VDD to GND, which must be positive, voltage across A to B,
W to A, and W to B can be at either polarity.
V
IN
A
W
V
OUT
B
Figure 67. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is
equal to the voltage applied across Terminal A and Terminal B,
divided by the 256/1024 positions of the potentiometer divider.
The general equations defining the output voltage at VW with
respect to ground for any valid input voltage applied to Terminal A
and Terminal B are
AD5291:
D
256
R
WB (D)
RAB
(1)
(2)
AD5292:
D
1024
RWB (D)
RAB
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
AD5291:
D
256
256 D
256
R
AB is the end-to-end resistance.
VW (D)
VA
VB
(5)
(6)
Similar to the mechanical potentiometer, the resistance of the
AD5292:
VW (D)
RDAC between the W terminal and the A terminal also produces a
digitally controlled complementary resistance, RWA. RWA is also
calibrated to give a maximum of 1% absolute resistance error.
1024 D
D
1024
VA
VB
1024
RWA starts at the maximum resistance value and decreases as the
If using the AD5291 and AD5292 in voltage divider mode as
data loaded into the latch increases. The general equations for
shown in Figure 67, then the 1% resistor tolerance calibration
feature reduces the error when matching with discrete resistors.
However, it is recommended to disable the internal 1% resistor
tolerance calibration feature by programming Bit C2 of the
control register (see Table 13 and Table 14) to optimize wiper
position update rate. In this configuration, the RDAC is ratiome-
tric and resistor tolerance error does not affect performance.
this operation are
AD5291:
256 D
R
WA (D)
AD5292:
WA (D)
RAB
(3)
(4)
256
1024 D
R
RAB
1024
Rev. F | Page 26 of 30
Data Sheet
AD5291/AD5292
Operation of the digital potentiometer in the voltage divider
mode results in a more accurate operation over temperature.
Unlike the rheostat mode, the output voltage is dependent
mainly on the ratio of the internal resistors, RWA and RWB, and
not the absolute values. Therefore, the temperature drift reduces
to 5 ppm/°C.
The ground pins of the AD5291 and AD5292 devices are
primarily used as a digital ground reference. To minimize the
digital ground bounce, the AD5291 and AD5292 ground
terminals should be joined remotely to the common ground.
The digital input control signals to the AD5291 and AD5292
must be referenced to the device ground pin (GND), and satisfy
the logic level defined in the Specifications section.
EXT_CAP CAPACITOR
Power-Up Sequence
A 1 μF capacitor to GND must be connected to the EXT_CAP pin
(see Figure 68) on power-up and throughout the operation of
the AD5291 and AD5292.
To ensure that the AD5291 and AD5292 power up correctly, a
1 μF capacitor must be connected to the EXT_CAP pin. Because
there are diodes to limit the voltage compliance at Terminal A,
Terminal B, and Terminal W (see Figure 69), it is important to
power VDD and VSS first before applying any voltage to Terminal A,
Terminal B, and Terminal W. Otherwise, the diode is forward-
biased such that VDD and VSS are powered up unintentionally.
The ideal power-up sequence is GND, VSS, VLOGIC and VDD, the
digital inputs, and then VA, VB, and VW. The order of powering
up VA, VB, VW, and the digital inputs is not important as long as
AD5291/
AD5292
EXT_CAP
OTP
MEMORY
BLOCK
C1
1µF
GND
Figure 68. Hardware Setup for EXT_CAP Pin
they are powered after VDD, VSS, and VLOGIC
.
TERMINAL VOLTAGE OPERATING RANGE
Regardless of the power-up sequence and the ramp rates of the
power supplies, after VLOGIC is powered, the power-on preset
activates, restoring the 20-TP memory value to the RDAC register.
The positive VDD and negative VSS power supplies of the
AD5291 and AD5292 define the boundary conditions for
proper 3-terminal digital potentiometer operation. Supply
signals present on Terminal A, Terminal B, and Terminal W
that exceed VDD or VSS are clamped by the internal forward-
biased diodes (see Figure 69).
V
DD
A
W
B
V
SS
Figure 69. Maximum Terminal Voltages Set by VDD and V SS
Rev. F | Page 2± of 30
AD5291/AD5292
Data Sheet
APPLICAꢂIONS INFOꢁMAꢂION
HIGH VOLTAGE DAC
HIGH ACCURACY DAC
The AD5292 can be configured as a high voltage DAC, with
output voltage as high as 33 V. The circuit is shown in Figure 70.
The output is
It is possible to configure the AD5292 as a high accuracy DAC
by optimizing the resolution of the device over a specific
reduced voltage range. This is achieved by placing external
resistors on either side of the RDAC, as shown in Figure 72.
The improved 1% R-Tolerance specification greatly reduces
error associated with matching to discrete resistors.
D
R
(7)
1.2 V 1
2
VOUT (D)
1024
R1
R3 (D1024 RAB ) V DD
R1 ((1024D)1024) RAB R3
where D is the decimal code from 0 to 1023.
VOUT (D)
(8)
V
DD
V
DD
V
DD
R
BIAS
U2
U1A
R
1
U1
V+
AD5292
D1
AD8512
V–
AD5292
V
DD
U1B
20kꢀ
ADR512
U2
V+
OP1177
V–
R
20kꢀ
2
V
OUT
B
V
AD8512
±1%
OUT
B
R
2
R
3
R
1
Figure 72. Optimizing Resolution
Figure 70. High Voltage DAC
VARIABLE GAIN INSTRUMENTATION AMPLIFIER
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
The AD8221 in conjunction with the AD5291 and AD5292 and
the ADG1207, as shown in Figure 73, make an excellent
instrumentation amplifier for use in data acquisition systems.
The data acquisition system’s low distortion and low noise
enable it to condition signals in front of a variety of ADCs.
For applications that require high current adjustments such as a
laser diode or tunable laser, a boosted voltage source can be
considered; see Figure 71.
U3 2N7002
V
V
OUT
IN
ADG1207
V
DD
U1
AD5292
R
+V
BIAS
C
IN1
C
A
U2
OP184
I
W
L
V
+V
–V
OUT
AD5292
IN4
IN1
SIGNAL
LD
AD8221
B
–V
IN4
V
SS
Figure 71. Programmable Boosted Voltage Source
Figure 73. Data Acquisition System
In this circuit, the inverting input of the op amp forces VOUT to
be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-channel
FET (U3). The N-Channel FET power handling must be adequate
to dissipate (VIN − VOUT) × IL power. This circuit can source a
maximum of 100 mA with a 33 V supply.
The gain can be calculated by using Equation 9.
49.4 kꢀ
(9)
G(D) 1
D 1024 RAB
Rev. F | Page 28 of 30
Data Sheet
AD5291/AD5292
The configuration to reduce zipper noise is shown in Figure 74,
and the results of using this configuration is shown in Figure 75.
The input is ac-coupled by C1 and attenuated down before feeding
into the window comparator formed by U2, U3, and U4B. U6 is
used to establish the signal zero reference. The upper limit of
the comparator is set above its offset and, therefore, the output
pulses high whenever the input falls between 2.502 V and 2.497 V
(or 0.005 V window) in this example. This output is AND’ed
AUDIO VOLUME CONTROL
The excellent THD performance and high voltage capability
make the AD5291 and AD5292 ideal for a digital volume
control as an audio attenuator or gain amplifier. A typical
problem in these systems is that a large step change in the
volume level at any arbitrary time can lead to an abrupt
discontinuity of the audio signal causing an audible zipper
noise. To prevent this, a zero-crossing window detector can be
SYNC
with the
updates whenever the signal crosses the window. To avoid a
SYNC
signal such that the AD5291 and AD5292
SYNC
inserted to the
line to delay the device update until the
audio signal crosses the window. Because the input signal can
operate on top of any dc level rather than absolute zero volt
level, zero-crossing in this case means the signal is ac-coupled,
and the dc offset level is the signal zero reference point.
constant update of the device, the
signal should be
programmed as two pulses, rather than as one.
In Figure 75, the lower trace shows that the volume level changes
from a quarter-scale to full-scale when a signal change occurs
near the zero-crossing window.
C1
1µF
V
IN
5V
AD5292
U1
+15V
R
1
+5V
V
DD
100kꢀ
C3
0.1µF
A
U2
CC
ADCMP371
GND
V
C2
0.1µF
R
2
+15V
U5
200ꢀ
R
90kꢀ
V
4
SS
W
–15V
U4B
V+
V
OUT
4
5
U4A
20kꢀ
6
1
2
+5V
U3
7408
SYNC
7408
R
5
V–
10kꢀ
V
CC
5V
SCLK
SDIN
SCLK
SDIN
ADCMP371
GND
B
–15V
U6
V+
AD8541
V–
SYNC
GND
R
3
100kꢀ
Figure 74. Audio Volume Control with Zipper Noise Reduction
T
1
2
CHANNEL 1
FREQ = 20.25kHz
1.03V p-p
B
B
CH1 500mV
CH2 500mV
M20µs A CH2
50.0%
210mV
W
W
T
Figure 75. Zipper Noise Detector
Rev. F | Page 29 of 30
AD5291/AD5292
Data Sheet
OUꢂLINꢄ DIMꢄNSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model12
ADꢀ291BRUZ-20
ADꢀ291BRUZ-20-RL±
ADꢀ291BRUZ-ꢀ0
ADꢀ291BRUZ-100
ADꢀ291BRUZ-100-RL±
ADꢀ292BRUZ-20
ADꢀ292BRUZ-20-RL±
ADꢀ292BRUZ-ꢀ0
ADꢀ292BRUZ-ꢀ0-RL±
ADꢀ292BRUZ-100
ADꢀ292BRUZ-100-RL±
EVAL-ADꢀ292DBZ
RAB (kΩ)
20
20
Resolution
2ꢀ6
2ꢀ6
2ꢀ6
2ꢀ6
Memory
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
Temperature Range
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
−40°C to +10ꢀ°C
Package Description
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
Evaluation Board
Package Option
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
ꢀ0
100
100
20
20
ꢀ0
ꢀ0
100
100
2ꢀ6
1,024
1,024
1,024
1,024
1,024
1,024
RU-14
RU-14
RU-14
1 Z = RoHS Compliant Part.
2 The EVAL-ADꢀ292DBZ is also used to test the ADꢀ291.
©2009–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07674-0-11/19(F)
Rev. F | Page 30 of 30
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