AD53041KRP [ADI]
High Speed Active Load with Inhibit Mode; 高速有源负载与禁止模式
| 型号： | AD53041KRP |
| 厂家： | 
ADI |
| 描述： | High Speed Active Load with Inhibit Mode |
| 文件： | 总4页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed Active Load
with Inhibit Mode
a
AD53041
FUNCTIONAL BLOCK DIAGRAM
FEATURES
؎50 mA Voltage Programmable Current Range
Three Selectable Gain Ranges
1.7 ns Propagation Delay
GAINA
GAINB
VOLTAGE-TO-CURRENT
CONVERTER
Inhibit Mode Function
High Speed Differential Inputs for Maximum Flexibility
Ultrasmall 20-Lead PSOP Package with Built-In Heatsink
I
OLPGM
INH
I
OLOUT
APPLICATIONS
I
OLRTN
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
I
OHRTN
INH
I
OHOUT
I
OHPGM
VOLTAGE-TO-CURRENT
CONVERTER
AD53041
PRODUCT DESCRIPTION
V
COMIN
V
COMOUT
The AD53041 is a complete, high speed, current switching load
designed for use in linear, digital or mixed signal test systems.
Combining a high speed monolithic process with a unique sur-
face mount package, this product attains superb electrical per-
formance while preserving optimum packaging densities in an
ultrasmall 20-lead, PSOP package with a built-in heatsink.
V
OUT_SENSE
COM
BUFFER
GAINA GAINB FULL-SCALE CURRENT
0
0
1
1
0
1
0
1
50mA
16mA
5mA
NOT VALID
Featuring current programmability of up to ±50 mA, the
AD53041 is designed to force the device under test to source
or sink the programmed IOH and IOL currents. IOH and IOL
currents are determined by applying a corresponding voltage
(5 V = 50 mA, 16 mA, 5 mA) to the IOHPGM and IOLPGM pins.
The voltage-to-current conversion is performed within the
AD53041, thus allowing the current levels to be set by a stan-
dard voltage out digital-to-analog converter.
The AD53041 is available in a 20-lead, PSOP package with a
built-in-heatsink and is specified to operate over the ambient
commercial temperature range from –25°C to +85°C.
INH
V
CC
AD53041
V
EE
0.1F
0.1F
INH
AGND
I
The AD53041 transition from IOH to IOL occurs when the out-
put voltage of the device under test slews above or below the
programmed threshold or commutation voltage. The commuta-
tion voltage is programmable from –2 V to +7 V, covering the
large spectrum of logic devices while able to support the large
current specifications (48 mA) typically associated with line
drivers. To test I/O devices, the active load can be switched into
a high impedance state (Inhibit Mode), electrically removing the
active load from the path through the Inhibit Mode feature. The
active load leakage current in Inhibit is typically 100 nA.
OLOUT
I
OHPGM
V
COMIN
TO DUT
V
COMOUT
OUT_SENSE
1Ω
I
OLPGM
0.1F
HSMS-2818
OR EQUIV.
GAINA
GAINB
I
OHOUT
I
OLRTN
I
OHRTN
GND
NOT SHOWN: THE AGND PINS ARE THE HIGH QUALITY GROUND
REFERENCE FOR THE VOLTAGE-TO-CURRENT CONVERTERS.
THE GND PINS PROVIDE RETURN PATHS FOR INTERNAL CURRENTS.
The Inhibit input circuitry is implemented using high speed
differential inputs with a common-mode voltage range of
–2 V to +3 V and a maximum differential voltage of 3 V. This
allows for direct interface to precision differential ECL timing or
the simplicity of switching active load from a single ended TTL
or CMOS logic source. With switching speeds from IOH or IOL
into Inhibit of less than 2.0 ns, the AD53041 can be electrically
removed from the signal path “on the fly.”
V
IS THE POSITIVE SUPPLY, V IS THE NEGATIVE SUPPLY.
CC
EE
ALL GROUND PINS SHOULD BE CONNECTED TO THE SYSTEM
ANALOG GROUND PLANE.
Figure 1. Typical Application Circuit
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
(All specifications apply at TJ = +85؇C ؎ 5؇C. +VS = +10.5 V ؎ 3%, –VS =
–5.2 V ؎ 3% unless otherwise specified. VCOMOUT is bypassed to ground with a series RC consisting of a 1 ⍀ resistor and a 0.1 F capacitor,
and is also connected directly to OUT_SENSE. All temperature coefficients are characterized over TJ = 75؇C–95؇C.)
AD53041–SPECIFICATIONS
Parameter
Min Typ
Max Units
Test Conditions
INPUT CHARACTERISTICS
INH, INH
Input Voltage
Bias Current
–2
–1
ECL
0
1
V
mA
INH, INH = –2 V, 0 V
GAINA, GAINB
Input Voltage
Bias Current
0
0
TTL/CMOS
5
2
V
mA
GAINA, GAINB = 5 V
IOHPGM, IOLPGM Voltage Range
IOH, 0 to + Full Scale, Any Gain Range
–0.1
–0.1
–300
5.2
5.2
300
V
V
µA
V(IOHOUT) = –2 V, 7 V
V(IOLOUT) = –2 V, 7 V
V(IOHPGM) = +5 V, V(IOLPGM) = 0 V
I
OL, 0 to – Full Scale, Any Gain Range
IOHPGM, IOLPGM Bias Current
VCOM BUFFER
Voltage Range
Offset
Offset Drift
Nonlinearity
Input Bias Current
Output Resistance
–2
7
V
±50 mA Output Current
VCOM = 0 V
VCOM = 0 V
VCOM = –2 V to 7 V
VCOM = –2 V to 7 V
±5
0.1
±5
mV
mV/°C
mV
µA
–50
50
<1
Ω
VCOM = 0 V, IOUT = ±50 mA
OUTPUT CHARACTERISTICS
Full-Scale Current Range
Range 0
See Functional Block Diagram
50
16
5
mA
mA
mA
Range 1
Range 2
Offset Error
Range 0
Range 1
V(IOHPGM) = V(IOLPGM) = 100 mV,
V(IOHOUT) = ±2 V, V(IOLOUT) = ±2 V
–1
–0.3
–0.3
1
0.3
0.3
mA
mA
mA
Range 2
Offset Drift
Range 0
Range 1
Range 2
V(IOHPGM) = V(IOLPGM) = 100 mV,
V(IOHOUT) = V(IOLOUT) = 0 V
1
1
1
µA/°C
µA/°C
µA/°C
Gain Error
Range 0
Range 1
Range 2
<1
<5
<8
% FSR
% FSR
% FSR
Gain Drift
Range 0
Range 1
Range 2
1
0.5
0.3
µA/°C
µA/°C
µA/°C
Gain Ratio Drift
Range 1 to Range 0
Range 2 to Range 0
Nonlinearity
Common-Mode Error
PSRR
0.01
0.01
±0.05
±0.05
±0.1
%/°C
%/°C
% FSR
%FSR
Range 0
Range 0
%FSR/V Range 0, V(IOHPGM) = V(IOLPGM
)
= 100 mV, Either Supply Over Operating
Range
OUTPUT VOLTAGE RANGE
IOHOUT, IOHRTN
IOLOUT, IOLRTN
–2.5
–2.5
7.5
7.5
V
V
IOH = 50 mA
IOL = 50 mA
REV. A
–2–
AD53041
Parameter
Min
Typ
Max
Units
Test Conditions
LEAKAGE CURRENTS
IOH Inhibit-Mode Leakage
IOL Inhibit-Mode Leakage
Range 0, Bridge Diode Leakage Not Included
V(IOHOUT) = –2.5 V to 7.5 V, Inhibited
V(IOLOUT) = –2.5 V to 7.5 V, Inhibited
–1
–1
–3
1
1
3
µA
µA
µA
I
OH Off-State Leakage
V(IOHOUT) = –2.5 V to 7.5 V, V(IOHPGM
)
= –0.2 V
IOL Off-State Leakage
–3
3
µA
V(IOLOUT) = –2.5 V to 7.5 V, V(IOLPGM
= –0.2 V
)
DYNAMIC PERFORMANCE
Propagation Delays
±IMAX to Inhibit
1.4
1
1.9
ns
ns
ns
Range 0, IMAX, RLOAD = 50 Ω
Range 0, IMAX, RLOAD = 50 Ω
Part-to-Part Skew
Inhibit to ±IMAX
Part-to-Part Skew
Propagation Delay Drift
Capacitance
1
10
3
ns
ps/°C
pF
±IMAX to Inhibit, Inhibit to ±IMAX
IOHOUT or IOLOUT Without Diodes
POWER SUPPLIES
–VS to +VS Range
Positive Supply Range
Negative Supply Range
Positive Supply Current
15.2
10.2
–5.4
15.7
10.5
–5.2
16.2
10.8
–5.0
160
V
V
V
mA
Range 0, V(IOHPGM) =
V(IOLPGM) = 5.0 V, Active
Range 0, V(IOHPGM) =
V(IOLPGM) = 200 mV, Active
Range 0, V(IOHPGM) =
V(IOLPGM) = 5.0 V, Active
Range 0, V(IOHPGM) =
10
10
60
mA
mA
mA
W
Negative Supply Current
Power Dissipation
160
60
V(IOLPGM) = 200 mV, Active
2.1
2.3
IOH = 50 mA, IOL = –50 mA, Active,
V(IOHOUT) = 7 V, V(IOLOUT) = –2 V
NOTES
Typical values are not tested or guaranteed.
Specifications subject to change without notice.
Table I. Active Load Truth Table
(Including External Diode Bridge per Figure 1; Scale Factors per Functional Block Diagram)
OUTPUT STATES (IFS Is Full-Scale Current Set by GAINA, GAINB)
V(DUT)
INH
INH
IOH
IOL
I(VDUT)
< VCOM
> VCOM
X
0
0
1
1
1
0
[V(IOHPGM) ÷ 5 V] × IFS
[V(IOHPGM) ÷ 5 V] × IFS
0
[V(IOLPGM) ÷ 5 V] × IFS
[V(IOLPGM) ÷ 5 V] × IFS
0
IOL
IOH
0
V
DUT
t
pdAH
PROPAGATION DELAY LOAD AND TEST CONDITIONS
t
pdIH
Vact–
Vact+
PARAMETER
DESCRIPTION
MEASURE POINT
0.50V
I
I
V
DUT
OL
OH
t
50mA 50mA
50mA 50mA
50mA 50mA
50mA 50mA
0V
0V
5V
5V
I
Inh → Act
Act → Inh
Inh → Act
Act → Inh
pdAH
OL
t
pdIL
t
2.00V
I
pdIL
OL
t
t
pdAL
4.50V
I
pdAH
OH
V
DUT
t
I
3.00V
pdIH
OH
ECL+
ECL–
Figure 2. Inhibit Propagation Delay Measurement
REV. A
–3–
AD53041
ABSOLUTE MAXIMUM RATINGS1
PIN CONFIGURATION
Power Supply Voltage
DIMPLE ON BOTTOM
OF PACKAGE
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
GND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.4 V
Inputs
INH, INH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V, –3 V
INH to INH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3 V
GAINA, GAINB . . . . . . . . . . . . . . . . . . . . . . . . +6 V, –3 V
GAINA to GAINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V
VCOMIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V, –3 V
AGND
1
2
3
4
5
6
7
8
9
20 GAINB
19 GAINA
18 DGND
I
OLPGM
I
OLOUT
17
V
CC
I
OLRTN
AD53041
TOP VIEW
16 INH
V
COMIN
(Not to Scale)
15
V
INH
COMOUT
14
V
EE
I
OHRTN
13 DGND
I
OHOUT
I
OHPGM, IOLPGM . . . . . . . . . . . . . . . . . . . . . . . . . +6 V, –1 V
Outputs
IOHOUT, IOHRTN . . . . . . . . . . . . . . . . . . . . . . . . +9 V, –2.5 V
AGND
DGND
12
11
DGND 10
I
OHPGM
NOTES:
AGND IS THE HIGH-QUALITY GROUND REFERENCE
FOR I AND I
I
OLOUT, IOLRTN . . . . . . . . . . . . . . . . . . . . . . . . . +8 V, –3.5 V
VCOMOUT Short Circuit Duration . . . . . . . . . Not Protected2
Environmental
.
OLPGM
OHPGM
DGND IS THE SUPPLY GROUND.
Operating Temperature (Junction) . . . . . . . . . . . . . .+175°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . .+260°C
PACKAGE THERMAL CHARACTERISTICS
Air Flow, FM
JC, ؇C/W
JA, ؇C/W
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
0
50
400
4
4
4
50
49
34
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
2 Short circuit to ground or to either supply will result in the destruction of the
device.
3 To ensure lead coplanarity (±0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24°C
± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%.
20-Lead Thermally Enhanced
Power Small Outline Package (PSOP)
(RP-20)
0.5118 (13.00)
0.4961 (12.60)
ORDERING GUIDE
Shipment Method,
Quantity
per Shipping
Container
20
11
0.1890 (4.80) 0.4193 (10.65)
0.1791 (4.55) 0.3937 (10.00)
HEAT
SINK
0.2992 (7.60)
0.2914 (7.40)
Package
Package
Option
Model
Description
1
10
AD53041KRP 20-Lead Power SOIC Tube, 38 Pieces
RP-20
PIN 1
0.3340 (8.61)
0.3287 (8.35)
0.1043 (2.65)
0.0926 (2.35)
8°
0°
0.0500
(1.27)
BSC
0.0201 (0.51)
0.0118 (0.30)
0.0295 (0.75)
0.0098 (0.25)
SEATING
PLANE
0.0500 (1.27)
0.0057 (0.40)
x 45°
0.0130 (0.33)
0.0040 (0.10)
STANDOFF
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53041 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
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