AD5315BRM_技术文档

2.5 V to 5.5 V, 500 ␮A, 2-Wire Interface

Quad Voltage Output, 8-/10-/12-Bit DACs

AD5305/AD5315/AD5325^*

FEATURES

GENERAL DESCRIPTION

AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP

A Version: ؎1 LSB INL, B Version: ؎0.625 LSB INL

AD5315: 4 Buffered 10-Bit DACs in 10-Lead MSOP

A Version: ؎4 LSB INL, B Version: ؎2.5 LSB INL

AD5325: 4 Buffered 12-Bit DACs in 10-Lead MSOP

A Version: ؎16 LSB INL, B Version: ؎10 LSB INL

Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V

2-Wire (I²C^®Compatible) Serial Interface

2.5 V to 5.5 V Power Supply

Guaranteed Monotonic by Design over All Codes

Power-Down to 80 nA @ 3 V, 200 nA @ 5 V

Three Power-Down Modes

Double-Buffered Input Logic

Output Range: 0 V to V_REF

The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit

buffered voltage output DACs in a 10-lead MSOP that operate

from a single 2.5 V to 5.5 V supply, consuming 500 µA at 3 V.

Their on-chip output ampliﬁers allow rail-to-rail output swing

with a slew rate of 0.7 V/µs. A 2-wire serial interface, which

operates at clock rates up to 400 kHz, is used. This interface is

SMBus compatible at V_DD< 3.6 V. Multiple devices can be

placed on the same bus.

The references for the four DACs are derived from one reference

pin. The outputs of all DACs may be updated simultaneously

using the software LDAC function. The parts incorporate a

power-on reset circuit, which ensures that the DAC outputs power

up to 0 V and remain there until a valid write takes place to the

device. There is also a software clear function that resets all input

and DAC registers to 0 V. The parts contain a power-down

feature that reduces the current consumption of the devices to

200 nA @ 5 V (80 nA @ 3 V).

Power-On Reset to 0 V

Simultaneous Update of Outputs (LDAC Function)

Software Clear Facility

Data Readback Facility

The low power consumption of these parts in normal operation

makes them ideally suited to portable battery-operated equipment.

The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing

to 1 µW in power-down mode.

On-Chip Rail-to-Rail Output Buffer Ampliﬁers

Temperature Range –40؇C to +105؇C

APPLICATIONS

Portable Battery-Powered Instruments

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

Programmable Attenuators

Industrial Process Control

FUNCTIONAL BLOCK DIAGRAM

V

REF IN

DD

LDAC

DAC

INPUT

STRING

DAC A

V

A

B

C

D

BUFFER

OUT

REGISTER

DAC

REGISTER

INPUT

REGISTER

SCL

SDA

STRING

DAC B

INTERFACE

LOGIC

DAC

REGISTER

INPUT

REGISTER

STRING

DAC C

BUFFER

A0

DAC

REGISTER

INPUT

REGISTER

STRING

DAC D

POWER-DOWN

LOGIC

POWER-ON

RESET

AD5305/AD5315/AD5325

GND

*Protected by U.S.Patent No. 5,969,657and 5,684,481.

REV. F

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD5305/AD5315/AD5325–SPECIFICATIONS

(V_DD= 2.5 V to 5.5 V; V_REF= 2 V; R_L= 2 k⍀ to GND;

C_L= 200 pF to GND; all speciﬁcations T_MINto T_MAX, unless otherwise noted.)

A Version²

Typ

B Version²

Typ

Parameter¹

Min

Max

Min

Max

Unit

Conditions/Comments

DC PERFORMANCE^{3, 4}

AD5305

Resolution

Relative Accuracy

Differential Nonlinearity

8

Bits

LSB

0.15

0.02

1

0.25

0.15

0.02

0.625

0.25

Guaranteed Monotonic by Design

over All Codes

AD5315

Resolution

Relative Accuracy

Differential Nonlinearity

10

0.5

0.05

10

0.5

0.05

Bits

LSB

4

0.5

2.5

0.5

Guaranteed Monotonic by Design

over All Codes

AD5325

Resolution

Relative Accuracy

Differential Nonlinearity

12

2

0.2

12

2

0.2

Bits

LSB

16

1

10

1

Guaranteed Monotonic by Design

over All Codes

Offset Error

Gain Error

Lower Deadband

0.4

0.15

20

3

1

60

0.4

0.15

20

3

1

60

% of FSR

mV

Lower deadband exists only if

offset error is negative.

Offset Error Drift⁵

Gain Error Drift⁵

–12

–5

–60

200

–12

–5

–60

200

ppm of FSR/°C

Power Supply Rejection Ratio⁵

DC Crosstalk⁵

dB

µV

⌬V_DD= 10%

R_L= 2 kΩ to GND or V_DD

DAC REFERENCE INPUTS⁵

V_REFInput Range

V_REFInput Impedance

0.25

37

V_DD

0.25

37

V_DD

V

45

>10

–90

45

>10

–90

kΩ

MΩ

dB

Normal Operation

Power-Down Mode

Frequency = 10 kHz

Reference Feedthrough

OUTPUT CHARACTERISTICS⁵

Minimum Output Voltage⁶

0.001

V

This is a measure of the minimum

and maximum drive capability

of the output ampliﬁer.

Maximum Output Voltage⁶

DC Output Impedance

Short Circuit Current

V_DD– 0.001

0.5

25

16

2.5

V_DD– 0.001

0.5

25

16

2.5

V

Ω

mA

µs

V_DD= 5 V

V_DD= 3 V

Coming out of Power-Down Mode.

V_DD= 5 V

Power-Up Time

5

µs

Coming out of Power-Down Mode.

V_DD= 3 V

LOGIC INPUTS (A0)⁵

Input Current

V_IL, Input Low Voltage

1

µA

V

0.8

0.6

0.5

0.8

0.6

0.5

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

V

V_IH, Input High Voltage

2.4

2.1

2.0

2.4

2.1

2.0

V

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

Pin Capacitance

3

8

3

pF

LOGIC INPUTS (SCL, SDA)⁵

V_IH, Input High Voltage

V_IL, Input Low Voltage

I_IN, Input Leakage Current

V_HYST, Input Hysteresis

C_IN, Input Capacitance

Glitch Rejection

0.7 V_DD

–0.3

V_DD+ 0.3 0.7 V_DD

V_DD+ 0.3

0.3 V_DD

1

V

µA

V

pF

ns

SMBus Compatible at V_DD< 3.6 V

0.3 V_DD

1

–0.3

0.05 V_DD

8

50

Input ﬁltering suppresses noise

spikes of less than 50 ns.

LOGIC OUTPUT (SDA)⁵

V_OL, Output Low Voltage

0.4

0.6

1

0.4

0.6

1

V

µA

pF

I_SINK= 3 mA

I_SINK= 6 mA

Three-State Leakage Current

Three-State Output Capacitance

8

–2–

REV. F

AD5305/AD5315/AD5325

A Version²

Typ

B Version²

Typ

Parameter¹

Min

Max

Min

Max

Unit

Conditions/Comments

POWER REQUIREMENTS

V_DD

2.5

5.5

2.5

5.5

V

I_DD(Normal Mode)⁷

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.6 V

I_DD(Power-Down Mode)

V_DD= 4.5 V to 5.5 V

V_IH= V_DDand V_IL= GND

600

500

900

700

600

500

900

700

µA

V_IH= V_DDand V_IL= GND

I_DD= 4 µA (Max) During 0

Readback on SDA

I_DD= 1.5 µA (Max) During 0

Readback on SDA

0.2

1

0.2

1

µA

V_DD= 2.5 V to 3.6 V

0.08

NOTES

¹See the Terminology section.

²Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.

³DC speciﬁcations tested with the outputs unloaded.

⁴Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).

⁵Guaranteed by design and characterization, not production tested.

⁶For the ampliﬁer output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V _REF= V_DDand offset plus gain error must be

positive.

⁷I_DDspeciﬁcation is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.

Speciﬁcations subject to change without notice.

(V_DD= 2.5 V to 5.5 V; R_L= 2 k⍀ to GND; C_L= 200 pF to GND; all speciﬁcations T_MINto T_MAX, unless

AC CHARACTERISTICS¹^{otherwise noted.)}

A, B Version³

Parameter²

Min

Typ

Max

Unit

Conditions/Comments

_REF= V_DD= 5 V

1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)

1/4 Scale to 3/4 Scale Change (0x100 to 0x300)

1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)

Output Voltage Settling Time

AD5305

AD5315

AD5325

Slew Rate

Major-Code Transition Glitch Energy

Digital Feedthrough

Digital Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

V

6

7

8

0.7

12

1

3

8

9

10

µs

V/µs

nV-s

kHz

dB

1 LSB Change around Major Carry

200

–70

V_REF= 2 V 0.1 V p-p

V_REF= 2.5 V 0.1 V p-p, Frequency = 10 kHz

NOTES

¹Guaranteed by design and characterization, not production tested.

²See the Terminology section.

³Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.

Speciﬁcations subject to change without notice.

REV. F

–3–

AD5305/AD5315/AD5325

TIMING CHARACTERISTICS^{1, 2}(V_DD= 2.5 V to 5.5 V; all speciﬁcations T_MINto T_MAX, unless otherwise noted.)

Limit at T_MIN, T_MAX

(A, B Version)

Parameter

Unit

Conditions/Comments

f_SCL

t₁

t₂

t₃

t₄

400

2.5

0.6

1.3

0.6

100

0.9

0

0.6

1.3

300

0

kHz max

µs min

ns min

µs max

µs min

ns max

ns min

ns max

ns min

ns max

ns min

pF max

SCL Clock Frequency

SCL Cycle Time

t_HIGH, SCL High Time

t_LOW, SCL Low Time

t_HD,STA, Start/Repeated Start Condition Hold Time

t_SU,DAT, Data Setup Time

t_HD,DAT, Data Hold Time

t₅₃

t₆

t_HD,DAT, Data Hold Time

t₇

t₈

t₉

t₁₀

t_SU,STA, Setup Time for Repeated Start

t_SU,STO, Stop Condition Setup Time

t_BUF, Bus Free Time between a STOP and a START Condition

t_R, Rise Time of SCL and SDA when Receiving

t_R, Rise Time of SCL and SDA when Receiving (CMOS Compatible)

t_F, Fall Time of SDA when Transmitting

t_F, Fall Time of SDA when Receiving (CMOS Compatible)

t_F, Fall Time of SCL and SDA when Receiving

t_F, Fall Time of SCL and SDA when Transmitting

Capacitive Load for Each Bus Line

t₁₁

250

0

300

20 + 0.1C_B

400

4

C_B

NOTES

¹See Figure 1.

²Guaranteed by design and characterization; not production tested.

³A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V_IHmin of the SCL signal) in order to bridge the undefined region of

SCL’s falling edge.

⁴C_Bis the total capacitance of one bus line in pF. t_Rand t_Fmeasured between 0.3 V_DDand 0.7 V_DD

Specifications subject to change without notice.

.

SDA

t₉

t₃

t₁₀

t₁₁

t₄

SCL

t₄

t₂

t₆

t₁

t₈

t₅

t₇

START

CONDITION

REPEATED

STOP

CONDITION

START

CONDITION

Figure 1. 2-Wire Serial Interface Timing Diagram

–4–

REV. F

AD5305/AD5315/AD5325

MSOP

Power Dissipation . . . . . . . . . . . . . . . . . . . (T_Jmax – T_A)/␪

ABSOLUTE MAXIMUM RATINGS^{1, 2}

(T_A= 25°C, unless otherwise noted.)

JA

␪

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

SCL, SDA to GND . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

A0 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Reference Input Voltage to GND . . . . . –0.3 V to V_DD+ 0.3 V

V_OUTA–D to GND . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating Temperature Range

Industrial (A, B Version) . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T_Jmax) . . . . . . . . . . . . . . . . . . . 150°C

_JCThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections

of this speciﬁcation is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

²Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

Branding

AD5305ARM

AD5305ARM-REEL7

AD5315ARM

AD5315ARM-REEL7

AD5325ARM

AD5325ARM-REEL7

AD5305BRM

AD5305BRM-REEL

AD5305BRM-REEL7

AD5315BRM

AD5315BRM-REEL

AD5315BRM-REEL7

AD5325BRM

–40°C to +105°C

10-Lead MSOP

RM-10

DEA

DFA

DGA

DEB

DFB

DGB

AD5325BRM-REEL

AD5325BRM-REEL7

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD5305/AD5315/AD5325 feature proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions

are recommended to avoid performance degradation or loss of functionality.

REV. F

–5–

AD5305/AD5315/AD5325

PIN CONFIGURATION

V

1

2

3

4

5

A0

10

9

DD

AD5305/

AD5315/

AD5325

SCL

V

A

B

C

OUT

SDA

GND

8

TOP VIEW

(Not to Scale)

7

6

REFIN

V

D

OUT

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic

Function

1

V_DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be

decoupled to GND.

2

3

4

5

6

7

8

V

_OUTA

_OUTB

Buffered Analog Output Voltage from DAC A. The output ampliﬁer has rail-to-rail operation.

Buffered Analog Output Voltage from DAC B. The output ampliﬁer has rail-to-rail operation.

Buffered Analog Output Voltage from DAC C. The output ampliﬁer has rail-to-rail operation.

V_OUT

REFIN

_OUTD

C

Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V_DD

.

V

Buffered Analog Output Voltage from DAC D. The output ampliﬁer has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

GND

SDA

Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit

input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with an

external pull-up resistor.

9

SCL

A0

Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit

input shift register. Clock rates of up to 400 kbit/s can be accommodated in the 2-wire interface.

10

Address Input. Sets the least signiﬁcant bit of the 7-bit slave address.

TERMINOLOGY

Relative Accuracy

Offset Error Drift

This is a measure of the change in offset error with changes in

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSB, from a straight

line passing through the endpoints of the DAC transfer function.

Typical INL versus code plots can be seen in TPCs 1, 2, and 3.

temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

Differential Nonlinearity

Power Supply Rejection Ratio (PSRR)

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A speciﬁed differential nonlinearity of 1 LSB

maximum ensures monotonicity. This DAC is guaranteed

monotonic by design. Typical DNL versus code plots can be

seen in TPCs 4, 5, and 6.

This indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in V_OUTto

a change in V_DDfor full-scale output of the DAC. It is measured

in dB. V_REFis held at 2 V and V_DDis varied 10%.

DC Crosstalk

This is the dc change in the output level of one DAC at midscale

in response to a full-scale code change (all 0s to all 1s and vice

versa) and output change of another DAC. It is expressed in µV.

Offset Error

This is a measure of the offset error of the DAC and the output

ampliﬁer. It is expressed as a percentage of the full-scale range.

Reference Feedthrough

Gain Error

This is the ratio of the amplitude of the signal at the DAC out-

put to the reference input when the DAC output is not being

updated. It is expressed in dB.

This is a measure of the span error of the DAC. It is the devia-

tion in slope of the actual DAC transfer characteristic from the

ideal expressed as a percentage of the full-scale range.

–6–

REV. F

AD5305/AD5315/AD5325

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse

injected into the analog output when the code in the DAC

register changes state. It is normally speciﬁed as the area of the

glitch in nV-s and is measured when the digital code is changed by

1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00,

or 100 . . . 00 to 011 . . . 11).

GAIN ERROR

PLUS

OFFSET ERROR

OUTPUT

VOLTAGE

IDEAL

ACTUAL

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the

analog output of the DAC from the digital input pins of the

device when the DAC output is not being updated. It is speciﬁed

in nV-s and is measured with a worst-case change on the

digital input pins, e.g., from all 0s to all 1s or vice versa.

NEGATIVE

OFFSET

ERROR

DAC CODE

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC

at midscale in response to a full-scale code change (all 0s to all

1s and vice versa) in the input register of another DAC. It is

expressed in nV-s.

DEAD BAND CODES

AMPLIFIER

FOOTROOM

(1mV)

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC

due to a digital code change and subsequent output change of

another DAC. This includes both digital and analog crosstalk. It

is measured by loading one of the DACs with a full-scale code

change (all 0s to all 1s and vice versa) with the LDAC bit set

low and monitoring the output of another DAC. The energy of

the glitch is expressed in nV-s.

NEGATIVE

OFFSET

ERROR

Figure 2. Transfer Function with Negative Offset

Multiplying Bandwidth

The ampliﬁers within the DAC have a ﬁnite bandwidth. The

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at

which the output amplitude falls to 3 dB below the input.

GAIN ERROR

PLUS

OFFSET ERROR

ACTUAL

OUTPUT

VOLTAGE

Total Harmonic Distortion

This is the difference between an ideal sine wave and its attenuated

version using the DAC. The sine wave is used as the reference for

the DAC and the THD is a measure of the harmonics present

on the DAC output. It is measured in dB.

IDEAL

POSITIVE

OFFSET

DAC CODE

Figure 3. Transfer Function with Positive Offset

REV. F

–7–

AD5305/AD5315/AD5325–Typical Performance Characteristics

12

3

1.0

T

V

= 25؇C

A

T

V

= 25؇C

T

= 25؇C

A

= 5V

DD

= 5V

V

= 5V

DD

8

DD

2

0.5

4

0

1

0

–0.5

–1.0

–1

–2

–3

–4

–8

–12

0

4000

0

1000

2000

3000

50

100

150

CODE

200

250

200

400

CODE

600

800

1000

0

CODE

TPC 3. AD5325 Typical INL Plot

TPC 1. AD5305 Typical INL Plot

TPC 2. AD5315 Typical INL Plot

0.3

1.0

0.6

T

V

= 25؇C

A

T

V

= 25؇C

T

V

= 25؇C

A

= 5V

DD

= 5V

DD

0.4

0.2

0.1

0.5

0

–0.5

–1.0

–0.1

–0.2

–0.3

–0.2

–0.4

–0.6

0

1000

2000

3000

4000

0

50

100

CODE

150

200

250

200

400

600

CODE

800

1000

CODE

TPC 6. AD5325 Typical DNL Plot

TPC 4. AD5305 Typical DNL Plot

TPC 5. AD5315 Typical DNL Plot

0.50

0.5

1.0

V

T

= 5V

= 25؇C

V

= 5V

= 3V

V

= 5V

= 2V

REF

0.4

0.3

0.2

0.1

DD

OFFSET ERROR

A

REF

MAX INL

0.5

0.25

0

MAX INL

MAX DNL

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

MIN DNL

MIN INL

GAIN ERROR

–0.5

–0.25

–0.50

MIN INL

3

–1.0

0

1

2

4

5

؊40

0

40

80

120

؊40

0

40

80

120

ؠ

V

(V)

TEMPERATURE ( C)

REF

TPC 7. AD5305 INL and DNL

Error vs. V_REF

TPC 8. AD5305 INL and DNL

Error vs. Temperature

TPC 9. AD5305 Offset Error and

Gain Error vs. Temperature

–8–

REV. F

AD5305/AD5315/AD5325

0.2

0.1

5

4

600

ؠ

T

V

= 25 C

= 5V

A

ؠ

T

V

= 25 C

A

DD

5V SOURCE

3V SOURCE

= 2V

500

400

300

200

100

0

REF

=2V

REF

GAIN ERROR

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

3

2

1

0

OFFSET ERROR

3V SINK

5V SINK

0

1

2

3

4

5

6

0

1

2

3

4

5

6

ZERO SCALE

FULL SCALE

V

(V)

SINK/SOURCE CURRENT (mA)

CODE

DD

TPC 10. Offset Error and

Gain Error vs. V_DD

TPC 11. V_OUTSource and

Sink Current Capability

TPC 12. Supply Current vs.

DAC Code

600

500

0.5

0.4

0.3

0.2

0.1

0

750

650

ؠ

T

V

= 25؇C

؊40 C

A

ؠ

= 5V

+25 C

DD

ؠ

+105 C

400

300

200

100

0

DECREASING

INCREASING

ؠ

؊40 C

ؠ

؉25 C

550

450

V

= 3V

DD

ؠ

؉105 C

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

2.5

3.0

3.5

4.0

V (V)

DD

4.5

5.0

5.5

0

1.0

2.0

3.0

(V)

4.0

5.0

V

DD

LOGIC

TPC 13. Supply Current vs.

Supply Voltage

TPC 14. Power-Down Current

vs. Supply Voltage

TPC 15. Supply Current vs. Logic

Input Voltage for SDA and SCL

Voltage Increasing and Decreasing

T

V

= 25؇C

T

V

= 25؇C

A

T

V

= 25؇C

A

5µs

= 5V

DD

= 5V

= 2V

REF

= 2V

REF

CH1

CH2

CH1

CH2

V

A

V

A

OUT

DD

OUT

V

A

SCL

OUT

SCL

CH2

CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV

CH1 500mV, CH2 5V, TIME BASE = 1␮s/DIV

CH1 1V, CH2 5V, TIME BASE = 1␮s/DIV

TPC 16. Half-Scale Settling (1/4 to

3/4 Scale Code Change)

TPC 17. Power-On Reset to 0 V

TPC 18. Exiting Power-Down

to Midscale

REV. F

–9–

AD5305/AD5315/AD5325

2.50

2.49

10

0

–10

–20

–30

V

= 3V

V

= 5V

DD

2.48

2.47

–40

–50

–60

300

350

400

450

(␮A)

500

550

600

10

100

1k

10k

100k

1M

10M

1␮s/DIV

I

DD

FREQUENCY (Hz)

TPC 19. I_DDHistogram with

V_DD= 3 V and V_DD= 5 V

TPC 20. AD5325 Major-Code

Transition Glitch Energy

TPC 21. Multiplying Bandwidth

(Small-Signal Frequency Response)

0.02

0.01

V

= 5V

DD

T

= 25؇C

A

0

–0.01

–0.02

0

1

2

3

4

5

6

V

(V)

50ns/DIV

REF

TPC 22. Full-Scale Error vs. V_REF

TPC 23. DAC-to-DAC Crosstalk

FUNCTIONAL DESCRIPTION

where

The AD5305/AD5315/AD5325 are quad resistor-string DACs

fabricated on a CMOS process with resolutions of 8, 10, and 12

bits, respectively. Each contains four output buffer ampliﬁers

and is written to via a 2-wire serial interface. They operate from

single supplies of 2.5 V to 5.5 V, and the output buffer ampliﬁers

provide rail-to-rail output swing with a slew rate of 0.7 V/µs.

The four DACs share a single reference input pin. The devices

have three programmable power-down modes, in which all

DACs may be turned off completely with a high impedance

output, or the outputs may be pulled low by on-chip resistors.

D = decimal equivalent of the binary code, which is loaded to

the DAC register:

0–255 for AD5305 (8 bits)

0–1023 for AD5315 (10 bits)

0–4095 for AD5325 (12 bits)

N = DAC resolution

REFIN

Digital-to-Analog Section

The architecture of one DAC channel consists of a resistor-string

DAC followed by an output buffer ampliﬁer. The voltage at the

REFIN pin provides the reference voltage for the DAC. Figure 4

shows a block diagram of the DAC architecture. Since the input

coding to the DAC is straight binary, the ideal output voltage is

given by

INPUT

REGISTER

DAC

RESISTOR

STRING

V

A

OUT

REGISTER

OUTPUT BUFFER

AMPLIFIER

Figure 4. DAC Channel Architecture

V_REF× D

V_OUT

=

2^N

–10–

REV. F

AD5305/AD5315/AD5325

Resistor String

SERIAL INTERFACE

The resistor string section is shown in Figure 5. It is simply a

string of resistors, each of value R. The digital code loaded to

the DAC register determines at what node on the string the

voltage is tapped off to be fed into the output ampliﬁer. The

voltage is tapped off by closing one of the switches connecting

the string to the ampliﬁer. Because it is a string of resistors, it is

guaranteed monotonic.

The AD5305/AD5315/AD5325 are controlled via an I²C

compatible serial bus. The DACs are connected to this bus as

slave devices (i.e., no clock is generated by the AD5305/AD5315/

AD5325 DACs). This interface is SMBus compatible at V_DD

< 3.6 V.

The AD5305/AD5315/AD5325 have a 7-bit slave address. The

6 MSB are 000110 and the LSB is determined by the state of

the A0 pin. The facility to make hardwired changes to A0 allows

the user to use up to two of these devices on one bus.

R

The 2-wire serial bus protocol operates as follows:

R

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high. The following byte is the

address byte, which consists of the 7-bit slave address fol-

lowed by an R/W bit (this bit determines whether data will

be read from or written to the slave device).

TO OUTPUT

R

AMPLIFIER

R

The slave whose address corresponds to the transmitted

address responds by pulling SDA low during the ninth clock

pulse (this is termed the acknowledge bit). At this stage, all

other devices on the bus remain idle while the selected device

waits for data to be written to or read from its shift register.

Figure 5. Resistor String

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

The transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of SCL.

DAC Reference Inputs

There is a single reference input pin for the four DACs. The

reference input is unbuffered. The user can have a reference

voltage as low as 0.25 V and as high as V_DDsince there is no

restriction due to headroom and footroom of any reference

ampliﬁer.

3. When all data bits have been read or written, a STOP condi-

tion is established. In write mode, the master will pull the

SDA line high during the 10th clock pulse to establish a

STOP condition. In read mode, the master will issue a No

Acknowledge for the ninth clock pulse (i.e., the SDA line

remains high). The master will then bring the SDA line low

before the 10th clock pulse and then high during the 10th

clock pulse to establish a STOP condition.

It is recommended to use a buffered reference in the external

circuit (e.g., REF192). The input impedance is typically 45 kΩ.

Output Ampliﬁer

The output buffer ampliﬁer is capable of generating rail-to-rail

voltages on its output, which gives an output range of 0 V to

V_DDwhen the reference is V_DD. It is capable of driving a load of

2 kΩ to GND or V_DD, in parallel with 500 pF to GND or V_DD

The source and sink capabilities of the output ampliﬁer can be

seen in the plot in TPC 11.

Read/Write Sequence

.

In the case of the AD5305/AD5315/AD5325, all write access

sequences and most read sequences begin with the device address

(with R/W = 0) followed by the pointer byte. This pointer byte

speciﬁes the data format and determines which DAC is being

accessed in the subsequent read/write operation. (See Figure 6.)

In a write operation, the data follows immediately. In a read

operation, the address is resent with R/W = 1 and then the data

is read back. However, it is also possible to perform a read

operation by sending only the address with R/W = 1. The

previously loaded pointer settings are then used for the read-

back operation. See Figure 7 for a graphical explanation of the

interface.

The slew rate is 0.7 V/µs with a half-scale settling time to 0.5 LSB

(at eight bits) of 6 µs.

POWER-ON RESET

The AD5305/AD5315/AD5325 are provided with a power-on

reset function, so that they power up in a deﬁned state. The

power-on state is

• Normal operation

• Output voltage set to 0 V

Both input and DAC registers are ﬁlled with zeros and remain

so until a valid write sequence is made to the device. This is

particularly useful in applications where it is important to know

the state of the DAC outputs while the device is powering up.

MSB

LSB

DACD DACC DACB DACA

0

X

Figure 6. Pointer Byte

REV. F

–11–

AD5305/AD5315/AD5325

Pointer Byte Bits

The following is an explanation of the individual bits that make

up the pointer byte.

CLR

0: All DAC registers and input registers are ﬁlled with

zeros on completion of the write sequence.

1: Normal operation.

X

Don’t care bits.

LDAC 0: All four DAC registers and, therefore, all DAC outputs

simultaneously updated on completion of the write

sequence.

0

Reserved bits, must be set to 0.

DACD

DACC

DACB

DACA

1: The following data bytes are for DAC D.

1: The following data bytes are for DAC C.

1: The following data bytes are for DAC B.

1: The following data bytes are for DAC A.

1: Only addressed input register is updated. There is no

change in the contents of the DAC registers.

Default Readback Condition

All pointer byte bits power up to 0. Therefore, if the user initiates a

readback without writing to the pointer byte ﬁrst, no single DAC

channel has been speciﬁed. In this case, the default readback

bits are all 0, except for the CLR bit, which is a 1.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the

device as two data bytes on the serial data line, SDA, under the

control of the serial clock input, SCL. The timing diagram for

this operation is shown in Figure 1. The two data bytes consist

of four control bits followed by 8, 10, or 12 bits of DAC data,

depending on the device type. The ﬁrst two bits loaded are PD1

and PD0 bits that control the mode of operation of the device.

See the Power-Down Modes section for a complete description.

Bit 13 is CLR, Bit 12 is LDAC, and the remaining bits are left-

justiﬁed DAC data bits, starting with the MSB. See Figure 7.

Multiple-DAC Write Sequence

Because there are individual bits in the pointer byte for each DAC,

it is possible to write the same data and control bits to 2, 3, or 4

DACs simultaneously by setting the relevant bits to 1.

Multiple-DAC Readback Sequence

If the user attempts to read back data from more than one DAC

at a time, the part will read back the default, power-on reset

conditions, i.e., all 0s except for CLR, which is 1.

DATA BYTES (WRITE AND READBACK)

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

8-BIT AD5305

MSB

PD1

8-BIT AD5305

LSB

D4

MSB

D3

LSB

0

PD0

D7

D6

D8

D5

D7

D9

D2

D4

D6

D1

D3

D5

D0

0

CLR LDAC

10-BIT AD5315

D9

LSB

D6

10-BIT AD5315

D2 D1

LSB

0

MSB

PD1

MSB

D5

D0

D2

LDAC

CLR

MSB

LSB

D8

MSB

D7

LSB

D0

12-BIT AD5325

D11

12-BIT AD5325

D4 D3

D1

PD1 PD0

D10

LDAC

Figure 7. Data Formats for Write and Readback

–12–

REV. F

AD5305/AD5315/AD5325

WRITE OPERATION

SDA low. This address byte is followed by the pointer byte,

which is also acknowledged by the DAC. Two bytes of data are

then written to the DAC, as shown in Figure 8. A STOP condi-

tion follows.

When writing to the AD5305/AD5315/AD5325 DACs, the user

must begin with an address byte (R/W = 0), after which the DAC

will acknowledge that it is prepared to receive data by pulling

SCL

0

1

0

A0

R/W

X

LSB

SDA

START

COND

BY

MASTER

ACK

BY

AD53x5

MSB

ACK

BY

AD53x5

ADDRESS BYTE

POINTER BYTE

SCL

MSB

MOST SIGNIFICANT DATA BYTE

LSB

MSB

LEAST SIGNIFICANT DATA BYTE

LSB

SDA

ACK

BY

ACK

BY

STOP

COND

BY

AD53x5

MASTER

Figure 8. Write Sequence

REV. F

–13–

AD5305/AD5315/AD5325

READ OPERATION

However, if the master sends an ACK and continues clocking

SCL (no STOP is sent), the DAC will retransmit the same two

bytes of data on SDA. This allows continuous readback of data

from the selected DAC register.

When reading data back from the AD5305/AD5315/AD5325

DACs, the user begins with an address byte (R/W = 0), after which

the DAC will acknowledge that it is prepared to receive data by

pulling SDA low. This address byte is usually followed by the

pointer byte, which is also acknowledged by the DAC. Following

this, there is a repeated start condition by the master and the

address is resent with R/W = 1. This is acknowledged by the DAC

indicating that it is prepared to transmit data. Two bytes of data

are then read from the DAC, as shown in Figure 9. A STOP

condition follows.

Alternatively, the user may send a START followed by the address

with R/W = 1. In this case, the previously loaded pointer settings

are used and readback of data can commence immediately.

SCL

0

1

0

A0

R/W

X

LSB

SDA

START

COND

BY

MASTER

ACK MSB

BY

ACK

BY

AD53x5

ADDRESS BYTE

POINTER BYTE

AD53x5

SCL

0

SDA

0

1

A0

R/W

MSB

LSB

REPEATED

START

COND

ACK

BY

MASTER

BY

DATA BYTE

ADDRESS BYTE

AD53x5

BY

MASTER

SCL

SDA

LSB

MSB

NO

ACK

BY

STOP

COND

BY

LEAST SIGNIFICANT DATA BYTE

MASTER

NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s.

Figure 9. Readback Sequence

–14–

REV. F

AD5305/AD5315/AD5325

DOUBLE-BUFFERED INTERFACE

input condition for whatever is connected to the output of the

DAC ampliﬁer. There are three different options. The output is

connected internally to GND through either a 1 kΩ resistor or a

100 kΩ resistor, or it is left open-circuited (three-state). Resistor

tolerance = 20%. The output stage is illustrated in Figure 10.

The AD5305/AD5315/AD5325 DACs have double-buffered

interfaces consisting of two banks of registers—input registers and

DAC registers. The input register is directly connected to the input

shift register and the digital code is transferred to the relevant input

register on completion of a valid write sequence. The DAC

register contains the digital code used by the resistor string.

Access to the DAC register is controlled by the LDAC bit. When

the LDAC bit is set high, the DAC register is latched and, there-

fore, the input register may change state without affecting the

contents of the DAC register. However, when the LDAC bit is

set low, the DAC register becomes transparent and the contents

of the input register are transferred to it.

RESISTOR

STRING DAC

AMPLIFIER

V

OUT

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

This is useful if the user requires simultaneous updating of all

DAC outputs. The user may write to three of the input registers

individually and then, by setting the LDAC bit low when writing

to the remaining DAC input register, all outputs will update

simultaneously.

Figure 10. Output Stage during Power-Down

The bias generator, the output ampliﬁers, the resistor string,

and all other associated linear circuitry are shut down when the

power-down mode is activated. However, the contents of the

DAC registers are unchanged when in power-down. The time to

exit power-down is typically 2.5 µs for V_DD= 5 V and 5 µs

when V_DD= 3 V. This is the time from the rising edge of the

eighth SCL pulse to when the output voltage deviates from its

power-down voltage. See TPC 18 for a plot.

These parts contain an extra feature whereby the DAC register

is not updated unless its input register has been updated since

the last time that LDAC was brought low. Normally, when LDAC

is brought low, the DAC registers are ﬁlled with the contents of

the input registers. In the case of the AD5305/AD5315/AD5325,

the part will update the DAC register only if the input register

has been changed since the last time the DAC register was

updated, thereby removing unnecessary digital crosstalk.

APPLICATIONS

Typical Application Circuit

The AD5305/AD5315/AD5325 can be used with a wide range

of reference voltages where the devices offer full, one-quadrant

multiplying capability over a reference range of 0 V to V_DD. More

typically, these devices are used with a ﬁxed, precision reference

voltage. Suitable references for 5 V operation are the AD780 and

REF192 (2.5 V references). For 2.5 V operation, a suitable exter-

nal reference would be the AD589, a 1.23 V band gap reference.

Figure 11 shows a typical setup for the AD5305/AD5315/AD5325

when using an external reference. Note that A0 can be high or low.

POWER-DOWN MODES

The AD5305/AD5315/AD5325 have very low power consump-

tion, dissipating typically 1.5 mW with a 3 V supply and 3 mW

with a 5 V supply. Power consumption can be further reduced

when the DACs are not in use by putting them into one of three

power-down modes, which are selected by Bits 15 and 14 (PD1

and PD0) of the data byte. Table I shows how the state of the

bits corresponds to the mode of operation of the DAC.

Table I. PD1/PD0 Operating Modes

PD1 PD0 Operating Mode

V

= 2.5V TO 5.5V

DD

10␮F

0.1␮F

AD5305/

AD5315/

AD5325

0

1

0

1

0

1

Normal Operation

Power-Down (1 kΩ Load to GND)

Power-Down (100 kΩ Load to GND)

Power-Down (Three-State Output)

V

IN

V

A

B

OUT

V

REFIN

OUT

EXT

REF

OUT

1␮F

When both bits are set to 0, the DAC works normally with its

normal power consumption of 600 µA at 5 V. However, for the

three power-down modes, the supply current falls to 200 nA at

5 V (80 nA at 3 V). Not only does the supply current drop, but

the output stage is also internally switched from the output of

the ampliﬁer to a resistor network of known values. This has an

advantage in that the output impedance of the part is known

while the part is in power-down mode and provides a deﬁned

V

C

D

OUT

AD780/REF192

SCL

SDA

WITH V = 5V

DD

OUT

OR AD589 WITH

V

= 2.5V

DD

A0

GND

SERIAL

INTERFACE

Figure 11. AD5305/AD5315/AD5325 Using External Reference

REV. F

–15–

AD5305/AD5315/AD5325

If an output range of 0 V to V_DDis required, the simplest solution

is to connect the reference input to V_DD. As this supply may not be

very accurate and may be noisy, the AD5305/AD5315/AD5325

may be powered from the reference voltage; for example, using

a 5 V reference such as the REF195. The REF195 will output

a steady supply voltage for the AD5305/AD5315/AD5325. The

typical current required from the REF195 is 600 µA supply cur-

rent and approximately 112 µA into the reference input. This is

with no load on the DAC outputs. When the DAC outputs are

loaded, the REF195 also needs to supply the current to the loads.

The total current required (with a 10 kΩ load on each output) is

Multiple Devices on One Bus

Figure 13 shows two AD5305 devices on the same serial bus.

Each has a different slave address since the state of the A0 pin is

different. This allows each of eight DACs to be written to or

read from independently.

V

A0

DD

AD5305

SCL

PULL-UP

RESISTORS

SDA

MICRO-

CONTROLLER

712 µA + 4 5V / 10 kΩ = 2.70 mA

(

)

SCL

SDA

A0

The load regulation of the REF195 is typically 2 ppm/mA, which

results in an error of 5.4 ppm (27 µV) for the 2.7 mA current

drawn from it. This corresponds to a 0.0014 LSB error at eight

bits and 0.022 LSB error at 12 bits.

AD5305

Figure 13. Multiple AD5305 Devices on One Bus

Bipolar Operation Using the AD5305/AD5315/AD5325

AD5305/AD5315/AD5325 as a Digitally Programmable Window

Detector

The AD5305/AD5315/AD5325 have been designed for single-

supply operation, but a bipolar output range is also possible using

the circuit in Figure 12. This circuit will give an output voltage

range of 5 V. Rail-to-rail operation at the ampliﬁer output is

achievable using an AD820 or an OP295 as the output ampliﬁer.

A digitally programmable upper/lower limit detector using two

of the DACs in the AD5305/AD5315/AD5325 is shown in

Figure 14. The upper and lower limits for the test are loaded to

DACs A and B, which, in turn, set the limits on the CMP04. If

the signal at the V_INinput is not within the programmed window,

an LED will indicate the fail condition. Similarly, DACs C and

D can be used for window detection on a second V_INsignal.

R2 = 10k⍀

+5V

6V TO 12V

R1 = 10k⍀

5V

AD820/

OP295

10␮F

0.1␮F

؎5V

+5V

1k⍀

0.1␮F

10␮F

1k⍀

V

IN

V

A

DD

OUT

AD5305

V

AD1585

–5V

PASS

FAIL

V

IN

V

B

C

V

DD

OUT

REFIN

V

REF

REFIN

GND

1␮F

V

A

B

OUT

1/2

AD5305/

AD5315/

V

D

OUT

1/2

CMP04

A0

PASS/FAIL

*

AD5325

GND SCL SDA

DIN

SDA

SCL

V

OUT

1/6 74HC05

GND

2-WIRE

SERIAL

INTERFACE

*

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 12. Bipolar Operation with the AD5305

Figure 14. Window Detection

The output voltage for any input code can be calculated as

follows:

Coarse and Fine Adjustment Using the AD5305/AD5315/

AD5325

N





















Two of the DACs in the AD5305/AD5315/AD5325 can be

paired together to form a coarse and ﬁne adjustment function,

as shown in Figure 15. DAC A is used to provide the coarse

adjustment while DAC B provides the ﬁne adjustment. Varying

the ratio of R1 and R2 will change the relative effect of the

coarse and ﬁne adjustments. With the resistor values and exter-

nal reference shown, the output ampliﬁer has unity gain for the

DAC A output, so the output range is 0 V to 2.5 V – 1 LSB. For

DAC B, the ampliﬁer has a gain of 7.6 × 10^–3, giving DAC B

a range equal to 19 mV. Similarly, DACs C and D can be paired

together for coarse and ﬁne adjustment.

REFIN × D / 2

×

(

)

V_OUT

=

– REFIN × R2 / R1

(

)



R1 + R2 / R1

(

)





where

D is the decimal equivalent of the code loaded to the DAC.

N is the DAC resolution.

REFIN is the reference voltage input.

with

REFIN= 5 V, R1 = R2 = 10 kΩ:

V_OUT= 10 × D / 2^N– 5 V

The circuit is shown with a 2.5 V reference, but reference volt-

ages up to V_DDmay be used. The op amps indicated will allow

a rail-to-rail output swing.

(

)

–16–

REV. F

AD5305/AD5315/AD5325

V

= 5V

to the device. The AD5305/AD5315/AD5325 should have ample

supply bypassing of 10 µF in parallel with 0.1 µF on the supply

located as close to the package as possible, ideally right up against

the device. The 10 µF capacitors are the tantalum bead type.

The 0.1 µF capacitor should have low effective series resistance

(ESR) and effective series inductance (ESI), like the common

ceramic types that provide a low impedance path to ground at

high frequencies, to handle transient currents due to internal

logic switching.

DD

R3

R4

390⍀

51.2k⍀

10␮F

0.1␮F

5V

V

IN

V

OUT

DD

EXT

REF

V

REFIN

V

A

OUT

AD820/

OP295

OUT

R1

1␮F

1/2

GND

390⍀

AD5305/

AD5315/

AD5325

*

AD780/REF192

WITH V = 5V

V

B

DD

OUT

The power supply lines of the AD5305/AD5315/AD5325 should

use as large a trace as possible to provide low impedance paths

and reduce the effects of glitches on the power supply line. Fast

switching signals such as clocks should be shielded with digital

ground to avoid radiating noise to other parts of the board, and

should never be run near the reference inputs. A ground line

routed between the SDA and SCL lines will help reduce crosstalk

between them (not required on a multilayer board as there will

be a separate ground plane, but separating the lines will help).

R2

51.2k⍀

GND

*

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 15. Coarse/Fine Adjustment

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD5305/AD5315/AD5325 is mounted should be designed so

that the analog and digital sections are separated and conﬁned

to certain areas of the board. If the AD5305/AD5315/AD5325

is in a system where multiple devices require an AGND-to-DGND

connection, the connection should be made at one point only.

The star ground point should be established as close as possible

Avoid crossover of digital and analog signals. Traces on oppo-

site sides of the board should run at right angles to each other.

This reduces the effects of feedthrough through the board. A

microstrip technique is by far the best, but is not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to ground plane while signal traces

are placed on the solder side.

REV. F

–17–

AD5305/AD5315/AD5325

Table II. Overview of All AD53xx Serial Devices

No. of

DACs

Settling

Time (␮s)

Part No.

Resolution

DNL

Interface

Package

Pins

SINGLES

AD5300

AD5310

AD5320

8

10

12

1

0.25

0.5

1.0

SPI^®

SPI

4

6

8

SOT-23, MSOP

6, 8

AD5301

AD5311

AD5321

8

10

12

1

0.25

0.5

1.0

2-Wire

6

7

8

SOT-23, MSOP

6, 8

DUALS

AD5302

AD5312

AD5322

8

10

12

2

0.25

0.5

1.0

SPI

6

7

8

MSOP

8

AD5303

AD5313

AD5323

8

10

12

2

0.25

0.5

1.0

SPI

6

7

8

TSSOP

16

QUADS

AD5304

AD5314

AD5324

8

10

12

4

0.25

0.5

1.0

SPI

6

7

8

MSOP

10

AD5305

AD5315

AD5325

8

10

12

4

0.25

0.5

1.0

2-Wire

6

7

8

MSOP

10

AD5306

AD5316

AD5326

8

10

12

4

0.25

0.5

1.0

2-Wire

6

7

8

TSSOP

16

AD5307

AD5317

AD5327

8

10

12

4

0.25

0.5

1.0

SPI

6

7

8

TSSOP

16

OCTALS

AD5308

AD5318

AD5328

8

10

12

8

0.25

0.5

1.0

SPI

6

7

8

TSSOP

16

Visit www.analog.com/support/standard_linear/selection_guides/AD53xx.html for more information.

Table III. Overview of AD53xx Parallel Devices

V_REFPins Settling Time (␮s) Additional Pin Functions

BUF GAIN HBEN CLR

Part No.

Resolution

DNL

Package Pins

SINGLES

AD5330

AD5331

AD5340

AD5341

8

0.25

0.5

1.0

1

6

7

8

✓

TSSOP

20

24

20

10

12

✓

DUALS

AD5332

AD5333

AD5342

AD5343

8

0.25

0.5

1.0

2

1

6

7

8

✓

TSSOP

20

24

28

20

10

12

✓

QUADS

AD5334

AD5335

AD5336

AD5344

8

0.25

0.5

1.0

2

4

6

7

8

✓

TSSOP

24

28

10

12

–18–

REV. F

AD5305/AD5315/AD5325

OUTLINE DIMENSIONS

10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

3.00 BSC

10

6

4.90 BSC

3.00 BSC

PIN 1

1

5

0.50 BSC

0.95

0.85

0.75

1.10 MAX

0.80

0.60

0.40

8؇

0؇

0.15

0.00

0.27

0.17

SEATING

PLANE

0.23

0.08

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

REV. F

–19–

AD5305/AD5315/AD5325

Revision History

Location

Page

10/04—Data Sheet changed from REV. E to REV. F.

Changes to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Changes to Pointer Byte Bits section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Changes to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8/03—Data Sheet changed from REV. D to REV. E.

Added A Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to TPC 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Added OCTALS SECTION to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4/01—Data Sheet changed from REV. C to REV. D.

Edit to Features section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edit to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to RIGHT/LEFT and DOUBLE sections of Pointer Byte Bits section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Edit to Input Shift Register section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Edit to Multiple-DAC Readback Sequence section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Edits to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Edits to WRITE OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Edits to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Edits to READ OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Edits to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Edits to POWER-DOWN MODES section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Edits to Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C

Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

–20–

REV. F


型号：	AD5315BRM
厂家：	ADI
描述：	2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs 2.5 V至5.5 V ， 500微安， 2线接口四路电压输出， 8位/ 10位/ 12位DAC
文件：	总20页 (文件大小：410K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5315BRM [ADI]

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