AD5316BRU-REEL [ADI]
2.5 V to 5.5 V, 400 μA, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs; 2.5 V至5.5 V ， 400 μA ， 2线接口，四路电压输出， 8位/ 10位/ 12位DAC
| 型号： | AD5316BRU-REEL |
| 厂家： | 
ADI |
| 描述： | 2.5 V to 5.5 V, 400 μA, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs |
| 文件： | 总24页 (文件大小：528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V to 5.5 V, 400 μA, 2-Wire Interface,
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5306/AD5316/AD5326
FEATURES
FUNCTIONAꢀ BꢀOCK DIAGRAM
V
V
REF
A V B
REF
DD
AD5306: 4 buffered, 8-bit DACs in 16-lead TSSOP
A version: 1 ꢀSB INꢀ; B version: 0.625 ꢀSB INꢀ
AD5316: 4 buffered, 10-bit DACs in 16-lead TSSOP
A version: 4 ꢀSB INꢀ; B version: 2.5 ꢀSB INꢀ
AD5326: 4 buffered, 12-bit DACs in 16-lead TSSOP
A version: 16 ꢀSB INꢀ; B version: 10 ꢀSB INꢀ
ꢀow power operation: 400 μA @ 3 V, 500 μA @ 5 V
2-wire (I2C®-compatible) serial interface
2.5 V to 5.5 V power supply
AD5306/AD5316/AD5326
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
BUFFER
BUFFER
BUFFER
V
V
A
B
OUT
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
SCL
SDA
A1
OUT
INTERFACE
LOGIC
A0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
V
C
OUT
OUT
LDAC
INPUT
REGISTER
DAC
REGISTER
Guaranteed monotonic by design over all codes
Power-down to 90 nA @ 3 V, 300 nA @ 5 V (PD pin or bit)
Double-buffered input logic
STRING
DAC D
V
D
POWER-ON
RESET
POWER-DOWN
LOGIC
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on reset to 0 V
V
REF
D V C
REF
PD GND
Figure 1.
Simultaneous update of outputs (ꢀDAC pin)
Software clear facility
Data readback facility
GENERAꢀ DESCRIPTION
The AD5306/AD5316/AD53261 are quad 8-/10-/12-bit buffered
voltage output DACs in 16-lead TSSOP packages that operate
from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/μs. A 2-wire serial interface, which
operates at clock rates up to 400 kHz, is used. This interface is
SMBus-compatible at VDD < 3.6 V. Multiple devices can be
placed on the same bus.
On-chip rail-to-rail output buffer amplifiers
Temperature range −40°C to +105°C
APPꢀICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Each DAC has a separate reference input that can be configured
as buffered or unbuffered. The outputs of all DACs can be
Industrial process control
updated simultaneously using the asynchronous
input.
LDAC
The parts incorporate a power-on reset circuit that ensures the
DAC outputs power up to 0 V and remain there until a valid
write to the device takes place. The software clear function
clears all DACs to 0 V. The parts contain a power-down feature
that reduces the current consumption of the device to
300 nA @ 5 V (90 nA @ 3 V).
All three parts have the same pinout, which allows users to select
the amount of resolution appropriate for their application without
redesigning their circuit board.
1 Protected by U.S. Patent Numbers 5,969,657 and 5,684,481.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD5306/AD5316/AD5326
TABLE OF CONTENTS
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 11
Functional Description.................................................................. 15
Digital-to-Analog Section ......................................................... 15
Resistor String............................................................................. 15
DAC Reference Inputs ............................................................... 15
Output Amplifier........................................................................ 15
Power-On Reset .......................................................................... 16
Serial Interface ............................................................................ 16
Read/Write Sequence................................................................. 16
Pointer Byte Bits ......................................................................... 16
Input Shift Register..................................................................... 16
Default Readback Conditions................................................... 17
Multiple DAC Write Sequence ................................................. 17
Multiple DAC Readback Sequence .......................................... 17
Write Operation.......................................................................... 18
Read Operation........................................................................... 18
Double-Buffered Interface ........................................................ 19
LDAC
Load DAC Input
............................................................. 19
Power-Down Mode.................................................................... 19
Applications..................................................................................... 20
Typical Application Circuit ....................................................... 20
Driving VDD from the Reference Voltage ................................ 20
Bipolar Operation Using the AD5306/AD5316/AD5326..... 20
Multiple Devices on One Bus ................................................... 20
AD5306/AD5316/AD5326 as a Digitally Programmable
Window Detector....................................................................... 21
Coarse and Fine Adjustment Using the
AD5306/AD5316/AD5326 ....................................................... 21
Power Supply Decoupling ............................................................. 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
8/05—Rev. E to Rev. F
8/03—Rev. B to Rev. C
Replaced Figure 22 ......................................................................... 13
Changes to Bipolar Operation
Using the AD5306/AD5316/AD5326 Section........................ 20
Changes to Ordering Guide .......................................................... 24
Added A Version ................................................................Universal
Changes to FEATURES ....................................................................1
Changes to SPECIFICATIONS .......................................................2
Changes to ABSOLUTE MAXIMUM RATINGS.........................5
Edits to ORDERING GUIDE ..........................................................5
Changes to TPC 21......................................................................... 11
Added OCTALS section to Table I............................................... 18
Updated OUTLINE DIMENSIONS ............................................ 19
5/05—Rev. D to Rev. E
Changes to Table 1............................................................................ 3
11/04—Rev. C to Rev. D
Change to Figure 31 ....................................................................... 16
Changes to Pointer Byte Section................................................... 16
Change to Figure 32 ....................................................................... 17
4/01—Rev. A to Rev. B
Edit to Figure 6 ............................................................................... 13
Edits to RIGHT/LEFT section of Pointer Byte Bits section...... 13
Edits to Input Shift Register section ............................................ 13
Edits to Figure 7.............................................................................. 13
Edits to Figure 8.............................................................................. 14
Edits to Figure 9.............................................................................. 14
Edit to Figure 12 ............................................................................. 16
2/01—Rev. 0 to Rev. A
6/00—Revision 0: Initial Version
Rev. F | Page 2 of 24
AD5306/AD5316/AD5326
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Version1
Typ
B Version1
Typ
Parameter2
DC PERFORMANCE3, 4
Min
Max
Min
Max
Unit
Conditions/Comments
AD5306
Resolution
8
8
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
0.15
0.02
1
0.15
0.02
0.625
0.25
0.25
Guaranteed monotonic by
design over all codes.
AD5316
Resolution
10
10
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
0.5
0.05
4
0.5
0.05
2.5
0.5
0.5
Guaranteed monotonic by
design over all codes.
AD5326
Resolution
12
2
12
2
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
16
1
10
1
0.2
0.2
Guaranteed monotonic by
design over all codes.
Offset Error
5
0.3
10
60
5
0.3
10
60
mV
VDD = 4.5 V, gain = 2;
see Figure 4 and Figure 5.
Gain Error
1.25
1.25
% of FSR
mV
VDD = 4.5 V, gain = 2;
see Figure 4 and Figure 5.
Lower Deadband5
60
60
See Figure 4; lower
deadband exists only if
offset error is negative.
Upper Deadband5
10
60
10
60
mV
See Figure 5; upper
deadband exists only if
VREF = VDD and offset plus
gain error is positive.
Offset Error Drift6
Gain Error Drift6
−12
–5
–12
–5
ppm of FSR/°C
ppm of FSR/°C
dB
DC Power Supply
Rejection Ratio6
–60
–60
ΔVDD = 10%.
DC Crosstalk6
200
200
μV
RL = 2 kΩ to GND or VDD.
DAC REFERENCE INPUTS6
VREF Input Range
1
VDD
VDD
1
VDD
VDD
V
Buffered reference mode.
Unbuffered reference mode.
0.25
0.25
V
VREF Input Impedance
>10
180
90
>10
180
90
MΩ
Buffered reference mode
and power-down mode.
148
74
148
74
kΩ
kΩ
Unbuffered reference mode;
0 V to VREF output range.
Unbuffered reference mode;
0 V to 2 VREF output range.
Reference Feedthrough
−90
−75
−90
−75
dB
dB
Frequency = 10 kHz.
Frequency = 10 kHz.
Channel-to-Channel Isolation
OUTPUT CHARACTERISTICS6
Minimum Output Voltage7
0.001
0.001
V
This is a measure of the
minimum and maximum
drive capability of the
output amplifier.
Maximum Output Voltage7
DC Output Impedance
VDD − 0.001
0.5
VDD − 0.001
0.5
V
Ω
Rev. F | Page 3 of 24
AD5306/AD5316/AD5326
A Version1
B Version1
Parameter2
Min
Typ
25
Max
Min
Typ
25
Max
Unit
mA
mA
μs
Conditions/Comments
VDD = 5 V.
Short-Circuit Current
16
16
VDD = 3 V.
Power-Up Time
2.5
2.5
Coming out of power-
down mode; VDD = 5 V.
5
5
μs
Coming out of power-
down mode; VDD = 3 V.
LOGIC INPUTS
(Excluding SCL, SDA)6
Input Current
1
0.8
0.6
0.5
1
0.8
0.6
0.5
μA
V
VIL, Input Low Voltage
VDD = 5 V 10%.
VDD = 3 V 10%.
VDD = 2.5 V.
V
V
VIH, Input High Voltage
1.7
1.7
V
VDD = 2.5 V to 5.5 V;
TTL and 1.8 V CMOS
compatible.
Pin Capacitance
LOGIC INPUTS (SCL, SDA)6
3
8
8
3
8
8
pF
VIH, Input High Voltage
0.7 VDD
−0.3
VDD + 0.3
+0.3 VDD
1
0.7 VDD
−0.3
VDD + 0.3
+0.3 VDD
1
V
V
SMBus compatible at
VDD < 3.6 V.
VIL, Input Low Voltage
SMBus compatible at
VDD < 3.6 V.
IIN, Input Leakage Current
VHYST, Input Hysteresis
CIN, Input Capacitance
Glitch Rejection
μA
V
0.05 VDD
0.05 VDD
See Figure 20.
pF
ns
50
50
Input filtering suppresses
noise spikes of less than
50 ns.
LOGIC OUTPUT (SDA)6
VOL, Output Low Voltage
0.4
0.6
1
0.4
0.6
1
V
ISINK = 3 mA.
ISINK = 6 mA.
V
Three-State Leakage Current
μA
pF
Three-State Output
Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)8
2.5
5.5
2.5
5.5
V
VIH = VDD and VIL = GND;
interface inactive.
VDD = 4.5 V to 5.5 V
500
400
900
500
400
900
μA
All DACs in unbuffered
mode.
Buffered mode, extra
current is typically x mA
per DAC, where
x = 5 μA + VREF/RDAC.
VDD = 2.5 V to 3.6 V
750
750
μA
IDD (Power-Down Mode)
VIH = VDD and VIL = GND;
interface inactive.
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
0.3
1
1
0.3
1
1
μA
μA
IDD = 3 μA (max) during
readback on SDA.
0.09
0.09
IDD = 1.5 μA (max) during
readback on SDA.
1 Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095).
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization; not production tested.
7 For the amplifier output to reach its minimum voltage, the offset error must be negative; for the amplifier output to reach its maximum voltage, VREF = VDD
the offset plus gain error must be positive.
,
8 Interface inactive; all DACs active. DAC outputs unloaded.
Rev. F | Page 4 of 24
AD5306/AD5316/AD5326
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A, B Versions1, 2
Typ
Parameter3
Min
Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5306
AD5316
VREF = VDD = 5 V
6
7
8
8
9
10
μs
μs
μs
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 to 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
AD5326
Slew Rate
0.7
12
0.5
0.5
1
3
200
−70
V/μs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1 LSB change around major carry
VREF = 2 V 0.1 V p-p, unbuffered mode
VREF = 2.5 V 0.1 V p-p, frequency = 10 kHz
1 Guaranteed by design and characterization; not production tested.
2 Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
3 See the Terminology section.
Rev. F | Page 5 of 24
AD5306/AD5316/AD5326
TIMING CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
A, B Versions
ꢀimit at TMIN, TMAX
Parameter2
Unit
Conditions/Comments
SCL cycle time
t1
t2
t3
t4
t5
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1CB
20
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
pF max
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
3
t6
t7
t8
t9
t10
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
LDAC pulse width
t11
4
t12
t13
400
400
SCL rising edge to LDAC rising edge
4
CB
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s
falling edge.
4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD
.
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
SDA
SCL
t9
t10
t11
t4
t3
t4
t2
t1
t6
t5
t7
t8
t12
1
2
t13
LDAC
LDAC
t12
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
2
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. F | Page 6 of 24
AD5306/AD5316/AD5326
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter1
Value
VDD to GND
−0.3 V to +7 V
SCL, SDA to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
A0, A1, LDAC, PD to GND
Reference Input Voltage to GND
VOUTA to VOUTD to GND
Operating Temperature Range
Industrial (A, B Versions)
Storage Temperature Range
Junction Temperature (TJ max)
16-Lead TSSOP
−40°C to +105°C
−65°C to +150°C
150°C
Power Dissipation
θJA Thermal Impedance
Reflow Soldering
(TJ max − TA)/θJA
150.4°C/W
Peak Temperature
220°C
Time at Peak Temperature
10 sec to 40 sec
1 Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 7 of 24
AD5306/AD5316/AD5326
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LDAC
A1
V
A0
DD
V
V
A
B
C
A
B
C
SCL
SDA
GND
OUT
AD5306/
AD5316/
AD5326
TOP VIEW
OUT
OUT
V
(Not to Scale)
V
V
V
V
D
D
REF
REF
REF
OUT
PD
V
REF
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This
allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
LDAC
2
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled
with a10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
3
4
5
6
VOUT
VOUT
VOUT
A
B
C
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Reference Input Pin for DAC A. This pin can be configured as a buffered or an unbuffered input depending on
the state of the BUF bit in the input word to DAC A. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
Reference Input Pin for DAC B. This pin can be configured as a buffered or an unbuffered input depending on
the state of the BUF bit in the input word to DAC B. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
Reference Input Pin for DAC C. This pin can be configured as a buffered or an unbuffered input depending on
the state of the BUF bit in the input word to DAC C. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
Reference Input Pin for DAC D. This pin can be configured as a buffered or an unbuffered input depending on
the state of the BUF bit in the input word to DAC D. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
Active Low Control Input. Acts as a hardware power-down option. All DACs go into power-down mode when
this pin is tied low. The DAC outputs go into a high impedance state. The current consumption of the part
drops to 300 nA @ 5 V (90 nA @ 3 V).
VREF
VREF
VREF
VREF
PD
A
7
B
8
C
9
D
10
11
12
13
VOUT
GND
SDA
D
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift register.
It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor.
14
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift register.
Clock rates of up to 400 kbps can be accommodated in the I2C-compatible interface.
15
16
A0
A1
Address Input. Sets the LSB of the 7-bit slave address.
Address Input. Sets the second LSB of the 7-bit slave address.
Rev. F | Page 8 of 24
AD5306/AD5316/AD5326
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, it is a measure, in LSB, of the maximum deviation
from a straight line passing through the endpoints of the DAC
transfer function. Typical INL vs. code plots are shown in
Figure 6, Figure 7, and Figure 8.
Major-Code Transition Glitch Energy
The energy of the impulse injected into the analog output when
the code in the DAC register changes state. This energy is
normally specified as the area of the glitch in nV-s and is
measured when the digital code is changed by 1 LSB at the
major carry transition (011...11 to 100...00 or 100...00 to
011...11).
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified differential
nonlinearity of 1 LSB maximum ensures monotonicity. This DAC
is guaranteed monotonic by design. Typical DNL vs. code plots
are shown in Figure 9, Figure 10, and Figure 11.
Digital Feedthrough
A measure of the impulse injected into the analog output of a
DAC from the digital input pins of the device when the DAC
output is not being updated. Digital feedthrough is specified in
nV-s and is measured with a worst-case change on the digital
input pins (that is, from all 0s to all 1s, and vice versa).
Offset Error
A measure of the offset error of the DAC and the output ampli-
fier. It can be positive or negative. See Figure 4 and Figure 5.
Offset error is expressed in mV.
Digital Crosstalk
The glitch impulse transferred to the output of one DAC at
midscale in response to a full-scale code change (all 0s to all 1s,
and vice versa) in the input register of another DAC. The
energy of the glitch is expressed in nV-s.
Gain Error
A measure of the span error of the DAC. It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
expressed as a percentage of the full-scale range.
Analog Crosstalk
Offset Error Drift
The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. Analog crosstalk is
measured by loading one of the DACs with a full-scale code
A measure of the change in offset error with changes in
temperature. Offset error drift is expressed in (ppm of full-scale
range)/°C.
change (all 0s to all 1s, and vice versa) while keeping
LDAC
high and then pulsing
the DAC whose digital code has not changed. The energy of the
glitch is expressed in nV-s.
low and monitoring the output of
LDAC
Gain Error Drift
A measure of the change in gain error with changes in
temperature. Gain error drift is expressed in (ppm of full-scale
range)/°C.
DAC-to-DAC Crosstalk
The glitch impulse transferred to the output of one DAC due to
a digital code change and subsequent output change of another
DAC. This includes both digital and analog crosstalk. Crosstalk
is measured by loading one of the DACs with a full-scale code
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. PSRR is
measured in dB. VREF is held at 2 V and VDD is varied 10%.
change (all 0s to all 1s, and vice versa) with
low and then
LDAC
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s, and vice
versa) and output change of another DAC. DC crosstalk is
expressed in μV.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Reference Feedthrough
The ratio of the amplitude of the signal at the DAC output to
the reference input when the DAC output is not being updated,
Total Harmonic Distortion (THD)
that is, when
is high. Reference feedthrough is expressed
LDAC
The difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonics
present on the DAC output. THD is measured in dB.
in dB.
Channel-to-Channel Isolation
The ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of another DAC.
Channel-to-channel isolation is measured in dB.
Rev. F | Page 9 of 24
AD5306/AD5316/AD5326
GAIN ERROR
PLUS
OFFSET ERROR
GAIN ERROR
PLUS
OFFSET ERROR
UPPER
DEADBAND
CODES
OUTPUT
VOLTAGE
IDEAL
OUTPUT
VOLTAGE
ACTUAL
ACTUAL
IDEAL
POSITIVE
OFFSET
ERROR
NEGATIVE
OFFSET
ERROR
DAC CODE
FULL SCALE
DAC CODE
Figure 5. Transfer Function with Positive Offset (VREF = VDD
)
LOWER
DEADBAND
CODES
AMPLIFIER
FOOTROOM
NEGATIVE
OFFSET
ERROR
Figure 4. Transfer Function with Negative Offset
Rev. F | Page 10 of 24
AD5306/AD5316/AD5326
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.3
0.2
T
V
= 25°C
= 5V
T = 25°C
A
A
V
= 5V
DD
DD
0.5
0
0.1
0
–0.1
–0.2
–0.3
–0.5
–1.0
0
50
100
150
200
250
0
50
100
150
200
250
CODE
CODE
Figure 6. AD5306 INL
Figure 9. AD5306 DNL
3
2
0.6
0.4
T
V
= 25°C
DD
T = 25°C
A
DD
A
= 5V
V
= 5V
1
0.2
0
0
–1
–2
–3
–0.2
–0.4
–0.6
0
200
400
600
800
1000
0
200
400
600
800
1000
CODE
CODE
Figure 7. AD5316 INL
Figure 10. AD5316 DNL
12
8
1.0
0.5
T
V
= 25°C
DD
T = 25°C
A
DD
A
= 5V
V
= 5V
4
0
0
–4
–8
–12
–0.5
–1.0
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
CODE
Figure 8. AD5326 INL
Figure 11. AD5326 DNL
Rev. F | Page 11 of 24
AD5306/AD5316/AD5326
0.2
0.1
0.50
T
V
= 25°C
= 2V
T
V
= 25°C
DD
A
A
= 5V
REF
GAIN ERROR
0
0.25
0
MAX DNL
MIN DNL
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
MAX INL
–0.25
–0.50
MIN INL
OFFSET ERROR
0
1
2
3
4
5
6
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
(V)
V
(V)
DD
REF
Figure 15. Offset Error and Gain Error vs. VDD
Figure 12. AD5306 INL and DNL Error vs. VREF
5
4
3
2
1
0
0.5
0.4
5V SOURCE
V
V
= 5V
DD
= 3V
REF
0.3
0.2
MAX INL
MIN DNL
3V SOURCE
0.1
MAX DNL
0
–0.1
–0.2
–0.3
–0.4
–0.5
MIN INL
5V SINK
3V SINK
4
0
1
2
3
5
6
–40
0
40
TEMPERATURE (°C)
80
120
SINK/SOURCE CURRENT (mA)
Figure 16. VOUT vs. Source and Sink Current Capability
Figure 13. AD5306 INL and DNL Error vs. Temperature
300
250
200
150
100
50
1.0
0.5
V
V
= 5V
DD
= 2V
REF
OFFSET ERROR
0
GAIN ERROR
–0.5
T
V
V
= 25°C
A
= 5V
DD
= 2V
REF
0
–1.0
ZERO SCALE
FULL SCALE
–40
0
40
TEMPERATURE (°C)
80
120
CODE
Figure 14. AD5306 Offset Error and Gain Error vs. Temperature
Figure 17. Supply Current vs. DAC Code
Rev. F | Page 12 of 24
AD5306/AD5316/AD5326
600
500
400
300
200
100
0
T
V
V
= 25°C
A
= 5V
–40°C
+25°C
DD
= 5V
REF
CH1
+105°C
V
A
OUT
SCL
CH2
CH1 1V, CH2 5V, TIME BASE = 1μs/DIV
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
Figure 18. Supply Current vs. Supply Voltage
Figure 21. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
0.5
0.4
0.3
0.2
0.1
0
T
V
V
= 25°C
A
= 5V
DD
= 2V
REF
CH1
V
DD
–40°C
+25°C
CH2
V
A
OUT
+105°C
CH1 2V, CH2 200mV, TIME BASE = 200μs/DIV
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
Figure 22. Power-On Reset to 0 V
Figure 19. Power-Down Current vs. Supply Voltage
400
350
300
250
200
150
100
50
T
V
V
= 25°C
A
= 5V
T
= 25°C
DD
A
= 2V
REF
DECREASING
INCREASING
CH1
V
= 5V
V
A
DD
OUT
DECREASING
INCREASING
CH2
PD
V
= 3V
1.0
DD
0
CH1 500mV, CH2 5V, TIME BASE = 1μs/DIV
0
0.5
1.5
2.0
2.5
3.0
(V)
3.5
4.0
4.5
5.0
V
LOGIC
Figure 23. Exiting Power-Down to Midscale
Figure 20. Supply Current vs. Logic Input Voltage
for SDA and SCL Voltage Increasing and Decreasing
Rev. F | Page 13 of 24
AD5306/AD5316/AD5326
0.02
0.01
0
T
V
= 25°C
DD
A
V
= 3V
= 5V
DD
V
= 5V
DD
–0.01
–0.02
350
400
450
500
(μA)
550
600
0
1
2
3
4
5
6
I
DD
V
(V)
REF
Figure 24. IDD Histogram with VDD = 3 V and VDD = 5 V
Figure 27. Full-Scale Error vs. VREF
2.50
2.49
2.48
2.47
50ns/DIV
1μs/DIV
Figure 28. DAC-to-DAC Crosstalk
Figure 25. AD5326 Major Code Transition Glitch Energy
10
0
–10
–20
–30
–40
–50
–60
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 26. Multiplying Bandwidth
(Small-Signal Frequency Response)
Rev. F | Page 14 of 24
AD5306/AD5316/AD5326
FUNCTIONAL DESCRIPTION
The AD5306/AD5316/AD5326 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits, respectively. Each contains four output buffer amplifiers
and is written to via a 2-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/μs. Each
DAC is provided with a separate reference input, which can be
buffered to draw virtually no current from the reference source,
or unbuffered to give a reference input range from 0.25 V to
DAC REFERENCE INPUTS
Each of the four DACs has a reference pin. The reference
inputs are buffered but can also be individually configured as
unbuffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it. However,
if the unbuffered mode is used, the user can have a reference
voltage as low as 0.25 V and as high as VDD, since there is no
restriction due to headroom and footroom of the reference
amplifier.
V
DD. The devices have a power-down mode in which all DACs
can be turned off completely with a high impedance output.
R
R
DIGITAꢀ-TO-ANAꢀOG SECTION
The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer amplifier. The voltage at the
VREF pin provides the reference voltage for the corresponding
DAC. Figure 29 shows a block diagram of the DAC architecture.
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
TO OUTPUT
AMPLIFIER
R
R
R
VREF × D
VOUT
where:
=
2N
Figure 30. Resistor String
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
If there is a buffered reference in the circuit (for example,
REF192), there is no need to use the on-chip buffers of the
AD5306/AD5316/AD5326. In unbuffered mode, the input
impedance is still large at typically 180 kΩ per reference input
for 0 V to VREF mode and 90 kΩ for 0 V to 2 VREF mode.
0 to 255 for AD5306 (8 bits)
0 to 1023 for AD5316 (10 bits)
0 to 4095 for AD5326 (12 bits)
The buffered/unbuffered option is controlled by the BUF bit in
the control byte. The BUF bit setting applies to whichever DAC
is selected in the pointer byte.
N is the DAC resolution.
V
A
REF
REFERENCE
BUFFER
OUTPUT AMPꢀIFIER
BUF
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of VREF, GAIN, offset error, and gain error. If a gain
DAC
REGISTER
INPUT
REGISTER
RESISTOR
STRING
V
A
OUT
of 1 is selected (GAIN = 0), the output range is 0.001 V to VREF.
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 VREF. Because of clamping, however, the maximum output
is limited to VDD – 0.001 V.
OUTPUT BUFFER
AMPLIFIER
Figure 29. Single DAC Channel Architecture
The output amplifier is capable of driving a load of 2 kΩ to
GND or VDD in parallel with 500 pF to GND or VDD. The source
and sink capabilities of the output amplifier can be seen in the
plot in Figure 16.
RESISTOR STRING
The resistor string section is shown in Figure 30. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
The slew rate is 0.7 V/μs with a half-scale settling time to
0.5 LSB (at eight bits) of 6 μs.
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
Rev. F | Page 15 of 24
AD5306/AD5316/AD5326
SDA line remains high. The master then brings the SDA
line low before the 10th clock pulse and then high during
the 10th clock pulse to establish a stop condition.
POWER-ON RESET
The AD5306/AD5316/AD5326 have a power-on reset function
so that they power up in a defined state. The power-on state is
READ/WRITE SEQUENCE
•
•
•
•
Normal operation
For the AD5306/AD5316/AD5326, all write access sequences
and most read sequences begin with the device address (with
Reference inputs unbuffered
0 V to VREF output range
Output voltage set to 0 V
R/ = 0) followed by the pointer byte. This pointer byte speci-
W
fies the data format and determines that DAC is being accessed
in the subsequent read/write operation (see Figure 1). In a write
operation, the data follows immediately. In a read operation, the
Both input and DAC registers are filled with 0s and remain so
until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
address is resent with R/ = 1, and the data is then read back.
However, it is also possible to perform a read operation by
W
sending only the address with R/ = 1. The previously loaded
W
pointer settings are then used for the readback operation.
MSB
LSB
SERIAꢀ INTERFACE
DACD DACC DACB DACA
0
0
X
X
The AD5306/AD5316/AD5326 are controlled via an I2C-
compatible serial bus. These devices are connected to this bus as
slave devices; that is, no clock is generated by the AD5306/
AD5316/AD5326 DACs. This interface is SMBus-compatible
at VDD < 3.6 V.
Figure 31. Pointer Byte
POINTER BYTE BITS
Table 6 describes the individual bits that make up the pointer byte.
Table 6. Pointer Byte Bits
The AD5306/AD5316/AD5326 has a 7-bit slave address. The
five MSBs are 00011, and the two LSBs are determined by the
state of the A0 and A1 pins. The facility to make hardwired
changes to A0 and A1 allows the user to have up to four of these
devices on one bus.
Bit
Description
X
Don’t care bits.
0
Reserved bits. Must be set to 0.
1: The following data bytes are for DAC D.
1: The following data bytes are for DAC C.
1: The following data bytes are for DAC B.
1: The following data bytes are for DAC A.
DACD
DACC
DACB
DACA
The 2-wire serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. Data is loaded into the
device as two data bytes on the serial data line, SDA, under the
control of the serial clock input, SCL. The timing diagram for
this operation is shown in Figure 2. The two data bytes consist
of four control bits followed by 8, 10, or 12 bits of DAC data,
depending on the device type. The first bits loaded are the
followed by an R/ bit. This bit determines whether data
W
is read from or written to the slave device.
The slave whose address corresponds to the transmitted
address responds by pulling SDA low during the ninth
clock pulse (this is termed the acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its shift register.
control bits: GAIN, BUF,
, and
; the remaining bits are
CLR
PD
left-justified DAC data bits, starting with the MSB (see Figure 32).
Table 7. Input Shift Register Control Bits
Bit
Description
2.
3.
Data is transmitted over the serial bus in sequences of
nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must
occur during the low period of SCL and remain stable
during the high period of SCL.
GAIN
0: Output range for that DAC set at 0 V to VREF.
1: Output range for that DAC set at 0 V to 2 VREF
.
BUF
CLR
0: Reference input for that DAC is unbuffered.
1: Reference input for that DAC is buffered.
0: All DAC registers and input registers are filled with
0s on completion of the write sequence.
1: Normal operation.
0: On completion of the write sequence, all four DACs
go into power-down mode. The DAC outputs enter a
high impedance state.
When all data bits have been read from or written to, a
stop condition is established. In write mode, the master
pulls the SDA line high during the 10th clock pulse to
establish a stop condition. In read mode, the master issues
a no acknowledge for the ninth clock pulse; that is, the
PD
1: Normal operation.
Rev. F | Page 16 of 24
AD5306/AD5316/AD5326
DEFAUꢀT READBACK CONDITIONS
MUꢀTIPꢀE DAC READBACK SEQUENCE
All pointer byte bits power up to 0. Therefore, if the user
initiates a readback without first writing to the pointer byte, no
single DAC channel has been specified. In this case, the default
If the user attempts to read back data from more than one DAC
at a time, the part reads back the power-on condition of GAIN,
BUF, and data bits (all 0), and the current state of
and
.
CLR
PD
readback bits are all 0 except for the
bit and the
bit,
CLR
PD
which are 1.
MUꢀTIPꢀE DAC WRITE SEQUENCE
Because there are individual bits in the pointer byte for each DAC,
it is possible to write the same data and control bits to two, three,
or four DACs simultaneously by setting the relevant bits to 1.
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
MSB
8-BIT AD5306
LSB
D4
MSB
D3
8-BIT AD5306
LSB
0
GAIN BUF
D7
D6
D8
D5
D7
D9
D2
D4
D6
D1
D3
D5
D0
0
0
0
CLR
CLR
PD
10-BIT AD5316
D9
LSB
D6
10-BIT AD5316
D2 D1
LSB
0
MSB
MSB
D5
GAIN BUF
D0
D2
0
PD
MSB
12-BIT AD5326
D11
LSB
D8
MSB
D7
12-BIT AD5326
D4 D3
LSB
D0
GAIN BUF CLR
D10
D1
PD
Figure 32. Data Formats for Write and Readback
Rev. F | Page 17 of 24
AD5306/AD5316/AD5326
READ OPERATION
WRITE OPERATION
When reading data back from the AD5306/AD5316/AD5326
When writing to the AD5306/AD5316/AD5326 DACs, the user
DACs, the user begins with an address byte (R/ = 0), after
W
must begin with an address byte (R/ = 0), after which the DAC
W
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. This address byte is usually followed by the
pointer byte, which is also acknowledged by the DAC. Following
this, there is a repeated start condition by the master, and the
acknowledges that it is prepared to receive data by pulling SDA
low. This address byte is followed by the pointer byte, which is
also acknowledged by the DAC. Two bytes of data are then
written to the DAC, as shown in Figure 33. A stop condition
follows.
address is resent with R/ = 1. This is acknowledged by the
W
DAC, indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC, as shown in Figure 34. A
stop condition follows.
SCL
0
0
0
1
1
A1
A0
R/W
X
X
LSB
SDA
START
CONDITION
BY
ACK
BY
AD533x
MSB
ACK
BY
AD53x6
ADDRESS BYTE
POINTER BYTE
MASTER
SCL
SDA
MSB
MOST SIGNIFICANT DATA BYTE
LSB
MSB
LEAST SIGNIFICANT DATA BYTE
LSB
STOP
CONDITION
BY
ACK
BY
ACK
BY
AD53x6
AD53x6
MASTER
Figure 33. Write Sequence
SCL
SDA
LSB
0
0
0
1
1
A1
A0
R/W
X
X
START
CONDITION
BY
MSB
ACK
BY
AD53x6
ACK
BY
AD53x6
ADDRESS BYTE
POINTER BYTE
MASTER
SCL
SDA
0
0
0
1
1
A1
A0
R/W
MSB
LSB
ACK
BY
MASTER
REPEATED
START
CONDITION
BY
ACK
BY
AD53x6
DATA BYTE
ADDRESS BYTE
MASTER
SCL
SDA
MSB
LSB
NO
ACK
BY
STOP
CONDITION
BY
LEAST SIGNIFICANT DATA BYTE
MASTER
MASTER
Figure 34. Readback Sequence
Rev. F | Page 18 of 24
AD5306/AD5316/AD5326
In asynchronous mode, the outputs are not updated at the same
However, if the master sends an ACK and continues clocking
SCL (no stop is sent), the DAC retransmits the same two bytes
of data on SDA. This allows continuous readback of data from
the selected DAC register.
time the input registers are written to. When
goes low,
LDAC
the DAC registers are updated with the contents of the input
registers.
POWER-DOWN MODE
Alternatively, the user can send a start followed by the address
with R/ = 1. In this case, the previously loaded pointer
settings are used and readback of data can start immediately.
W
The AD5306/AD5316/AD5326 have very low power consump-
tion, dissipating typically at 1.2 mW with a 3 V supply and
2.5 mW with a 5 V supply. Power consumption can be reduced
further when the DACs are not in use by putting them into
DOUBꢀE-BUFFERED INTERFACE
The AD5306/AD5316/AD5326 DACs have double-buffered
interfaces consisting of two banks of registers: input registers
and DAC registers. The input registers are connected directly to
the input shift register and the digital code is transferred to the
relevant input register on completion of a valid write sequence.
The DAC registers contain the digital code used by the resistor
strings.
power-down mode, which is selected by setting the
or by setting Bit 12 ( ) of the data-word to 0.
PD
pin low
PD
When the
pin is high and the
bit is set to 1, all DACs work
PD
PD
normally with a typical power consumption of 500 μA at 5 V
(400 μA at 3 V). In power-down mode, however, the supply
current falls to 300 nA at 5 V (90 nA at 3 V) when all DACs are
powered down. Not only does the supply current drop, but each
output stage is internally switched from the output of its ampli-
fier, making it open-circuit. This has the advantage that the
outputs are three-state while the part is in power-down mode
and provides a defined input condition for whatever is connected
to the output of the DAC amplifiers. The output stage is shown
in Figure 35.
Access to the DAC registers is controlled by the
pin.
LDAC
When
is high, the DAC registers are latched and the
LDAC
input registers can change state without affecting the contents of
the DAC registers. When is low, however, the DAC
LDAC
registers become transparent and the contents of the input
registers are transferred to them.
Double-buffering is useful if the user requires simultaneous
updating of all DAC outputs. The user may write to each of the
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
input registers individually and then, by pulsing the
LDAC
input low, all outputs update simultaneously.
POWER-DOWN
CIRCUITRY
These parts contain an extra feature whereby a DAC register is
not updated unless its input register has been updated since the
Figure 35. Output Stage During Power-Down
last time that
was low. Normally, when
is low, the
LDAC
LDAC
The bias generator, output amplifiers, resistor strings, and all
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the registers
are unaffected when in power-down. In fact, it is possible to
load new data into the input registers and DAC registers during
DAC registers are filled with the contents of the input registers.
In the AD5306/AD5316/AD5326, the part updates the DAC
register only if the input register has been changed since the last
time the DAC register was updated, thereby removing
unnecessary digital crosstalk.
power-down. The DAC outputs update as soon as the
pin
PD
ꢀOAD DAC INPUT ꢀDAC
goes high or the
bit is reset to 1. The time to exit power-
PD
down is typically 2.5 μs for VDD = 5 V and 5 μs for VDD = 3 V.
This is the time from the rising edge of the eighth SCL pulse or
transfers data from the input registers to the DAC
registers and, therefore, updates the outputs. The
LDAC
function enables double-buffering of the DAC data, GAIN,
LDAC
from the rising edge of
to when the output voltage deviates
PD
from its power-down voltage (see Figure 23).
and BUF. There are two
modes: synchronous mode and
LDAC
asynchronous mode.
In synchronous mode, the DAC registers are updated after new
data is read in on the rising edge of the eighth SCL pulse.
LDAC
can be tied permanently low or pulsed as in Figure 2.
Rev. F | Page 19 of 24
AD5306/AD5316/AD5326
APPLICATIONS
TYPICAꢀ APPꢀICATION CIRCUIT
BIPOꢀAR OPERATION USING THE
AD5306/AD5316/AD5326
The AD5306/AD5316/AD5326 can be used with a wide range
of reference voltages where the devices offer full one-quadrant
multiplying capability over a reference range of 0 V to VDD
More typically, these devices are used with a fixed precision-
reference voltage. Suitable references for 5 V operation are the
AD780 and REF192 (2.5 V references). For 2.5 V operation, a
suitable external reference is the AD589, a 1.23 V band gap
reference. Figure 36 shows a typical setup for the AD5306/
AD5316/AD5326 when using an external reference. Note that
A0 and A1 can be high or low.
The AD5306/AD5316/AD5326 are designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 37. This circuit gives an output voltage range
of 5 V. Rail-to-rail operation at the amplifier output is
.
achievable using an AD820 or an OP295 as the output amplifier.
R2
10kΩ
+5V
+5V
R1
6V TO 12V
10kΩ
AD820/
OP295
10μF
0.1μF
±5V
V
DD
V
A
V
= 2.5V TO 5.5V
OUT
DD
AD5306/
AD5316/
AD5326
V
IN
–5V
10μF
AD1585
0.1μF
1μF
AD5306/
AD5316/
AD5326
A
V
OUT
V
V
V
V
A
B
C
D
REF
REF
REF
REF
V
V
V
B
C
D
OUT
OUT
OUT
1μF
GND
V
IN
V
V
V
V
V
V
A
B
C
D
OUT
REF
OUT
V
V
V
B
C
D
REF
REF
REF
OUT
OUT
OUT
A1
A0
EXT
REF
GND SCL SDA
AD780/REF192
SCL
SDA
WITH V = 5V
DD
2-WIRE
SERIAL
INTERFACE
OR AD599 WITH
V
= 2.5V
DD
A0
A1
GND
Figure 37. Bipolar Operation with the AD5306/AD5316/AD5326
SERIAL
INTERFACE
The output voltage for any input code can be calculated as follows:
Figure 36. AD5306/AD5316/AD5326
Using a 2.5 V External Reference
N
⎡
⎤
REFIN × D / 2
)
×
(R1 + R2
)
V
= ⎢
⎥ − REFIN ×
(
R2 / R1
)
OUT
DRIVING VDD FROM THE REFERENCE VOꢀTAGE
R1
⎢
⎣
⎥
⎦
If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered, the simplest solution is to
connect the reference inputs to VDD. Because this supply may be
noisy and somewhat inaccurate, the AD5306/AD5316/AD5326
may be powered from the reference voltage, for example, using
a 5 V reference such as the REF195. The REF195 outputs a
steady supply voltage for the AD5306/AD5316/AD5326. The
typical current required from the REF195 is 500 μA supply
current and approximately 112 μA to supply the reference
inputs, if unbuffered. This is with no load on the DAC outputs.
When the DAC outputs are loaded, the REF195 also needs to
supply the current to the loads. The total current required (with
a 10 kΩ load on each output) is
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input.
With REFIN = 5 V, R1 = R2 = 10 kΩ,
V
OUT = (10 × D/2N) − 5 V
MUꢀTIPꢀE DEVICES ON ONE BUS
Figure 38 shows four AD5306 devices on the same serial bus.
Each has a different slave address since the states of the A0 and
A1 pins are different. This allows each of 16 DACs to be written
to or read from independently.
612 μA + (5 V/10 kΩ) = 2.6 mA
V
V
DD
DD
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 5.2 ppm (26 μV) for the 2.6 mA
current drawn from it. This corresponds to a 0.0013 LSB error
at eight bits and a 0.021 LSB error at 12 bits.
A1
A0
A1
A0
AD5306
AD5306
PULL-UP
RESISTORS
MASTER
SDA
SCL
SDA
SCL
V
DD
SCL
SCL
SDA
SDA
A1
A0
A1
A0
AD5306
AD5306
Figure 38. Multiple AD5306 Devices on One Bus
Rev. F | Page 20 of 24
AD5306/AD5316/AD5326
AD5306/AD5316/AD5326 AS A DIGITAꢀꢀY
PROGRAMMABꢀE WINDOW DETECTOR
COARSE AND FINE ADJUSTMENT USING THE
AD5306/AD5316/AD5326
A digitally programmable upper/lower limit detector using two
of the DACs in the AD5306/AD5316/AD5326 is shown in
Figure 39. The upper and lower limits for the test are loaded to
DACs A and B, which, in turn, set the limits on the CMP04. If
the signal at the VIN input is not within the programmed
window, an LED indicates the fail condition. Similarly, DAC C
and DAC D can be used for window detection on a second
Two of the DACs in the AD5306/AD5316/AD5326 can be
paired together to form a coarse and fine adjustment function,
as shown in Figure 40. DAC A is used to provide the coarse
adjustment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 changes the relative effect of the coarse
and fine adjustments. With the resistor values and external
reference shown, the output amplifier has unity gain for the
DAC A output; therefore, the output range is 0 V to 2.5 V − 1
LSB. For DAC B, the amplifier has a gain of 7.6 × 10−3, giving
DAC B a range of 19 mV. Similarly, DAC C and DAC D can be
paired together for coarse and fine adjustment.
VIN signal.
5V
1kΩ
0.1μF
10μF
1kΩ
V
IN
PASS
FAIL
V
DD
V
V
V
A
B
REF
The circuit in Figure 40 is shown with a 2.5 V reference, but
reference voltages up to VDD may be used. The op amps
indicated allow a rail-to-rail output swing.
REF
A
B
V
OUT
REF
1/2
AD5306/
AD5316/
AD53261
1/2
CMP04
PASS/FAIL
1/6 74HC05
R3
51.2kΩ
R4
390Ω
DIN
SDA
SCL
V
= 5V
DD
SCL
V
OUT
GND
5V
10μF
0.1μF
1
ADDITIONAL PINS OMITTED FOR CLARITY
V
V
OUT
DD
V
V
A
AD820/
OP295
V
EXT
REF
OUT
IN
R1
390Ω
Figure 39. Window Detection
V
V
A
VOUT
REF
1μF
GND
B
REF
B
OUT
R2
51.2kΩ
1/2
AD5306/
AD5316/
AD5326
AD780/REF192
WITH V = 5V
DD
GND
Figure 40. Coarse/Fine Adjustment
Rev. F | Page 21 of 24
AD5306/AD5316/AD5326
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5306/AD5316/AD5326 is mounted should be designed so
the analog and digital sections are separated and confined to
certain areas of the board.
The power supply lines of the AD5306/AD5316/AD5326 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line.
Components with fast-switching signals, such as clocks, should
be shielded with digital ground to avoid radiating noise to other
parts of the board, and they should never be run near the
reference inputs. A ground line routed between the SDA and
SCL lines helps to reduce crosstalk between them. Although a
ground line is not required on a multilayer board because there is
a separate ground plane, separating the lines helps.
If the AD5306/AD5316/AD5326 is in a system where multiple
devices require an AGND-to-DGND connection, the connection
should be made at one point only. The star ground point should
be established as close as possible to the device. The AD5306/
AD5316/AD5326 should have ample supply bypassing of 10 μF
in parallel with 0.1 μF on the supply located as close to the
package as possible, ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. The 0.1 μF capacitor should
have low effective series resistance (ESR) and low effective
series inductance (ESI), like the common ceramic types that
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is the best method, but its use is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground plane while
signal traces are placed on the solder side.
Table 8. Overview of AD53xx Serial Devices1
Part No.
SINGꢀES
AD5300
AD5310
AD5320
AD5301
AD5311
AD5321
DUAꢀS
AD5302
AD5312
AD5322
AD5303
AD5313
AD5323
QUADS
AD5304
AD5314
AD5324
AD5305
AD5315
AD5325
AD5306
AD5316
AD5326
AD5307
AD5317
AD5327
OCTAꢀS
AD5308
AD5318
AD5328
Resolution
No. of DACs
DNꢀ
0.25
0.5
1.0
0.25
0.5
1.0
Interface
Settling Time (μs) Package
Pins
8
1
1
1
1
1
1
SPI
SPI
SPI
2-wire
2-wire
2-wire
4
6
8
6
7
8
SOT-23, MSOP
6, 8
6, 8
6, 8
6, 8
6, 8
6, 8
10
12
8
10
12
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
8
2
2
2
2
2
2
0.25
0.5
1.0
0.25
0.5
1.0
SPI
SPI
SPI
SPI
SPI
SPI
6
7
8
6
7
8
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
8
8
8
16
16
16
10
12
8
10
12
8
4
4
4
4
4
4
4
4
4
4
4
4
0.25
0.5
1.0
0.25
0.5
1.0
0.25
0.5
1.0
0.25
0.5
1.0
SPI
SPI
SPI
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
SPI
6
7
8
6
7
8
6
7
8
6
7
8
MSOP
MSOP
MSOP
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
10
10
10
10
10
10
16
16
16
16
16
16
10
12
8
10
12
8
10
12
8
10
12
SPI
SPI
8
10
12
8
8
8
0.25
0.5
1.0
SPI
SPI
SPI
6
7
8
TSSOP
TSSOP
TSSOP
16
16
16
1 Visit www.analog.com/support/standard_linear/selection_guides/AD53xx.html for more information.
Rev. F | Page 22 of 24
AD5306/AD5316/AD5326
Table 9. Overview of AD53xx Parallel Devices
Part No.
Resolution
DNꢀ
VREF Pins
Settling Time (μs)
Additional Pin Functions
Package
Pins
SINGꢀES
BUF
GAIN
HBEN
CꢀR
AD5330
AD5331
AD5340
AD5341
DUAꢀS
AD5332
AD5333
AD5342
AD5343
QUADS
AD5334
AD5335
AD5336
AD5344
8
0.25
1
1
1
1
6
7
8
8
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
TSSOP
TSSOP
TSSOP
TSSOP
20
20
24
20
10
12
12
0.5
1.0
1.0
Yes
Yes
Yes
8
0.25
0.5
1.0
2
2
2
1
6
7
8
8
Yes
Yes
Yes
Yes
TSSOP
TSSOP
TSSOP
TSSOP
20
24
28
20
10
12
12
Yes
Yes
Yes
Yes
1.0
Yes
Yes
8
0.25
0.5
0.5
2
2
4
4
6
7
7
8
Yes
Yes
Yes
Yes
Yes
TSSOP
TSSOP
TSSOP
TSSOP
24
24
28
28
10
10
12
1.0
Rev. F | Page 23 of 24
AD5306/AD5316/AD5326
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5306ARU
AD5306ARU-REEL7
AD5306ARUZ1
AD5306ARUZ-REEL71
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
AD5306BRU
AD5306BRU-REEL
AD5306BRU-REEL7
AD5306BRUZ1
AD5306BRUZ-REEL1
AD5306BRUZ-REEL71
AD5316ARU
AD5316ARU-REEL7
AD5316ARUZ1
AD5316BRU
AD5316BRU-REEL
AD5316BRU-REEL7
AD5316BRUZ1
AD5316BRUZ-REEL1
AD5316BRUZ-REEL71
AD5326ARU
AD5326ARU-REEL7
AD5326ARUZ1
AD5326BRU
AD5326BRU-REEL
AD5326BRU-REEL7
AD5326BRUZ1
AD5326BRUZ-REEL1
AD5326BRUZ-REEL71
1 Z = Pb-free part.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02066–0–8/05(F)
Rev. F | Page 24 of 24
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