AD5317RBCPZ-RL7 [ADI]
Quad, 10-Bit nanoDAC® with 2 ppm/°C Reference, SPI Interface;
| 型号： | AD5317RBCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Quad, 10-Bit nanoDAC® with 2 ppm/°C Reference, SPI Interface 转换器 |
| 文件： | 总28页 (文件大小：781K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, 10-Bit nanoDAC®
with 2 ppm/°C Reference, SPI Interface
Data Sheet
AD5317R
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
V
GND
V
REF
DD
2.5V
REFERENCE
AD5317R
Total unadjusted error (TUE): 0.1% of FSR maximum
Offset error: 1.5 mV maximum
V
LOGIC
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
V
V
V
V
A
B
C
D
OUT
OUT
OUT
OUT
Gain error: 0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
SCLK
SYNC
SDIN
SDO
BUFFER
BUFFER
BUFFER
BUFFER
STRING
DAC B
INPUT
DAC
REGISTER
REGISTER
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
STRING
DAC D
INPUT
REGISTER
DAC
REGISTER
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
POWER-ON
RESET
GAIN
×1/×2
POWER-
DOWN
LOGIC
2.7 V to 5.5 V power supply
LDAC RESET
RSTSEL
GAIN
−40°C to +105°C temperature range
Figure 1.
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Industrial automation
Data acquisition systems
Table 1. Related Devices
GENERAL DESCRIPTION
Interface
Reference
Internal
External
Internal
External
12-Bit
10-Bit
The AD5317R, a member of the nanoDAC® family, is a low
power, quad, 10-bit buffered voltage output DAC. The device
includes a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The device operates from a single
2.7 V to 5.5 V supply, is guaranteed monotonic by design, and
exhibits less than 0.1% FSR gain error and 1.5 mV offset error
performance. The device is available in a 3 mm × 3 mm LFCSP
and a TSSOP package.
SPI
AD5684R
AD5684
AD5694R
AD5694
AD53171
AD5316R
AD5316
I2C
1 The AD5317 and AD5317R are not pin-to-pin or software compatible.
PRODUCT HIGHLIGHTS
1. Precision DC Performance.
Total unadjusted error: 0.1% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.1% of FSR maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
The AD5317R also incorporates a power-on reset circuit and a
RSTSEL pin that ensures that the DAC outputs power up to
zero scale or midscale and remain at that level until a valid write
takes place. Each part contains a per-channel power-down
feature that reduces the current consumption of the device to
4 µA at 3 V while in power-down mode.
The AD5317R employs a versatile SPI interface that operates at
clock rates up to 50 MHz and contains a VLOGIC pin intended for
1.8 V/3 V/5 V logic.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
AD5317R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Write and Update Commands.................................................. 21
Daisy-Chain Operation ............................................................. 21
Readback Operation .................................................................. 22
Power-Down Operation............................................................ 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Daisy-Chain and Readback Timing Characteristics................ 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
Digital-to-Analog Converter .................................................... 19
Transfer Function ....................................................................... 19
DAC Architecture....................................................................... 19
Serial Interface ............................................................................ 20
Standalone Operation................................................................ 21
LDAC
Load DAC (Hardware
Pin)........................................... 23
Mask Register ................................................................. 23
Hardware Reset ( ) .......................................................... 24
LDAC
RESET
Reset Select Pin (RSTSEL) ........................................................ 24
Internal Reference Setup ........................................................... 25
Solder Heat Reflow..................................................................... 25
Long-Term Temperature Drift ................................................. 25
Thermal Hysteresis .................................................................... 25
Applications Information .............................................................. 26
Microprocessor Interfacing....................................................... 26
AD5317R to ADSP-BF531 Interface ....................................... 26
AD5317R to SPORT Interface.................................................. 26
Layout Guidelines....................................................................... 26
Galvanically Isolated Interface ................................................. 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet
AD5317R
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE1
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error
10
Bits
LSB
LSB
mV
mV
0.12
0.5
0.5
1.5
1.5
0.1
0.1
0.1
0.2
Guaranteed monotonic by design
All 0s loaded to DAC register
0.4
+0.1
+0.01
0.02
0.01
% of FSR All 1s loaded to DAC register
% of FSR
% of FSR External reference; gain = 2; TSSOP
% of FSR Internal reference; gain = 1; TSSOP
µV/°C
ppm
mV/V
µV
µV/mA
µV
Offset Error Drift2
1
1
0.15
2
3
2
Gain Temperature Coefficient2
DC Power Supply Rejection Ratio2
DC Crosstalk2
Of FSR/°C
DAC code = midscale; VDD = 5 V 10%
Due to single channel, full-scale output change
Due to load current change
Due to power-down (per channel)
OUTPUT CHARACTERISTICS2
Output Voltage Range
0
0
VREF
2 × VREF
V
V
nF
Gain = 1
Gain = 2, see Figure 29
RL = ∞
Capacitive Load Stability
2
10
nF
kΩ
µV/mA
RL = 1 kΩ
Resistive Load3
Load Regulation
1
80
80
5 V 10%, DAC code = midscale; −30 mA ≤ IOUT
+30 mA
3 V 10%, DAC code = midscale; −20 mA ≤ IOUT
+20 mA
≤
≤
µV/mA
Short-Circuit Current4
Load Impedance at Rails5
Power-Up Time
40
25
2.5
mA
Ω
µs
See Figure 29
Coming out of power-down mode; VDD = 5 V
REFERENCE OUTPUT
Output Voltage6
2.4975
2.5025
5
V
At ambient
See the Terminology section
Reference TC7, 8
2
0.04
12
240
20
40
ppm/°C
Ω
Output Impedance2
Output Voltage Noise2
Output Voltage Noise Density2
Load Regulation, Sourcing2
Load Regulation, Sinking2
Output Current Load Capability2
Line Regulation2
µV p-p
nV/√Hz
µV/mA
µV/mA
mA
0.1 Hz to 10 Hz
At ambient; f = 10 kHz, CL = 10 nF
At ambient
At ambient
VDD ≥ 3 V
±5
100
12
125
25
µV/V
ppm
ppm
ppm
At ambient
After 1000 hours at 125°C
First cycle
Long-Term Stability/Drift2
Thermal Hysteresis2
Additional cycles
Rev. 0 | Page 3 of 28
AD5317R
Data Sheet
Parameter
LOGIC INPUTS2
Min
Typ
Max
Unit
Test Conditions/Comments
Input Current
2
µA
V
V
Per pin
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
LOGIC OUTPUTS (SDO)2
Output Low Voltage, VOL
Output High Voltage, VOH
0.3 × VLOGIC
0.7 × VLOGIC
2
4
pF
0.4
V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
VLOGIC − 0.4
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
1.8
5.5
3
5.5
5.5
V
µA
V
2.7
VREF + 1.5
Gain = 1
Gain = 2
V
IDD
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off
Internal reference on, at full scale
−40°C to +85°C
Normal Mode9
0.59
1.1
1
0.7
1.3
4
mA
mA
µA
All Power-Down Modes10
6
µA
−40°C to +105°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 4 to 1020.
2 Guaranteed by design and characterization; not production tested.
3 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 29).
6 Initial accuracy presolder reflow is 750 µV; output voltage includes the effects of preconditioning drift. See the Terminology section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.
8 Reference temperature coefficient calculated as per the box method. See the Terminology section for more information.
9 Interface inactive. All DACs active. DAC outputs unloaded.
10 All DACs powered down.
Rev. 0 | Page 4 of 28
Data Sheet
AD5317R
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless
otherwise noted.1
Table 3.
Parameter2
Min
Typ
5
Max
Unit
Test Conditions/Comments3
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
7
µs
V/µs
¼ to ¾ scale settling to 1 LSB
0.8
0.5
0.13
0.1
0.2
0.3
−80
300
6
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
dB
1 LSB change around major carry
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion4
Output Noise Spectral Density
Output Noise
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz, gain = 2
0.1 Hz to 10 Hz
nV/√Hz
µV p-p
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
4 Digitally generated sine wave @ 1 kHz.
Rev. 0 | Page 5 of 28
AD5317R
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
DD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
V
Table 4.
1.8 V ≤ VLOGIC < 2.7 V 2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter1
Symbol Min
Max
Min
20
10
10
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
t1
t2
t3
t4
33
16
16
15
8
t5
Data Hold Time
t6
t7
8
5
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
15
20
16
25
30
20
30
30
4.5
10
20
10
15
20
20
30
30
4.5
t8
t9
t10
t11
t12
t13
t14
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
Power-Up Time2
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
2 Time to exit power-down to normal mode of AD5317R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
t9
t1
SCLK
t2
t8
t7
t3
t4
SYNC
SDIN
t6
t5
DB23
DB0
t12
t10
1
LDAC
t11
2
LDAC
t13
RESET
t14
V
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. 0 | Page 6 of 28
Data Sheet
AD5317R
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 5.
1.8 V ≤ VLOGIC < 2.7 V
Max
2.7 V ≤ VLOGIC ≤ 5.5 V
Max
Parameter1
Symbol
Min
66
33
33
33
5
Min
40
20
20
20
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Data Hold Time
5
5
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
Minimum SYNC High Time
SDO Data Valid from SCLK Rising Edge
SCLK Falling Edge to SYNC Rising Edge
15
60
60
10
30
30
36
25
15
15
10
10
SYNC Rising Edge to SCLK Rising Edge
t12
ns
1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
200µA
I
OL
TO OUTPUT
PIN
V
(MIN)
OH
C
L
20pF
200µA
I
OH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
24
48
t11
t8
t12
t4
SYNC
SDIN
t6
t5
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t10
DB23
DB0
SDO
UNDEFINED
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 7 of 28
AD5317R
Data Sheet
t1
SCLK
24
24
1
1
t3
t7
t9
t4
t2
t8
SYNC
SDIN
t6
t5
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
t10
DB23
DB0
DB23
DB0
SDO
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. Readback Timing Diagram
Rev. 0 | Page 8 of 28
Data Sheet
AD5317R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VLOGIC to GND
−0.3 V to +7 V
VOUT to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +105°C
−65°C to +150°C
125°C
ESD CAUTION
16-Lead TSSOP, θJA Thermal
112.6°C/W
Impedance, 0 Airflow (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
Reflow Soldering Peak
70°C/W
260°C
Temperature, Pb Free (J-STD-020)
ESD
HBM1
4 kV
FICDM
1.5 kV
1 Human body model (HBM) classification.
Rev. 0 | Page 9 of 28
AD5317R
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5317R
V
V
A 1
12 SDIN
11 SYNC
10 SCLK
OUT
GND 2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
RSTSEL
RESET
SDIN
REF
V
3
DD
V
V
B
A
OUT
OUT
9
V
LOGIC
C 4
OUT
AD5317R
GND
SYNC
SCLK
TOP VIEW
(Not to Scale)
V
DD
V
V
C
D
V
LOGIC
OUT
OUT
TOP VIEW
(Not to Scale)
GAIN
LDAC
SDO
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 6. 16-Lead LFCSP Pin Configuration
Figure 7. 16-Lead TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic Description
1
2
3
3
4
5
VOUT
GND
VDD
A
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. This part can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4
5
6
6
7
8
VOUT
VOUT
SDO
C
D
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Serial Data Output. Can be used to daisy-chain a number of AD5317R devices together or can be
used for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling
edge of the clock.
7
8
9
LDAC
GAIN
LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows
any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs
to be simultaneously updated. This pin can also be tied permanently low.
10
Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to VREF. When this
pin is tied to VDD, all four DAC outputs have a span of 0 V to 2 × VREF
.
9
10
11
12
VLOGIC
SCLK
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
11
12
13
13
14
15
SYNC
SDIN
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC
pulses are ignored. When RESET is activated, the input register and the DAC register are updated with
zero scale or midscale, depending on the state of the RSTSEL pin.
RESET
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
VDD powers up all four DACs to midscale.
Reference Voltage. The AD5317R has a common reference pin. When using the internal reference,
this is the reference output pin. When using an external reference, this is the reference input pin.
The default for this pin is as a reference output.
14
15
16
1
RSTSEL
VREF
16
17
2
N/A
VOUT
EPAD
B
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
Rev. 0 | Page 10 of 28
Data Sheet
AD5317R
TYPICAL PERFORMANCE CHARACTERISTICS
2.5020
1600
1400
1200
1000
800
600
400
200
0
V
= 5V
= 25°C
DD
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
V
= 5V
DD
T
A
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
10
100
1k
10k
100k
1M
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 11. Internal Reference Noise Spectral Density vs. Frequency
Figure 8. Internal Reference Voltage vs. Temperature (Grade B)
90
V
= 5V
DD
V
= 5V
= 25°C
DD
80
70
60
50
40
30
20
10
0
T
A
1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TEMPERATURE DRIFT (ppm/°C)
CH1 2µV
M1.0s
Figure 9. Reference Output Temperature Drift Histogram
Figure 12. Internal Reference Noise, 0.1 Hz to 10 Hz
2.5000
2.4999
2.4998
2.4997
2.4996
2.4995
2.4994
2.4993
V
= 5.5V
0 HOUR
V
= 5V
DD
DD
168 HOURS
500 HOURS
1000 HOURS
60
50
40
30
20
10
0
T = 25°C
A
–0.005
–0.003
–0.001
I
0.001
(A)
0.003
0.005
2.498
2.499
2.500
(V)
2.501
2.502
V
LOAD
REF
Figure 13. Internal Reference Voltage vs. Load Current
Figure 10. Reference Long-Term Stability/Drift
Rev. 0 | Page 11 of 28
AD5317R
Data Sheet
2.5002
2.5000
2.4998
2.4996
2.4994
2.4992
10
8
T
= 25°C
A
D1
D3
6
4
2
INL
0
DNL
–2
–4
–6
–8
–10
V
= 5V
DD
= 25°C
D2
(V)
T
A
INTERNAL REFERENCE = 2.5V
2.4990
2.5
3.0
3.5
4.0
V
4.5
5.0
5.5
–40 10
60
110
TEMPERATURE (°C)
DD
Figure 14. Internal Reference Voltage vs. Supply Voltage
Figure 17. INL Error and DNL Error vs. Temperature
10
8
0.5
6
0.3
0.1
4
2
INL
0
DNL
–2
–4
–6
–8
–10
–0.1
–0.3
–0.5
V
= 5V
DD
= 25°C
T
A
INTERNAL REFERENCE = 2.5V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
156
312
468
CODE
625
781
938
V
(V)
REF
Figure 15. INL
Figure 18. INL Error and DNL Error vs. VREF
0.5
0.3
10
8
6
4
2
0.1
INL
0
DNL
–2
–4
–6
–8
–10
–0.1
–0.3
–0.5
V
= 5V
DD
= 25°C
T
A
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
4.2
4.7
5.2
0
156
312
468
CODE
625
781
938
Figure 19. INL Error and DNL Error vs. Supply Voltage
Figure 16. DNL
Rev. 0 | Page 12 of 28
Data Sheet
AD5317R
1.5
1.0
0.10
0.08
0.06
0.04
0.02
0
0.5
ZERO-CODE ERROR
FULL-SCALE ERROR
GAIN ERROR
0
OFFSET ERROR
–0.02
–0.04
–0.06
–0.5
–1.0
–1.5
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
DD
DD
–0.08
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
–20 20 40
TEMPERATURE (°C)
–0.10
–40
0
60
80
100
120
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
Figure 20. Gain Error and Full-Scale Error vs. Temperature
Figure 23. Zero-Code Error and Offset Error vs. Supply Voltage
0.10
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
DD
DD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
A
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
ZERO-CODE ERROR
OFFSET ERROR
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. Zero-Code Error and Offset Error vs. Temperature
Figure 24. TUE vs. Temperature
0.10
0.08
0.06
0.04
0.02
0
0.10
0.08
0.06
0.04
0.02
0
GAIN ERROR
FULL-SCALE ERROR
–0.02
–0.04
–0.06
–0.08
–0.10
–0.02
–0.04
–0.06
–0.08
–0.10
V
= 5V
= 25°C
V
= 5V
DD
DD
T
T = 25°C
A
A
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7
SUPPLY VOLTAGE (V)
4.2
4.7
5.2
4.2
4.7
5.2
Figure 22. Gain Error and Full-Scale Error vs. Supply Voltage
Figure 25. TUE vs. Supply Voltage, Gain = 1
Rev. 0 | Page 13 of 28
AD5317R
Data Sheet
1.0
0.8
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
0.6
0.4
SINKING 2.7V
0.2
SINKING 5V
0
–0.2
–0.4
–0.6
–0.8
–1.0
SOURCING 5V
SOURCING 2.7V
15
V
= 5V
= 25°C
DD
–0.09
–0.10
T
A
INTERNAL REFERENCE = 2.5V
0
156
312
468
CODE
624
780
936 1023
0
5
10
20
25
30
LOAD CURRENT (mA)
Figure 26. TUE vs. Code
Figure 29. Headroom/Footroom vs. Load Current
7
6
V
T
= 5V
= 25°C
V
= 5V
= 25°C
DD
DD
25
T
A
A
EXTERNAL
REFERENCE = 2.5V
GAIN = 2
INTERNAL
REFERENCE = 2.5V
0xFFFF
5
20
15
10
5
4
0xC000
0x8000
0x4000
0x0000
3
2
1
0
–1
0
–2
–0.06
540
560
580
600
620
640
–0.04
–0.02
0
0.02
0.04
0.06
I
(mA)
DD
LOAD CURRENT (A)
Figure 27. IDD Histogram with External Reference, 5 V
Figure 30. Source and Sink Capability at 5 V
5
4
V
T
= 5V
V
T
= 3V
= 25°C
DD
= 25°C
DD
30
25
20
15
10
5
A
A
INTERNAL
REFERENCE = 2.5V
EXTERNAL REFERENCE = 2.5V
GAIN = 1
0xFFFF
3
0xC000
0x8000
2
1
0x4000
0x0000
0
–1
–2
0
1000
1020
1040
I
1060
1080
1100
1120
1140
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
FULL SCALE (mA)
DD
LOAD CURRENT (A)
Figure 28. IDD Histogram with Internal Reference, VREF = 2.5 V, Gain = 2
Figure 31. Source and Sink Capability at 3 V
Rev. 0 | Page 14 of 28
Data Sheet
AD5317R
3
2
1
0
CH A
CH B
CH C
CH D
SYNC
1.4
1.2
1.0
0.8
GAIN = 2
FULL-SCALE
ZERO CODE
GAIN = 1
EXTERNAL REFERENCE, FULL-SCALE
0.6
0.4
0.2
0
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
–5
0
5
10
–40
10
60
110
TIME (µs)
TEMPERATURE (°C)
Figure 35. Exiting Power-Down to Midscale
Figure 32. Supply Current vs. Temperature
2.5008
2.5003
2.4998
2.4993
2.4988
4.0
DAC A
DAC B
DAC C
DAC D
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CHANNEL B
T
= 25°C
A
V
T
= 5V
= 25°C
V
= 5.25V
DD
DD
INTERNAL REFERENCE = 2.5V
CODE = 7FFF TO 8000
ENERGY = 0.227206nV-sec
A
INTERNAL REFERENCE = 2.5V
1/4 TO 3/4 SCALE
0
2
4
6
8
10
12
10
20
40
80
160
320
TIME (µs)
TIME (µs)
Figure 36. Digital-to-Analog Glitch Impulse
Figure 33. Settling Time, 5 V
0.003
0.002
0.001
0
0.06
0.05
0.04
0.03
0.02
0.01
0
6
CH A
CH B
CH C
CH D
CH B
CH C
CH D
5
V
DD
4
3
2
1
–0.001
–0.002
0
T
= 25°C
A
INTERNAL REFERENCE = 2.5V
–0.01
–1
0
5
10
15
20
25
–10
–5
0
5
10
15
TIME (µs)
TIME (µs)
Figure 37. Analog Crosstalk, Channel A
Figure 34. Power-On Reset to 0 V
Rev. 0 | Page 15 of 28
AD5317R
Data Sheet
20
0
V
T
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
–20
–40
–60
–80
1
–100
–120
–140
–160
–180
V
= 5V
= 25°C
DD
T
A
EXTERNAL REFERENCE = 2.5V
0
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
FREQUENCY (Hz)
CH1 10µV M1.0s
A
CH1
802mV
Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 41. Total Harmonic Distortion @ 1 kHz
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
0nF
V
T
= 5V
= 25°C
DD
0.1nF
10nF
0.22nF
4.7nF
T
A
INTERNAL REFERENCE = 2.5V
1
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
1.590 1.595 1.600 1.605 1.610 1.615 1.620 1.625 1.630
TIME (ms)
CH1 10µV M1.0s
A
CH1
802mV
Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
Figure 42. Settling Time vs. Capacitive Load
1600
V
= 5V
DD
FULL-SCALE
MIDSCALE
ZERO-SCALE
T
= 25°C
A
1400
1200
1000
800
600
400
200
0
INTERNAL REFERENCE = 2.5V
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 40. Noise Spectral Density
Rev. 0 | Page 16 of 28
Data Sheet
AD5317R
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 15.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change
in VOUT to a change in VDD for full-scale output of the DAC. It
is measured in mV/V. VREF is held at 2.5 V, and VDD is varied
by 10%.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 16.
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the rising edge of
SYNC
.
Digital-to-Analog Glitch Impulse
Zero-Code Error
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 36).
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5317R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV. A plot
of zero-code error vs. temperature can be seen in Figure 21.
Digital Feedthrough
Digital feedthrough is a measurement of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec and measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range (% of FSR). A plot of full-scale error
vs. temperature can be seen in Figure 20.
Noise Spectral Density
Gain Error
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale
and measuring noise at the output. It is measured in nV/√Hz.
A plot of noise spectral density is shown in Figure 40.
Gain error is a measurement of the span error of the DAC. It is
the deviation in slope of the DAC transfer characteristic from
the ideal expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC
in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in μV.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Offset Error
DC crosstalk due to load current change is a measurement of
the impact that a change in load current on one DAC has on
another DAC kept at midscale. It is expressed in μV/mA.
Offset error is a measurement of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV in the linear region of
the transfer function. Offset error is measured on the AD5317R
with Code 4 loaded to the DAC register. It can be negative or
positive.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
Rev. 0 | Page 17 of 28
AD5317R
Data Sheet
Analog Crosstalk
Voltage Reference TC
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa). Then execute a
software LDAC and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-sec.
Voltage reference TC is a measurement of the change in the
reference output voltage with a change in temperature. The
reference TC is calculated using the box method, which defines
the TC as the maximum change in the reference output over a
given temperature range expressed in ppm/°C, as follows:
V
REFmax −VREFmin
TC =
×106
V
×TempRange
REFnom
DAC-to-DAC Crosstalk
where:
REFmax is the maximum reference output measured over the
total temperature range.
REFmin is the minimum reference output measured over the total
temperature range.
REFnom is the nominal reference output voltage, 2.5 V.
DAC-to-DAC crosstalk is the glitch impulse transferred to
the output of one DAC in response to a digital code change
and subsequent analog output change of another DAC. It is
measured by loading one channel with a full-scale code change
(all 0s to all 1s and vice versa) using the write to and update
commands while monitoring the output of another channel that
is at midscale. The energy of the glitch is expressed in nV-sec.
V
V
V
TempRange is the specified temperature range of −40°C to
+105°C.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Rev. 0 | Page 18 of 28
Data Sheet
AD5317R
THEORY OF OPERATION
The resistor string structure is shown in Figure 44. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because the DAC is a string of resistors,
it is guaranteed monotonic.
DIGITAL-TO-ANALOG CONVERTER
The AD5317R is a quad, 10-bit, serial input, voltage output
DAC with an internal reference. The part operates from supply
voltages of 2.7 V to 5.5 V. Data is written to the AD5317R in a
24-bit word format via a 3-wire serial interface. The AD5317R
incorporates a power-on reset circuit to ensure that the DAC
output powers up to a known output state. The device also has
a software power-down mode that reduces the typical current
consumption to typically 4 µA.
V
REF
R
TRANSFER FUNCTION
The internal reference is on by default. Because the input
coding to the DAC is straight binary, the ideal output voltage
when using an external reference is given by
R
R
TO OUTPUT
AMPLIFIER
D
2
VOUT =VREF ×Gain
N
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows: 0 to 1023 for the 10-bit device.
N is the DAC resolution (10-bits).
Gain is the gain of the output amplifier and is set to 1 by default.
The gain can be set to ×1 or ×2 using the gain select pin. When
this pin is tied to GND, all four DAC outputs have a span from
0 V to VREF. When this pin is tied to VDD, all four DAC outputs
R
R
Figure 44. Resistor String Structure
have a span of 0 V to 2 × VREF
.
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, offset error,
and gain error. The GAIN pin selects the gain of the output.
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 43 shows a block diagram of the DAC
architecture.
V
•
If this pin is tied to GND, all four outputs have a gain of 1,
and the output range is 0 V to VREF
If this pin is tied to VDD, all four outputs have a gain of 2,
and the output range is 0 V to 2 × VREF
REF
.
2.5V
REF
•
REF (+)
.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
X
OUT
The output amplifiers are capable of driving a load of 1 kΩ in
parallel with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼
to ¾ scale settling time of 5 µs.
REF (–)
GAIN
(GAIN = 1 OR 2)
GND
Figure 43. Single DAC Channel Architecture Block Diagram
Rev. 0 | Page 19 of 28
AD5317R
Data Sheet
Table 8. Command Bit Definitions
SERIAL INTERFACE
Command
SYNC
The AD5317R has a 3-wire serial interface (
, SCLK, and
C3
0
0
C2 C1 C0 Description
SDIN) that is compatible with SPI, QSPI™, and MICROWIRE¬
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence. The AD5317R
contain an SDO pin to allow the user to daisy-chain multiple
devices together (see the Daisy-Chain Operation section) or for
readback.
0
0
0
0
0
1
0
1
0
No operation
LDAC
)
Write to Input Register n (dependent on
0
Update DAC Register n with contents of Input
Register n
0
0
0
0
0
1
1
1
…
1
0
1
1
1
1
0
0
0
…
1
1
0
0
1
1
0
0
1
…
1
1
0
1
0
1
0
1
0
…
1
Write to and update DAC Channel n
Power down/power up DAC
LDAC
Hardware
mask register
Input Shift Register
Software reset (power-on reset)
Internal reference setup register
Set up DCEN register (daisy-chain enable)
Set up readback register (readback enable)
Reserved
The input shift register of the AD5317R is 24 bits wide. Data is
loaded MSB first (DB23) and the first four bits are the command
bits, C3 to C0 (see Table 8), followed by the 4-bit DAC address
bits, DAC A, DAC B, DAC C, DAC D (see Table 9), and finally
the data-word.
Reserved
Reserved
The data-word comprises the 10-bit input code, followed by six
don’t care bits (see Figure 45). These data bits are transferred to
the input register on the 24 falling edges of SCLK and are
Table 9. Address Bits and Selected DACs
Address Bits
DAC D DAC C DAC B DAC A Selected DAC Channel1
SYNC
updated on the rising edge of
.
0
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
1
1
1
0
0
0
1
1
DAC A
DAC B
DAC C
DAC D
DAC A and DAC B
All DACs
Commands can be executed on individual DAC channels,
combined DAC channels, or on all DAC channels, depending on
the address bits selected (see Table 9).
1 Any combination of DAC channels can be selected using the address bits.
DB23 (MSB)
DB0 (LSB)
DAC DAC DAC DAC
C3 C2 C1 C0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
X
X
X
X
X
X
D
C
B
A
COMMAND BITS
ADDRESS BITS
Figure 45. AD5317R Input Shift Register Contents
Rev. 0 | Page 20 of 28
Data Sheet
AD5317R
STANDALONE OPERATION
68HC11*
AD5317R
SYNC
The write sequence begins by bringing the
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of the 24 data bits is
line low. Data
SDIN
MOSI
SCK
PC7
PC6
SCLK
SYNC
LDAC
SYNC
clocked in,
should be brought high. The programmed
LDAC
function is then executed, that is, an
-dependent change
SDO
MISO
in DAC register contents and/or a change in the mode of
th
SYNC
operation. If
data may be loaded to the DAC.
for a minimum of 20 ns (single channel, see t8 in Figure 2)
SYNC
is taken high before the 24 clock, invalid
SYNC
SDIN
must be brought high
AD5317R
before the next write sequence so that a falling edge of
SYNC
SCLK
can initiate the next write sequence.
the rails between write sequences for even lower power opera-
SYNC
should be idled at
SYNC
LDAC
tion of the part. The
of SCLK, and the DAC is updated on the rising edge of
After the data is transferred into the input register of the
addressed DAC, all DAC registers and outputs can be updated
LDAC SYNC
line is kept low for 24 falling edges
SDO
SYNC
.
SDIN
by taking
low while the
line is high.
AD5317R
WRITE AND UPDATE COMMANDS
SCLK
Write to Input Register n (Dependent on
)
SYNC
LDAC
LDAC
Command 0001 allows the user to write to each DAC’s
LDAC
SDO
dedicated input register individually. When
the input register is transparent (if not controlled by the
LDAC
is low,
mask register).
*ADDITIONAL PINS OMITTED FOR CLARITY.
Update DAC Register n with Contents of Input Register n
Figure 46. Daisy-Chaining the AD5317R
Command 0010 loads the DAC registers/outputs with the
contents of the input registers selected and updates the DAC
outputs directly.
The SCLK pin is continuously applied to the input shift register
SYNC
when
is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting the SDO line to
the SDIN input on the next DAC in the chain, a daisy-chain
interface is constructed. Each DAC in the system requires 24
clock pulses. Therefore, the total number of clock cycles must
equal 24 × N, where N is the total number of devices that are
Write to and Update DAC Channel n (Independent of
)
LDAC
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.
DAISY-CHAIN OPERATION
SYNC
updated. If
of 24, invalid data may be loaded to the DAC. When the serial
SYNC
is taken high at a clock that is not a multiple
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. This function
is enabled through a software executable daisy-chain enable
(DCEN) command. Command 1000 is reserved for this DCEN
function (see Table 8). The daisy-chain mode is enabled by
setting Bit DB0 in the DCEN register. The default setting is
standalone mode, where DB0 = 0. Table 10 shows how the state
of the bit corresponds to the mode of operation of the device.
transfer to all devices is complete,
is taken high. This
latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input
shift register. The serial clock can be a continuous or a gated clock.
A continuous SCLK source can be used only if
held low for the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
SYNC
can be
Table 10. Daisy-Chain Enable (DCEN) Register
SYNC
must be used, and
to latch the data.
must be taken high after the final clock
DB0
Description
0
1
Standalone mode (default)
DCEN mode
Rev. 0 | Page 21 of 28
AD5317R
Data Sheet
Table 11. Modes of Operation
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
READBACK OPERATION
PDx1
PDx0
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisy-
chain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one of
the address bits, DAC A to DAC D, selects the register to read.
Note that only one DAC register can be selected during
readback. The remaining three address bits must be set to Logic
0. The remaining data bits in the write sequence are don’t care
bits. If more than one or no bits are selected, DAC Channel A is
read back by default. During the next SPI write, the data
appearing on the SDO output contains the data from the
previously addressed register.
0
0
0
1
1
1
0
1
100 kΩ to GND
Three-State
Any or all DACs (DAC A to DAC D) can be powered down to
the selected mode by setting the corresponding bits. See
Table 12 for the contents of the input shift register during the
power-down/power-up operation.
When both Bit PDx1 and Bit PDx0 (where x is the channel
selected) in the input shift register are set to 0, the part works
normally with its normal power consumption of 1.1 m A at 5 V.
However, for the three power-down modes, the supply current
falls to 4 μA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
power-down options (see Table 11). The output is connected
internally to GND through either a 1 kΩ or a 100 kΩ resistor, or
it is left open-circuited (three-state). The output stage is
illustrated in Figure 47.
For example, to read back the DAC register for Channel A, the
following sequence should be implemented:
1. Write 0x900000 to the AD5317R input register. This
configures the part for read mode with the DAC register of
Channel A selected. Note that all data bits, DB15 to DB0,
are don’t care bits.
2. Follow this with a second write, a NOP condition,
0x000000. During this write, the data from the register is
clocked out on the SDO line. DB23 to DB20 contain
undefined data, and the last 16 bits contain the DB19 to
DB4 DAC register contents.
AMPLIFIER
V
X
DAC
OUT
POWER-DOWN OPERATION
The AD5317R provides three separate power-down modes.
Command 0100 is designated for the power-down function (see
Table 8). These power-down modes are software programmable
by setting eight bits, Bit DB7 to Bit DB0, in the input shift register.
There are two bits associated with each DAC channel. Table 11
shows how the state of the two bits corresponds to the mode of
operation of the device.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 47. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC registers
are unaffected when in power-down. The DAC registers can be
updated while the device is in power-down mode. The time
required to exit power-down is typically 4.5 µs for VDD = 5 V.
Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation1
DB15
to
DB8
DB0
(LSB)
DB23 DB22
DB21
DB20
DB19 to DB16
DB7
DB6
DB5
DB4
DB3
DB2
DB1
0
1
0
0
X
X
PDD1
PDD0
PDC1
PDC0
PDB1
PDB0 PDA1
PDA0
Command bits (C3 to C0)
Address bits
(don’t care)
Power-Down
Select DAC D
Power-Down
Select DAC C
Power-Down
Select DAC B
Power-Down
Select DAC A
1 X = don’t care.
Rev. 0 | Page 22 of 28
Data Sheet
AD5317R
LOAD DAC (HARDWARE LDAC PIN)
LDAC MASK REGISTER
The AD5317R DAC has double buffered interfaces consisting
of two banks of registers: input registers and DAC registers.
The user can write to any combination of the input registers.
LDAC
function.
Command 0101 is reserved for the software
Address bits are ignored. Writing to the DAC using Command
LDAC
0101 loads the 4-bit
for each channel is 0; that is, the
Setting the bits to 1 forces this DAC channel to ignore transitions
LDAC LDAC
register (DB3 to DB0). The default
LDAC
Updates to the DAC register are controlled by the
pin.
LDAC
pin works normally.
OUTPUT
AMPLIFIER
on the
pin. This flexibility is useful in applications where the user
LDAC
pin, regardless of the state of the hardware
V
10-BIT
DAC
REF
V
X
OUT
wishes to select which channels respond to the
pin.
mask register gives the user extra flexibility and
LDAC
DAC
REGISTER
LDAC
LDAC
The
control over the hardware
LDAC
pin (see Table 13). Setting
bits (DB3 to DB0) to 0 for a DAC channel means that
LDAC
the
this channel’s update is controlled by the hardware
INPUT
REGISTER
pin.
LDAC
Table 13.
Load
Overwrite Definition
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
Register
LDAC
Bits
(DB3 to DB0)
LDAC
Figure 48. Simplified Diagram of Input Loading Circuitry for a Single DAC
Pin
Operation
LDAC
LDAC
1 or 0
X1
LDAC
Instantaneous DAC Updating (
Held Low)
is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
0
1
Determined by the LDAC pin.
DAC channels are updated and
override the LDAC pin. DAC
channels see LDAC as 1.
LDAC
SYNC
the DAC register are updated on the rising edge of
the output begins to change (see Table 14).
and
1 X = don’t care.
LDAC
Deferred DAC Updating (
Is Pulsed Low)
is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
LDAC SYNC
LDAC
updated by taking
low after
has been taken high.
LDAC
The update now occurs on the falling edge of
.
1
LDAC
Table 14. Write Commands and
Pin Truth Table
Hardware
Pin State
LDAC
Input Register
Contents
Command
Description
DAC Register Contents
No change (no update)
Data update
0001
Write to Input Register n (dependent on LDAC)
VLOGIC
Data update
Data update
No change
GND2
0010
0011
Update DAC Register n with contents of Input
Register n
VLOGIC
Updated with input register
contents
GND
No change
Updated with input register
contents
Write to and update DAC Channel n
VLOGIC
GND
Data update
Data update
Data update
Data update
1
LDAC
A high to low hardware
pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
mask register.
2 When LDAC is permanently tied low, the LDAC mask bits are ignored.
LDAC
(blocked) by the
Rev. 0 | Page 23 of 28
AD5317R
Data Sheet
HARDWARE RESET (
)
RESET SELECT PIN (RSTSEL)
RESET
The AD5317R contains a power-on reset circuit that controls
the output voltage during power-up. By connecting the RSTSEL
pin low, the output powers up to zero scale. Note that this is
outside the linear region of the DAC. By connecting the
RSTSEL pin high, VOUT powers up to midscale. The output
remains powered up at this level until a valid write sequence is
made to the DAC.
RESET
is an active low reset that allows the outputs to be
cleared to either zero scale or midscale. The clear code value is
RESET
user selectable via the
select pin. It is necessary to
low for a minimum of 30 ns to complete the
RESET
RESET
keep
operation (see Figure 2). When the
signal is returned
high, the output remains at the cleared value until a new value is
programmed. The outputs cannot be updated with a new value
RESET
while the
pin is low. There is also a software executable
reset function that resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function
LDAC RESET
(see Table 8). Any events on
reset are ignored.
or
during power-on
Rev. 0 | Page 24 of 28
Data Sheet
AD5317R
INTERNAL REFERENCE SETUP
LONG-TERM TEMPERATURE DRIFT
By default, the internal reference is on at power-up. To reduce
the supply current, the on-chip reference can be turned off.
Command 0111 is reserved for setting up the internal reference.
To turn off the internal reference, set the software programmable
bit, DB0, in the input shift register using Command 0111, as
shown in Table 16. Table 15 shows how the state of the DB0 bit
corresponds to the mode of operation.
Figure 50 shows the change in the VREF value after 1000 hours
in life test at 150°C.
0 HOUR
168 HOURS
500 HOURS
1000 HOURS
60
50
40
30
20
10
0
Table 15. Internal Reference Setup Register
Internal Reference
Setup Register (Bit DB0)
Action
0
1
Reference on (default)
Reference off
SOLDER HEAT REFLOW
2.498
2.499
2.500
(V)
2.501
2.502
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test called precondition to
mimic the effect of soldering a device to a board. The output
voltage specification in Table 2 includes the effect of this
reliability test.
V
REF
Figure 50. Reference Drift to 1000 Hours
THERMAL HYSTERESIS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
Figure 49 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).
Thermal hysteresis data is shown in Figure 51. It is measured by
sweeping the temperature from ambient to −40°C, then to +105°C,
and then back to ambient. The VREF delta is then measured between
the two ambient measurements (shown in blue in Figure 51). The
same temperature sweep and measurements were immediately
repeated, and the results are shown in red in Figure 51.
9
POSTSOLDER
HEAT REFLOW
60
50
40
30
20
10
0
PRESOLDER
HEAT REFLOW
FIRST TEMPERATURE SWEEP
SUBSEQUENT TEMPERATURE SWEEPS
8
7
6
5
4
3
2
1
0
2.498
2.499
2.500
(V)
2.501
2.502
V
REF
Figure 49. SHR Reference Voltage Shift
–200
–150
–100
–50
0
50
DISTORTION (ppm)
Figure 51. Thermal Hysteresis
Table 16. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1
DB23 (MSB) DB22
DB21
DB20
DB19 to DB16
DB15 to DB1
DB0 (LSB)
0
1
1
1
X
X
1 or 0
Command bits (C3 to C0)
Address bits (don’t care)
Don’t care
Reference setup register
1 X = don’t care.
Rev. 0 | Page 25 of 28
AD5317R
Data Sheet
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
LAYOUT GUIDELINES
Microprocessor interfacing to the AD5317R is via a serial bus
that uses a standard protocol that is compatible with DSP
processors and microcontrollers. The communications channel
requires a 3- or 4-wire interface consisting of a clock signal, a
data signal, and a synchronization signal. The device requires a
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performance. The PCB on which the AD5317R is
mounted should be designed so that the AD5317R lies on the
analog plane.
SYNC
24-bit data-word with data valid on the rising edge of
.
The AD5317R should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply, located as close to the
package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
AD5317R TO ADSP-BF531 INTERFACE
The SPI interface of the AD5317R is designed to be easily
connected to industry-standard DSPs and microcontrollers.
Figure 52 shows the AD5317R connected to the Analog
Devices, Inc., Blackfin® DSP. The Blackfin has an integrated SPI
port that can be connected directly to the SPI pins of the
AD5317R.
AD5317R
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
ADSP-BF531
SPISELx
SCK
SYNC
SCLK
SDIN
The AD5317R LFCSP model has an exposed pad beneath the
device. Connect this pad to the GND supply for the part. For
optimum performance, use special considerations to design the
motherboard and to mount the package. For enhanced thermal,
electrical, and board level performance, solder the exposed pad
on the bottom of the package to the corresponding thermal land
pad on the PCB. Design thermal vias into the PCB land pad
area to further improve heat dissipation.
MOSI
PF9
PF8
LDAC
RESET
Figure 52. ADSP-BF531 Interface
AD5317R TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 53 shows how one SPORT interface can be used to
control the AD5317R.
The GND plane on the device can be increased (as shown in
Figure 54) to provide a natural heat sinking effect.
AD5317R
AD5317R
ADSP-BF527
SPORT_TFS
SPORT_TSCK
SPORT_DTO
SYNC
SCLK
SDIN
GND
PLANE
GPIO0
GPIO1
LDAC
RESET
BOARD
Figure 53. SPORT Interface
Figure 54. Pad Connection to Board
Rev. 0 | Page 26 of 28
Data Sheet
AD5317R
ADuM14001
CONTROLLER
GALVANICALLY ISOLATED INTERFACE
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
TO
SERIAL
In many process control applications, it is necessary to
provide an isolation barrier between the controller and
the unit being controlled to protect and isolate the controlling
circuitry from any hazardous common-mode voltages that
may occur. iCoupler® products from Analog Devices provide
voltage isolation in excess of 2.5 kV. The serial loading struc-
ture of the AD5317R makes the part ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 55 shows a 4-channel isolated interface to the AD5317R
using an ADuM1400. For further information, visit
ENCODE
DECODE
DECODE
DECODE
DECODE
SCLK
CLOCK IN
TO
SDIN
SERIAL
DATA OUT
ENCODE
ENCODE
ENCODE
TO
SYNC
SYNC OUT
LOAD DAC
OUT
TO
LDAC
1
http://www.analog.com/icouplers.
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 55. Isolated Interface
Rev. 0 | Page 27 of 28
AD5317R
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 56. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 57. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Reference
Temperature
Range
Accuracy
(Typ)
Tempco
(ppm/°C)
Package
Description
16-Lead LFCꢀP_WQ CP-16-22
Package
Option
Model1
Resolution
Branding
AD5317RBCPZ-RL7
AD5317RBRUZ
AD5317RBRUZ-RL7
10 Bits
10 Bits
10 Bits
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
0.12 LꢀB INL 5 (max)
0.12 LꢀB INL 5 (max)
0.12 LꢀB INL 5 (max)
DG6
16-Lead TꢀꢀOP
16-Lead TꢀꢀOP
RU-16
RU-16
1 Z = RoHꢀ Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10800-0-7/12(0)
Rev. 0 | Page 28 of 28
相关型号：
AD5318BRUZ
SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16
ROCHESTER
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