AD5324ACPZ-WP_技术文档

2.5 V to 5.5 V, 500 ␮A, Quad Voltage Output

a

8-/10-/12-Bit DACs in 10-Lead microSOIC

AD5304/AD5314/AD5324*

GENERAL DESCRIPTION

FEATURES

The AD5304/AD5314/AD5324 are quad 8-, 10- and 12-bit

AD5304

buffered voltage output DACs in a 10-lead microSOIC package

that operate from a single 2.5 V to 5.5 V supply consuming

500 µA at 3 V. Their on-chip output ampliﬁers allow rail-to-

rail output swing to be achieved with a slew rate of 0.7 V/µs.

A 3-wire serial interface is used which operates at clock rates

up to 30 MHz and is compatible with standard SPI, QSPI,

MICROWIRE and DSP interface standards.

Four Buffered 8-Bit DACs in 10-Lead microSOIC

AD5314

Four Buffered 10-Bit DACs in 10-Lead microSOIC

AD5324

Four Buffered 12-Bit DACs in 10-Lead microSOIC

Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V

2.5 V to 5.5 V Power Supply

Guaranteed Monotonic By Design Over All Codes

Power-Down to 80 nA @ 3 V, 200 nA @ 5 V

Double-Buffered Input Logic

Output Range: 0–V_REF

Power-On-Reset to Zero Volts

Simultaneous Update of Outputs (LDAC Function)

Low Power, SPI™, QSPI™, MICROWIRE™, and

DSP-Compatible 3-Wire Serial Interface

On-Chip Rail-to-Rail Output Buffer Ampliﬁers

Temperature Range –40؇C to +105؇C

The references for the four DACs are derived from one reference

pin. The outputs of all DACs may be updated simultaneously

using the software LDAC function. The parts incorporate a

power-on-reset circuit that ensures that the DAC outputs power

up to zero volts and remain there until a valid write takes place

to the device. The parts contain a power-down feature that

reduces the current consumption of the device to 200 nA @ 5 V

(80 nA @ 3 V).

The low power consumption of these parts in normal operation

makes them ideally suited to portable battery-operated equipment.

The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing

to 1 µW in power-down mode.

APPLICATIONS

Portable Battery-Powered Instruments

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

Programmable Attenuators

Industrial Process Control

FUNCTIONAL BLOCK DIAGRAM

V

REFIN

DD

LDAC

DAC

INPUT

STRING

DAC A

BUFFER

V

A

B

OUT

REGISTER

DAC

REGISTER

INPUT

REGISTER

SCLK

STRING

DAC B

OUT

INTERFACE

LOGIC

SYNC

DAC

INPUT

STRING

DAC C

BUFFER

V

C

D

OUT

REGISTER

DIN

DAC

REGISTER

INPUT

REGISTER

STRING

DAC D

V

POWER-DOWN

LOGIC

POWER-ON

RESET

AD5304/AD5314/AD5324

GND

*Protected by U.S. Patent No. 5,969,657; other patents pending.

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD5304/AD5314/AD5324–SPECIFICATIONS^(V_DD= 2.5 V to 5.5 V; V_REF= 2 V; R_L= 2 k⍀ to

GND; C_L= 200 pF to GND; All speciﬁcations T_MINto T_MAXunless otherwise noted.)

B Version²

Typ

Parameter¹

Min

Max

Unit

Conditions/Comments

DC PERFORMANCE^{3, 4}

AD5304

Resolution

8

Bits

LSB

Relative Accuracy

Differential Nonlinearity

AD5314

0.15

0.02

1

0.25

Guaranteed Monotonic by Design Over All Codes

Resolution

10

0.5

0.05

Bits

LSB

Relative Accuracy

Differential Nonlinearity

AD5324

4

0.5

Resolution

12

Bits

Relative Accuracy

Differential Nonlinearity

Offset Error

2

16

1

3

1

60

LSB

0.2

0.4

0.15

20

–12

–5

Guaranteed Monotonic by Design Over All Codes

See Figures 2 and 3

% of FSR

mV

ppm of FSR/°C

dB

Gain Error

Lower Deadband

Offset Error Drift⁵

Gain Error Drift⁵

DC Power Supply Rejection Ratio⁵

DC Crosstalk⁵

Lower Deadband Exists Only If Offset Error Is Negative

–60

200

∆V_DD= 10%

R_L= 2 kΩ to GND or V_DD

µV

DAC REFERENCE INPUTS⁵

V_REFInput Range

V_REFInput Impedance

0.25

37

V_DD

V

45

>10

–90

kΩ

MΩ

dB

Normal Operation

Power-Down Mode

Frequency = 10 kHz

Reference Feedthrough

OUTPUT CHARACTERISTICS⁵

Minimum Output Voltage⁶

Maximum Output Voltage⁶

DC Output Impedance

0.001

V_DD– 0.001

V

Ω

This is a measure of the minimum and maximum drive

capability of the output ampliﬁer.

0.5

25

16

2.5

5

Short Circuit Current

mA

µs

V_DD= 5 V

V_DD= 3 V

Power-Up Time

Coming Out of Power-Down Mode. V_DD= 5 V

Coming Out of Power-Down Mode. V_DD= 3 V

µs

LOGIC INPUTS⁵

Input Current

V_IL, Input Low Voltage

1

µA

V

0.8

0.6

0.5

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

V

V_IH, Input High Voltage

Pin Capacitance

2.4

2.1

2.0

V

pF

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

3

POWER REQUIREMENTS

V_DD

2.5

5.5

V

I_DD(Normal Mode)⁷

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.6 V

I_DD(Power-Down Mode)

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.6 V

600

500

900

700

µA

V_IH= V_DDand V_IL= GND

0.2

0.08

1

µA

V_IH= V_DDand V_IL= GND

NOTES

¹See Terminology.

²Temperature range: B Version: –40°C to +105°C; typical at 25°C.

³DC speciﬁcations tested with the outputs unloaded.

⁴Linearity is tested using a reduced code range: AD5304 (Code 8 to 248); AD5314 (Code 28 to 995); AD5324 (Code 115 to 3981).

⁵Guaranteed by design and characterization, not production tested.

⁶In order for the ampliﬁer output to reach its minimum voltage, Offset Error must be negative. In order for the ampliﬁer output to reach its maximum voltage,

V_REF= V_DDand “Offset plus Gain” Error must be positive.

⁷I_DDspeciﬁcation is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

Speciﬁcations subject to change without notice.

REV. B

–2–

AD5304/AD5314/AD5324

(V_DD= 2.5 V to 5.5 V; R_L= 2 k⍀ to GND; C_L= 200 pF to GND; all speciﬁcations T_MINto T_MAXunless

otherwise noted.)

AC CHARACTERISTICS¹

B Version³

Parameter²

Min

Typ

Max

Unit

Conditions/Comments

Output Voltage Settling Time

AD5304

AD5314

AD5324

Slew Rate

Major-Code Transition Glitch Energy

Digital Feedthrough

Digital Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

V_REF= V_DD= 5 V

6

7

8

0.7

12

1

3

8

9

10

µs

1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)

1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)

1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)

µs

V/µs

nV-s

kHz

dB

1 LSB Change Around Major Carry

200

–70

V_REF= 2 V 0.1 V p-p

V_REF= 2.5 V 0.1 V p-p. Frequency = 10 kHz

NOTES

¹Guaranteed by design and characterization, not production tested.

²See Terminology.

³Temperature range: B Version: –40°C to +105°C; typical at 25°C.

Speciﬁcations subject to change without notice.

TIMING CHARACTERISTICS^{1, 2, 3}

(V_DD= 2.5 V to 5.5 V. All speciﬁcations T_MINto T_MAXunless otherwise noted)

Limit at T_MIN, T_MAX

V_DD= 2.5 V to 3.6 V V_DD= 3.6 V to 5.5 V

Parameter

Unit

Conditions/Comments

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

40

16

0

5

4.5

0

33

13

0

5

4.5

0

ns min

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNC to SCLK Rising Edge Setup Time

Data Setup Time

Data Hold Time

SCLK Falling Edge to SYNC Rising Edge

Minimum SYNC High Time

80

33

NOTES

¹Guaranteed by design and characterization, not production tested.

²All input signals are speciﬁed with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

³See Figure 1.

Speciﬁcations subject to change without notice.

t

1

SCLK

t

2

t

7

t

3

8

t

4

SYNC

t

6

t

5

DB15

DB0

DIN

Figure 1. Serial Interface Timing Diagram

REV. B

–3–

AD5304/AD5314/AD5324

ABSOLUTE MAXIMUM RATINGS^{1, 2}

(T_A= 25°C unless otherwise noted)

PIN CONFIGURATION

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V_DD+ 0.3 V

Reference Input Voltage to GND . . . . –0.3 V to V_DD+ 0.3 V

V

SYNC

SCLK

DIN

1

2

3

4

5

10

9

DD

AD5304/

AD5314/

AD5324

V

A

OUT

V

_OUTA–D to GND . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

B

C

8

Operating Temperature Range

GND

7

TOP VIEW

(Not to Scale)

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T_Jmax) . . . . . . . . . . . . . . . . . . 150°C

10-Lead microSOIC Package

6

REFIN

V

D

OUT

Power Dissipation . . . . . . . . . . . . . . . . . . (T_Jmax – T_A)/θ_JA

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W

_JCThermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W

θ

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C

Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; and functional operation of

the device at these or any other conditions above those listed in the operational

sections of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²Transient currents of up to 100 mA will not cause SCR latch-up.

PIN FUNCTION DESCRIPTIONS

No. Mnemonic Function

1

2

3

4

5

6

7

8

V_DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND.

Buffered Analog Output Voltage from DAC A. The output ampliﬁer has rail-to-rail operation.

Buffered Analog Output Voltage from DAC B. The output ampliﬁer has rail-to-rail operation.

Buffered Analog Output Voltage from DAC C. The output ampliﬁer has rail-to-rail operation.

Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V_DD.

Buffered Analog Output Voltage from DAC D. The output ampliﬁer has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

V

_OUTA

_OUTB

_OUTC

REFIN

_OUTD

V

GND

DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of

the serial clock input. The DIN input buffer is powered down after each write cycle.

9

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

10

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If SYNC is

taken high before the sixteenth falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the

write sequence is ignored by the device.

ORDERING GUIDE

Temperature

Range

Package

Description

Package

Option

Branding

Information

Model

AD5304BRM

AD5314BRM

AD5324BRM

–40°C to +105°C

10-Lead microSOIC

RM-10

DBB

DCB

DDB

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD5304/AD5314/AD5324 features proprietary ESD protection circuitry, permanent damage

may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–4–

AD5304/AD5314/AD5324

TERMINOLOGY

DIGITAL CROSSTALK

RELATIVE ACCURACY

This is the glitch impulse transferred to the output of one DAC

at midscale in response to a full-scale code change (all 0s to all

1s and vice versa) in the input register of another DAC. It is

expressed in nV-secs.

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer function.

Typical INL versus Code plots can be seen in Figures 4, 5, and 6.

DAC-TO-DAC CROSSTALK

DIFFERENTIAL NONLINEARITY

This is the glitch impulse transferred to the output of one DAC

due to a digital code change and subsequent output change of

another DAC. This includes both digital and analog crosstalk. It

is measured by loading one of the DACs with a full-scale code

change (all 0s to all 1s and vice versa) with the LDAC bit set low

and monitoring the output of another DAC. The energy of the

glitch is expressed in nV-secs.

Differential Nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A speciﬁed differential nonlinearity of 1 LSB

maximum ensures monotonicity. This DAC is guaranteed mono-

tonic by design. Typical DNL versus Code plots can be seen in

Figures 7, 8, and 9.

OFFSET ERROR

MULTIPLYING BANDWIDTH

This is a measure of the offset error of the DAC and the output

ampliﬁer. It is expressed as a percentage of the full-scale range.

The ampliﬁers within the DAC have a ﬁnite bandwidth. The

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at which

the output amplitude falls to 3 dB below the input.

GAIN ERROR

This is a measure of the span error of the DAC. It is the devia-

tion in slope of the actual DAC transfer characteristic from the

ideal expressed as a percentage of the full-scale range.

TOTAL HARMONIC DISTORTION

This is the difference between an ideal sine wave and its attenuated

version using the DAC. The sine wave is used as the reference

for the DAC and the THD is a measure of the harmonics present

on the DAC output. It is measured in dBs.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

GAIN ERROR

PLUS

GAIN ERROR DRIFT

This is a measure of the change in gain error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

OUTPUT

VOLTAGE

IDEAL

OFFSET ERROR

ACTUAL

POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in V_OUTto

a change in V_DDfor full-scale output of the DAC. It is measured

in dBs. V_REFis held at 2 V and V_DDis varied 10%.

NEGATIVE

OFFSET

ERROR

DAC CODE

DEADBAND CODES

DC CROSSTALK

AMPLIFIER

FOOTROOM

(1mV)

This is the dc change in the output level of one DAC at midscale

in response to a full-scale code change (all 0s to all 1s and vice

versa) and output change of another DAC. It is expressed in µV.

NEGATIVE

OFFSET

ERROR

REFERENCE FEEDTHROUGH

This is the ratio of the amplitude of the signal at the DAC

output to the reference input when the DAC output is not being

updated. It is expressed in dBs.

Figure 2. Transfer Function with Negative Offset

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-code transition glitch energy is the energy of the impulse

injected into the analog output when the code in the DAC

register changes state. It is normally speciﬁed as the area of the

glitch in nV-secs and is measured when the digital code is changed

by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00

or 100 . . . 00 to 011 . . . 11).

GAIN ERROR

PLUS

OFFSET ERROR

ACTUAL

OUTPUT

VOLTAGE

IDEAL

DIGITAL FEEDTHROUGH

POSITIVE

OFFSET

Digital feedthrough is a measure of the impulse injected into the

analog output of the DAC from the digital input pins of the device

when the DAC output is not being written to (SYNC held high). It

is speciﬁed in nV-secs and is measured with a worst-case change on

the digital input pins, e.g., from all 0s to all 1s or vice versa.

DAC CODE

Figure 3. Transfer Function with Positive Offset

REV. B

–5–

AD5304/AD5314/AD5324

12

8

3

2

1.0

T

V

= 25؇C

A

T

V

= 25؇C

T

V

= 25؇C

A

= 5V

DD

= 5V

DD

0.5

0

4

0

1

0

–1

–2

–3

–4

–8

–0.5

–1.0

–12

0

4000

50

100

150

CODE

200

250

0

1000

2000

CODE

3000

0

200

400

CODE

600

800

1000

Figure 6. AD5324 Typical INL Plot

Figure 4. AD5304 Typical INL Plot

Figure 5. AD5314 Typical INL Plot

0.3

1

0.6

T

V

= 25؇C

T

V

= 25؇C

T

V

= 25؇C

A

= 5V

DD

0.2

0.1

0.4

0.2

0.5

0

–0.5

–1

0

–0.1

–0.2

–0.3

–0.2

–0.4

–0.6

0

50

100

150

200

250

0

1000

2000

3000

4000

0

200

400

600

800

1000

CODE

Figure 7. AD5304 Typical DNL Plot

Figure 8. AD5314 Typical DNL Plot

Figure 9. AD5324 Typical DNL Plot

0.5

1

V

T

= 5V

= 25؇C

V

= 5V

= 3V

V

= 5V

= 2V

REF

DD

0.4

0.3

0.2

0.1

DD

A

REF

MAX INL

0.25

0

0.5

MAX DNL

GAIN ERROR

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

MIN DNL

MIN INL

3

OFFSET ERROR

MIN DNL

MIN INL

–0.25

–0.5

–1

0

1

2

4

5

؊40

0

40

80

120

؊40

0

40

80

120

V

– V

ؠ

REF

TEMPERATURE –

C

TEMPERATURE – C

Figure 10. AD5304 INL and DNL

Error vs. V_REF

Figure 11. AD5304 INL Error and

DNL Error vs. Temperature

Figure 12. AD5304 Offset Error and

Gain Error vs. Temperature

REV. B

–6–

AD5304/AD5314/AD5324

0.2

0.1

5

4

600

ؠ

T

V

= 25 C

= 5V

A

ؠ

T

V

= 25 C

A

DD

5V SOURCE

3V SOURCE

= 2V

500

400

300

200

100

0

REF

= 2V

REF

GAIN ERROR

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

3

2

1

0

OFFSET ERROR

3V SINK

5V SINK

0

1

2

3

4

5

6

0

1

2

3

4

5

6

FULL – SCALE

ZERO – SCALE

V

– Volts

SINK/SOURCE CURRENT – mA

CODE

DD

Figure 13. Offset Error and Gain

Error vs. V_DD

Figure 14. V_OUTSource and Sink

Current Capability

Figure 15. Supply Current vs. DAC

Code

600

0.5

0.4

0.3

1000

ؠ

؊40 C

T = 25؇C

A

500

900

800

700

ؠ

+25 C

ؠ

+105 C

400

300

200

100

0

ؠ

؊40 C

V

= 5V

DD

0.2

ؠ

؉25 C

600

500

400

0.1

V

= 3V

ؠ

DD

؉105 C

0

2.5

3.0

3.5

4.0

– Volts

4.5

5.0

5.5

3.0

3.5

4.0

4.5

5.0

5.5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

– Volts

V

– Volts

DD

V

LOGIC

Figure 16. Supply Current vs. Supply

Voltage

Figure 17. Power-Down Current vs.

Supply Voltage

Figure 18. Supply Current vs. Logic

Input Voltage

ؠ

T

V

= 25 C

= 5V

ؠ

T

V

= 25 C

A

T

V

= 25 C

= 5V

5µs

A

= 5V

DD

= 2V

REF

= 2V

REF

CH1

CH2

CH1

CH2

CH1

CH2

V

A

DD

V

A

OUT

SCLK

V

A

OUT

SCLK

CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV

CH1 1V, CH2 5V, TIME BASE= 1␮s/DIV

CH1 500mV, CH2 5V, TIME BASE= 1␮s/DIV

Figure 19. Half-Scale Settling (1/4 to

3/4 Scale Code Change)

Figure 20. Power-On Reset to 0 V

Figure 21. Exiting Power-Down to

Midscale

REV. B

–7–

AD5304/AD5314/AD5324

2.50

2.49

10

0

–10

–20

–30

V

DD

= 3V

V

DD

= 5V

2.48

2.47

–40

–50

–60

300

350

400

450

– ␮A

500

550

600

0.01

0.1

1

10

100

1k

10k

1␮s/DIV

I

DD

FREQUENCY – kHz

Figure 22. I_DDHistogram with

_DD= 3 V and V_DD= 5 V

Figure 23. AD5324 Major-Code

Transition Glitch Energy

Figure 24. Multiplying Bandwidth

(Small-Signal Frequency Response)

V

0.02

V

DD

= 5V

T

= 25؇C

A

0.01

0

–0.01

–0.02

0

1

2

3

4

5

6

150ns/DIV

V

– Volts

REF

Figure 25. Full-Scale Error vs. V_REF

Figure 26. DAC-to-DAC Crosstalk

REV. B

–8–

AD5304/AD5314/AD5324

FUNCTIONAL DESCRIPTION

DAC Reference Inputs

The AD5304/AD5314/AD5324 are quad resistor-string DACs

fabricated on a CMOS process with resolutions of 8, 10, and 12

bits respectively. Each contains four output buffer ampliﬁers and

is written to via a 3-wire serial interface. They operate from

single supplies of 2.5 V to 5.5 V and the output buffer ampliﬁers

provide rail-to-rail output swing with a slew rate of 0.7 V/µs. The

four DACs share a single reference input pin. The devices have

programmable power-down modes, in which all DACs may be

turned off completely with a high-impedance output.

There is a single reference input pin for the four DACs. The

reference input is unbuffered. The user can have a reference

voltage as low as 0.25 V and as high as V_DDsince there is no

restriction due to headroom and footroom of any reference

ampliﬁer.

It is recommended to use a buffered reference in the external

circuit (e.g., REF192). The input impedance is typically 45 kΩ.

Output Ampliﬁer

The output buffer ampliﬁer is capable of generating rail-to-rail

voltages on its output, which gives an output range of 0 V to V_DD

when the reference is V_DD. It is capable of driving a load of

Digital-to-Analog Section

The architecture of one DAC channel consists of a resistor-string

DAC followed by an output buffer ampliﬁer. The voltage at the

REFIN pin provides the reference voltage for the DAC. Figure

27 shows a block diagram of the DAC architecture. Since the

input coding to the DAC is straight binary, the ideal output

voltage is given by:

2 kΩ to GND or V_DD, in parallel with 500 pF to GND or V_DD

.

The source and sink capabilities of the output ampliﬁer can be

seen in the plot in Figure 14.

The slew rate is 0.7 V/µs with a half-scale settling time to

0.5 LSB (at 8 bits) of 6 µs.

V_REF× D

V_OUT

=

2^N

POWER-ON RESET

The AD5304/AD5314/AD5324 are provided with a power-on

reset function, so that they power up in a deﬁned state. The

power-on state is:

where

D = decimal equivalent of the binary code, which is loaded to the

DAC register;

– Normal operation.

– Output voltage set to 0 V.

0–255 for AD5304 (8 Bits)

0–1023 for AD5314 (10 Bits)

0–4095 for AD5324 (12 Bits)

Both input and DAC registers are ﬁlled with zeros and remain

so until a valid write sequence is made to the device. This is

particularly useful in applications where it is important to know

the state of the DAC outputs while the device is powering up.

N = DAC resolution

REFIN

SERIAL INTERFACE

INPUT

REGISTER

The AD5304/AD5314/AD5324 are controlled over a versatile,

3-wire serial interface, which operates at clock rates up to 30 MHz

and is compatible with SPI, QSPI, MICROWIRE, and DSP

interface standards.

DAC

REGISTER

RESISTOR

STRING

V

A

OUT

OUTPUT BUFFER

AMPLIFIER

Input Shift Register

Figure 27. DAC Channel Architecture

Resistor String

The input shift register is 16 bits wide. Data is loaded into the

device as a 16-bit word under the control of a serial clock input,

SCLK. The timing diagram for this operation is shown in Figure 1.

The 16-bit word consists of four control bits followed by 8, 10,

or 12 bits of DAC data, depending on the device type. Data

is loaded MSB ﬁrst (Bit 15) and the ﬁrst two bits determine

whether the data is for DAC A, DAC B, DAC C, or DAC D.

Bits 13 and 12 control the operating mode of the DAC. Bit 13 is

PD, which determines whether the part is in normal or power-

down mode. Bit 12 is LDAC, which controls when DAC registers

and outputs are updated.

The resistor string section is shown in Figure 28. It is simply a

string of resistors, each of value R. The digital code loaded to the

DAC register determines at which node on the string the voltage

is tapped off to be fed into the output ampliﬁer. The voltage is

tapped off by closing one of the switches connecting the string to

the ampliﬁer. Because it is a string of resistors, it is guaranteed

monotonic.

R

Table I. Address Bits for the AD53x4

TO OUTPUT

AMPLIFIER

R

A1

A0

DAC Addressed

0

1

0

1

0

1

DAC A

DAC B

DAC C

DAC D

R

Figure 28. Resistor String

REV. B

–9–

AD5304/AD5314/AD5324

BIT15

(MSB)

BIT0

(LSB)

A1 A0 PD LDAC D7 D6 D5

D4 D3 D2 D1 D0

DATA BITS

X

Figure 29. AD5304 Input Shift Register Contents

BIT15

(MSB)

BIT0

(LSB)

A1

A0 PD

LDAC

D9 D8 D7

D6 D5 D4 D3 D2 D1 D0

DATA BITS

X

Figure 30. AD5314 Input Shift Register Contents

BIT15

(MSB)

BIT0

(LSB)

A1

A0 PD

LDAC

D11 D10 D9

D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

Figure 31. AD5324 Input Shift Register Contents

Address and Control Bits

Low-Power Serial Interface

PD:

0: All four DACs go into power-down mode consuming

only 200 nA @ 5 V. The DAC outputs enter a high-

impedance state.

To reduce the power consumption of the device even further, the

interface only powers up fully when the device is being written

to, i.e., on the falling edge of SYNC. As soon as the 16-bit control

word has been written to the part, the SCLK and DIN input

buffers are powered down. They only power up again following

a falling edge of SYNC.

1: Normal operation.

LDAC: 0: All four DAC registers and hence all DAC outputs

updated simultaneously on completion of the write

sequence.

Double-Buffered Interface

1: Addressed input register only is updated. There is

no change in the content of the DAC registers.

The AD5304/AD5314/AD5324 DACs all have double-buffered

interfaces consisting of two banks of registers—input registers

and DAC registers. The input register is directly connected to

the input shift register and the digital code is transferred to the

relevant input register on completion of a valid write sequence.

The DAC register contains the digital code used by the resis-

tor string.

The AD5324 uses all 12 bits of DAC data, the AD5314 uses

10 bits and ignores the two LSBs. The AD5304 uses eight bits

and ignores the last four bits. The data format is straight binary,

with all zeros corresponding to 0 V output and all ones corre-

sponding to full-scale output (V_REF–1 LSB).

Access to the DAC register is controlled by the LDAC bit. When

the LDAC bit is set high, the DAC register is latched and hence

the input register may change state without affecting the contents

of the DAC register. However, when the LDAC bit is set low,

all DAC registers are updated after a complete write sequence.

The SYNC input is a level-triggered input that acts as a frame

synchronization signal and chip enable. Data can only be trans-

ferred into the device while SYNC is low. To start the serial data

transfer, SYNC should be taken low, observing the minimum

SYNC to SCLK active edge setup time, t₄. After SYNC goes low,

serial data will be shifted into the device's input shift register on

the falling edges of SCLK for sixteen clock pulses. Any data and

clock pulses after the sixteenth falling edge of SCLK will be

ignored because the SCLK and DIN input buffers are powered

down. No further serial data transfer will occur until SYNC is

taken high and low again.

This is useful if the user requires simultaneous updating of all DAC

outputs. The user may write to three of the input registers indi-

vidually and then, by setting the LDAC bit low when writing

to the remaining DAC input register, all outputs will update

simultaneously.

These parts contain an extra feature whereby the DAC register

is not updated unless its input register has been updated since

the last time that LDAC was brought low. Normally, when LDAC

is brought low, the DAC registers are ﬁlled with the contents of

the input registers. In the case of the AD5304/AD5314/AD5324,

the part will only update the DAC register if the input register

has been changed since the last time the DAC register was

updated, thereby removing unnecessary digital crosstalk.

SYNC may be taken high after the falling edge of the sixteenth

SCLK pulse, observing the minimum SCLK falling edge to

SYNC rising edge time, t₇.

After the end of serial data transfer, data will automatically be

transferred from the input shift register to the input register of

the selected DAC. If SYNC is taken high before the sixteenth

falling edge of SCLK, the data transfer will be aborted and the

DAC input registers will not be updated.

POWER-DOWN MODE

When data has been transferred into three of the DAC input

registers, all DAC registers and all DAC outputs may simulta-

neously be updated by setting LDAC low when writing to the

remaining DAC input register.

The AD5304/AD5314/AD5324 have low power consumption,

dissipating only 1.5 mW with a 3 V supply and 3 mW with a 5 V

supply. Power consumption can be further reduced when the

DACs are not in use by putting them into power-down mode,

which is selected by a zero on Bit 13 (PD) of the control word.

REV. B

–10–

AD5304/AD5314/AD5324

When the PD bit is set to 1, all DACs work normally with a

typical power consumption of 600 µA at 5 V (500 µA at 3 V).

However, in power-down mode, the supply current falls to 200 nA

at 5 V (80 nA at 3 V) when all DACs are powered down. Not

only does the supply current drop, but the output stage is also

internally switched from the output of the ampliﬁer making it

open-circuit. This has the advantage that the output is three-

stated while the part is in power-down mode, and provides a

deﬁned input condition for whatever is connected to the output

of the DAC ampliﬁer. The output stage is illustrated in Figure 32.

AD5304/AD5314/AD5324 to 68HC11/68L11 Interface

Figure 34 shows a serial interface between the AD5304/AD5314/

AD5324 and the 68HC11/68L11 microcontroller. SCK of the

68HC11/68L11 drives the SCLK of the AD5304/AD5314/

AD5324, while the MOSI output drives the serial data line (DIN)

of the DAC. The SYNC signal is derived from a port line (PC7).

The setup conditions for correct operation of this interface are

as follows: the 68HC11/68L11 should be conﬁgured so that its

CPOL bit is a 0 and its CPHA bit is a 1. When data is being

transmitted to the DAC, the SYNC line is taken low (PC7).

When the 68HC11/68L11 is conﬁgured as above, data appearing

on the MOSI output is valid on the falling edge of SCK. Serial

data from the 68HC11/68L11 is transmitted in 8-bit bytes with

only eight falling clock edges occurring in the transmit cycle. Data

is transmitted MSB ﬁrst. In order to load data to the AD5304/

AD5314/AD5324, PC7 is left low after the ﬁrst eight bits are

transferred, a second serial write operation is performed to the

DAC, and PC7 is taken high at the end of this procedure.

The bias generator, the output ampliﬁer, the resistor string, and

all other associated linear circuitry are all shut down when the

power-down mode is activated. However, the contents of the

registers are unaffected when in power-down. The time to exit

power-down is typically 2.5 µs for V_DD= 5 V and 5 µs when

V

_DD= 3 V. This is the time from the falling edge of the sixteenth

SCLK pulse to when the output voltage deviates from its power-

down voltage. See Figure 21 for a plot.

AD5304/

AD5314/

AD5324*

68HC11/68L11*

RESISTOR

STRING DAC

AMPLIFIER

V

OUT

SYNC

PC7

SCK

SCLK

DIN

MOSI

POWER-DOWN

CIRCUITRY

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 32. Output Stage During Power-Down

Figure 34. AD5304/AD5314/AD5324 to 68HC11/68L11

Interface

MICROPROCESSOR INTERFACING

AD5304/AD5314/AD5324 to 80C51/80L51 Interface

AD5304/AD5314/AD5324 to ADSP-2101/ADSP-2103 Interface

Figure 33 shows a serial interface between the AD5304/AD5314/

AD5324 and the ADSP-2101/ADSP-2103. The ADSP-2101/

ADSP-2103 should be set up to operate in the SPORT Transmit

Alternate Framing Mode. The ADSP-2101/ADSP-2103 SPORT

is programmed through the SPORT control register and should

be conﬁgured as follows: Internal Clock Operation, Active-Low

Framing, 16-Bit Word Length. Transmission is initiated by writing

a word to the Tx register after the SPORT has been enabled.

The data is clocked out on each rising edge of the DSP’s serial

clock and clocked into the AD5304/AD5314/AD5324 on the

falling edge of the DAC’s SCLK.

Figure 35 shows a serial interface between the AD5304/AD5314/

AD5324 and the 80C51/80L51 microcontroller. The setup for

the interface is as follows: TxD of the 80C51/80L51 drives SCLK

of the AD5304/AD5314/AD5324, while RxD drives the serial

data line of the part. The SYNC signal is again derived from a

bit-programmable pin on the port. In this case port line P3.3 is

used. When data is to be transmitted to the AD5304/AD5314/

AD5324, P3.3 is taken low. The 80C51/80L51 transmits data

only in 8-bit bytes; thus only eight falling clock edges occur in

the transmit cycle. To load data to the DAC, P3.3 is left low

after the ﬁrst eight bits are transmitted, and a second write cycle

is initiated to transmit the second byte of data. P3.3 is taken high

following the completion of this cycle. The 80C51/80L51 outputs

the serial data in a format which has the LSB ﬁrst. The AD5304/

AD5314/AD5324 requires its data with the MSB as the ﬁrst bit

received. The 80C51/80L51 transmit routine should take this

into account.

AD5304/

AD5314/

AD5324*

ADSP-2101/

ADSP-2103*

SYNC

TFS

DT

DIN

SCLK

AD5304/

AD5314/

AD5324*

80C51/80L51*

*ADDITIONAL PINS OMITTED FOR CLARITY.

SYNC

P3.3

Figure 33. AD5304/AD5314/AD5324 to ADSP-2101/

ADSP-2103 Interface

TxD

RxD

SCLK

DIN

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 35. AD5304/AD5314/AD5324 to 80C51/80L51

Interface

REV. B

–11–

AD5304/AD5314/AD5324

AD5304/AD5314/AD5324 to MICROWIRE Interface

The load regulation of the REF195 is typically 2 ppm/mA, which

results in an error of 5.4 ppm (27 µV) for the 2.7 mA current

drawn from it. This corresponds to a 0.0014 LSB error at 8 bits

and 0.022 LSB error at 12 bits.

Figure 36 shows an interface between the AD5304/AD5314/

AD5324 and any MICROWIRE-compatible device. Serial data is

shifted out on the falling edge of the serial clock, SK and is

clocked into the AD5304/AD5314/AD5324 on the rising edge

of SK, which corresponds to the falling edge of the DAC’s SCLK.

Bipolar Operation Using the AD5304/AD5314/AD5324

The AD5304/AD5314/AD5324 have been designed for single-

supply operation, but a bipolar output range is also possible

using the circuit in Figure 38. This circuit will give an output

voltage range of 5 V. Rail-to-rail operation at the ampliﬁer output

is achievable using an AD820 or an OP295 as the output ampliﬁer.

AD5304/

AD5314/

AD5324*

MICROWIRE*

SYNC

CS

SK

SO

SCLK

DIN

R2 = 10k⍀

+5V

R1 = 10k⍀

6V TO 16V

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD820/

OP295

0.1␮F

10␮F

؎5V

5V

Figure 36. AD5304/AD5314/AD5324 to MICROWIRE

Interface

V

A

B

V

OUT

DD

AD5304

REF195

–5V

APPLICATIONS

Typical Application Circuit

The AD5304/AD5314/AD5324 can be used with a wide range

of reference voltages where the devices offer full, one-quadrant

V

IN

V

OUT

V

OUT

REFIN

GND

1␮F

V

C

D

OUT

multiplying capability over a reference range of 0 V to V_DD

More typically, these devices are used with a ﬁxed, precision

.

GND

DIN

SCLK

SYNC

reference voltage. Suitable references for 5 V operation are the

AD780 and REF192 (2.5 V references). For 2.5 V operation, a

suitable external reference would be the AD589, a 1.23 V band-

gap reference. Figure 37 shows a typical setup for the AD5304/

AD5314/AD5324 when using an external reference.

SERIAL

INTERFACE

Figure 38. Bipolar Operation with the AD5304

V

= 2.5V TO 5.5V

The output voltage for any input code can be calculated as

follows:

DD

10␮F

0.1␮F

V

_OUT= [(REFIN × D/2^N) × (R1+R2)/R1 – REFIN × (R2/R1)]

AD5304/

AD5314/

AD5324

where:

V

IN

V

A

B

D is the decimal equivalent of the code loaded to the DAC.

N is the DAC resolution.

OUT

V

REFIN

OUT

EXT

REF

OUT

1␮F

REFIN is the reference voltage input.

with:

SCLK

DIN

V

C

D

OUT

AD780/REF192

WITH V = 5V

OR AD589 WITH

DD

SYNC

OUT

V

= 2.5V

REFIN = 5 V, R1 = R2 = 10 kΩ:

DD

A0

GND

V

_OUT= (10 × D/2^N) – 5 V

SERIAL

INTERFACE

Opto-Isolated Interface for Process Control Applications

The AD5304/AD5314/AD5324 have a versatile 3-wire serial

interface making them ideal for generating accurate voltages

in process control and industrial applications. Due to noise,

safety requirements or distance, it may be necessary to isolate

the AD5304/AD5314/AD5324 from the controller. This can easily

be achieved by using opto-isolators, which will provide isolation in

excess of 3 kV. The actual data rate achieved may be limited by

the type of optocouplers chosen. The serial loading structure

of the AD5304/AD5314/ AD5324 makes them ideally suited for

use in opto-isolated applications. Figure 39 shows an opto-iso-

lated interface to the AD5304 where DIN, SCLK, and SYNC

are driven from optocouplers. The power supply to the part

also needs to be isolated. This is done by using a transformer. On

the DAC side of the transformer, a 5 V regulator provides the 5 V

supply required for the AD5304.

Figure 37. AD5304/AD5314/AD5324 Using External

Reference

If an output range of 0 V to V_DDis required, the simplest solu-

tion is to connect the reference input to V_DD. As this supply may

not be very accurate and may be noisy, the AD5304/AD5314/

AD5324 may be powered from the reference voltage; for example,

using a 5 V reference such as the REF195. The REF195 will

output a steady supply voltage for the AD5304/AD5314/AD5324.

The current required from the REF195 is 600 µA supply current

and approximately 112 µA into the reference input. This is with no

load on the DAC outputs. When the DAC outputs are loaded, the

REF195 also needs to supply the current to the loads. The total

current required (with a 10 kΩ load on each output) is:

712 µA + 4(5 V/10 kΩ) = 2.70 mA

REV. B

–12–

AD5304/AD5314/AD5324

AD5304/AD5314/AD5324 as a Digitally Programmable

Window Detector

5V

REGULATOR

10␮F

0.1␮F

POWER

A digitally programmable upper/lower limit detector using two

of the DACs in the AD5304/AD5314/AD5324 is shown in

Figure 41. The upper and lower limits for the test are loaded to

DACs A and B which, in turn, set the limits on the CMP04. If

the signal at the V_INinput is not within the programmed window,

an LED will indicate the fail condition. Similarly, DACs C and

D can be used for window detection on a second V_INsignal.

V

DD

10k⍀

V

DD

SCLK

SYNC

DIN

SCLK

REFIN

AD5304

V

5V

10k⍀

V

A

B

C

D

OUT

0.1␮F

10␮F

1k⍀

SYNC

V

IN

FAIL

PASS

V

DD

V

REF

REFIN

V

A

B

OUT

10k⍀

1/2

DIN

AD5304/

AD5314/

AD5324*

1/2

CMP04

PASS/FAIL

SYNC

DIN

GND

DIN

SCLK

V

SCLK

OUT

1/6 74HC05

GND

Figure 39. AD5304 in an Opto-Isolated Interface

*ADDITIONAL PINS OMITTED FOR CLARITY

Decoding Multiple AD5304/AD5314/AD5324s

The SYNC pin on the AD5304/AD5314/AD5324 can be used

in applications to decode a number of DACs. In this application,

all the DACs in the system receive the same serial clock and

serial data, but the SYNC to only one of the devices will be active

at any one time, allowing access to four channels in this 16-

channel system. The 74HC139 is used as a 2-to-4-line decoder

to address any of the DACs in the system. To prevent timing

errors, the enable input should be brought to its inactive state

while the coded address inputs are changing state. Figure 40

shows a diagram of a typical setup for decoding multiple

AD5304 devices in a system.

Figure 41. Window Detection

POWER SUPPLY BYPASSING AND GROUNDING

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure the

rated performance. The printed circuit board on which the

AD5304/AD5314/AD5324 is mounted should be designed so

that the analog and digital sections are separated, and conﬁned

to certain areas of the board. If the AD5304/AD5314/AD5324

is in a system where multiple devices require an AGND-to-DGND

connection, the connection should be made at one point only.

The star ground point should be established as close as possible

to the device. The AD5304/AD5314/AD5324 should have ample

supply bypassing of 10 µF in parallel with 0.1 µF on the supply

located as close to the package as possible, ideally right up against

the device. The 10 µF capacitors are the tantalum bead type. The

0.1 µF capacitor should have low Effective Series Resistance

(ESR) and Effective Series Inductance (ESI), like the common

ceramic types that provide a low impedance path to ground at

high frequencies, to handle transient currents due to internal logic

switching.

SCLK

AD5304

V

A

B

C

D

OUT

DIN

SYNC

V

DD

DIN

SCLK

V

CC

1G

1A

1B

ENABLE

1Y0

1Y1

1Y2

1Y3

AD5304

SYNC

V

A

B

C

D

OUT

CODED

ADDRESS

74HC139

DGND

DIN

SCLK

The power supply lines of the AD5304/AD5314/AD5324 should

use as large a trace as possible to provide low impedance paths

and reduce the effects of glitches on the power supply line. Fast

switching signals such as clocks should be shielded with digital

ground to avoid radiating noise to other parts of the board, and

should never be run near the reference inputs. Avoid crossover

of digital and analog signals. Traces on opposite sides of the

board should run at right angles to each other. This reduces the

effects of feedthrough through the board. A microstrip technique is

by far the best, but not always possible with a double-sided

board. In this technique, the component side of the board is

dedicated to ground plane while signal traces are placed on the

solder side.

AD5304

V

A

B

C

D

SYNC

OUT

DIN

SCLK

AD5304

SYNC

V

A

B

C

D

OUT

DIN

SCLK

Figure 40. Decoding Multiple AD5304 Devices in a System

REV. B

–13–

AD5304/AD5314/AD5324

Table II. Overview of All AD53xx Serial Devices

No. of

DACs

Settling

Time

Part No.

Resolution

DNL

Interface

Package

Pins

SINGLES

AD5300

AD5310

AD5320

8

10

12

1

0.25

0.5

1.0

SPI

4 µs

6 µs

8 µs

SOT-23, microSOIC

6, 8

AD5301

AD5311

AD5321

8

10

12

1

0.25

0.5

1.0

2-Wire

6 µs

7 µs

8 µs

SOT-23, microSOIC

6, 8

DUALS

AD5302

AD5312

AD5322

8

10

12

2

0.25

0.5

1.0

SPI

6 µs

7 µs

8 µs

microSOIC

8

AD5303

AD5313

AD5323

8

10

12

2

0.25

0.5

1.0

SPI

6 µs

7 µs

8 µs

TSSOP

16

QUADS

AD5304

AD5314

AD5324

8

10

12

4

0.25

0.5

1.0

SPI

6 µs

7 µs

8 µs

microSOIC

10

AD5305

AD5315

AD5325

8

10

12

4

0.25

0.5

1.0

2-Wire

6 µs

7 µs

8 µs

microSOIC

10

AD5306

AD5316

AD5326

8

10

12

4

0.25

0.5

1.0

2-Wire

6 µs

7 µs

8 µs

TSSOP

16

AD5307

AD5317

AD5327

8

10

12

4

0.25

0.5

1.0

SPI

6 µs

7 µs

8 µs

TSSOP

16

Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html

REV. B

–14–

AD5304/AD5314/AD5324

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

10-Lead microSOIC

(RM-10)

0.122 (3.10)

0.114 (2.90)

10

6

5

0.199 (5.05)

0.187 (4.75)

0.122 (3.10)

0.114 (2.90)

1

PIN 1

0.0197 (0.50) BSC

0.120 (3.05)

0.112 (2.85)

0.120 (3.05)

0.112 (2.85)

0.037 (0.94)

0.031 (0.78)

0.043 (1.10)

MAX

6؇

SEATING

PLANE

0.006 (0.15) 0.012 (0.30)

0.002 (0.05) 0.006 (0.15)

0؇

0.028 (0.70)

0.016 (0.40)

0.009 (0.23)

0.005 (0.13)

REV. B

–15–


型号：	AD5324ACPZ-WP
厂家：	ADI
描述：	IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, DSO10, LEAD FREE, 3 X 3 MM, LFCSP-10, Digital to Analog Converter
文件：	总15页 (文件大小：227K)
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AD5324ACPZ-WP [ADI]

相关型号：

AD5324ARM

AD5324ARM-REEL7

AD5324ARMZ

AD5324ARMZ-REEL7

AD5324BCPZ-REEL7

AD5324BCPZ-WP

AD5324BRM

AD5324BRM-REEL

AD5324BRM-REEL7

AD5324BRMZ

AD5324BRMZ-REEL

AD5324BRMZ-REEL7