AD5341BRUZ-REEL7 [ADI]
2.5V to 5.5V, 115µA Parallel Interface Single Voltage Output 12-Bit DAC;
| 型号： | AD5341BRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 2.5V to 5.5V, 115µA Parallel Interface Single Voltage Output 12-Bit DAC 光电二极管 转换器 |
| 文件： | 总28页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V to 5.5 V, 115 μA, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330/AD5331/AD5340/AD5341
FEATURES
GENERAL DESCRIPTION
AD5330: single 8-bit DAC in 20-lead TSSOP
AD5331: single 10-bit DAC in 20-lead TSSOP
AD5340: single 12-bit DAC in 24-lead TSSOP
AD5341: single 12-bit DAC in 20-lead TSSOP
Low power operation: 115 μA @ 3 V, 140 μA @ 5 V
The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12-
bit DACs. They operate from a 2.5 V to 5.5 V supply consuming
just 115 μA at 3 V and feature a power-down mode that further
reduces the current to 80 nA. The devices incorporate an on-chip
output buffer that can drive the output to both supply rails, but
PD
Power-down to 80 nA @ 3 V, 200 nA @ 5 V via
2.5 V to 5.5 V power supply
Pin
the AD5330, AD5340, and AD5341 allow a choice of buffered
or unbuffered reference input.
Double-buffered input logic
The AD5330/AD5331/AD5340/AD5341 have a parallel
Guaranteed monotonic by design over all codes
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
CS
interface.
input registers on the rising edge of
The GAIN pin allows the output range to be set at 0 V to VREF or
0 V to 2 × VREF
Input data to the DACs is double-buffered, allowing simultane-
LDAC
selects the device and data is loaded into the
WR
.
LDAC
.
Simultaneous update of DAC outputs via
CLR
pin
Asynchronous
facility
Low power parallel data interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
ous update of multiple DACs in a system using the
pin.
input is also provided, which resets the
CLR
An asynchronous
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
The AD5330/AD5331/AD5340/AD5341 are available in thin
shrink small outline packages (TSSOP).
Industrial process control
1 Protected by U.S. Patent Number 5,969,657.
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
REF
3
12
POWER-ON
RESET
AD5330
BUF
GAIN
DB
1
8
DAC
REGISTER
INPUT
REGISTER
8-BIT
DAC
20
13
4
BUFFER
7
0
V
OUT
.
.
DB
6
7
CS
WR
CLR
RESET
POWER-DOWN
LOGIC
9
10
LDAC
11
5
PD GND
Figure 1. AD5330
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved.
AD5330/AD5331/AD5340/AD5341
TABLE OF CONTENTS
Features .............................................................................................. 1
Double-Buffered Interface ........................................................ 18
CLR
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 13
Theory of Operation ...................................................................... 17
Digital-to-Analog Section......................................................... 17
Resistor String............................................................................. 17
DAC Reference Input................................................................. 17
Output Amplifier........................................................................ 17
Parallel Interface ............................................................................. 18
Clear Input (
Chip Select Input ( )............................................................... 18
WR
) ...................................................................... 18
CS
)....................................................................... 18
LDAC
Write Input (
Load DAC Input (
).......................................................... 18
High-Byte Enable Input (HBEN)............................................. 18
Power-On Reset.......................................................................... 18
Power-Down Mode ........................................................................ 19
Suggested Databus Formats .......................................................... 20
Applications Information.............................................................. 21
Typical Application Circuits ..................................................... 21
Driving VDD From the Reference Voltage ............................... 21
Bipolar Operation Using the AD5330/AD5331/
AD5340/AD5341......................................................................... 21
Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21
Programmable Current Source ................................................ 22
Power Supply Bypassing and Grounding................................ 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 25
REVISION HISTORY
2/08—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Table 4.......................................................................... 16
Replaced Driving VDD from the Reference Voltage Section ..... 21
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 25
4/00—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD5330/AD5331/AD5340/AD5341
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
B Version2
Parameter1
DC PERFORMANCE3, 4
Min Typ
Max
Unit
Conditions/Comments
AD5330
Resolution
8
Bits
LSB
0.25 LSB
Relative Accuracy
Differential Nonlinearity
AD533ꢀ
0.ꢀ5
0.02
ꢀ
Guaranteed monotonic by design over all codes
Guaranteed monotonic by design over all codes
Guaranteed monotonic by design over all codes
Resolution
ꢀ0
0.5
0.05
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5340/AD534ꢀ
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
4
0.5
ꢀ2
2
0.2
0.4
0.ꢀ5
ꢀ0
ꢀ0
−ꢀ2
−5
−10
Bits
LSBs
LSB
% of FSR
% of FSR
mV
ꢀ1
ꢀ
3
ꢀ
10
Gain Error
Lower Deadband5
Upper Deadband
Offset Error Drift1
Gain Error Drift1
DC Power Supply Rejection Ratio1
DAC REFERENCE INPUT1
VREF Input Range
Lower deadband exists only if offset error is negative
VDD = 5 V; upper deadband exists only if VREF = VDD
10
mV
ppm of FSR/°C
ppm of FSR/°C
dB
ΔVDD = ꢀ0%
ꢀ
0.25
VDD
VDD
V
V
Buffered reference (AD5330, AD5340, and AD534ꢀ)
Unbuffered reference
VREF Input Impedance
>ꢀ0
ꢀ80
90
MΩ
kΩ
kΩ
dB
Buffered reference (AD5330, AD5340, and AD534ꢀ)
Unbuffered reference; gain = ꢀ, input impedance = RDAC
Unbuffered reference; gain = 2, input impedance = RDAC
Frequency = ꢀ0 kHz
Reference Feedthrough
OUTPUT CHARACTERISTICS1
Minimum Output Voltage4, 7
Maximum Output Voltage4, 7
DC Output Impedance
−90
0.00ꢀ
VDD − 0.00ꢀ
V min
V max
Ω
mA
mA
μs
Rail-to-rail operation
0.5
25
ꢀ5
2.5
5
Short-Circuit Current
VDD = 5 V
VDD = 3 V
Power-Up Time
Coming out of power-down mode; VDD = 5 V
Coming out of power-down mode; VDD = 3 V
μs
LOGIC INPUTS1
Input Current
Input Low Voltage, VIL
ꢀ
μA
V
V
0.8
0.1
0.5
VDD = 5 V ꢀ0%
VDD = 3 V ꢀ0%
VDD = 2.5 V
V
Input High Voltage, VIH
Pin Capacitance
2.4
2.ꢀ
2.0
V
V
V
pF
VDD = 5 V ꢀ0%
VDD = 3 V ꢀ0%
VDD = 2.5 V
3
Rev. A | Page 3 of 28
AD5330/AD5331/AD5340/AD5341
B Version2
Min Typ
Parameter1
Max
Unit
Conditions/Comments
POWER REQUIREMENTS
VDD
2.5
5.5
V
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.1 V
DACs active and excluding load currents. Unbuffered
Reference, VIH = VDD, VIL = GND
IDD increases by 50 μA at VREF > VDD − ꢀ00 mV.
ꢀ40
ꢀꢀ5
250
200
μA
μA
In buffered mode, extra current is (5 + VREF/RDAC) μA,
where RDAC is the resistance of the resistor string.
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.1 V
0.2
0.08
ꢀ
ꢀ
μA
μA
ꢀ See the Terminology section.
2 Temperature range: B Version: −40°C to +ꢀ05°C; typical specifications are at 25°C.
3 Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD533ꢀ (Code 28 to Code ꢀ023); AD5340/AD534ꢀ (Code ꢀꢀ5 to Code 4095).
4 DC specifications tested with output unloaded.
5 This corresponds to x codes. x = deadband voltage/LSB size.
1 Guaranteed by design and characterization, not production tested.
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus
gain error must be positive.
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Version3
Min Typ Max
Parameter2
Unit
Conditions/Comments
Output Voltage Settling Time
AD5330
AD533ꢀ
AD5340
AD534ꢀ
VREF = 2 V; see Figure 29
1
7
8
8
8
9
ꢀ0
ꢀ0
μs
μs
μs
μs
¼ scale to ¾ scale change (0x40 to 0xC0)
¼ scale to ¾ scale change (0xꢀ00 to 0x300)
¼ scale to ¾ scale change (0x400 to 0xC00)
¼ scale to ¾ scale change (0x400 to 0xC00)
Slew Rate
0.7
1
0.5
200
−70
V/μs
nV/s
nV/s
kHz
dB
Major Code Transition Glitch Energy
Digital Feedthrough
Multiplying Bandwidth
Total Harmonic Distortion
ꢀ LSB change around major carry
VREF = 2 V 0.ꢀ V p-p; unbuffered mode
VREF = 2.5 V 0.ꢀ V p-p; frequency = ꢀ0 kHz
ꢀ Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range: B Version: −40°C to +ꢀ05°C; typical specifications are at 25°C.
Rev. A | Page 4 of 28
AD5330/AD5331/AD5340/AD5341
TIMING CHARACTERISTICS1, 2, 3
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Condition/Comments
tꢀ
0
ns min
CS to WR setup time.
t2
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR hold time.
t3
20
5
4.5
5
WR pulse width.
t4
t5
t1
Data, GAIN, BUF, HBEN setup time.
Data, GAIN, BUF, HBEN hold time.
Synchronous mode; WR falling to LDAC falling.
Synchronous mode; LDAC falling to WR rising.
Synchronous mode; WR rising to LDAC rising.
Asynchronous mode; LDAC rising to WR rising.
Asynchronous mode; WR rising to LDAC falling.
LDAC pulse width.
t7
5
t8
4.5
5
t9
tꢀ0
tꢀꢀ
tꢀ2
tꢀ3
4.5
20
20
50
CLR pulse width.
Time between WR cycles.
ꢀ Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 5 ns (ꢀ0% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
t1
t2
CS
t3
t13
WR
t5
t4
DATA,
GAIN,
BUF,
HBEN
t8
t6
t7
t9
1
LDAC
t10
t11
2
LDAC
t12
CLR
NOTES:
1
2
SYNCHRONOUS LDAC UPDATE MODE
ASYNCHRONOUS LDAC UPDATE MODE
Figure 2. Parallel Interface Timing Diagram
Rev. A | Page 5 of 28
AD5330/AD5331/AD5340/AD5341
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input Voltage to GND
VOUT to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
TSSOP Package
ESD CAUTION
−40°C to +ꢀ05°C
−15°C to +ꢀ50°C
ꢀ50°C
Power Dissipation
(TJ max – TA)/θJA mW
θJA Thermal Impedance (20-Lead TSSOP)ꢀ 85°C/W
θJA Thermal Impedance (24-Lead TSSOP)ꢀ 80°C/W
Reflow Soldering
Peak Temperature
210°C
Time at Peak Temperature
20 sec to 40 sec
ꢀ Thermal resistance (JEDEC 4-layer (2S2P) board).
Rev. A | Page 1 of 28
AD5330/AD5331/AD5340/AD5341
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
V
DD
REF
3
12
POWER-ON
RESET
AD5330
BUF
1
8
1
2
20
19
18
17
16
15
14
13
12
11
BUF
NC
DB
DB
DB
DB
DB
DB
DB
DB
7
6
DAC
REGISTER
INPUT
REGISTER
GAIN
8-BIT
DAC
DB 20
4
BUFFER
7
0
V
OUT
.
.
V
3
REF
OUT
5
13
DB
8-BIT
AD5330
TOP VIEW
V
4
4
6
CS
5
GND
CS
3
(Not to Scale)
7
6
WR
CLR
2
RESET
7
WR
POWER-DOWN
LOGIC
1
9
8
GAIN
CLR
LDAC
0
10
LDAC
9
V
DD
10
PD
11
5
PD GND
NC = NO CONNECT
Figure 3. AD5330 Functional Block Diagram
Figure 4. AD5330 Pin Configuration
Table 5. AD5330 Pin Function Descriptions
Pin No.
Mnemonic
BUF
NC
Description
ꢀ
2
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
No Connect.
3
VREF
Reference Input.
4
5
VOUT
GND
CS
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
1
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
7
WR
8
9
GAIN
CLR
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
.
ꢀ0
ꢀꢀ
ꢀ2
LDAC
PD
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
ꢀ0 μF capacitor in parallel with a 0.ꢀ μF capacitor to GND.
ꢀ3 to 20
DB0 to DB7
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
Rev. A | Page 7 of 28
AD5330/AD5331/AD5340/AD5341
V
V
DD
REF
3
12
POWER-ON
RESET
AD5331
DB
DB
1
2
8
9
DAC
REGISTER
INPUT
REGISTER
GAIN
DB
8
1
2
20
19
18
17
16
15
14
13
12
11
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
8
9
7
6
10-BIT
DAC
20
13
4
BUFFER
7
0
V
OUT
.
.
DB
V
3
REF
OUT
5
6
7
10-BIT
AD5331
TOP VIEW
CS
V
4
4
5
GND
CS
3
WR
CLR
(Not to Scale)
RESET
6
2
POWER-DOWN
LOGIC
9
7
WR
1
10
LDAC
8
GAIN
CLR
LDAC
0
9
V
DD
11
5
10
PD
PD GND
Figure 5. AD5331 Functional Block Diagram
Figure 6. AD5331 Pin Configuration
Table 6. AD5331 Pin Function Descriptions
Pin No.
Mnemonic
Description
ꢀ
DB8
Parallel Data Input.
2
DB9
Most Significant Bit of Parallel Data Input.
Unbuffered Reference Input.
3
VREF
4
VOUT
GND
CS
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
5
1
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
7
WR
8
GAIN
CLR
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF
Active low control input that clears all input registers and DAC registers to zero.
.
9
ꢀ0
ꢀꢀ
ꢀ2
LDAC
PD
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
ꢀ0 μF capacitor in parallel with a 0.ꢀ μF capacitor to GND.
ꢀ3 to 20 DB0 to DB7
Eight Parallel Data Inputs.
Rev. A | Page 8 of 28
AD5330/AD5331/AD5340/AD5341
V
V
DD
REF
4
14
POWER-ON
RESET
AD5340
DB
DB
1
2
3
10
11
1
2
24
23
22
21
20
19
18
DB
DB
DB
DB
DB
DB
DB
DB
DB
9
8
10
11
BUF
DAC
REGISTER
INPUT
REGISTER
GAIN 10
12-BIT
DAC
5
3
BUF
BUFFER
V
OUT
7
6
5
4
3
2
1
0
DB 24
9
.
.
4
V
REF
OUT
NC
15
8
DB
0
12-BIT
AD5340
TOP VIEW
V
5
CS
6
9
WR
CLR
(Not to Scale)
7
GND
CS
RESET
POWER-DOWN
LOGIC
11
12
8
17 DB
16 DB
15 DB
9
WR
LDAC
10
11
12
GAIN
CLR
LDAC
14
V
DD
13
7
13
PD
PD GND
Figure 7. AD5340 Functional Block Diagram
Figure 8. AD5340 Pin Configuration
Table 7. AD5340 Pin Function Descriptions
Pin No.
Mnemonic
DBꢀ0
DBꢀꢀ
Description
ꢀ
2
3
4
5
1
7
Parallel Data Input.
Most Significant Bit of Parallel Data Input.
BUF
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
VREF
Reference Input.
VOUT
Output of DAC. Buffered output with rail-to-rail operation.
No Connect.
Ground reference point for all circuitry on the part.
NC
GND
8
CS
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
9
WR
ꢀ0
ꢀꢀ
ꢀ2
ꢀ3
ꢀ4
GAIN
CLR
LDAC
PD
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
.
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
ꢀ0 μF capacitor in parallel with a 0.ꢀ μF capacitor to GND.
ꢀ5 to 24 DB0 to DB9
Ten Parallel Data Inputs.
Rev. A | Page 9 of 28
AD5330/AD5331/AD5340/AD5341
V
V
DD
REF
3
12
POWER-ON
RESET
AD5341
HIGH BYTE
REGISTER
BUF
2
8
GAIN
1
2
20
19
18
17
16
15
14
13
12
11
HBEN
BUF
DB
DB
DB
DB
DB
DB
DB
DB
7
6
DB 20
7
.
LOW BYTE
REGISTER
12-BIT
DAC
.
4
BUFFER
V
OUT
13
DB
0
V
3
REF
5
10-BIT
AD5341
TOP VIEW
1
V
4
HBEN
OUT
4
5
GND
CS
3
6
CS
(Not to Scale)
6
RESET
2
POWER-DOWN
LOGIC
7
WR
7
WR
1
9
CLR
8
GAIN
CLR
LDAC
0
10
LDAC
9
V
DD
11
5
10
PD
PD GND
Figure 9. AD5341 Functional Block Diagram
Figure 10. AD5341 Pin Configuration
Table 8. AD5341 Pin Function Descriptions
Pin No.
Mnemonic
Description
ꢀ
HBEN
High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high
byte register or the low byte register.
2
BUF
VREF
VOUT
GND
CS
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
3
4
5
1
Ground reference point for all circuitry on the part.
Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
7
WR
8
9
GAIN
CLR
LDAC
PD
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
.
ꢀ0
ꢀꢀ
ꢀ2
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
ꢀ0 μF capacitor in parallel with a 0.ꢀ μF capacitor to GND.
ꢀ3 to 20 DB0 to DB7
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
Rev. A | Page ꢀ0 of 28
AD5330/AD5331/AD5340/AD5341
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or INL is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the actual endpoints of the DAC transfer function.
Typical INL vs. code plots can be seen in Figure 14, Figure 15,
and Figure 16.
GAIN ERROR
AND
OFFSET ERROR
OUTPUT
VOLTAGE
Differential Nonlinearity (DNL)
ACTUAL
IDEAL
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of 1 LSB maximum ensures mono-
tonicity. This DAC is guaranteed monotonic by design. Typical
DNL vs. code plots can be seen in Figure 17, Figure 18, and
Figure 19.
POSITIVE
OFFSET
Gain Error
DAC CODE
This is a measure of the span error of the DAC (including any
error in the gain of the buffer amplifier). It is the deviation in
slope of the actual DAC transfer characteristic from the ideal,
expressed as a percentage of the full-scale range. This is
illustrated in Figure 11.
Figure 12. Positive Offset Error and Gain Error
GAIN ERROR
AND
OFFSET ERROR
Offset Error
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
If the offset voltage is positive, the output voltage is still positive
at zero input code. This is shown in Figure 12. Because the
DACs operate from a single supply, a negative offset cannot
appear at the output of the buffer amplifier. Instead, there is
a code close to zero at which the amplifier output saturates
(amplifier footroom). Below this code, there is a deadband over
which the output voltage does not change. This is illustrated in
Figure 13.
OUTPUT
VOLTAGE
ACTUAL
IDEAL
NEGATIVE
OFFSET
DAC CODE
POSITIVE
GAIN ERROR
NEGATIVE
GAIN ERROR
DEADBAND CODES
AMPLIFIER
FOOTROOM
(~1mV)
OUTPUT
VOLTAGE
ACTUAL
IDEAL
NEGATIVE
OFFSET
DAC CODE
Figure 13. Negative Offset Error and Gain Error
Figure 11. Gain Error
Rev. A | Page ꢀꢀ of 28
AD5330/AD5331/AD5340/AD5341
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital Feedthrough
Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
CS
device; it is measured when the DAC is not being written to (
held high). It is specified in nV/s and is measured with a full-
scale change on the digital input pins, that is, from all 0s to all
1s and vice versa.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Power-Supply Rejection Ratio (PSRR)
Multiplying Bandwidth
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V and VDD is varied 10ꢀ.
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with a full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
Total Harmonic Distortion (THD)
This is the difference between an ideal sine wave and its atte-
nuated version using the DAC. The sine wave is used as the
reference for the DAC and THD is a measure of the harmonics
present on the DAC output. It is measured in decibels.
LDAC
updated (that is,
is high). It is expressed in decibels.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the DAC changes state. It
is normally specified as the area of the glitch in nV/s and is
measured when the digital code is changed by 1 LSB at the
major carry transition (011 … 11 to 100 … 00 or 100 … 00
to 011 … 11).
Rev. A | Page ꢀ2 of 28
AD5330/AD5331/AD5340/AD5341
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.3
T
V
= 25°C
A
T
V
= 25°C
A
= 5V
DD
= 5V
DD
0.2
0.1
0.5
0
0
–0.1
–0.2
–0.3
–0.5
–1.0
0
0
0
50
100
150
200
250
1000
4000
0
0
0
50
100
150
200
250
1000
4000
CODE
CODE
Figure 14. AD5330 Typical INL Plot
Figure 17. AD5330 Typical DNL Plot
3
2
0.6
0.4
T
V
= 25°C
T
V
= 25°C
A
A
= 5V
= 5V
DD
DD
1
0.2
0
–1
–2
0
–0.2
–0.4
–0.6
–3
200
400
500
800
200
400
600
800
CODE
CODE
Figure 15. AD5331 Typical INL Plot
Figure 18. AD5331 Typical DNL Plot
12
8
1.0
0.5
T
V
= 25°C
= 5V
A
T
V
= 25°C
A
DD
= 5V
DD
4
0
0
–4
–8
–12
–0.5
–1.0
1000
2000
3000
1000
2000
3000
CODE
CODE
Figure 16. AD5340/AD5341 Typical INL Plot
Figure 19. AD5340/AD5341 Typical DNL Plot
Rev. A | Page ꢀ3 of 28
AD5330/AD5331/AD5340/AD5341
1.00
0.2
0.1
T
V
= 25°C
= 5V
A
T
= 25°C
DD
A
0.75
0.50
0.25
0
V
= 2V
REF
0
GAIN ERROR
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
MAX INL
MAX DNL
MIN DNL
–0.25
–0.50
–0.75
–1.00
MIN INL
OFFSET ERROR
2
3
4
5
0
1
2
3
4
5
6
V
(V)
V
(V)
REF
DD
Figure 20. AD5330 INL and DNL Error vs. VREF
Figure 23. Offset Error and Gain Error vs. VDD
5
4
3
2
1
0
1.00
0.75
0.50
0.25
0
V
V
= 5V
DD
= 3V
REF
5V SOURCE
3V SOURCE
MAX DNL
MAX INL
–0.25
–0.50
–0.75
–1.00
MIN DNL
MIN INL
3V SINK
5V SINK
–40
0
40
TEMPERATURE (°C)
80
120
0
1
2
3
4
5
6
SINK/SOURCE CURRENT (mA)
Figure 21. AD5330 INL Error and DNL Error vs. Temperature
Figure 24. VOUT Source and Sink Current Capability
1.0
300
250
200
150
100
50
V
V
= 5V
= 2V
T
V
= 25°C
= 2V
DD
REF
A
REF
V
V
= 5.5V
= 3.6V
DD
0.5
0
GAIN ERROR
DD
OFFSET ERROR
–0.5
–1.0
–40
0
0
40
80
120
ZERO-SCALE
FULL-SCALE
TEMPERATURE (°C)
DAC CODE
Figure 22. AD5330 Offset Error and Gain Error vs. Temperature
Figure 25. Supply Current vs. DAC Code
Rev. A | Page ꢀ4 of 28
AD5330/AD5331/AD5340/AD5341
300
200
100
0
T
= 25°C
A
T
= 25°C
DD
A
V
= 5V
CH2
5V
CLK
V
OUT
CH1
1V
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
TIME BASE = 5µs/DIV
DD
Figure 26. Supply Current vs. Supply Voltage
Figure 29. Half-Scale Settling (¼ to ¾ Scale Code Change)
0.5
0.4
0.3
0.2
0.1
0
T
= 25°C
A
T
V
V
= 25°C
A
= 5V
DD
= 2V
REF
CH1
2V
V
DD
V
A
OUT
CH2
200mV
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
TIME BASE = 200µs/DIV
DD
Figure 27. Power-Down Current vs. Supply Voltage
Figure 30. Power-On Reset to 0 V
1800
1600
1400
1200
1000
800
600
400
200
0
T
= 25°C
A
T
V
V
= 25°C
A
= 5V
DD
= 2V
REF
CH1
500mV
V
= 5V
DD
V
A
OUT
PD
CH2
5V
V
= 3V
DD
0
1
2
3
4
5
V
(V)
TIME BASE = 1µs/DIV
LOGIC
Figure 28. Supply Current vs. Logic Input Voltage
Figure 31. Exiting Power-Down to Midscale
Rev. A | Page ꢀ5 of 28
AD5330/AD5331/AD5340/AD5341
10
0
–10
–20
–30
–40
–50
–60
V
= 3V
DD
V
= 5V
DD
80 90 100 110 120 130 140 150 160 170 180 190 200
(µA)
0.01
0.1
1
10
100
1k
10k
I
FREQUENCY (kHz)
DD
Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V
Figure 34. Multiplying Bandwidth (Small-Signal Frequency Response)
0.4
0.917
0.916
0.915
0.914
0.913
0.912
0.911
0.910
0.909
0.908
0.907
0.906
0.905
0.904
0.903
T
= 25°C
A
V
= 5V
DD
0.2
0
–0.2
0
1
2
3
4
5
V
(V)
250ns/DIV
REF
Figure 33. AD5340 Major-Code Transition Glitch Energy
Figure 35. Full-Scale Error vs. VREF
Rev. A | Page ꢀ1 of 28
AD5330/AD5331/AD5340/AD5341
THEORY OF OPERATION
V
REF
The AD5330/AD5331/AD5340/AD5341 are single resistor-
string DACs fabricated on a CMOS process with resolutions
of 8, 10, and 12 bits, respectively. They are written to using a
parallel interface. They operate from single supplies of 2.5 V to
5.5 V and the output buffer amplifiers offer rail-to-rail output
swing. The AD5330, AD5340, and AD5341 have a reference
input that can be buffered to draw virtually no current from
the reference source. The reference input of the AD5331 is
unbuffered. The devices have a power-down feature that
reduces current consumption to only 80 nA @ 3 V.
R
R
R
TO OUTPUT
AMPLIFIER
R
R
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 36 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
Figure 37. Resistor String
DAC REFERENCE INPUT
There is a reference input pin for the DAC. The reference
input is buffered on the AD5330, AD5340, and AD5341 but
can be configured as unbuffered also. The reference input of
the AD5331 is unbuffered. The buffered/unbuffered option is
controlled by the BUF pin.
D
VOUT = VREF
×
×Gain
2N
where:
In buffered mode (BUF = 1), the current drawn from an
external reference voltage is virtually zero because the
impedance is at least 10 MΩ. The reference input range is
1 V to 5 V with a 5 V supply.
D is the decimal equivalent of the binary code, which is loaded
to the DAC register:
0 to 255 for AD5330 (8 Bits)
0 to 1023 for AD5331 (10 Bits)
0 to 4095 for AD5340/AD5341 (12 Bits)
In unbuffered mode (BUF = 0), the user can have a reference
voltage as low as 0.25 V and as high as VDD because there is no
restriction due to headroom and footroom of the reference
amplifier. The impedance is still large at typically 180 kΩ for
0 V to VREF mode and 90 kΩ for 0 V to 2 × VREF mode. If there is
an external buffered reference (for example, REF192), there is
no need to use the on-chip buffer.
N is the DAC resolution.
Gain is the output amplifier gain (1 or 2).
V
REF
REFERENCE
BUFFER
BUF
OUTPUT AMPLIFIER
GAIN
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on VREF, GAIN, the load on VOUT, and offset error.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
OUT
OUTPUT
BUFFER AMPLIFIER
If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to VREF
.
Figure 36. Single DAC Channel Architecture
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 × VREF. However, because of clamping, the maximum
output is limited to VDD – 0.001 V.
RESISTOR STRING
The resistor-string section is shown in Figure 37. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
The output amplifier is capable of driving a load of 2 kΩ to
GND or 2 kΩ to VDD in parallel with 500 pF to GND or 500 pF
to VDD. The source and sink capabilities of the output amplifier
can be seen in Figure 24.
The slew rate is 0.7 V/μs with a half-scale settling time to
0.5 ꢀSB (at eight bits) of 6 μs with the output unloaded (see
Figure 29).
Rev. A | Page 17 of 28
AD5330/AD5331/AD5340/AD5341
PARALLEL INTERFACE
LOAD DAC INPUT (LDAC)
The AD5330, AD5331, and AD5340 load their data as a single
8-, 10-, or 12-bit word, while the AD5341 loads data as a low
byte of eight bits and a high byte containing four bits.
LDAC
transfers data from the input register to the DAC register
LDAC
(and therefore updates the outputs). Use of the
function
enables double-buffering of the DAC data, GAIN, and BUF.
LDAC
DOUBLE-BUFFERED INTERFACE
There are two
asynchronous mode.
In synchronous mode, the DAC register is updated after new
WR LDAC
can
modes: synchronous mode and
The AD5330/AD5331/AD5340/AD5341 DACs all have double-
buffered interfaces consisting of an input register and a DAC
register. DAC data, BUF, and GAIN inputs are written to the
CS
WR
input register under the control of chip select ( ) and write (
).
data is read in on the rising edge of the
be tied permanently low or pulsed, as shown in Figure 2.
In asynchronous mode, the outputs are not updated at the same
LDAC
input.
LDAC
Access to the DAC register is controlled by the
function.
is high, the DAC register is latched and the input
register may change state without affecting the contents of the
LDAC
LDAC
When
time that the input register is written to. When
goes low,
the DAC register is updated with the contents of the input
register.
DAC register. However, when
is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it. The gain and buffer control signals
are also double-buffered and are only updated when
taken low.
HIGH BYTE ENABLE INPUT (HBEN)
LDAC
is
High byte enable is a control input on the AD5341 only. It
determines if data is written to the high byte input register
or the low byte input register.
Double-buffering is also useful where the DAC data is loaded
in two bytes, as in the AD5341, because it allows the whole
data word to be assembled in parallel before updating the DAC
register. This prevents spurious outputs that can occur if the DAC
register is updated with only the high byte or the low byte.
The low data byte of the AD5341 consists of Data Bits [0:7]
at the data inputs DB0 to DB7, whereas the high byte consists
of Data Bits [8:11] at the data inputs DB0 to DB3, as shown in
Figure 38. DB4 to DB7 are ignored during a high byte write, but
they can be used for data to set up the reference input as buffered/
unbuffered, and buffer amplifier gain (see Figure 42).
HIGH BYTE
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
LDAC
the last time that
was brought low. Normally, when
LDAC
is brought low, the DAC register is filled with the
X
X
X
X
DB
DB
DB
DB
11
10
9
8
contents of the input register. In the case of the AD5330/
AD5331/AD5340/AD5341, the parts only update the DAC
register if the input register has been changed since the last time
the DAC register was updated. This removes unnecessary crosstalk.
LOW BYTE
DB DB
DB
DB
DB
DB
DB
1
DB
7
6
5
4
3
2
0
X = UNUSED BIT
Figure 38. Data Format for AD5341
CLEAR INPUT (CLR)
POWER-ON RESET
CLR
is an active low, asynchronous clear that resets the input
The AD5330/AD5331/AD5340/AD5341 are provided with a
power-on reset function, so that they power up in a defined
state. The power-on state is
and DAC registers.
CHIP SELECT INPUT (CS)
CS
is an active low input that selects the device.
•
•
•
•
Normal operation
WRITE INPUT (WR)
Reference input unbuffered
0 V to VREF output range
Output voltage set to 0 V
WR
is an active low input that controls writing of data to the
device. Data is latched into the input register on the rising
WR
edge of
.
Both input and DAC registers are filled with zeros and remain
as such until a valid write sequence is made to the device. This
is particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
Rev. A | Page ꢀ8 of 28
AD5330/AD5331/AD5340/AD5341
POWER-DOWN MODE
The AD5330/AD5331/AD5340/AD5341 have low power
consumption, dissipating only 0.35 mW with a 3 V supply and
0.7 mW with a 5 V supply. Power consumption can be further
reduced when the DAC is not in use by putting it into power-
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
POWER-DOWN
CIRCUITRY
PD
down mode, which is selected by taking Pin
low.
Figure 39. Output Stage During Power-Down
PD
When the
pin is high, the DAC works normally with a
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 μs for VDD = 5 V and 5 μs when
PD
typical power consumption of 140 μA at 5 V (115 μA at 3 V).
In power-down mode, however, the supply current falls to
200 nA at 5 V (80 nA at 3 V) when the DAC is powered down.
Not only does the supply current drop, but the output stage
is also internally switched from the output of the amplifier,
making it open-circuit. This has the advantage that the output
is three-state while the part is in power-down mode and provides
a defined input condition for whatever is connected to the
output of the DAC amplifier. The output stage is illustrated in
Figure 39.
VDD = 3 V. This is the time from a rising edge on the
pin to
when the output voltage deviates from its power-down voltage
(see Figure 31).
Table 9. AD5330/AD5331/AD5340 Truth Table1
CLR
LDAC
CS
WR
Function
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X
ꢀ
0
0
ꢀ
X
X
0
0
X
X
No data transfer
ꢀ
X
No data transfer
Clear all registers
Load input register
Load input register and DAC register
Update DAC register
0→ꢀ
0→ꢀ
X
ꢀ X = don’t care.
Table 10. AD5341 Truth Table1
CLR
LDAC
CS
WR
HBEN
Function
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
X
ꢀ
ꢀ
0
0
0
ꢀ
X
X
0
0
0
0
X
X
X
X
X
0
ꢀ
0
ꢀ
X
No data transfer
ꢀ
X
No data transfer
Clear all registers
Load low byte input register
Load high byte input register
Load low byte input register and DAC register
Load high byte input register and DAC register
Update DAC register
0→ꢀ
0→ꢀ
0→ꢀ
0→ꢀ
X
ꢀ X = don’t care.
Rev. A | Page ꢀ9 of 28
AD5330/AD5331/AD5340/AD5341
SUGGESTED DATABUS FORMATS
The AD5341 is a 12-bit device that uses byte load, so only four
bits of the high byte are actually used as data. Two of the unused
bits can be used for GAIN and BUF data by connecting them to
the GAIN and BUF inputs; for example, Bit 6 and Bit 7, as
shown in Figure 41 and Figure 42.
In most applications, GAIN and BUF are hard-wired. However,
if more flexibility is required, they can be included in a databus.
This enables the user to software program GAIN, giving the
option of doubling the resolution in the lower half of the DAC
range. In a bused system, GAIN and BUF can be treated as data
inputs because they are written to the device during a write
8-BIT
DATA BUS
DATA
LDAC
operation and take effect when
is taken low. This means
INPUTS
DB DB
6
7
that the reference buffers and the output amplifier gain of
multiple DAC devices can be controlled using common GAIN
and BUF lines.
BUF
AD5341
GAIN
LDAC
CLR
CS
In the case of the AD5330, this means that the databus must be
wider than eight bits. The AD5331 and AD5340 databuses must
be at least 10 bits and 12 bits wide, respectively, and are best
suited to a 16-bit databus system.
WR
HBEN
Figure 41. AD5341 Data Format for Byte Load with GAIN and BUF Data
on 8-Bit Bus
Examples of data formats for putting GAIN and BUF on a
16-bit databus are shown in Figure 40. Note that any unused bits
above the actual DAC data can be used for BUF and GAIN. DAC
devices can be controlled using common GAIN and BUF lines.
In this case, the low byte is written to first in a write operation
with HBEN = 0. Bit 6 and Bit 7 of DAC data are written into
GAIN and BUF registers but have no effect. The high byte is
then written to. Only the lower four bits of data are written into
the DAC high byte register, so Bit 6 and Bit 7 can be GAIN and
BUF data.
AD5330
X
DB
BUF GAIN
BUF GAIN
BUF GAIN
X
X
X
X
X
X
X
DB
DB DB DB DB DB
4 3 2 1
5
DB
6
7
0
AD5331
X
X
X
DB DB DB DB DB DB DB DB DB DB
9 8 7 6 5 4 3 2 1
0
AD5340
LDAC
is used to update the DAC, GAIN, and BUF values.
X
DB DB DB DB DB DB DB DB DB DB DB DB
11 10
9
8
7
6
5
4
3
2
1
0
X = UNUSED BIT
HIGH BYTE
BUF
GAIN
X
X
DB
DB
DB
DB
11
10
9
8
Figure 40. GAIN and BUF Data on a 16-Bit Bus
LOW BYTE
DB
DB
DB
2
DB
DB
6
DB
DB
1
DB
5
4
7
3
0
X = UNUSED BIT
Figure 42. AD5341 with GAIN and BUF Data on 8-Bit Bus
Rev. A | Page 20 of 28
AD5330/AD5331/AD5340/AD5341
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUITS
BIPOLAR OPERATION USING THE AD5330/AD5331/
AD5340/AD5341
The AD5330/AD5331/AD5340/AD5341 can be used with
a wide range of reference voltages, especially if the reference
inputs are configured to be unbuffered, in which case the
devices offer full, one-quadrant multiplying capability over a
reference range of 0.25 V to VDD. More typically, these devices
can be used with a fixed, precision reference voltage. Figure 43
shows a typical setup for the devices when using an external
reference connected to the unbuffered reference inputs. If the
reference inputs are unbuffered, the reference input range is
from 0.25 V to VDD, but if the on-chip reference buffers are
used, the reference range is reduced. Suitable references for 5 V
operation are the AD780 and REF192. For 2.5 V operation, a
suitable external reference is the AD589, a 1.23 V band gap
reference.
The AD5330/AD5331/AD5340/AD5341 are designed for
single-supply operation, but bipolar operation is achievable
using the circuit shown in Figure 45. The circuit shown has
been configured to achieve an output voltage range of –5 V <
VO < +5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as follows:
VO = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] –
R4 × VREF/R3
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
V
= 2.5V TO 5.5V
V
REF is the reference voltage input.
with:
VREF = 2.5 V.
DD
+
0.1µF
10µF
V
R1 = R3 = 10 kΩ.
IN
V
DD
R2 = R4 = 20 kΩ and VDD = 5 V.
EXT
REF
V
V
OUT
REF
VO = (10 × D/2N) − 5.
V
OUT
GND
AD5330/AD5331/
AD5340/AD5341
V
= 5V
DD
R4
20kΩ
AD780/REF192
WITH V = 5V
+
0.1µF
10µF
REF
DD
+5V
OR
R3
10kΩ
GND
AD589 WITH V = 2.5V
DD
V
IN
V
= ±5V
O
EXT
REF
V
OUT
V
DD
Figure 43. AD5330/AD5331/AD5340/AD5341 Using External Reference
V
GND
0.1µF
–5V
AD5330/AD5331/
AD5340/AD5341
DRIVING VDD FROM THE REFERENCE VOLTAGE
R1
10kΩ
AD780/REF192
V
OUT
WITH V = 5V
If an output range of 0 V to VDD is required, the simplest
solution is to connect the reference inputs to VDD. Because this
supply may not be very accurate and may be noisy, the devices
can be powered from the reference voltage, for example using
a 5 V reference such as the ADP667, as shown in Figure 44.
6V TO 16V
DD
OR
R2
20kΩ
AD589 WITH V = 2.5V
DD
GND
Figure 45. Bipolar Operation using the AD5330/AD5331/AD5340/AD5341
DECODING MULTIPLE AD5330/AD5331/
AD5340/AD5341
+
0.1µF
10µF
CS
The pin on these devices can be used in applications to
V
IN
decode a number of DACs. In this application, all DACs in the
system receive the same data and
of the DACs is active at any one time, so data is only written to
the DAC whose is low. If multiple AD5341s are being used, a
common HBEN line is also required to determine if the data is
written to the high byte or low byte register of the selected DAC.
ADP667
WR
CS
pulses, but only to one
V
V
DD
REF
V
V
OUT
OUT
CS
VSET
GND SHDN
0.1µF
AD5330/AD5331/
AD5340/AD5341
The 74HC139 is used as a 2-line to 4-line decoder to address
any of the DACs in the system. To prevent timing errors, the
enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 46 shows a
diagram of a typical setup for decoding multiple devices in a
system. Once data has been written sequentially to all DACs in
GND
Figure 44. Using an ADP667 as Power and Reference to
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 2ꢀ of 28
AD5330/AD5331/AD5340/AD5341
V
= 5V
DD
a system, all the DACs can be updated simultaneously using a
LDAC
CLR
common
line. A common
line can also be used to
+
0.1µF
0.1µF
10µF
reset all DAC outputs to zero.
V
SOURCE
V
IN
AD5330/AD5331/
AD5340/AD5341
EXT
REF
LOAD
V
5V
OUT
V
DD
HBEN*
HBEN*
V
V
OUT
REF
WR
LDAC
CLR
WR
DATA
INPUTS
GND
AD820/
OP295
LDAC
CLR
CS
AD5330/AD5331/
AD5340/AD5341
AD780/REF192
WITH V = 5V
DD
4.7kΩ
470Ω
AD5330/AD5331/
AD5340/AD5341
GND
HBEN*
WR
DATA
INPUTS
LDAC
CLR
CS
V
V
DD
Figure 47. Programmable Current Source
CC
1Y0
ENABLE
G1
A1
POWER SUPPLY BYPASSING AND GROUNDING
AD5330/AD5331/
AD5340/AD5341
74HC139
1Y1
1Y2
1Y3
CODED
ADDRESS
In any circuit where accuracy is important, careful consid-
eration of the power supply and ground return layout helps
to ensure the rated performance. The printed circuit board on
which the AD5330/AD5331/AD5340/AD5341 are mounted
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. If the
device is in a system where multiple devices require an AGND-
to-DGND connection, the connection should be made at one
point only. The star ground point should be established as
closely as possible to the device. The AD5330/AD5331/
AD5340/AD5341 should have ample supply bypassing of
10 μF in parallel with 0.1 μF on the supply located as close to
the package as possible, ideally right up against the device.
The 10 μF capacitors are the tantalum bead type. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
HBEN*
B1
WR
DATA
INPUTS
LDAC
CLR
CS
DGND
AD5330/AD5331/
AD5340/AD5341
HBEN*
WR
DATA
INPUTS
LDAC
CLR
CS
*AD5341 ONLY
Figure 46. Decoding Multiple DAC Devices
PROGRAMMABLE CURRENT SOURCE
Figure 47 shows the AD5330/AD5331/AD5340/AD5341 used
as the control element of a programmable current source. In
this example, the full-scale current is set to 1 mA. The output
voltage from the DAC is applied across the current setting
resistor of 4.7 kΩ in series with the 470 Ω adjustment poten-
tiometer, which gives an adjustment of about 5ꢀ. Suitable
transistors to place in the feedback loop of the amplifier include
the BC107 and the 2N3904, which enable the current source to
operate from a minimum VSOURCE of 6 V. The operating range is
determined by the operating characteristics of the transistor.
Suitable amplifiers include the AD820 and the OP295, both
having rail-to-rail operation on their outputs. The current for
any digital input code and resistor value can be calculated as
follows:
The power supply lines of the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough through the board. A microstrip technique is by
far the best, but not always possible with a double-sided board.
In this technique, the component side of the board is dedicated to
the ground plane while signal traces are placed on the solder side.
D
I = G ×VREF
×
mA
(2N × R)
where:
G is the gain of the buffer amplifier (1 or 2).
D is the digital equivalent of the digital input code.
N is the DAC resolution (8, 10, or 12 bits).
R is the sum of the resistor plus adjustment potentiometer
in kilo ohms.
Rev. A | Page 22 of 28
AD5330/AD5331/AD5340/AD5341
Table 11. Overview of AD53xx Parallel Devices
Additional Pin Functions
CLR
Part No. Resolution Bits DNL
Singles
No. of VREF Pins Settling Time BUF
GAIN
HBEN
Package No. of Pins
AD5330
AD533ꢀ
AD5340
AD534ꢀ
8
0.25
0.5
ꢀ
ꢀ
ꢀ
ꢀ
1 μs
7 μs
8 μs
8 μs
BUF
GAIN
GAIN
GAIN
GAIN
CLR
CLR
CLR
CLR
TSSOP
TSSOP
TSSOP
TSSOP
20
20
24
20
ꢀ0
ꢀ2
ꢀ2
ꢀ.0
BUF
BUF
ꢀ.0
HBEN
Duals
AD5332
AD5333
AD5342
AD5343
8
0.25
0.5
2
2
2
ꢀ
1 μs
7 μs
8 μs
8 μs
CLR
CLR
CLR
CLR
TSSOP
TSSOP
TSSOP
TSSOP
20
24
28
20
ꢀ0
ꢀ2
ꢀ2
BUF
BUF
GAIN
GAIN
ꢀ.0
ꢀ.0
HBEN
HBEN
Quads
AD5334
AD5335
AD5331
AD5344
8
0.25
0.5
2
2
4
4
1 μs
7 μs
7 μs
8 μs
GAIN
GAIN
CLR
CLR
CLR
TSSOP
TSSOP
TSSOP
TSSOP
24
24
28
28
ꢀ0
ꢀ0
ꢀ2
0.5
ꢀ.0
Table 12. Overview of AD53xx Serial Devices
Part No.
Singles
AD5300
AD53ꢀ0
AD5320
AD530ꢀ
AD53ꢀꢀ
AD532ꢀ
Resolution Bits
No. of DACs
DNL
Interface
Settling Time
Package
No of Pins
8
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0.25
0.5
ꢀ.0
SPI
SPI
SPI
4 μs
1 μs
8 μs
1 μs
7 μs
8 μs
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
SOT-23, MSOP
1, 8
1, 8
1, 8
1, 8
1, 8
1, 8
ꢀ0
ꢀ2
8
ꢀ0
ꢀ2
0.25
0.5
ꢀ.0
2-Wire
2-Wire
2-Wire
Duals
AD5302
AD53ꢀ2
AD5322
AD5303
AD53ꢀ3
AD5323
8
2
2
2
2
2
2
0.25
0.5
ꢀ.0
SPI
SPI
SPI
SPI
SPI
SPI
1 μs
7 μs
8 μs
1 μs
7 μs
8 μs
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
ꢀ0
ꢀ0
ꢀ0
ꢀ1
ꢀ1
ꢀ1
ꢀ0
ꢀ2
8
ꢀ0
ꢀ2
0.25
0.5
ꢀ.0
Quads
AD5304
AD53ꢀ4
AD5324
AD5305
AD53ꢀ5
AD5325
AD5301
AD53ꢀ1
AD5321
AD5307
AD53ꢀ7
AD5327
8
4
4
4
4
4
4
4
4
4
4
4
4
0.25
0.5
ꢀ.0
SPI
SPI
SPI
1 μs
7 μs
8 μs
1 μs
7 μs
8 μs
1 μs
7 μs
8 μs
1 μs
7 μs
8 μs
MSOP, LFCSP
MSOP, LFCSP
MSOP, LFCSP
MSOP
MSOP
MSOP
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ1
ꢀ1
ꢀ1
ꢀ1
ꢀ1
ꢀ1
ꢀ0
ꢀ2
8
ꢀ0
ꢀ2
8
ꢀ0
ꢀ2
8
ꢀ0
ꢀ2
0.25
0.5
ꢀ.0
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
2-Wire
SPI
0.25
0.5
ꢀ.0
TSSOP
TSSOP
TSSOP
0.25
0.5
ꢀ.0
TSSOP
TSSOP
TSSOP
SPI
SPI
Rev. A | Page 23 of 28
AD5330/AD5331/AD5340/AD5341
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 48. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 49. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
Rev. A | Page 24 of 28
AD5330/AD5331/AD5340/AD5341
ORDERING GUIDE
Model
AD5330BRU
AD5330BRU-REEL
AD5330BRU-REEL7
AD5330BRUZꢀ
Temperature Range
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
Package Description
Package Option
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-20
RU-20
RU-20
RU-20
RU-20
RU-20
AD5330BRUZ-REELꢀ
AD5330BRUZ-REEL7ꢀ –40°C to +ꢀ05°C
AD533ꢀBRU
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
AD533ꢀBRU-REEL
AD533ꢀBRU-REEL7
AD533ꢀBRUZꢀ
AD533ꢀBRUZ-REELꢀ
AD533ꢀBRUZ-REEL7ꢀ –40°C to +ꢀ05°C
AD5340BRU
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
AD5340BRU-REEL
AD5340BRU-REEL7
AD5340BRUZꢀ
AD5340BRUZ-REELꢀ
AD5340BRUZ-REEL7ꢀ –40°C to +ꢀ05°C
AD534ꢀBRU
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
–40°C to +ꢀ05°C
AD534ꢀBRU-REEL
AD534ꢀBRU-REEL7
AD534ꢀBRUZꢀ
AD534ꢀBRUZ-REELꢀ
AD534ꢀBRUZ-REEL7ꢀ –40°C to +ꢀ05°C
ꢀ Z = RoHS Compliant Part.
Rev. A | Page 25 of 28
AD5330/AD5331/AD5340/AD5341
NOTES
Rev. A | Page 21 of 28
AD5330/AD5331/AD5340/AD5341
NOTES
Rev. A | Page 27 of 28
AD5330/AD5331/AD5340/AD5341
NOTES
©2000–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06852-0-2/08(A)
Rev. A | Page 28 of 28
相关型号：
AD5341BRUZ-REEL71
2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
ADI
AD5341BRUZ1
2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
ADI
AD5342BRU-REEL
DUAL, PARALLEL, WORD INPUT LOADING, 8us SETTLING TIME, 12-BIT DAC, PDSO28, PLASTIC, TSSOP-28
ADI
AD5342BRU-REEL7
IC DUAL, PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO28, TSSOP-28, Digital to Analog Converter
ADI
AD5342BRUZ-REEL7
+2.5V to 5.5V, 230 µA Dual Rail-to-Rail Voltage Output 12-Bit DAC with Parallel Interface in 28-lead TSSOP
ADI
©2020 ICPDF网 联系我们和版权申明