AD53519_技术文档

PRELIMINARY TECHNICAL DATA

Dual Ultrafast

Voltage Comparator

a

Preliminary Technical Data

AD53519

FEATURES

Robust Input Protection

FUNCTIONAL BLOCK DIAGRAM

300 ps Propagation Delay Input to Output

75 ps Propagation Delay Variation

Differential ECL Compatible Outputs

Differential Latch Control

NONINVERTING

INPUT

Q OUTPUT

/Q OUTPUT

+

-

Power Supply Rejection Greater than 70 dB

200ps Minimum Pulse Width (Bandwidth > 2.5

GHz)

INVERTING

INPUT

5 Gbps Toggle Rate

Typical Output Rise/Fall of 150 ps

APPLICATIONS

/LATCH ENABLE

INPUT

LATCH ENABLE

INPUT

Automatic Test Equipment

High Speed Instrumentation

Scope & Logic Analyzers Front End

Window Comparators

Figure 1

High Speed Line Receivers

Threshold Detection

Peak Detection

High Speed Triggers

Patient Diagnostics

Disk Drive Read Channel Detection

Hand-Held Test Instruments

Zero Crossing Detectors

Line Receivers & Signal Restoration

Clock Driver

Upgrade for SPT9689 Designs

Upgrade for AD96687 Designs

mode range from –2.0 V to +3.0 V. Outputs are

GENERAL DESCRIPTION

complementary digital signals fully compatible with ECL 10 K

and 10 KH logic families. The outputs provide sufficient drive

current to directly drive transmission lines terminated in 50 Ω

to –2 V. A latch input is included which permits tracking,

track-hold, or sample-hold modes of operation.

The AD53519 is an ultrafast voltage comparator fabricated on

ADI’s proprietary XFCB process. The device features 300 ps

propagation delay with better than 75 ps overdrive dispersion.

Dispersion is a particularly important characteristic of high

speed comparators. It is a measure of the difference in

propagation delay under differing overdrive conditions.

The AD53519 is available in a 20-lead PLCC package.

A fast, high precision differential input stage permits consistent

propagation delay with a wide variety of signals in the common

REV. Pr J July 22, 2002

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its use,

nor for any infringements of patents or other rights of third parties that may

result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

PRELIMINARY TECHNICAL DATA

AD53519

AD53519 ELECTRICAL CHARACTERISTICS (V_CC= +5.0V, V_EE= -5.2V, T_A= +25°C unless otherwise noted)

PARAMETER

SYMBOL

CONDITION

Min

UNITS

Typ

Max

INPUT

CHARACTERISTICS

Input Offset Voltage

V_OS

-10.0

10.0

mV

±3.0

Input Offset Voltage

Channel Matching

Offset Voltage Tempco

Input Bias Current

Input Bias Current Tempco

Input Offset Current

Input Voltage Range

Input Capacitance

Input Resistance

DV_OS/d_T

I_BC

10.0

±16

µV/°C

µA

±25.0

nA/°C

µA

±1.0

±3.0

3.0

-2.0

V

C_IN

R_ins

pF

kΩ

Input Resistance,

40

kΩ

Differential Mode

Input Resistance, Common

Mode

kΩ

Input Common Mode Range V_CM

Open Loop Gain

3.0

V

dB

60

70

Common Mode Rejection

Ratio

CMRR

V_CM= -1.0 V to +3.0 V

Input Differential Voltage

Hysteresis Skew

V

mV

ENABLE INPUT

CHARACTERISTICS

Latch Enable Common

Mode Range

V_LCM

V_LD

-2.0

0.4

0

V

Latch Enable Differential

Input Voltage

2.0

Input HIGH Voltage

Input LOW Voltage

Input HIGH Current

Input LOW Current

Latch Set-up Time

V_IH

V_IL

V

@ 0.0 Volts

µA

ps

@ -2.0 Volts

t_S

250 mV Over Drive

150

375

150

0

Latch to Output Rise Delay

Latch to Output Fall Delay

Latch Pulse Width

t_PLOH

t_PLOL

t_PL

Latch Hold Time

t_H

OUTPUT

CHARACTERISTICS

Output Voltage - High Level V_OH

Output Voltage - Low Level V_OL

ECL 50 Ohms to –2.0 V

-1.00

-1.95

-0.81

-1.54

V

SWITCHING

PERFORMANCE

Propagation Delay – Input

to Output – Rise

t_PDR

t_PDF

300

ps

Propagation Delay – Input

to Output – Fall

REV. Pr J July 22, 2002

- 2 -

PRELIMINARY TECHNICAL DATA

AD53519

Propagation Delay – Input

to Output – Rise

t_PDR

t_PDF

20 mV Over Drive

375

2

ps

Propagation Delay – Input

to Output – Fall

Propagation Delay –

Tempco

ps/°C

Rise Time

Fall Time

t_R

20% to 80%

150

2500

5

ps

t_F

Equivalent Bandwidth

Toggle Rate

BW

MHz

Gbps

ps

Prop Delay vs. Duty Cycle

Slow Edge

10

20

ps

Prop Delay vs. Over Drive

(20mV to 1.5V)

75

25

ps

Prop Delay Skew

ps

Dispersion - Slew Rate

Within Device Skew,

Channel to Channel Prop

Delay Match

Prop Delay Dispersion

Overdrive

ps

Prop Delay Dispersion

Common Mode Voltage

Prop Delay Dispersion Input

Slew Rate

Prop Delay Dispersion Input

Duty Cycle

Prop Delay Dispersion Input

Pulse Width

Unit to Unit Prop Delay

ps

Minimum Pulse Width - Pos PW_H

200

Minimum Pulse Width -

Neg

PW_L

POWER SUPPLY

Positive Supply Current

Negative Supply Current

Positive Supply Voltage

Negative Supply Voltage

Power Dissipation

Power Supply Sensitivity –

VCC

I_VCC

I_VEE

@ +5.0 Volts

@ -5.2 Volts

Dual

mA

V

VCC

VEE

4.75

-4.96

5.0

5.25

-5.45

Dual

-5.2

V

Dual, Without Load

Dual, With Load

mW

dB

550

70

PSS_VCC

PSS_VEE

Power Supply Sensitivity –

VEE

70

dB

NOTES:

1.

2.

Under no circumstances should the input voltages exceed the supply voltages

REV. Pr J July 22, 2002

- 3 -

PRELIMINARY TECHNICAL DATA

AD53519

Supply Voltages

ABSOLUTE MAXIMUM RATINGS

Positive Supply Voltage (V_CCto GND)...............–0.5V to +6.0V

Negative Supply Voltage (V_EEto GND) ..............-6.0V to +0.5V

Ground Voltage Differential................................–0.5V to +0.5V

Input Voltages

Input Common Mode Voltage.............................–2.0V to +3.0V

Differential Input Voltage ...................................–3.0V to +3.0V

Input Voltage, Latch Controls .................................... VEE to 0V

Output

Output Current....................................................................30mA

Temperature

Operating Temperature, ambient............................ 0°C to +70°C

Operating Temperature, junction..................................... +150°C

Storage Temperature Range ............................. –65°C to +150°C

Lead Temperature (10 sec).............................................. +300°C

Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage

to the device. This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

ORDERING GUIDE

TEMP

RANGE

0/+70^oC

Package

Description

PLCC-20

MODEL

AD53519JP

REV. Pr J July 22, 2002

- 4 -

PRELIMINARY TECHNICAL DATA

AD53519

AD53519 PIN DESCRIPTION

PIN# Name

Function

PIN# Name

Function

1

2

NC

QA

No Connect. Leave pin unconnected.

One of two complementary outputs for channel

A. QA will be at logic HIGH if the analog

voltage at the NONINVERTING INPUT is

greater than the analog voltage at the

INVERTING INPUT (provided the

comparator is in the “compare” mode). See

LATCH ENABLE channel A for additional

information

14

15

V_CC

Positive Supply Terminal.

/LEB

One of two complementary inputs for channel

B Latch Enable. In the “compare” mode

(logic LOW), the output will track changes at

the input of the comparator. In the “latch”

mode (logic HIGH), the output will reflect the

input state just prior to the comparator being

placed in the “latch” mode. LEB must be

driven in conjunction with /LEB.

3

/QA

One of two complementary outputs for channel

A. /QA will be at logic LOW if the analog

voltage at the NONINVERTING INPUT is

greater than the analog voltage at the

INVERTING INPUT (provided the

comparator is in the “compare” mode). See

LATCH ENABLE channel A for additional

information.

16

17

NC

No Connect. Leave pin unconnected.

One of two complementary inputs for channel

B Latch Enable. In the “compare” mode

(logic HIGH), the output will track changes at

the input of the comparator. In the “latch”

mode (logic LOW), the output will reflect the

input state just prior to the comparator being

placed in the “latch” mode. /LEB must be

driven in conjunction with LEB.

LEB

4

5

GND

LEA

Analog ground.

One of two complementary inputs for channel

A Latch Enable. In the “compare” mode

(logic HIGH), the output will track changes at

the input of the comparator. In the “latch”

mode (logic LOW), the output will reflect the

input state just prior to the comparator being

placed in the “latch” mode. /LEA must be

driven in conjunction with LEA.

18

19

GND

/QB

Analog ground.

One of two complementary outputs for channel

B. /QB will be at logic LOW if the analog

voltage at the NONINVERTING INPUT is

greater than the analog voltage at the

INVERTING INPUT (provided the

comparator is in the “compare” mode). See

LATCH ENABLE channel B for additional

information

6

7

NC

No Connect. Leave pin unconnected.

One of two complementary inputs for channel

A Latch Enable. In the “compare” mode

(logic LOW), the output will track changes at

the input of the comparator. In the “latch”

mode (logic HIGH), the output will reflect the

input state just prior to the comparator being

placed in the “latch” mode. LEA must be

driven in conjunction with /LEA.

/LEA

20

QB

One of two complementary outputs for channel

B. QB will be at logic HIGH if the analog

voltage at the NONINVERTING INPUT is

greater than the analog voltage at the

INVERTING INPUT (provided the

comparator is in the “compare” mode). See

LATCH ENABLE channel B for additional

information

8

9

V_EE

Negative Supply Terminal

-INA

Inverting analog input of the differential input

stage for channel A. The INVERTING A

INPUT must be driven in conjunction with the

NONINVERTING A INPUT.

AD53519 PIN CONFIGURATION

3

2

1

20 19

10

+INA

Noninverting analog input of the differential

input stage for channel A. The

PIN 1

IDENTIFIER

4

5

6

7

8

18

17

16

15

14

GND

LEA

NC

GND

LEB

NC

NONINVERTING A INPUT must be driven

in conjunction with the INVERTING A

INPUT.

AD53519

TOP VIEW

(Not to Scale)

/LEA

VEE

/LEB

VCC

11

12

NC

No Connect. Leave pin unconnected.

Noninverting analog input of the differential

input stage for channel B. The

+INB

9

10 11 12 13

NC = NO CONNECT

NONINVERTING B INPUT must be driven in

conjunction with the INVERTING B INPUT.

Inverting analog input of the differential input

stage for channel B. The INVERTING B

INPUT must be driven in conjunction with the

NONINVERTING B INPUT.

13

-INB

Figure 2

REV. Pr J July 22, 2002

- 5 -

PRELIMINARY TECHNICAL DATA

AD53519

TIMING INFORMATION

The timing diagram is presented to illustrate the AD53519 compare and latch features.

SYSTEM TIMING DIAGRAM

/LATCH ENABLE

LATCH ENABLE

50%

t

S

t

PL

t

H

DIFFERENTIAL

V

IN

V

± V

OS

REF

V

OD

INPUT VOLTAGE

t

PLOH

t

PDL

Q OUTPUT

/Q OUTPUT

50%

t

F

t

PDH

t

PLOL

t

R

Figure 3

Terms used in timing diagrams:

t_PDH

t_PDL

t_PLOH

t_PLOL

t_H

INPUT TO OUTPUT HIGH

DELAY

The propagation delay measured from the time the input signal crosses the reference (±

the input offset voltage) to the 50% point of an output LOW to HIGH transition

The propagation delay measured from the time the input signal crosses the reference (±

the input offset voltage) to the 50% point of an output HIGH to LOW transition

The propagation delay measure from the 50% point of the Latch Enable signal LOW to

HIGH transition to the 50% point of an output LOW to HIGH transition

The propagation delay measured from the 50% point of the Latch Enable signal LOW

to HIGH transition to the 50% point of an output HIGH to LOW transition

The minimum time after the negative transition of the Latch Enable signal that the

input signal must remain unchanged in order to be acquired and held at the outputs

The minimum time that the Latch Enable signal must be HIGH in order to acquire and

input signal change

The minimum time before the negative transition of the Latch Enable signal that an

input signal change must be present in order to be acquired and held at the outputs

The amount of time required to transition from a LOW to HIGH output as measured at

the 20 and 80% points

The amount of time required to transition from a HIGH to LOW output as measured at

the 20 and 80% points

The difference between the differential input and reference input voltages

INPUT TO OUTPUT LOW

DELAY

LATCH ENABLE TO

OUTPUT HIGH DELAY

LATCH ENABLE TO

OUTPUT LOW DELAY

MINIMUM HOLD TIME

t_PL

MINIMUM LATCH

ENABLE PULSE WIDTH

MINIMUM SETUP TIME

t_S

t_R

OUTPUT RISE TIME

OUTPUT FALL TIME

VOLTAGE OVERDRIVE

t_F

V_OD

REV. Pr J July 22, 2002

- 6 -

PRELIMINARY TECHNICAL DATA

AD53519

comparator can be used to recover the distorted waveform while

maintaining a minimum of delay.

APPLICATIONS INFORMATION

The AD53519 comparators are very high speed devices.

Consequently, high speed design techniques must be

OPTIMIZING HIGH SPEED PERFORMANCE

employed to achieve the best performance. The most critical

aspect of any AD53519 design is the use of low impedance

ground plane. A ground plane, as part of a multilayer board,

is recommended for proper high speed performance. Using a

continuous conductive plane over the surface of the circuit

board can create this, only allowing breaks in the plane for

necessary current paths. The ground plane provides a low

inductance ground, eliminating any potential differences at

different ground points throughout the circuit board caused

by “ground bounce”. A proper ground plane also minimizes

the effects of stray capacitance on the circuit board.

As with any high speed comparator or amplifier, proper design

and layout techniques should be used to ensure optimal

performance from the AD53519. The performance limits of

high speed circuitry can easily be a result of stray capacitance,

improper ground impedance or other layout issues.

Minimizing resistance from source to the input is an important

consideration in maximizing the high speed operation of the

AD53519. Source resistance in combination with equivalent

input capacitance could cause a lagged response at the input,

thus delaying the output. The input capacitance of the

AD53519 in combination with stray capacitance from an input

pin to ground could result in several picofarads of equivalent

capacitance. A combination of 3 kΩ source resistance and 5 pF

of input capacitance yield a time constant of 15ns, which is

significantly slower than the sub 500 ps capability of the

AD53519. Source impedances should be significantly less than

100 Ω for best performance.

It is also important to provide bypass capacitors for the power

supply in a high speed application. A 1µF electrolytic bypass

capacitor should be placed within 0.5 inches of each power

supply pin to ground. These capacitors will reduce any

potential voltage ripples from the power supply. In addition,

a 10nF ceramic capacitor should be placed as close as

possible from the power supply pins on the AD53519 to

ground. These capacitors act as a charge reservoir for the

device during high frequency switching.

Sockets should be avoided due to stray capacitance and

inductance. If proper high speed techniques are used, the

AD53519 should be free from oscillation when the comparator

input signal passes through the switching threshold.

The LATCH ENABLE input is active LOW (latched). If the

latching function is not used, the LATCH ENABLE input

should be grounded (ground is an ECL logic HIGH). The

complimentary input, /LATCH ENABLE, should be tied to

–2.0 V to disable the latching function.

COMPARATOR PROPAGATION DELAY

DISPERSION

Occasionally, one of the two comparator stages within the

AD53519 will not be used. The inputs of the unused

comparator should not be allowed to “float”. The high

internal gain may cause the output to oscillate (possibly

affecting the other comparator which is being used) unless the

output is forced into a fixed state. This is easily

accomplished by insuring that the two inputs are at least one

diode drop apart, while also appropriately connecting the

LATCH ENABLE and /LATCH ENABLE inputs as

described above.

The AD53519 has been specifically designed to reduce

propagation delay dispersion over an input overdrive range of

100 mV to 1 V. Propagation delay dispersion is the change in

propagation delay which results from a change in the degree of

overdrive (how far the switching point is exceeded by the

input). The overall result is a higher degree of timing accuracy

since the AD53519 is far less sensitive to input variations than

most comparator designs.

Propagation delay dispersion is a specification, which is

important in critical timing application such as ATE, bench

instruments and nuclear instrumentation. Dispersion is defined

as the variation in propagation delay as the input overdrive

conditions are changed. For the AD53519 dispersion is

typically 50 ps as the overdrive is changed from 100 mV to 1 V.

This specification applies for both positive and negative

overdrive since the AD53519 has equal delays for positive and

negative going inputs.

The best performance will be achieved with the use of proper

ECL terminations. The open-emitter outputs of the AD53519

are designed to be terminated through 50Ω resistors to –2.0

V, or any other equivalent ECL termination. If a –2.0 V

supply is not available, an 82Ω resistor to ground and a 130Ω

resistor to –5.2 V provides a suitable equivalent. If high

speed ECL signals must be routed more than a centimeter,

microstrip or stripline techniques may be required to insure

proper transition times and prevent output ringing.

The 50 ps propagation delay dispersion of the AD53519 offers

considerable improvement of the 100 ps dispersion of other

similar series comparators.

Clock Timing Recovery

Comparators are often used in digital systems to recover clock

timing signals. High-speed square waves transmitted over a

distance, even tens of centimeters, can become distorted due to

stray capacitance and inductance. Poor layout or improper

termination can also cause reflections on the transmission line,

further distorting the signal waveform. A high-speed

REV. Pr J July 22, 2002

- 7 -

PRELIMINARY TECHNICAL DATA

AD53519

The customary technique for introducing hysteresis into a

comparator uses positive feedback. The major problems with

this approach are that the amount of hysteresis varies with the

output logic levels resulting in a hysteresis that is not

symmetrical around zero.

PROPAGATION DELAY DISPERSION

1.5 V OVERDRIVE

INPUT VOLTAGE

20 mV OVERDRIVE

Another method to implement hysteresis is generated by

introducing a differential voltage between LATCH ENABLE

and /LATCH ENABLE as shown in Figure X.X. Hysteresis

generated in this manner is independent of output swing and is

symmetrical around zero. The variation of hysteresis with input

voltage is shown in Figure 5.

V

± V

OS

REF

DISPERSION

Q OUTPUT

Figure 4

COMPARATOR HYSTERESIS TRANSFER

FUNCTION USING LATCH ENABLE INPUT

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often useful in a

noisy environment or where it is not desirable for the

comparator to toggle between states when the input signal is at

the switching threshold. The transfer function for a comparator

with hysteresis is shown in Figure 4 below. If the input voltage

approaches the threshold from the negative direction, the

comparator will switch from a “0” to a “1” when the input

crosses +V_H/2. The “new” switching threshold now becomes –

V_H/2. The comparator will remain in a “1” state until the

threshold –V_H/2 is crossed coming from the positive direction.

In this manner, noise centered around 0 V input will not cause

the comparator to switch states unless it exceeds the region

bounded by ±V_H/2.

0

-30

-20

-10

10

20

30

DIFFERENTIAL LATCH VOLTAGE - mV

Figure 6

Positive feedback from the output to the input is often used to

produce hysteresis in a comparator.

THERMAL CONSIDERATIONS

COMPARATOR HYSTERESIS TRANSFER FUNCTION

The AD53519 PLCC package option has a theta JA (junction to

ambient thermal resistance) of 89.4 °C /W in still air.

-V

+V

2

H

2

0 V

INPUT

Upgrading the SPT9689 and AD96687

“1"

The AD53519 dual comparator is pin-for-pin compatible with

the SPT9689 and AD96687 and offers many improvements over

these devices. The most notable difference is in propagation

delay. The SPT9689 and AD96687 can be easily replaced with

the higher performance AD53519, but there are differences and

it is useful to check that these ensure proper operation.

The major differences between the SPT9689 and AD53519

include Propagation Delay, Latch to Output Delay, Bandwidth,

Rise Time, Fall Time, Input Offset Voltage (SPT9689B) and

Offset Voltage Tempco (SPT9689B).

“0"

OUTPUT

Figure 5

REV. Pr J July 22, 2002

- 8 -

PRELIMINARY TECHNICAL DATA

AD53519

TYPCIAL APPLICATION CIRCUITS

HIGH SPEED SAMPLING CIRCUIT

AD53519

V

+

IN

OUTPUTS

V

-

REF

ALL RESISTORS 50 OHM

UNLESS OTHERWISE

NOTED

LATCH

-2.0 V

ENABLE

INPUTS

Figure 7

HIGH SPEED WINDOW COMPARATOR

AD53519

+V

REF

+

OUTPUTS

V

-

IN

AD53519

+

-V

-

REF

LATCH

-2.0 V

ENABLE

INPUTS

ALL RESISTORS 50 OHM UNLESS OTHERWISE NOTED

Figure 8

REV. Pr J July 22, 2002

- 9 -

PRELIMINARY TECHNICAL DATA

AD53519

HYSTERESIS USING POSITIVE FEEDBACK

AD53519

V

+

IN

OUTPUTS

-

V

REF

R2

R1

-2.0 V

Figure 9

HYSTERESIS USING LATCH ENABLE INPUT

AD53519

V

+

IN

OUTPUTS

-

HYSTERESIS

VOLTAGE

-2.0 V

450

ALL RESISTORS 50 OHM

UNLESS OTHERWISE

NOTED

Figure 10

REV. Pr J July 22, 2002

- 10 -

PRELIMINARY TECHNICAL DATA

AD53519

HOW TO INTERFACE AN ECL OUTPUT TO AN INSTRUMENT WITH A 50 OHM

TO GROUND INPUT

AD53519

30

50

+

-

V

IN

127

-5.2 V

Figure 11

ESD PROTECTION CIRCUITS

All input and output pins contain ADI Proprietary ESD

ESD WARNING!!! ESD (Electrostatic

discharge) sensitive device. Electrostatic

charges as high as 4000 V readily accumulate

on the human body and test equipment and

can discharge without detection. Although

the AD53519 features proprietary ESD

protection circuitry, permanent damage may

occur on devices subjected to high energy

electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid

performance degradation or loss of

protection diodes.

V

CC

EQUIVALENT ESD

PROTECTION CIRCUIT

INPUT

V

EE

functionality.

Figure 12

TYPICAL PERFORMANCE CHARACTERISTICS (V_CC= +5.0V, V_EE= -5.20V, T_A= +25°C UNLESS OTHERWISE

NOTED)

0

Title

POSSIBLE CHARTS TO BE ADDED.

REV. Pr J July 22, 2002

- 11 -

PRELIMINARY TECHNICAL DATA

AD53519

•

Propagation Delay vs. Overdrive Voltage

Propagation Delay vs. Temperature

Propagation Delay vs. Common Mode Voltage

Rise Time vs. Temperature

Hysteresis vs. ∆Latch

Rise and Fall of Outputs vs. Time Crossover

Fall Time vs. Temperature

Input Bias Current vs. Common Mode Voltage

Input Bias Current vs. Input Voltage

Input Bias Current vs. Temperature

Input Offset Voltage vs. Temperature

REV. Pr J July 22, 2002

- 12 -

PRELIMINARY TECHNICAL DATA

AD53519

Mechanical Outline Dimensions

Dimensions shown in inches and (mm).

20-Pin PLCC

0.180

0.048

(4.57)

(1.21)

0.042

0.056

(1.42)

0.042

0.165

(4.19)

0.025 (0.63)

0.015 (0.38)

0.020 (0.50)

R

0.048 (1.21)

(1.07)

3

19

0.021

(1.07)

0.042 (1.07)

PIN 1

18

4

(0.53)

PIN 1

IDENTIFIE

0.050

(1.27)

BSC

IDENTIFIE

TOP ^RVIEW

(PINS DOWN)

0.330

0.013

BOT^RTOM

VIEW

(8.38)

0.290

(7.37)

(0.33)0.032

(0.81)

(PINS UP)

14

8

0.026

9

13

0.020

(0.66)

(0.50

0.040 (1.01)

0.356 (9.04)

0.350 (8.89)

)

SQ

0.025 (0.64)

R

0.110

0.395

(2.79)

0.085

(2.16)

(10.02)

0.385 (9.78)

REV. Pr J July 22, 2002

- 13 -


型号：	AD53519
厂家：	ADI
描述：	Preliminary Technical Data 初步的技术数据
文件：	总13页 (文件大小：288K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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