AD5370 [ADI]
40-Channel, 16-Bit, Serial Input, Voltage-Output DACs; 40通道， 16位，串行输入，电压输出DAC
| 型号： | AD5370 |
| 厂家： | 
ADI |
| 描述： | 40-Channel, 16-Bit, Serial Input, Voltage-Output DACs |
| 文件： | 总24页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
40-Channel, 16-Bit, Serial Input,
Voltage-Output DACs
Preliminary Technical Data
AD5370
DSP/microcontroller-compatible serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
FEATURES
40-channel DAC in 64 Lead LFCSP and LQFP
Guaranteed monotonic to 16 bits
Digital reset (RESET)
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of -4 V to +8 V
Multiple, independent output span available
System calibration function allowing user-programmable
offset and gain
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
Channel grouping and addressing features
Thermal Monitor Function
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DVCC
VDD
VSS
AGND DNGD
LDAC
VREF0
GROUP 0
BUFFER
16
CONTROL
REGISTER
14
16
14
16
OFFSET
DAC 0
OFS0
REGISTER
8
8
A/B SELECT
REGISTER
TO
MUX 2's
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
16
16
16
X2A REGISTER
DAC 0
REGISTER
16
A/B
MUX
2
DAC 0
X1 REGISTER
MUX
X2B REGISTER
16
16
·
·
·
·
·
·
M REGISTER
C REGISTER
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
16
·
·
·
·
·
·
16
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
OUTPUT BUFFER
AND POWER
16
16
16
16
X2A REGISTER
SERIAL
INTERFACE
16
DAC 7
A/B
MUX
2
SYNC
SDI
DAC 7
X1 REGISTER
DOWN CONTROL
SIGGND0
REGISTER
MUX
X2B REGISTER
16
16
M REGISTER
C REGISTER
16
SCLK
SDO
VREF1
GROUP 1
14
16
14
16
OFFSET
DAC 1
OFS1
REGISTER
BUSY
8
8
TO
MUX 2's
A/B SELECT
REGISTER
BUFFER
RESET
CLR
OUTPUT BUFFER
AND POWER
DOWN CONTROL
VOUT8
16
16
16
X2A REGISTER
16
DAC 0
REGISTER
A/B
MUX
2
DAC 0
X1 REGISTER
VOUT9
MUX
X2B REGISTER
16
16
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
M REGISTER
C REGISTER
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
STATE
MACHINE
16
·
·
·
·
·
·
16
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
16
OUTPUT BUFFER
AND POWER
·
16
16
16
POWER-ON
RESET
16
X2A REGISTER
DAC 7
16
A/B
MUX
2
DAC 7
X1 REGISTER
DOWN CONTROL
SIGGND1
REGISTER
MUX
X2B REGISTER
16
16
M REGISTER
C REGISTER
16
AD5370
VREF1 SUPPLIES
GROUP 1 TO GROUP 4
VOUT16
TO
VOUT39
GROUP 2 TO GROUP 4
ARE IDENTICAL TO GROUP 1
5370-0001C
SIGGND3
SIGGND4
SIGGND2
Figure 1.
AD5370—Protected by U.S. Patent No. 5,969,657; other patents pending
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.
Preliminary Technical Data
AD5370
TABLE OF CONTENTS
Specifications......................................................................................4
Reset Function............................................................................ 16
Clear Function............................................................................ 16
Power-Down Mode.................................................................... 16
Thermal Monitor function........................................................ 16
Toggle Mode................................................................................ 17
Serial Interface .................................................................................18
SPI Write Mode .......................................................................... 18
SPI Readback Mode ................................................................... 18
Register Update Rates................................................................ 19
Channel Addressing And Special Modes................................ 19
Special Function Mode.............................................................. 20
Power Supply Decoupling ......................................................... 21
Power Supply Sequencing ......................................................... 22
Interfacing Examples ................................................................. 22
Outline Dimensions........................................................................23
Ordering Guide .......................................................................... 23
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings.............................................................8
ESD Caution.................................................................................. 8
Terminology .....................................................................................11
Functional Description...................................................................12
DAC Architecture—General..................................................... 12
Channel Groups.......................................................................... 12
A/ B Registers and Gain/Offset Adjustment........................... 13
Load DAC.................................................................................... 13
Offset DACs ................................................................................ 13
Output Amplifier........................................................................ 14
Transfer Function....................................................................... 14
Reference Selection .................................................................... 14
Calibration................................................................................... 15
Additional Calibration............................................................... 15
REVISION HISTORY
Pr B1. Ti ming diagrams modified
Reference Selection and Calibration example added
Pr. B2 Added Reset Function text
Pr. B3 Added Power Down Mode text
Pr. B4 Added Terminology section
Pr F
Rewrote calibration section
Changed SPI Read diagram
Rev. PrF | Page 2 of 24
Preliminary Technical Data
AD5370
General Description
The AD5370 has a high-speed serial interface, which is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP
interface standards and can handle clock speeds of up to 50
MHz.
The AD5370 contains 40, 16-bit DACs in a single, 64-lead,
LFCSP or LQFP package. The AD5370 provides buffered
voltage outputs with a span 4 times the reference voltage. The
gain and offset of each DAC can be independently trimmed to
remove errors. For even greater flexibility, the device is divided
into 5 groups of 8 DACs. Two offset DACs allow the output
range of the groups to be altered. Group 0 can be adjusted by
Offset DAC 0 and group 1 to group 4 can be adjusted by Offset
DAC 2.
The DAC outputs are updated on reception of new data into the
DAC registers. All the outputs can be updated simultaneously
LDAC
by taking the
input low. Each channel has a program-
mable gain and an offset adjust register.
Each DAC output is gained and buffered on-chip with respect
to an external SIGGND input. The DAC outputs can also be
The AD5370 offers guaranteed operation over a wide supply
range with VSS from -4.5V to -16.5 V and VDD from +8 V to
+16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
CLR
switched to SIGGND via the
pin.
Table 1. High Channel Count Bipolar DACs
Model
Resolution Nominal Output Span Output
Channels
Linearity Error
(LSB)
Package Description Package Option
AD5360BCPZ
AD5360BSTZ
AD5361BCPZ
AD5361BSTZ
AD5362BCPZ
AD5362BSTZ
AD5363BCPZ
AD5363BSTZ
AD5370BCPZ
AD5370BSTZ
AD5371BCPZ
AD5371BSTZ
AD5372BCPZ
AD5372BSTZ
AD5373BCPZ
AD5373BSTZ
16 Bits
16 Bits
14 Bits
14 Bits
16 Bits
16 Bits
14 Bits
14 Bits
16 Bits
16 Bits
14 Bits
14 Bits
16 Bits
16 Bits
14 Bits
14 Bits
16
16
16
16
8
4
4
1
1
4
4
1
1
4
4
1
1
4
4
1
1
56-Lead LFCSP
52-Lead LQFP
56-Lead LFCSP
52-Lead LQFP
56-Lead LFCSP
52-Lead LQFP
56-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
64-Lead LQFP
100-Ball CSPBGA
80-Lead LQFP
56-Lead LFCSP
64-Lead LQFP
56-Lead LFCSP
64-Lead LQFP
CP-56
ST-52
CP-56
ST-52
CP-56
ST-52
CP-56
ST-52
CP-64
ST-64
BC-100-2
ST-80
CP-56
ST-64
CP-56
ST-64
4 × V REF (20 V)
4 × V REF (20 V)
4 × V REF (20 V)
4 × V REF (20 V)
4 × V REF (20 V)
4 × V REF (20 V)
4 × V REF (20 V)
4 × V REF (20 V)
4 × V REF (12 V)
4 × V REF (12 V)
4 × V REF (12 V)
4 × V REF (12 V)
4 × V REF (12 V)
4 × V REF (12 V)
4 × V REF (12 V)
4 × V REF (12 V)
8
8
8
40
40
40
40
32
32
32
32
Rev. PrF | Page 3 of 24
Preliminary Technical Data
SPECIFICATIONS
AD5370
DVCC = 2.5 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; RL = Open Circuit;
Gain (m), Offset (c) and DAC Offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Performance Characteristics
Parameter
B Version1
Unit
Test Conditions/Comments2
ACCURACY
Resolution
16
4
1
20
20
100
100
35
Bits
Relative Accuracy
Differential Nonlinearity
Offset Error
LSB max
LSB max
mV min/max
mV max
µV max
µV max
mV max
−40°C to +85°C.
Guaranteed monotonic by design over temperature.
Before Calibration
Before Calibration
After Calibration
After Calibration
Positive or Negative Full Scale. See Offset DACs section
for details
Gain Error
Offset Error2
Gain Error2
Gain Error of Offset DAC
VOUT Temperature Coefficient
DC Crosstalk2
5
1.5
ppm FSR/°C typ Includes linearity, offset, and gain drift.
mV max
Typically 100 µV. Measured channel at mid-scale, full-
scale change on any other channel
REFERENCE INPUTS (VREF0, VREF1)2
VREF Input Current
VREF Range
60
2/5
nA max
V min/max
Per input. Typically 30 nA.
2ꢀ for specified operation.
SIGGND INPUT (SIGGND0 TO SIGGND4)2
DC Input Impedance
55
kΩ min
Typically 60 kΩ.
Input Range
0.5
V min/max
OUTPUT CHARACTERISTICS2
Output Voltage Range
VSS + 1.4
VDD − 1.4
-4 to +8
10
1
V min
V max
V
mA max
mA max
nF max
Ω max
ILOAD = 1 mA.
ILOAD = 1 mA.
Nominal Output Range
Short Circuit Current
Load Current
Capacitive Load Stability
DC Output Impedance
DIGITAL INPUTS
2
0.5
JEDEC compliant.
Input High Voltage
1.7
2.0
0.8
1
V min
V min
V max
µA max
pF max
IOVCC = 2.5 V to 3.6 V.
IOVCC = 3.6 V to 5.5 V.
IOVCC = 2.5 V to 5.5 V.
Except CLR and RESET
Input Low Voltage
Input Current
Input Capacitance2
10
DIGITAL OUTPUTS (SDO)
Output Low Voltage
Output High Voltage (SDO)
High Impedance Leakage Current
High Impedance Output Capacitance2
0.5
IOVCC − 0.5
−70
V max
V min
µA max
pF typ
Sinking 200 µA.
Sourcing 200 µA.
SDO only.
10
Rev. PrF | Page 4 of 24
Preliminary Technical Data
AD5370
Parameter
B Version1
Unit
Test Conditions/Comments2
POWER REQUIREMENTS
DVCC
VDD
VSS
2.5/5.5
8/16.5
−4.5/−16.5
V min/max
V min/max
V min/max
Power Supply Sensitivity2
∆ Full Scale/∆ VDD
∆ Full Scale/∆ VSS
∆ Full Scale/∆ VCC
DICC
−75
−75
−90
2
14
14
dB typ
dB typ
dB typ
mA max
mA max
mA max
VCC = 5.5 V, VIH = VCC, VIL = GND.
Outputs unloaded. DAC Outputs = 0V
Outputs unloaded. DAC Outputs = 0V
IDD
ISS
Power Dissipation
Power Dissipation Unloaded (P)
Junction Temperature
350
130
mW
°C max
VSS = -5.5 V, VDD = +9.5 V, DVCC = 2.5V
TJ = TA + PTOTAL × θJ.3
1 Temperature range for B Version: −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization, not production tested.
3 Where θJ represents the package thermal impedance.
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND; RL = 10 kΩ to GNDGain
(m), Offset (c) and DAC Offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. AC Characteristics
Parameter
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
TBD
30
1
20
10
100
40
10
0.1
1
µs typ
µs max
Full-scale change
Slew Rate
V/µs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)1/2 typ
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
VREF(+) = 2 V p-p, 1 kHz.
Between DACs inside a group.
Between DACs from different groups.
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
Effect of input bus activity on DAC output under test.
VREF = 0 V.
250
1 Guaranteed by design and characterization, not production tested.
Rev. Prr F | Page 5 of 24
Preliminary Technical Data
AD5370
TIMING CHARACTERISTICS
DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; RL = Open Circuit;
Gain (m), Offset (c) and DAC Offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
SPI INTERFACE (Figure 4 and Figure 5)
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
t5
t6
t7
t8
20
8
8
11
20
10
5
5
42
1.25
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
SCLK Cycle Time.
SCLK High Time.
SCLK Low Time.
SYNC Falling Edge to SCLK Falling Edge Setup Time.
Minimum SYNC High Time.
24th SCLK Falling Edge to SYNC Rising Edge.
Data Setup Time.
Data Hold Time.
SYNC Rising Edge to BUSY Falling Edge.
3
t9
t10
µs max
ns max
ns min
ns min
BUSY Pulse Width Low (Single-Channel Update.) See Table 7.
Single-Channel Update Cycle Time
24th SCLK Falling Edge to LDAC Falling Edge.
LDAC Pulse Width Low.
t11
t12
t13
t14
500
20
10
3
BUSY Rising Edge to DAC Output Response Time.
µs max
ns min
µs max
t15
t16
0
3
BUSY Rising Edge to LDAC Falling Edge.
LDAC Falling Edge to DAC Output Response Time.
t17
t18
t19
t20
20/30
125
30
µs typ/max DAC Output Settling Time.
ns max
ns min
µs max
ns min
ns max
CLR/RESET Pulse Activation Time.
RESET Pulse Width Low.
400
RESET Time Indicated by BUSY Low.
Minimum SYNC High Time in Readback Mode.
SCLK Rising Edge to SDO Valid.
t21
270
25
5
t22
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 2 ns (10ꢀ to 90ꢀ of VCC) and timed from a voltage level of 1.2 V.
3 See Figure 4and Figure 5.
4 This is measured with the load circuit of Figure 2.
5 This is measured with the load circuit of Figure 3.
V
CC
I
200µA
OL
R
2.2kΩ
L
TO
OUTPUT
PIN
V
(min) - V
2
(max)
OL
OH
TO
OUTPUT
PIN
C
L
50pF
V
OL
50pF
C
I
L
200µA
OL
Figure 2. Load Circuit for BUSY Timing Diagram
Figure 3. Load Circuit for SDO Timing Diagram
Rev. PrF | Page 6 of 24
Preliminary Technical Data
AD5370
t1
SCLK
1
24
1
24
2
t3
t11
t2
t4
t6
t5
SYNC
SDI
t7
t8
DB0
DB23
t9
t10
BUSY
t12
t13
1
LDAC
t17
t14
t15
1
VOUT
t13
2
LDAC
t17
2
VOUT
t
16
CLR
t18
VOUT
t19
RESET
VOUT
t18
t20
BUSY
1
LDAC ACTIVE DURING BUSY.
LDAC ACTIVE AFTER BUSY.
2
Figure 4.SPI Write Timing
t22
SCLK
48
24
t21
SYNC
SDI
DB23
DB0
DB0
DB23
DB23
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB0
DB0
SDO
5371-0005D
SELECTED REGISTER DATA
CLOCKED OUT
LSB FROM PREVIOUS WRITE
Figure 5.SPI Read Timing
Rev. PrF | Page 7 of 24
Preliminary Technical Data
AD5370
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 4. Absolute Maximum Ratings
Parameter
Stresses above those listed under Absolute Maximum Ratings
Rating
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
VDD to AGND
VSS to AGND
DVCC to DGND
Digital Inputs to DGND
Digital Outputs to DGND
VREF1, VREF2 to AGND
VOUT0–VOUT39 to AGND
SIGGND to AGND
−0.3 V to +17 V
−17 V to +0.3 V
−0.3 V to +7 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−0.3 V to +7 V
VSS − 0.3 V to VDD + 0.3 V
-1 V to + 1 V
AGND to DGND
−0.3 V to +0.3 V
Operating Temperature Range (TA)
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
θJA Thermal Impedance
64-LFCSP
−40°C to +85°C
−65°C to +150°C
130°C
25°C/W
64-LQFP
45.5°C/W
Reflow Soldering
Peak Temperature
Time at Peak Temperature
230°C
10 s to 40 s
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrF | Page 8 of 24
Preliminary Technical Data
AD5370
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
1
2
VOUT5
VOUT4
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
VREF0
RESET
BUSY
PIN 1
IDENTIFIER
PIN 1
INDICATOR
RESET
BUSY
1
2
3
4
5
6
7
8
9
48 VOUT5
47 VOUT4
46 SIGGND0
45 VOUT3
44 VOUT2
43 VOUT1
42 VOUT0
41 VREF0
40 VOUT23
39 VOUT22
38 VOUT21
37 VOUT20
36 VSS
3
VOUT27
SIGGND3
VOUT28
VOUT29
VOUT30
VOUT31
VOUT32
VOUT33
VOUT34
VOUT35
SIGGND4
VOUT36
VOUT37
VDD
4
VOUT27
SIGGND3
VOUT28
VOUT29
VOUT30
VOUT31
VOUT32
VOUT33 10
VOUT34 11
VOUT35 12
SIGGND4 13
VOUT36 14
VOUT37 15
VDD 16
5
6
7
AD5370
TOP VIEW
(Not to Scale)
8
VOUT23
VOUT22
VOUT21
VOUT20
9
TOP VIEW
10
11
37
36
12
13
14
VSS
35
34
33
VDD
35 VDD
34 SIGGND2
33 VOUT19
15
16
SIGGND2
VOUT19
090605
25 26
29
30
27
32
17 18 19 20 21 22 23 24
31
28
Figure 6.64-Lead LQFP Pin Configuration
Figure 7.64-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin
Function
DVCC
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 µF ceramic capacitors and 10 µF
capacitors.
IOVCC
VSS
Power supply for interface logic.
Negative Analog Power Supply; −11.4 V to −16.5 V for specified performance. These pins should be decoupled with
0.1 µF ceramic capacitors and 10 µF capacitors.
VDD
Positive Analog Power Supply; +11.4 V to +16.5 V for specified performance. These pins should be decoupled with
0.1 µF ceramic capacitors and 10 µF capacitors.
AGND
DGND
Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.
Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.
Reference Input for DACs 0 to 7. This voltage is referred to AGND.
VREF
VREF
0
1
Reference Inpus for DACs 8 to 39. This voltage is referred to AGND.
VOUT0 to VOUT39 DAC Outputs. Buffered analog outputs for each of the 40 DAC channels. Each analog output is capable of driving an
output load of 10 kΩ to ground. Typical output impedance of these amplifiers is 1 Ω.
SYNC
SCLK
Active Low Input. This is the frame synchronization signal for the serial interface.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds
up to 50 MHz.
SDI
Serial Data Input. Data must be valid on the falling edge of SCLK.
SDO
Serial Data Output. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the rising edge of
SCLK and is valid on the falling edge of SCLK.
CLR
Asynchronous Clear Input (level sensitive, active low). See the Clear Function section for more information
Load DAC Logic Input (active low). See the BUSY AND LDAC FUNCTIONS section for more information
LDAC
Rev. PrF | Page 9 of 24
Preliminary Technical Data
AD5370
Pin
Function
RESET
Asynchronous Digital Reset Input
BUSY
Digital Input/Open-Drain Output. BUSY is open-drain when an output. See the BUSY AND LDAC FUNCTIONS section
for more information
SIGGND0
SIGGND1
SIGGND1
SIGGND3
SIGGND4
EXPOSED PADDLE
Reference Ground for DACs 0 to 7. VOUT0 to VOUT7 are referenced to this voltage.
Reference Ground for DACs 8 to 15. VOUT7 to VOUT15 are referenced to this voltage.
Reference Ground for DACs 16 to 23. VOUT16 to VOUT23 are referenced to this voltage.
Reference Ground for DACs 24 and 31. VOUT24 to VOUT31 are referenced to this voltage.
Reference Ground for DACs 32 to 39. VOUT32 to VOUT39 are referenced to this voltage.
The Lead Free Chip Scale Package (LFCSP) has an exposed paddle on the underside. This should be connected to VSS
Rev. PrF | Page 10 of 24
Preliminary Technical Data
AD5370
DC Crosstalk
TERMINOLOGY
The DAC outputs are buffered by op amps that share common
VDD and VSS power supplies. If the dc load current changes in
Relative Accuracy
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
one channel (due to an update), this can result in a further dc
change in one or more channel outputs. This effect is more
significant at high load currents and reduces as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple VDD and VSS terminals are
Differential Nonlinearity
provided to minimize dc crosstalk.
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Output Voltage Settling Time
The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.
Digital-to-Analog Glitch Energy
Zero-Scale Error
The amount of energy injected into the analog output at the
major code transition. It is specified as the area of the glitch in
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register.
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. Zero-scale error is
mainly due to offsets in the output amplifier.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input that appears at the
output of another DAC operating from another reference. It is
expressed in dB and measured at midscale.
Full-Scale Error
Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC register.
Full-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. It does not include
zero-scale error.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.
Gain Error Gain error is the difference between full-scale error
and zero-scale error. It is expressed in mV.
Gain Error = Full-Scale Error − Zero-Scale Error
Digital Crosstalk
VOUT Temperature Coefficient
This includes output error contributions from linearity, offset,
and gain drift.
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.
DC Output Impedance
DC output impedance is the effective output source resistance.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
It is dominated by package lead resistance.
Output Noise Spectral Density
Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading all
DACs to midscale and measuring noise at the output. It is
measured in nV/(Hz)1/2.
Rev. PrF | Page 11 of 24
Preliminary Technical Data
AD5370
fed into the output amplifier. The output amplifier multiplies
the DAC out voltage by 4. The output span is 12 V with a 3 V
reference and 20 V with a 5 V reference.
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5370 contains 40 DAC channels and 40 output
CHANNEL GROUPS
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit resistor-string DAC followed by an
output buffer amplifier. The resistor-string section is simply a
string of resistors, each of value R, from VREF to AGND. This
type of architecture guarantees DAC monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
which node on the string the voltage is tapped off before being
The 40 DAC channels of the AD5370 are arranged into five
groups of 8 channels. The eight DACs of Group 0 derive their
reference voltage from VREF0, those of Group 1 from VREF0,
while the remaining groups derive their reference voltage from
VREF1. Each group has its own signal ground pin
Table 6. AD5370 Registers
Register Name
Word Length (Bits)
Description
X1A (group)(channel)
X1B (group) (channel)
M (group) (channel)
C (group) (channel)
X2A (group)(channel)
16
16
16
16
16
Input data register A, one for each DAC channel.
Input data register B, one for each DAC channel.
Gain trim registers, one for each DAC channel.
Offset trim registers, one for each DAC channel.
Output data register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.
X2B (group) (channel)
DAC (group) (channel)
16
Output data register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable, nor directly writable.
OFS0
14
14
3
Offset DAC 0 data register, sets offset for Group 0.
Offset DAC 1 data register, sets offset for Group 1.
OFS1
Control
A
Bit 2 = /B. 0 = global selection of X1A input data registers. 1 = X1B registers.
Bit 1 = Enable Temp Shutdown. 0 = disable temp shutdown. 1 = enable.
Bit 0 = Soft Power Down. 0 = soft power up. 1 = soft power down.
A/B Select 0
A/B Select 1
A/B Select 2
A/B Select 3
A/B Select 4
8
8
8
8
8
Each bit in this register determines if a DAC in Group 0 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Each bit in this register determines if a DAC in Group 1 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Each bit in this register determines if a DAC in Group 2 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Each bit in this register determines if a DAC in Group 3 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Each bit in this register determines if a DAC in Group 4 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Rev. PrF | Page 12 of 24
Preliminary Technical Data
AD5370
A/ B REGISTERS AND GAIN/OFFSET ADJUSTMENT
LOAD DAC
Each DAC channel has seven data registers. The actual DAC
data word can be written to either the X1A or X1B input
All DACs in the AD5370 can be updated simultaneously by
LDAC
taking
low, when each DAC register will be updated
A
register, depending on the setting of the /B bit in the Control
from either its X2A or X2B register, depending on the setting of
the A/B select registers. The DAC register is not readable, nor
directly writable by the user.
A
A
Register. If the /B bit is 0, data will be written to the X1A
register. If the /B bit is 1, data will be written to the X1B
register. Note that this single bit is a global control and affects
every DAC channel in the device. It is not possible to set up the
device on a per-channel basis so that some writes are to X1A
registers and some writes are to X1B registers.
OFFSET DACS
In addition to the gain and offset trim for each DAC, there are
two 14-bit Offset DACs, one for Group 0, one for Group 1 to
Group 4. These allow the output range of all DACs connected to
them to be offset within a defined range. Thus, subject to the
limitations of headroom, it is possible to set the output range of
Group 0, or Groups 1 to Group 4 to be unipolar positive,
unipolar negative, or bipolar, either symmetrical or
X1A
X2A
REGISTER
REGISTER
DAC
REGISTER
MUX
DAC
MUX
X1B
REGISTER
X2B
REGISTER
2049-0007
M
asymmetrical about zero volts. The DACs in the AD5370 are
factory trimmed with the Offset DACs set at their default
values. This gives the best offset and gain performance for the
default output range and span.
REGISTER
C
REGISTER
Figure 8. Data Registers Associated With Each DAC Channel
When the output range is adjusted by changing the value of the
Offset DAC an extra offset is introduced due to the gain error
of the Offset DAC. The amount of offset is dependent on the
magnitude of the reference and how much the Offset DAC
moves from its default value. This offset is quoted on the
specification page. The worst case offset occurs when the Offset
DAC is at positive or negative full-scale. This value can be
added to the offset present in the main DAC of a channel to
give an indication of the overall offset for that channel. In most
cases the offset can be removed by programming the channels
C register with an appropriate value. The extra offset cause by
the Offset DACs only needs to be taken into account when the
Offset DAC is changed from its default value. Figure 9 shows
the allowable code range which may be loaded to the Offset
DAC and this is dependant on the reference value used. Thus,
for a 5V reference, the Offset DAC should not be programmed
with a value greater than 8192 (0x2000).
Each DAC channel also has a gain (M) and offset (C) register,
which allow trimming out of the gain and offset errors of the
entire signal chain. Data from the X1A register is operated on by
a digital multiplier and adder controlled by the contents of the M
and C registers. The calibrated DAC data is then stored in the
X2A register. Similarly, data from the X1B register is operated on
by the multiplier and adder and stored in the X2B register.
Although a multiplier and adder symbol are shown for each
channel, there is only one multiplier and one adder in the
device, which are shared between all channels. This has
implications for the update speed when several channels are
updated at once, as described later.
Each time data is written to the X1A register, or to the M or C
A
register with the /B control bit set to 0, the X2A data is
recalculated and the X2A register is automatically updated.
Similarly, X2B is updated each time data is written to X1B, or to
5
A
M or C with /B set to 1. The X2A and X2B registers are not
RESERVED
readable, nor directly writable by the user.
4
3
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or X2B register is controlled
by an 8-bit A/B Select Register associated with each group of 8
DACs. If a bit in this register is 0, the DAC takes its data from
the X2A register; if 1 the DAC takes its data from the X2B
register (bit 0 controls DAC 0, bit 1 controls DAC 1 etc.).
2
1
0
Note that, since there are 40 bits in 5 registers, it is possible to
set up, on a per-channel basis, whether each DAC takes its data
from the X2A or X2B register. A global command is also
provided that sets all bits in the A/B Select Registers to 0 or to 1.
0
4096
8192
12288
16383
OFFSET DAC CODE
Figure 9. Offset DAC Code Range
Rev. PrF | Page 13 of 24
Preliminary Technical Data
AD5370
is 5461 (0x1555). With a 3V reference this gives a span of -4 V
to +8 V.
OUTPUT AMPLIFIER
As the output amplifiers can swing to 1.4 V below the positive
supply and 1.4 V above the negative supply, this limits how
much the output can be offset for a given reference voltage. For
example, it is not possible to have a unipolar output range of
20V, since the maximum supply voltage is 16.5 V.
REFERENCE SELECTION
The AD5370 has two reference input pins. The voltage applied
to the reference pins determines the output voltage span on
VOUT0 to VOUT39. VREF0 determines the voltage span for
VOUT0 to VOUT7 (Group 0) and VREF1 determines the
voltage span for VOUT8 to VOUT39 (Group 1 to Group 4).
The reference voltage applied to each VREF pin can be
different, if required, allowing the groups to have a different
voltage spans. The output voltage range can be adjusted further
by programming the offset and gain registers for each channel
as well as programming the offset DACs. If the offset and gain
features are not used (i.e. the m and c registers are left at their
default values) the required reference levels can be calculated as
follows:
S1
DAC
CHANNEL
OUTPUT
S2
R6
10kΩ
CLR
R5
R1
CLR
CLR
S3
R2
R3
R4
SIGGND
SIGGND
CHECK VALUE OF R1 &R5
R1,R2,R3 = 20kΩ
R4,R5 = 60kΩ
OFFSET
DAC
R6 = 10kΩ
2049-0008
VREF = (VOUTmax – VOUTmin)/4
Figure 10. Output Amplifier and Offset DAC
If the offset and gain features of the AD5370 are used, then the
required output range is slightly different. The chosen output
range should take into account the system offset and gain errors
that need to be trimmed out. Therefore, the chosen output
range should be larger than the actual, required range.
Figure 10 shows details of a DAC output amplifier and its
connections to the Offset DAC. On power up, S1 is open,
disconnecting the amplifier from the output. S3 is closed, so the
output is pulled to SIGGND (R1 and R2 are very much greater
than R6). S2 is also closed to prevent the output amplifier being
CLR
open-loop. If
this condition until
be programmed, and the outputs will assume the programmed
CLR CLR
is low at power-up, the output will remain in
The required reference levels can be calculated as follows:
1. Identify the nominal output range on VOUT.
CLR
is taken high. The DAC registers can
values when
is taken high. Even if
is high at power-
2. Identify the maximum offset span and the maximum
gain required on the full output signal range.
up, the output will remain in the above condition until
VDD> 6 V and VSS < -4 V and the initialization sequence has
finished. The outputs will then go to their power-on default
value.
3. Calculate the new maximum output range on VOUT
including the expected maximum offset and gain
errors.
TRANSFER FUNCTION
4. Choose the new required VOUTmax and VOUTmin
,
From the foregoing, it can be seen that the output voltage of a
DAC in the AD5370 depends on the value in the input register,
the value of the M and C registers, and the offset from the
Offset DAC. The transfer function is given by:
keeping the VOUT limits centered on the nominal
values. Note that VDD and VSS must provide sufficient
headroom.
Code applied to DAC from X1A or X1B register:-
DAC_CODE = INPUT_CODE × (m+1)/216 + c - 215
DAC output voltage:-
5. Calculate the value of VREF as follows:
VREF = (VOUTMAX – VOUTMIN)/4
Reference Selection Example
VOUT = 4
× VREF ×
(DAC_CODE – OFFSET_CODE )/216 +VSIGGND
Nominal Output Range = 12V (-4V to +8V)
Offset Error = 70mV
Gain Error = 3ꢀ
Notes
DAC_CODE should be within the range of 0 to 65535.
For 12 V span VREF = 3.0 V.
SIGGND = AGND = 0V
For 20 V span VREF = 5.0 V.
X1A or X1B default code = 21844
1) Gain Error = 3ꢀ
=> Maximum Positive Gain Error = +3ꢀ
=> Output Range incl. Gain Error = 12 + 0.03(12)=12.36V
m = code in gain register - default code = 216 – 1.
c = code in offset register - default code = 215.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function as this DAC is a 14 bit
device. On power up the default code loaded to the offset DAC
2) Offset Error = 70mV
=> Maximum Offset Error Span = 2(70mV)=0.14V
=> Output Range including Gain Error and Offset Error =
Rev. PrF | Page 14 of 24
Preliminary Technical Data
AD5370
12.36V + 0.14V = 12.5V
AD5370 Calibration Example
This example assumes that a −4 V to +8 V output is required.
The DAC output is set to −4 V but measured at −4.03 V. This
gives an zero-scale error of −30 mV.
3) VREF Calculation
Actual Output Range = 12.5V, that is -4.25V to +8.25V
(centered);
VREF = (8.25V + 4.25V)/4 = 3.125V
1. 1 LSB = 12 V/65536 = 183.105 µV
2. 30 mV = 164 LSB
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
3. 164 LSB should be added to the default C register value:
(32768 + 164) = 32932
1. Use a resistor divider to divide down a convenient,
higher reference level to the required level.
4. 32932 should be programmed to the C register
2. Select a convenient reference level above VREF and
modify the Gain and Offset registers to digitally
downsize the reference. In this way the user can use
almost any convenient reference level but may reduce
the performance by overcompaction of the transfer
function.
The full-scale error can now be removed. The output is set to +8
V and a value of +8.02 V is measured. The full-scale error is
+20 mV – (–30 mV) = +50 mV
This is a full-scale error of +50 mV.
1. 50 mV = 273 LSBs
3. Use a combination of these two approaches
2. 273 LSB should be subtracted from the default M register
value: (65535 − 273) = 65262
CALIBRATION
The user can perform a system calibration on the AD5370 to
reduce gain and offset errors to below 1 LSB. This is achieved
by calculating new values for the M and C registers and reprogram-
ming them.
3. 65262 should be programmed to the M register
ADDITIONAL CALIBRATION
The techniques described in the previous text are usually
enough to reduce the zero-scale and full-scale errors in most
applications. However, there are limitations whereby the errors
may not be sufficiently removed. For example, the offset (C)
register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, i.e. a
negative full-scale error, the gain (M) register cannot be used to
increase the gain to compensate for the error.
Reducing Zero-scale and Full-scale Error
Zero-scale error can be reduced as follows:
1. Set the output to the lowest possible value.
2. Measure the actual output voltage and compare it with the
required value. This gives the zero-scale error.
3. Calculate the number of LSBs equivalent to the
error and subtract this from the default value of
the C register. Note that only negative zero-scale error can
be reduced.
These limitations can be overcome by increasing the reference
value. With a 3V reference a 12V span will be achieved. The
ideal voltage range, for the AD5371, would be −4V to +8V.
Using a 3.1V reference would increase the range to −4.133V to
+8.2667V. Clearly, in this case, the offset and gain errors are
insignificant and the M and C registers can be used to raise the
negative voltage to −4V and then reduce the maximum voltage
down to +8V to give the most accurate values possible.
Full-scale error can be reduced as follows:
1. Measure the zero-scale error.
2. Set the output to the highest possible value.
3. Measure the actual output voltage and compare it with the
required value. Add this error to the zero-scale error. This
is the full-scale error.
4. Calculate the number of LSBs equivalent to the full-scale
error and subtract it from the default value of the M
register. Note that only positive full-scale error can be
reduced.
5. The M and C registers should not be programmed until
both zero-scale and full-scale errors have been calculated.
Rev. PrF | Page 15 of 24
Preliminary Technical Data
AD5370
BUSY
and the DAC outputs update immediately after
goes
RESET FUNCTION
LDAC
high. A user can also hold the
input permanently low. In
When the
pin is taken low, the DAC buffers are
RESET
BUSY
this case, the DAC outputs update immediately after
goes high.
disconnected and the DAC outputs VOUT0 to VOUT39 are
tied to their associated SIGGND signals via a 10 kΩ resistor. On
the rising edge of
the AD5370 state machine initiates a
RESET
As described later, the AD5370 has flexible addressing that
allows writing of data to a single channel, all channels in a
group, the same channel in groups 0 to 4 or groups 1 to 4, or all
channels in the device. This means that 1, 5, 8 or 40 X2 register
values may need to be calculated and updated. As there is only
one multiplier shared between 40 channels, this task must be
reset sequence to reset the X, M and C registers to their default
values. This sequence typically takes 300µs and the user should
not write to the part during this time. When the reset sequence
is complete, and provided that
be at a potential specified by the default register settings which
will be equivalent to SIGGGND. The DAC outputs will remain
is high, the DAC output will
CLR
BUSY
done sequentially, so the length of the
pulse will vary
LDAC
according to the number of channels being updated.
at SIGGND until the X, M or C registers are updated and
is taken low.
BUSY
Table 7.
Pulse Widths
Action
BUSY
Pulse
Width (µs max)
CLEAR FUNCTION
is an active low input which should be high for normal
CLR
Loading X1A, X1B, C, or M to 1 channel
Loading X1A, X1B, C, or M to 5 channels
Loading X1A, X1B, C, or M to 8 channels
Loading X1A, X1B, C, or M to 40 channels
1.25
3.25
4.75
20.75
operation. The
resistor. When
pin has in internal 500kΩ pull-down
is low, the input to each of the DAC output
CLR
CLR
buffer stages, VOUT0 to VOUT39, is switched to the externally
set potential on the relevant SIGGND pin. While is low, all
CLR
BUSY
Pulse Width = ((Number of Channels +1) × 500ns) +250ns
pulses are ignored. When
is taken high again, the
is taken low. The
LDAC
CLR
LDAC
DAC outputs remain cleared until
The AD5370 contains an extra feature whereby a DAC register
is not updated unless its X2A or X2B register has been written
to since the last time
contents of input registers and DAC registers 0 to 39 are not
affected by taking low. To prevent glitches appearing on
LDAC
was brought low. Normally, when
is brought low, the DAC registers are filled with the
CLR
should be brought low whenever the output
LDAC
the outputs
CLR
contents of the X2A or X2B registers, depending on the setting
of the A/B Select Registers. However the AD5370 updates the
DAC register only if the X2 data has changed, thereby
removing unnecessary digital crosstalk.
span is adjusted by writing to the offset DAC.
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M registers.
POWER-DOWN MODE
BUSY
During the calculation of X2, the
BUSY
output goes low. While
is low, the user can continue writing new data to the X1,
M, or C registers, but no DAC output updates can take place.
LDAC
The AD5370 can be powered down by setting Bit 0 in the
control register. This will turn off the DACs thus reducing the
current consumption. The DAC outputs will be connected to
their respective SIGGND potentials. The power-down mode
doesn’t change the contents of the registers and the DACs will
return to their previous voltage when the power-down bit is
cleared.
The DAC outputs are updated by taking the
LDAC BUSY LDAC
input low. If
event is stored
BUSY
goes
goes low while
is active, the
and the DAC outputs update immediately after
LDAC
high. A user can also hold the
input permanently low. In
BUSY
this case, the DAC outputs update immediately after
goes
also goes low, for approximately 500ns, whenever
the A/B Select Registers are written to.
BUSY
THERMAL MONITOR FUNCTION
BUSY
high.
The AD5370 can be programmed to power down the DAC s if
the temperature on the die exceeds 130°C. Setting Bit 1 in the
control register (see Table 12) will enable this function. If the
die temperature exceeds 130°C the AD5370 will enter a
temperature power-down mode, which is equivalent to setting
the power-down bit in the control register. To indicate that the
AD5370 has entered temperature shutdown mode Bit 4 of the
control register is set. The AD5370 will remain in temperature
power-down mode, even if the die temperature falls, until Bit 1
in the control register is cleared.
The
resistor. Where multiple AD5370 devices may be used in one
BUSY
pin is bidirectional and has a 50 kΩ internal pullup
system the
pins can be tied together. This is useful where
it is required that no DAC in any device is updated until all
other DACs are ready. When each device has finished updating
BUSY
the X2 (A or B) registers it will release the
device hasn’t finished updating its X2 registers it will hold
LDAC
pin. If another
BUSY
low, thus delaying the effect of
The DAC outputs are updated by taking the
LDAC BUSY LDAC
event is stored
going low.
LDAC
input low. If
goes low while
is active, the
Rev. PrF | Page 16 of 24
Preliminary Technical Data
AD5370
TOGGLE MODE
The AD5370 has two X2 registers per channel, X2A and X2B,
which can be used to switch the DAC output between two levels
with ease. This approach greatly reduces the overhead required
by a micro-processor which would otherwise have to write to
each channel individually. When the user writes to either the
X1A ,X2A, M or C registers the calculation engine will take a
certain amount of time to calculate the appropriate X2A or X2B
values. If the application only requires that the DAC output
switch between two levels, such as a data generator, any method
which reduces the amount of calculation time encountered is
advantageous. For the data generator example the user need
only set the high and low levels for each channel once, by
writing to the X1A and X1B registers. The values of X2A and
X2B will be calculated and stored in their respective registers.
The calculation delay therefore only happens during the setup
phase, i.e. when programming the initial values. To toggle a
DAC output between the two levels it is only required to write
to the relevant A/B Select Register to set the MUX2 register bit.
Furthermore, since there are 8 MUX2 control bits per register it
is possible to update eight channels with a single write. Table 14
shows the bits that correspond to each DAC output.
Rev. PrF | Page 17 of 24
Preliminary Technical Data
SERIAL INTERFACE
AD5370
SYNC
of
must be applied to SCLK to clock in 24 bits of data, before
SYNC SYNC
starts the write cycle. At least 24 falling clock edges
The AD5370 contains a high-speed SPI serial interface
operating at clock frequencies up to 50MHz (20MHz for read
operations) To minimize both the power consumption of the
device and on-chip digital noise, the interface powers up fully
only when the device is being written to, that is, on the falling
is taken high again. If
is taken high before the
24th falling clock edge, the write operation will be aborted.
SYNC
If a continuous clock is used,
must be taken high before
the 25th falling clock edge. This inhibits the clock within the
AD5370. If more than 24 falling clock edges are applied before
SYNC
edge of
.
SYNC
is taken high again, the input data will be corrupted. If
The serial interface is 2.5 V LVTTL compatible when operating
from a 2.7 V to 3.6 V DVCC supply. It is controlled by four pins,
as follows.
SYNC
an externally gated clock of exactly 24 pulses is used,
may
be taken high any time after the 24th falling clock edge.
The input register addressed is updated on the rising edge of
SYNC
SYNC SYNC
. In order for another serial transfer to take place,
Frame synchronization input.
must be taken low again
SDI
Serial data input pin.
SPI READBACK MODE
SCLK
The AD5370 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the DAC data registers. In order to read
back a register, it is first necessary to tell the AD5370 which
register is to be read. This is achieved by writing to the device a
word whose first two bits are the special function code 00. The
remaining bits then determine if the operation is a readback,
and the register which is to be read back, or if it is a write to of
the special function registers such as the control register.
Clocks data in and out of the device.
SDO
Serial data output pin for data readback.
SPI WRITE MODE
The AD5370 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which is
all registers except the X2A and X2B registers and the DAC
registers. The X2A and X2B registers are updated when writing
to the X1A, X1B, M and C registers, and the DAC registers are
After the special function write has been performed, if it is a
readback command then data from the selected register will be
clocked out of the SDO pin during the next SPI operation. The
SDO pin is normally three-state but becomes driven as soon as
a read command has been issued. The pin will remain driven
until the registers data has been clocked out. See Figure 5 for
the read timing diagram. Note that due to the timing
LDAC
updated by
.
The serial word (see Table 8) is 24 bits long. 14 of these bits are
data bits, six bits are address bits, and two bits are mode bits
that determine what is done with the data. Two bits are
reserved.
requirements of t5 (25ns) the maximum speed of the SPI
interface during a read operation should not exceed 20MHz.
The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into the
AD5370 by clock pulses applied to SCLK. The first falling edge
Table 8. Serial Word Bit Assignation
I23
I22
I21
I20
I19
I18
I17
I16
A0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
M1
M0
A5
A4
A3
A2
A1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Rev. PrF | Page 18 of 24
Preliminary Technical Data
AD5370
determine to which register (X1A, X1B, C or M) the data is
written, as shown in Table 8. If data is to be written to the X1A
REGISTER UPDATE RATES
As mentioned previously the value of the X2 (A or B) register is
calculated each time the user writes new data to the
A
or X1B register, the setting of the /B bit in the Control
Register determines which (0 Æ X1A, 1 Æ X1B).
corresponding X1, C or M registers. The calculation is
performed by a three stage process. The first two stages take
500ns each and the third stage takes 250ns. When the write to
one of the X1, C or M registers is complete the calculation
process begins. If the write operation involves the update of a
single DAC channel the user is free to write to another register
provided that the write operation doesn’t finish until the first
stage calculation is complete, i.e. 500ns after the completion of
the first write operation. If a group of channels is being updated
by a single write operation the first stage calculation will be
repeated for each channel, taking 500ns per channel. In this
case the user should not complete the next write operation until
this time has elapsed.
Table 9. Mode Bits
M1 M0 Action
1
1
Write DAC input data (X1A or X1B) register,
A
depending on Control Register /B bit.
1
0
0
0
1
0
Write DAC offset (C) register
Write DAC gain (M) register
Special function, used in combination with other
bits of word
The AD5370 has very flexible addressing that allows writing of
data to a single channel, all channels in a group, the same
channel in groups 0 to 4 or groups 1 to 4, or all channels in the
device. Table 10 shows all these address modes.
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, then the data word D13 to D0 is
written to the device. Address bits A5 to A0 determine which
channel or channels is/are written to, while the mode bits
Table 10. Group and Channel Addressing
This table shows which group(s) and which channel(s) is/are addressed for every combination of address bits A5 to A0.
ADDRESS BITS A5 TO A3
000
001
010
011
100
101
110
111
All groups,
all channels
Group 0,
channel 0
Group 1,
channel 0
Group 2,
channel 0
Group 3,
channel 0
Group 4,
channel 0
Groups 0,1,2,3,4
channel 0
Groups 1,2,3,4
channel 0
000
001
010
011
100
101
110
111
Group 0, all
channels
Group 0,
channel 1
Group 1,
channel 1
Group 2,
channel 1
Group 3,
channel 1
Group 4,
channel 1
Groups 0,1,2,3,4
channel 1
Groups 1,2,3,4
channel 1
Group 1, all
channels
Group 0,
channel 2
Group 1,
channel 2
Group 2,
channel 2
Group 3,
channel 2
Group 4,
channel 2
Groups 0,1,2,3,4
channel 2
Groups 1,2,3,4
channel 2
Group 2, all
channels
Group 0,
channel 3
Group 1,
channel 3
Group 2,
channel 3
Group 3,
channel 3
Group 4,
channel 3
Groups 0,1,2,3,4
channel 3
Groups 1,2,3,4
channel 3
ADDRESS
BITS A2 TO
A0
Group 3, all
channels
Group 0,
channel 4
Group 1,
channel 4
Group 2,
channel 4
Group 3,
channel 4
Group 4,
channel 4
Groups 0,1,2,3,4
channel 4
Groups 1,2,3,4
channel 4
Group 4, all
channels
Group 0,
channel 5
Group 1,
channel 5
Group 2,
channel 5
Group 3,
channel 5
Group 4,
channel 5
Groups 0,1,2,3,4
channel 5
Groups 1,2,3,4
channel 5
Reserved
Group 0,
channel 6
Group 1,
channel 6
Group 2,
channel 6
Group 3,
channel 6
Group 4,
channel 6
Groups 0,1,2,3,4
channel 6
Groups 1,2,3,4
channel 6
Reserved
Group 0,
channel 7
Group 1,
channel 7
Group 2,
channel 7
Group 3,
channel 7
Group 4,
channel 7
Groups 0,1,2,3,4
channel 7
Groups 1,2,3,4
channel 7
Rev. PrF | Page 19 of 24
Preliminary Technical Data
AD5370
data required for execution of the special function, for example
the channel address for data readback.
SPECIAL FUNCTION MODE
If the mode bits are 00, then the special function mode is
selected, as shown in Table 11. Bits I21 to I16 of the serial data
word select the special function, while the remaining bits are
The codes for the special functions are shown in Table 12. Table
13 shows the addresses for data readback.
Table 11. Special Function Mode
I23
I22
I21
I20
I19
I18
I17
S1
I16
S0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
0
0
S5
S4
S3
S2
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
Table 12. Special Function Codes
SPECIAL FUNCTION CODE DATA
S5 S4 S3 S2 S1 S0 F15-F0
ACTION
0
0
0
0
0
0
0
0
0
0
0
1
0000 0000 0000 0000
NOP
XXXX XXXX XXXX X[F2:F0]
Write control register
F2 = 1 Æ Select B register for input.
F2 = 0 Æ Select A register for input.
F1 = 1 Æ Enable temperature shutdown.
F1 = 0 Æ Disable temperature shutdown.
F0 = 1 Æ Soft power down; F0 = 0 Æ Soft power up.
Write data in F13:F0 to OFS0 register
Write data in F13:F0 to OFS1 register
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
XX[F13:F0]
XX[F13:F0]
XX[F13:F0]
See Table 13
Select register for readback
XXXX XXXX[F7:F0]
XXXX XXXX[F7:F0]
XXXX XXXX[F7:F0]
XXXX XXXX[F7:F0]
XXXX XXXX[F7:F0]
XXXX XXXX [F7:F0]
Write data in F7:F0 to A/B Select Register 0
Write data in F7:F0 to A/B Select Register 1
Write data in F7:F0 to A/B Select Register 2
Write data in F7:F0 to A/B Select Register 3
Write data in F7:F0 to A/B Select Register 4
Block write A/B Select Registers
F7:F0 = 0, write all 0’s (all channels use X2A register)
F7:F0 = 1, wrote all 1’s (all channels use X2B register)
Rev. PrF | Page 20 of 24
Preliminary Technical Data
AD5370
Table 13. Address Codes for Data Readback
F15 F14 F13 F12 F11 F10 F9
F8
F7
REGISTER READ
X1A Register
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
Bits F12 to F7 select channel to be read
back, from Channel 0 = 001000 to
Channel 39 = 101111
X1B Register
C Register
M Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
Control Register
OFS0 Data Register
OFS1 Data Register
Reserved
A/B Select Register 0
A/B Select Register 1
A/B Select Register 2
A/B Select Register 3
A/B Select Register 4
Note: F6 to F0 are don’t care for data readback function.
Table 14. DACs Select by A/B Select Registers
A/B Select
Bits
F3
Register
F7
F6
F5
F4
F2
F1
F0
0
1
2
3
4
VOUT7
VOUT15
VOUT23
VOUT31
VOUT39
VOUT6
VOUT14
VOUT22
VOUT30
VOUT38
VOUT5
VOUT4
VOUT3
VOUT2
VOUT10
VOUT18
VOUT26
VOUT34
VOUT1
VOUT9
VOUT17
VOUT25
VOUT33
VOUT0
VOUT8
VOUT16
VOUT24
VOUT32
VOUT13
VOUT21
VOUT29
VOUT37
VOUT12
VOUT20
VOUT28
VOUT36
VOUT11
VOUT19
VOUT27
VOUT35
Digital lines running under the device should be avoided,
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5370 to avoid
noise coupling. The power supply lines of the AD5370 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching digital signals should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. It is essential to mini-
mize noise on all VREF lines. Avoid crossover of digital and
analog signals. Traces on opposite sides of the board should run
at right angles to each other. This reduces the effects of
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5370 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5370 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
For supplies with multiple pins (VSS, VDD, VCC), it is
recommended to tie these pins together and to decouple each
supply once.
feedthrough through the board. A microstrip technique is by far
the best, but not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground plane, while signal traces are placed on the solder side.
The AD5370 should have ample supply decoupling of 10 µF in
parallel with 0.1 µF on each supply located as close to the
package as possible, ideally right up against the device. The
10µF capacitors are the tantalum bead type. The 0.1 µF capaci-
tor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
this package during the assembly process.
Rev. PrF | Page 21 of 24
Preliminary Technical Data
AD5370
POWER SUPPLY SEQUENCING
The Analog Devices ADSP-21065L is a floating point DSP with
two serial ports (SPORTS). Figure 12 shows how one SPORT
can be used to control the AD5370. In this example the
Transmit Frame Synchronization (TFS) pin is connected to the
Receive Frame Synchronization (RFS) pin. Similarly the
transmit and receive clocks (TCLK and RCLK) are also
connected together. The user can write to the AD5370 by
writing to the transmit register. A read operation can be
accomplished by first writing to the AD5370 to tell the part that
a read operation is required. A second write operation with a
NOP instruction will cause the data to be read from the
AD5370. The DSPs receive interrupt can be used to indicate
when the read operation is complete.
When the supplies are connected to the AD5370 it is important
that the AGND and DGND pins are connected to the relevant
ground plane before the positive or negative supplies are
applied. In most applications this is not an issue as the ground
pins for the power supplies will be connected to the ground pins
of the AD5370 via ground planes. Where the AD5370 is to be
used in a hot-swap card care should be taken to ensure that the
ground pins are connected to the supply grounds before the
positive or negative supplies are connected. This is required to
prevent currents flowing in directions other than towards an
analog or digital ground.
INTERFACING EXAMPLES
ADSP-21065L
AD537x
The SPI interface of the AD5370 is designed to allow the parts
to be easily connected to industry standard DSPs and micro-
controllers. Figure 11 shows how the AD5370 could be
connected to the Analog Devices Blackfin® DSP. The Blackfin
has an integrated SPI port which can be connected directly to
the SPI pins of the AD5370 and programmable I/O pins which
can be used to set or read the state of the digital input or output
pins associated with the interface.
TFSx
RFSx
SYNC
TCLKx
RCLKx
SCLK
SDI
DTxA
DRxA
SDO
FLAG0
FLAG1
FLAG2
FLAG3
RESET
LDAC
CLR
BUSY
AD537x
537x-0101
SPISELx
SCK
SYNC
SCLK
SDI
Figure 12. Interfacing to an ADSP-21065L DSP
MOSI
MISO
SDO
PF10
PF9
PF8
PF7
RESET
LDAC
CLR
ADSP-BF531
BUSY
537x-0101
Figure 11. Interfacing to a Blackfin DSP
Rev. PrF | Page 22 of 24
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5370
0.75
0.60
0.45
12.00
BSC SQ
1.60
MAX
64
49
1
48
SEATING
PLANE
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
10°
1.45
1.40
1.35
6°
2°
0.20
0.09
VIEW A
7°
3.5°
16
33
0.15
0.05
0°
17
32
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BCD
Figure 13. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
49
48
64
1
PIN 1
INDICATOR
*
7.25
7.10 SQ
6.95
8.75
BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
TOP
VIEW
0.45
0.40
0.35
33
32
16
17
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 14. 64-Lead Free Chip Scale Package [LFCSP]
(CP-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5370BSTZ
AD5370BCPZ
Temperature Range
-40°C to +85°C
-40°C to +85°C
Package Description
Package Option
ST-64
CP-64
64-Lead Quad Flat Pack (LQFP)
64-Lead Free Chip Scale Package (LFCSP)
Rev. PrF | Page 23 of 24
Preliminary Technical Data
NOTES
AD5370
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05813-0-10/06(PrF)
Rev. PrF | Page 24 of 24
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