AD5391BCPZ-3_技术文档

8-/16-Channel, 3 V/5 V, Serial Input,

Single-Supply, 12-/14-Bit Voltage Output

AD5390/AD5391/AD5392

Data Sheet

I²C-compatible interface

Integrated functions

channel monitor

FEATURES

AD5390: 16-channel, 14-bit voltage output DAC

AD5391: 16-channel, 12-bit voltage output DAC

AD5392: 8-channel, 14-bit voltage output DAC

Guaranteed monotonic

simultaneous output update via

LDAC

clear function to user-programmable code

amplifier boost mode to optimize slew rate

user-programmable offset and gain adjust

toggle mode enables square wave generation

thermal monitor

INL

1 LSB max (AD5391)

3 LSB max (AD5390-5/AD5392-5)

4 LSB max (AD5390-3/AD5392-3)

On-chip 1.25 V/2.5 V, 10 ppm/°C reference

Temperature range: −40°C to +85°C

Rail-to-rail output amplifier

Power-down mode

Robust 6.5 kV HBM and 2 kV FICDM ESD rating

APPLICATIONS

Instrumentation and industrial control

Power amplifier control

Level setting (ATE)

Package types

64-lead LFCSP (9 mm × 9 mm)

52-lead LQFP (10 mm × 10 mm)

User interfaces

Control systems

Microelectromechanical systems (MEMs)

Variable optical attenuators (VOAs)

Optical transceivers (MSA 300, XFP)

Serial SPI-, QSPI-, MICROWIRE-, and DSP-compatible

(featuring data readback)

FUNCTIONAL BLOCK DIAGRAM

DV

(×3)

DGND (×3/×4)

AV

(×2)

AGND (×2)

DAC_GND (×2)

REF_GND

REFOUT/REFIN SIGNAL_GND (×2)

DD

1.25V/2.5V

REFERENCE

AD5390

2

SPI/I C

INPUT

REG

0

DAC

14

REG

0

DAC 0

DCEN/AD1

VOUT 0

14

m REG0

c REG0

DIN/SDA

SCLK/SCL

SYNC/AD0

SDO

R

STATE

R

INTERFACE MACHINE

CONTROL

LOGIC

AND

CONTROL

LOGIC

INPUT

REG

1

DAC

REG

1

14

DAC 1

VOUT 1

VOUT 2

VOUT 3

VOUT 4

VOUT 5

VOUT 6

14

m REG1

c REG1

BUSY

PD

INPUT

REG

6

DAC

REG

6

14

DAC 6

DAC 7

CLR

POWER-ON

RESET

14

RESET

m REG6

c REG6

R

V

0

V

15

IN

INPUT

DAC

REG

7

14

REG

7

VOUT 7

VOUT 8

14

MON_IN1

MON_IN2

m REG7

c REG7

MUX

×2

VOUT 15

LDAC

MON_OUT

Figure 1.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

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Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD5390/AD5391/AD5392

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

I²C Serial Interface ..................................................................... 27

I²C Write Operation ....................................................................... 28

4-Byte Mode................................................................................ 28

3-Byte Mode................................................................................ 29

2-Byte Mode................................................................................ 30

AD539x On-Chip Special Function Registers........................ 31

Control Register Write............................................................... 33

Hardware Functions....................................................................... 35

Reset Function ............................................................................ 35

Asynchronous Clear Function.................................................. 35

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 4

Specifications..................................................................................... 5

AD5390-5/AD5391-5/AD5392-5 Specifications ..................... 5

AD5390-5/AD5391-5/AD5392-5 AC Characteristics............. 7

AD5390-3/AD5391-3/AD5392-3 Specifications ..................... 8

AD5390-3/AD5391-3/AD5392-3 AC Characteristics........... 10

Timing Characteristics................................................................... 11

and

Functions...................................................... 35

LDAC

BUSY

Serial SPI-, QSPI-, MICROWIRE-, and DSP-Compatible

Interface ....................................................................................... 11

Power-On Reset.......................................................................... 35

Power-Down ............................................................................... 35

Microprocessor Interfacing....................................................... 35

Application Information................................................................ 37

Power Supply Decoupling ......................................................... 37

Typical Configuration Circuit .................................................. 37

AD539x Monitor Function ....................................................... 38

Toggle Mode Function............................................................... 38

Thermal Monitor Function....................................................... 38

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 41

I²C Serial Interface...................................................................... 13

Absolute Maximum Ratings.......................................................... 14

ESD Caution................................................................................ 14

Pin Configuratons and Function Descriptions .......................... 15

Terminology .................................................................................... 18

Typical Performance Characteristics ........................................... 19

Functional Description.................................................................. 23

DAC Architecture....................................................................... 23

Data Decoding ............................................................................ 24

Interfaces.......................................................................................... 25

DSP-, SPI-, and MICROWIRE-Compatible Serial Interface 25

REVISION HISTORY

6/12—Rev. D to Rev. E

1/09—Rev. B to Rev. C

Changes to Table 1........................................................................... 4

Change to Accuracy Parameter, Gain Error, Table 2 ................... 5

Change to Accuracy Parameter, Gain Error, Table 4 ................... 8

Added Exposed Pad Notation to Figure 7 and Figure 8............ 15

Updated Format..................................................................Universal

Changes to Figure 33...................................................................... 27

Added Figure 34 and Renumbered Sequentially........................ 27

Changes to Figure 34...................................................................... 28

Changes to Table 28 ....................................................................... 33

Change order of Figure 41 and Figure 42.................................... 36

Changes to Toggle Mode Function Section ................................ 37

5/12—Rev. C to Rev. D

Changes to Product Title and Features Section............................ 1

Changes to Table 2 ............................................................................ 4

Changes to Table 3............................................................................ 6

Changes to Table 4............................................................................ 7

Changes to Table 5 ............................................................................ 9

Changes to Table 6.......................................................................... 10

Changes to Table 8.......................................................................... 13

Changes to Figure 8 and Figure 10............................................... 14

Changes to Table 9.......................................................................... 16

Changes to Figure 17, Figure 18, Figure 19, And Figure 22...... 19

Changes to Figure 23, Figure 24, Figure 25, and Figure 26....... 20

Changes to Table 26........................................................................ 32

Changes to Ordering Guide .......................................................... 40

3/06—Rev. A to Rev. B

Changes to Figure 1...........................................................................1

Changes to Table 9.......................................................................... 14

Changes to Table 12 and Table 15 ................................................ 23

Updated Outline Dimensions....................................................... 39

Changes to Ordering Guide.......................................................... 40

Rev. E | Page 2 of 44

Data Sheet

AD5390/AD5391/AD5392

10/04—Rev. 0 to Rev. A

Changes to Figure 36 ......................................................................35

Changes to Figure 37 ......................................................................36

Changes to Figure 38 ......................................................................36

Changes to Ordering Guide...........................................................41

Changes to Features ..........................................................................1

Changes to Table 1 ............................................................................3

Changes to Table 2 ............................................................................4

Changes to Table 3 ............................................................................6

Changes to Table 4 ............................................................................7

4/04—Revision 0: Initial Version

Rev. E | Page 3 of 44

AD5390/AD5391/AD5392

Data Sheet

GENERAL DESCRIPTION

The AD5390/AD5391 are complete single-supply, 16-channel,

14-bit and 12-bit DACs, respectively. The AD5392 is a complete

single-supply, 8-channel, 14-bit DAC. The devices are available

in either a 64-lead LFCSP or a 52-lead LQFP. All channels have

an on-chip output amplifier with rail-to-rail operation. All

devices include an internal 1.25/2.5 V, 10 ppm/°C reference, an

on-chip channel monitor function that multiplexes the analog

outputs to a common MON_OUT pin for external monitoring,

and an output amplifier boost mode that optimizes the output

amplifier slew rate.

The AD5390/AD5391/AD5392 contain a 3-wire serial interface

with interface speeds in excess of 30 MHz that are compatible

with SPI®, QSPI™, MICROWIRE™, and DSP interface standards

and an I²C-compatible interface supporting a 400 kHz data

transfer rate.

An input register followed by a DAC register provides double-

buffering, allowing DAC outputs to be updated independently

or simultaneously using the

input. Each channel has a

LDAC

programmable gain and offset adjust register, letting the user

fully calibrate any DAC channel.

Power consumption is typically 0.25 mA per channel.

Table 1. Additional High Channel Count, Low Voltage, Single-Supply DACs in Portfolio

Model

Resolution AV_DDRange

Output

Channels

Linearity Error (LSB)

Package Description

Package Option

AD5380BSTZ-5

AD5380BSTZ-3

AD5381BSTZ-5

AD5381BSTZ-3

AD5382BSTZ-5

AD5382BSTZ-3

AD5383BSTZ-5

AD5383BSTZ-3

14 Bits

12 Bits

14 Bits

12 Bits

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

40

32

4

1

4

1

100-Lead LQFP

ST-100

Rev. E | Page 4 of 44

Data Sheet

AD5390/AD5391/AD5392

SPECIFICATIONS

AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS

AV_DD= 4.5 V to 5.5 V; DV_DD= 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external. All specifications T_MINto T_MAX

,

unless otherwise noted.

Table 2.

AD5390-5¹

Parameter

AD5392-5¹AD5391-5¹

Unit

Test Conditions/Comments

ACCURACY

Resolution

14

3

−1/+2

4

12

1

Bits

Relative Accuracy

Differential Nonlinearity

Zero-Scale Error

Offset Error

LSB max

mV max

Guaranteed monotonic over temperature

4

Measured at Code 32 in the linear region

(AD5390-5/AD5392-5); measured at Code 8 in

the linear region (AD5391-5)

Offset Error TC

Gain Error

5

0.05

0.06

2

5

0.05

0.06

µV/°C typ

% FSR max

ppm FSR/°C typ

LSB max

At 25°C T_MINto T_MAX

Gain Temperature Coefficient²

DC Crosstalk²

2

1

REFERENCE INPUT/OUTPUT

Reference Input²

Reference Input Voltage

2.5

V

1% for specified performance,

AV_DD= 2 × REFIN + 50 mV

DC Input Impedance

Input Current

1

MΩ min

µA max

Typically 100 MΩ

Typically 30 nA

Reference Range

Reference Output³

1 V to AV_DD/2 1 V to AV_DD/2

V min/max

Enabled via internal/external bit in control

register; REF select bit in control register

selects the reference voltage

Output Voltage

Reference TC

2.495/2.505 2.495/2.505

V min/max

ppm max

Ω typ

At ambient, optimized for 2.5 V operation

At ambient when 1.25 V reference is selected

Temperature range: 25°C to 85°C

1.22/1.28

10

1.22/1.28

10

15

Temperature range: −40°C to +85°C

Output Impedance

OUTPUT CHARACTERISTICS²

Output Voltage Range⁴

Short-Circuit Current

Load Current

800

0/AV_DD

V min/max

mA max

40

1

40

1

Capacitive Load Stability

R_L= ∞

200

1000

0.6

200

1000

0.6

pF max

Ω max

R_L= 5 kΩ

DC Output Impedance

MONITOR OUTPUT PIN

Output Impedance

Three-State Leakage Current

LOGIC INPUTS²

1000

100

1000

100

Ω typ

nA typ

DV_DD= 2.7 V to 5.5 V

V_IH, Input High Voltage

V_IL, Input Low Voltage

DVDD > 3.6 V

DVDD ≤ 3.6 V

Input Current

2

V min

0.8

0.6

10

0.8

0.6

10

V max

µA max

pF max

Total for all pins, T_A= T_MINto T_MAX

Pin Capacitance

10

Rev. E | Page 5 of 44

AD5390/AD5391/AD5392

Data Sheet

AD5390-5¹

Parameter

AD5392-5¹AD5391-5¹

Unit

Test Conditions/Comments

LOGIC INPUTS (SCL, SDA Only)

V_IH, Input High Voltage

V_IL, Input Low Voltage

I_IN, Input Leakage Current

V_HYST, Input Hysteresis

C_IN, Input Capacitance

Glitch Rejection

0.7 × DV_DD

0.3 × DV_DD

1

0.05 × DV_DD0.05 × DV_DD

8

0.7 × DV_DD

0.3 × DV_DD

1

V min

SMBus-compatible at DV_DD< 3.6 V

V max

µA max

V min

pF typ

ns max

8

50

Input filtering suppresses noise spikes of <50 ns

LOGIC OUTPUTS (BUSY, SDO)²

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

High Impedance Leakage Current

High Impedance Output Capacitance

LOGIC OUTPUT (SDA)²

V_OL, Output Low Voltage

0.4

DV_DD− 1

0.4

DV_DD− 0.5

1

5

0.4

DV_DD− 1

0.4

DV_DD− 0.5

1

5

V max

V min

V max

V min

µA max

pF typ

DV_DD= 5 V 10%, sinking 200 µA

DV_DD= 5 V 10%, SDO only, sourcing 200 µA

DV_DD= 2.7 V to 3.6 V, sinking 200 µA

DV_DD= 2.7 V to 3.6 V SDO only, sourcing 200 µA

0.4

0.6

1

0.4

0.6

1

V max

µA max

pF typ

I_SINK= 3 mA

I_SINK= 6 mA

Three-State Leakage Current

Three-State Output Capacitance

POWER REQUIREMENTS

AV_DD

8

4.5/5.5

2.7/5.5

4.5/5.5

2.7/5.5

V min/max

DV_DD

Power Supply Sensitivity²

∆Midscale/∆AV_DD

AI_DD

−85

0.375

−85

0.375

dB typ

mA/channel

max

Outputs unloaded, boost off,

0.25 mA/channel typ

AI_DD

0.475

mA/channel

max

Outputs unloaded, boost on,

0.325 mA/channel typ

DI_DD

1

mA max

µA max

mW max

V_IH= DV_DD, V_IL= DGND

Typically 100 nA

Typically 1 µA

AD5390/AD5391 with outputs unloaded,

AV_DD= DV_DD= 5 V, boost off

AI_DD(Power-Down)

DI_DD(Power-Down)

Power Dissipation

20

35

20

35

20

mW max

AD5392 with outputs unloaded,

AV_DD= DV_DD= 5 V, boost off

¹AD539x-5 products are calibrated with a 2.5 V reference. Temperature range for all versions: −40°C to +85°C.

²Guaranteed by characterization, not production tested.

³Programmable either to 1.25 V typical or 2.5 V typical via the AD539x control register. Operating the AD539x-5 products with a reference of 1.25 V leads to a

degradation in performance accuracy.

⁴Accuracy guaranteed from VOUT = 10 mV to AV_DD− 50 mV.

Rev. E | Page 6 of 44

Data Sheet

AD5390/AD5391/AD5392

AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS

AV_DD= 4.5 V to 5.5 V; DV_DD= 2.7 V to 5.5 V; AGND = DGND = 0 V.

Table 3.

Parameter

All¹

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

AD5390/AD5392

¼ scale to ¾ scale change settling to 1 LSB

Boost mode off, CR11 = 0

Boost mode on

3

8

3

8

µs typ

µs max

µs typ

µs max

AD5391

Slew rate²

2.5

1.5

12

15

100

1

0.8

0.1

15

40

V/µs typ

nV-s typ

mV typ

dB typ

nV-s typ

µV p-p typ

Boost mode off

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

Channel-to-Channel Isolation

DAC-to-DAC Crosstalk

Digital Crosstalk

Digital Feedthrough

See the Terminology section

Effect of input bus activity on DAC output under test

External reference midscale loaded to DAC

Internal reference midscale loaded to DAC

Output Noise (0.1 Hz to 10 Hz)

Output Noise Spectral Density

@ 1 kHz

@ 10 kHz

150

100

nV/(Hz)^1/2typ

¹Guaranteed by characterization, not production tested.

²The slew rate can be adjusted via the current boost control bit in the DAC control register.

Rev. E | Page 7 of 44

AD5390/AD5391/AD5392

Data Sheet

AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS

AV_DD= 2.7 V to 3.6 V; DV_DD= 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications T_MINto T_MAX

,

unless otherwise noted.

Table 4.

AD5390-3¹

Parameter

AD5392-3¹

AD5391-3¹

Unit

Test Conditions/Comments

ACCURACY

Resolution

14

4

−1/+2

4

12

1

Bits

Relative Accuracy

Differential Nonlinearity

Zero-Scale Error

Offset Error

LSB max

mV max

Guaranteed monotonic over temperature

Measured at code 64 in the linear region

4

mV max

Offset Error TC

Gain Error

5

µV/°C typ

% FSR max

ppm FSR/°C typ

LSB max

0.05

0.1

2

0.05

0.1

2

At 25°C

T_MINto T_MAX

Gain Temperature Coefficient²

DC Crosstalk

1

REFERENCE INPUT/OUTPUT

Reference Input²

Reference Input Voltage

DC Input Impedance

Input Current

Reference Range

Reference Output³

1.25

1

1.25

1

V

1% for specified performance

Typically 100 MΩ

Typically 30 nA

MΩ min

µA max

V min/max

1 V to AV_DD/2

Enabled via internal/external bit in control

register; REF select bit in control register

selects the reference voltage

Output Voltage

Reference TC

1.245/1.255

2.47/2.53

10

15

800

1.245/1.255

2.47/2.53

10

15

800

V min/max

ppm max

Ω typ

At ambient, optimized for 1.25 V operation

At ambient when 2.5 V reference is selected

Temperature range: 25°C to 85°C

Temperature range: −40°C to +85°C

Output Impedance

OUTPUT CHARACTERISTICS²

Output Voltage Range⁴

Short-Circuit Current

Load Current

0/AV_DD

40

1

0/AV_DD

40

1

V min/max

mA max

Capacitive Load Stability

R_L= ∞

R_L= 5 kΩ

DC Output Impedance

MONITOR OUTPUT PIN²

Output Impedance

Three-State Leakage Current

LOGIC INPUTS²

200

1000

0.6

200

1000

0.6

pF max

Ω max

1000

100

1000

100

Ω typ

nA typ

DV_DD= 2.7 V to 5.5 V

V_IH, Input High Voltage

V_IL, Input Low Voltage

DVDD > 3.6 V

DVDD ≤ 3.6 V

Input Current

2

V min

0.8

0.6

10

0.8

0.6

10

V max

µA max

pF max

Total for all pins. T_A= T_MINto T_MAX

Pin Capacitance

10

Rev. E | Page 8 of 44

Data Sheet

AD5390/AD5391/AD5392

AD5390-3¹

AD5392-3¹

Parameter

AD5391-3¹

Unit

Test Conditions/Comments

Logic Inputs (SCL, SDA Only)

V_IH, Input High Voltage

V_IL, Input Low Voltage

I_IN, Input Leakage Current

V_HYST, Input Hysteresis

Glitch Rejection

0.7 × DV_DD

0.3 × DV_DD

1

0.05 × DV_DD

50

0.7 × DV_DD

0.3 × DV_DD

1

0.05 × DV_DD

50

V min

SMBus-compatible at DV_DD< 3.6 V

V max

µA max

V min

ns max

Input filtering suppresses noise spikes <50 ns

Logic Outputs (BUSY, SDO)²

Output Low Voltage

Output High Voltage

0.4

DV_DD− 0.5

DV_DD− 0.1

1

5

0.4

DV_DD− 0.5

DV_DD− 0.1

1

5

V max

V min

µA max

pF typ

DV_DD= 2.7 V to 5.5 V, sinking 200 µA

DV_DD= 2.7 V to 3.6 V, SDO only, sourcing 200 µA

DV_DD= 4.5 V to 5.5 V, SDO only, sourcing 200 µA

High Impedance Leakage Current

High Impedance Output

Capacitance

Logic Output (SDA)²

V_OL, Output Low Voltage

0.4

0.6

1

0.4

0.6

1

V max

µA max

pF typ

I_SINK= 3 mA

I_SINK= 6 mA

Three-State Leakage Current

Three-State Output

Capacitance

8

POWER REQUIREMENTS

AV_DD

DV_DD

2.7/3.6

2.7/5.5

2.7/3.6

2.7/5.5

V min/max

Power Supply Sensitivity²

∆Midscale/∆AV_DD

AI_DD

−85

0.375

−85

0.375

dB typ

mA/channel

max

Outputs unloaded, boost off,

0.25 mA/channel typ

AI_DD

0.475

mA/channel

max

Outputs unloaded, boost on,

0.325 mA/channel typ

DI_DD

1

mA max

µA max

mW max

V_IH= DV_DD, V_IL= DGND

Typically 100 nA

Typically 1 µA

AD5390/AD5391 with outputs unloaded,

AV_DD= DV_DD= 3 V, boost off

AI_DD(Power-Down)

DI_DD(Power-Down)

Power Dissipation

20

21

20

21

12

mW max

AD5392 with outputs unloaded,

AV_DD= DV_DD= 3 V, boost off

¹AD539x-3 products are calibrated with a 1.25 V reference. Temperature range for all versions: −40°C to +85°C.

²Guaranteed by characterization, not production tested.

³Programmable either to 1.25 V typical or 2.5 V typical via the AD539x control register. Operating the AD539x-3 products with a reference of 2.5 V leads to a

degradation in performance accuracy.

⁴Accuracy guaranteed from VOUT = 39 mV to AV_DD− 50 mV.

Rev. E | Page 9 of 44

AD5390/AD5391/AD5392

Data Sheet

AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS

AV_DD= 2.7 V to 3.6 V; DV_DD= 2.7 V to 5.5 V; AGND = DGND = 0 V; C_L= 200 pF to AGND.

Table 5.

Parameter

All¹

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

AD5390/AD5392

¼ scale to ¾ scale change settling to 1 LSB

Boost mode off, CR11 = 0

Boost mode on, CR11 = 1

Boost mode on

3

8

3

8

µs typ

µs max

µs typ

µs max

AD5391

Slew Rate²

2.5

1.5

12

15

100

1

0.8

0.1

15

40

V/µs typ

nV-s typ

mV typ

dB typ

nV-s typ

µV p-p typ

Boost mode off, CR11 = 0

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

Channel-to-Channel Isolation

DAC-to-DAC Crosstalk

Digital Crosstalk

Digital Feedthrough

See the Terminology section

Effect of input bus activity on DAC output under test

External reference midscale loaded to DAC

Internal reference midscale loaded to DAC

OUTPUT NOISE (0.1 Hz to 10 Hz)

Output Noise Spectral Density

@ 1 kHz

@ 10 kHz

150

100

nV/(Hz)^1/2typ

¹Guaranteed by design and characterization, not production tested.

²The slew rate can be programmed via the current boost control bit in the AD539x control registers.

Rev. E | Page 10 of 44

Data Sheet

AD5390/AD5391/AD5392

TIMING CHARACTERISTICS

SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE

DV_DD= 2 V to 5.5 V; AV_DD= 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications T_MINto T_MAX, unless otherwise noted.

Table 6. 3-Wire Serial Interface¹

Parameter^{2, 3}

Limit at T_MIN, T_MAX

Unit

Description

t₁

t₂

t₃

t₄

33

13

33

10

50

5

4.5

30

670

20

2

ns min

ns max

ns min

μs max

ns min

µs typ

ns min

µs max

ns max

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC falling edge to SCLK falling edge setup time

24^thSCLK falling edge to SYNC falling edge

Minimum SYNC low time

4

t₅

4

t₆

t₇

t₈

t₉

Minimum SYNC high time

Minimum SYNC high time in readback mode

Data setup time

Data hold time

24^thSCLK falling edge to BUSY falling edge

BUSY pulse width low (single channel update)

24^thSCLK falling edge to LDAC falling edge

LDAC pulse width low

4

t₁₀

t₁₁

4

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

BUSY rising edge to DAC output response time

BUSY rising edge to LDAC falling edge

LDAC falling edge to DAC output response time

DAC output settling time, AD5390/AD5392

DAC output settling time, AD5391

CLR pulse width low

0

100

8

6

20

40

20

5

CLR pulse activation time

5

t₂₀

t₂₁

SCLK rising edge to SDO valid

SCLK falling edge to SYNC rising edge

SYNC rising edge to SCLK rising edge

SYNC rising edge to LDAC falling edge

4

t₂₂

8

4

t₂₃

20

¹Guaranteed by design and characterization, not production tested.

²All input signals are specified with tr = tf = 5 ns (10% to 90% of V_CC) and timed from a voltage level of 1.2 V.

³See Figure 2, Figure 3, Figure 4, and Figure 5.

⁴Standalone mode only.

⁵Daisy-chain mode only.

t₁

SCLK

24

48

t₂₂

t₃

t₂

t₇

t₂₁

SYNC

DIN

t₄

t₈

t₉

DB23

DB0 DB23

DB0

INPUT WORD FOR DAC N

INPUT WORD FOR DAC N+1

t₂₀

DB23

SDO

DB0

t₂₃

UNDEFINED

INPUT WORD FOR DAC N

t₁₃

LDAC

Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)

Rev. E | Page 11 of 44

AD5390/AD5391/AD5392

Data Sheet

t₁

SCLK

24

1

2

t₃

t₂

t₄

t₅

SYNC

t₇

t₆

t₈

t₉

DB23

DIN

DB0

t₁₀

BUSY

t₁₁

t₁₃

t₁₂

1

LDAC

t₁₇

t₁₄

t₁₅

VOUT 1

t₁₃

t₁₇

2

LDAC

t₁₆

VOUT 2

CLR

t₁₈

t₁₉

VOUT

1

LDAC ACTIVE DURING BUSY

2

Figure 3. Serial Interface Timing Diagram (Standalone Mode)

SCLK

SYNC

24

48

t_7A

DB0

DB23'

DB23

DB0

DB23

DIN

INPUT WORD SPECIFIES

REGISTER TO BE READ

NOP CONDITION

SDO

DB0

UNDEFINED

SELECTED REGISTER DATA

CLOCKED OUT

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

I

200µA

OL

TO

OUTPUT

V

OR

OH (MIN)

OL (MAX)

C

L

50pF

I

OH

200µA

Figure 5. Load Circuit for Digital Output Timing

Rev. E | Page 12 of 44

Data Sheet

AD5390/AD5391/AD5392

I²C SERIAL INTERFACE

DV_DD= 2.7 V to 5.5 V; AV_DD= 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications T_MINto T_MAX, unless otherwise noted.

Table 7. I²C Serial Interface¹

Parameter²

Limit at T_MIN, T_MAX

Unit

Description

F_SCL

t₁

t₂

t₃

t₄

400

2.5

0.6

1.3

0.6

100

0.9

0

0.6

1.3

300

0

300

0

300

20 + 0.1 C_B

400

kHz max

µs min

ns min

µs max

µs min

ns max

ns min

ns max

ns min

ns max

ns min

pF max

SCL clock frequency

SCL cycle time

t_HIGH, SCL high time

t_LOW, SCL low time

t_HD, _STA, start/repeated start condition hold time

t_SU, _DAT, data setup time

t_HD, _DATdata hold time

t₅

t₆

3

t_HD, _DATdata hold time

t₇

t₈

t₉

t₁₀

t_SU, _STAsetup time for repeated start

t_SU, _STOstop condition setup time

t_BUF, bus free time between a stop and a start condition

t_F, fall time of SDA when transmitting

t_R, rise time of SCL and SDA when receiving (CMOS-compatible)

t_F, fall time of SDA when transmitting

t_F, fall time of SDA when receiving (CMOS-compatible)

t_F, fall time of SCL and SDA when receiving

t_F, fall time of SCL and SDA when transmitting

Capacitive load for each bus line

t₁₁

4

C_B

¹Guaranteed by design and characterization, not production tested.

²See Figure 6.

³A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHMIN of the SCL signal) to bridge the undefined region of SCL’s falling edge.

⁴C_Bis the total capacitance of one bus line in pF; t_Rand t_Fmeasured between 0.3 DV_DDand 0.7 DV_DD

.

SDA

t₉

t₁₁

t₄

t₃

t₁₀

SCL

t₄

t₆

t₂

t₅

t₇

t₈

t₁

REPEATED

START

CONDITION

STOP

CONDITION

START

CONDITION

Figure 6. I²C Interface Timing Diagram

Rev. E | Page 13 of 44

AD5390/AD5391/AD5392

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Transient currents of up to 100 mA do not cause SCR latch-up.

T_A= 25°C, unless otherwise noted.

Stresses above absolute maximum ratings may cause permanent

damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above

those listed in the operational sections of this specification is

not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Table 8.

Parameter

Rating

AV_DDto AGND

−0.3 V to +7 V

DV_DDto DGND

−0.3 V to +7 V

Digital Inputs to DGND

Digital Outputs to DGND

VREF to AGND

−0.3 V to DV_DD+ 0.3 V

−0.3 V to +7 V

ESD CAUTION

REFOUT to AGND

AGND to DGND

VOUTX to AGND

−0.3 V to +7 V

−0.3 V to +0.3 V

−0.3 V to AV_DD+ 0.3 V

ESD

HBM

FICSM

6.5 kV

2 kV

Operating Temperature Range

Commercial (B Version)

Storage Temperature Range

Junction Temperature (T_Jmax)

64-Lead LFCSP, θ_JA

52-Lead LQFP, θ_JA

Reflow Soldering Peak Temperature

−40°C to +85°C

−65°C to +150°C

150°C

22°C/W

38°C/W

230°C

Rev. E | Page 14 of 44

Data Sheet

AD5390/AD5391/AD5392

PIN CONFIGURATONS AND FUNCTION DESCRIPTIONS

52 51 50 49 48 47 46 45 44 43 42 41 40

CLR

NC

1

2

39 LDAC

38 BUSY

37 RESET

PIN 1

1

2

48 NC

47 BUSY

46 RESET

45 NC

44 NC

43 NC

42 NC

41 NC

40 NC

39 NC

38 NC

NC

3

INDICATOR

NC

3

36

35

34

33

32

31

30

29

28

27

REF_GND

REFOUT/REFIN

SIGNAL_GND 1

DAC_GND 1

4

NC

AV

PIN 1

4

NC

INDICATOR

5

NC

AD5390/

AD5391

TOP VIEW

(Not to Scale)

6

NC

7

REF_GND

REFOUT/REFIN

SIGNAL_GND 1

DAC_GND 1

AD5390/

AD5391

7

8

AV

1

2

DD

9

10

11

12

13

14

15

9

VOUT 0

VOUT 1

VOUT 2

VOUT 3

VOUT 4

AGND 2

TOP VIEW

AV

1

DD

(Not to Scale)

10

11

12

13

VOUT 15

VOUT 0

VOUT 1

VOUT 2

VOUT 3

37 AV

2

DD

VOUT 14

36 AGND 2

35 VOUT 15

34 VOUT 14

33 VOUT 13

VOUT 13

SIGNAL_GND 2

VOUT 4 16

14 15 16 17 18 19 20 21 22 23 24 25 26

NC = NO CONNECT

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD SHOULD BE CONNECTED TO THE GROUND PLANE.

Figure 7. AD5390/AD5391 LFCSP Pin Configuration

Figure 9. AD5390/AD5391 LQFP Pin Configuration

52 51 50 49 48 47 46 45 44 43 42 41 40

CLR

NC

1

2

39 LDAC

38 BUSY

37 RESET

36 NC

1

2

NC

48 NC

47 BUSY

46 RESET

45 NC

44 NC

43 NC

42 NC

41 NC

40 NC

39 NC

38 NC

37 NC

36 NC

35 NC

34 NC

33 NC

PIN 1

NC

3

NC

INDICATOR

PIN 1

3

REF_GND

REFOUT/REFIN

SIGNAL_GND 1

DAC_GND 1

4

INDICATOR

4

NC

5

35

34

33

32

31

30

29

28

NC

5

NC

6

NC

6

AD5392

7

REF_GND

REFOUT/REFIN

SIGNAL_GND 1

DAC_GND 1

7

AD5392

TOP VIEW

(Not to Scale)

8

TOP VIEW

(Not to Scale)

9

8

AV

1

DD

10

11

12

13

14

15

9

VOUT 0

VOUT 1

VOUT 2

VOUT 3

VOUT 4

AV

1

DD

VOUT 0

VOUT 1

VOUT 2

VOUT 3

10

11

12

13

VOUT 4 16

27 SIGNAL_GND 2

14 15 16 17 18 19 20 21 22 23 24 25 26

NC = NO CONNECT

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD SHOULD BE CONNECTED TO THE GROUND PLANE.

Figure 8. AD5392 LFCSP Pin Configuration

Figure 10. AD5392 LQFP Pin Configuration

Rev. E | Page 15 of 44

AD5390/AD5391/AD5392

Data Sheet

Table 9. Pin Function Descriptions

Mnemonic

Function

VOUT X

Buffered Analog Outputs for Channel X. Each analog output is driven by a rail-to-rail output amplifier operating at a gain

of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.

SIGNAL_GND 1,

SIGNAL_GND 2

Analog Ground Reference Points for each group of eight output channels. All SIGNAL_GND pins are tied together

internally and should be connected to the AGND plane as close as possible to the AD539x.

DAC_GND 1,

DAC_GND 2

Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DACs.

These pins should be connected to the AGND plane.

AGND 1, AGND 2 Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be

connected externally to the AGND plane.

AV_DD1, AV_DD

2

Analog Supply Pins. Each group of eight channels has a separate AV_DDpin. These pins should be decoupled with 0.1 uF

ceramic capacitors and 10 µF tantalum capacitors. Operating range is 5 V 10%.

DGND

DV_DD

Ground for All Digital Circuitry.

Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. Recommended that these pins be decoupled with

0.1 µF ceramic capacitors and 10 µF tantalum capacitors to DGND.

REF_GND

Ground Reference Point for the Internal Reference. Connect to AGND.

REFOUT/REFIN

The AD539x contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference

output. If the application necessitates the use of an external reference, it can be applied to this pin and the internal

reference disabled via the control register. The default for this pin is a reference input.

MON_OUT

Analog Output Pin. When the monitor function is enabled on the AD5390/AD5391, the MON_OUT acts as the output of

a 16-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin. When the

monitor function is enabled on the AD5392, the MON_OUT acts as the output of an 8-to-1 channel multiplexer that can

be programmed to multiplex any channel output to the MON_OUT pin. The MON_OUT pin output impedance is

typically 500 Ω and is intended to drive a high input impedance such as that exhibited by SAR ADC inputs.

MON_IN 1,

MON_IN 2

Monitor Input Pins. The AD539x contains two monitor input pins to which the user can connect input signals (within the

maximum ratings of the device) for monitoring purposes. Any of the signals applied to the MON_IN pins along with the

output channels can be switched to the MON_OUT pin via software. An external ADC, for example, can be used to

monitor these signals.

SYNC/AD0

DCEN/AD1

Serial Interface Pin. This is the frame synchronization input signal for the serial interface. When taken low, the internal

counter is enabled to count the required number of clocks before the addressed register is updated.

In I²C mode, AD0 acts as a hardware address pin.

Interface Control Pin. Operation is determined by the interface select bit SPI/I²C.

Serial Interface Mode: Daisy-Chain Select Input (level-sensitive, active high). When high, this pin enables daisy-chain

operation to allow a number of devices to be cascaded together.

I²C Mode: This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for

this device on the I²C bus.

SDO

Serial Data Output. Three-state CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is

clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.

BUSY

Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During

this time, the user can continue writing new data to further the x1, c, and m registers (these are stored in a FIFO), but no

further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is

stored. BUSY also goes low during power-on reset and when the RESET pin is low. During this time the interface is

disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low.

LDAC

Load DAC Logic Input (active low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers

are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and

internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes

inactive. However, any events on LDAC during power-on reset or RESET are ignored.

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored.

When CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a

duration of 20 µs (AD5390/AD5391) and 15 µs (AD5392) while all channels are being updated with the CLR code.

RESET

Asynchronous Digital Reset Input (falling edge sensitive). The function of this pin is equivalent to that of the power-on

reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and

x2 registers to their default power-on values. This sequence takes 270 µs maximum. This falling edge of RESET initiates

the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all

interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation

and the status of the RESET pin is ignored until the next falling edge is detected.

Rev. E | Page 16 of 44

Data Sheet

AD5390/AD5391/AD5392

Mnemonic

Function

PD

Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes

1 µA analog current and 20 µA digital current. In power-down mode, all internal analog circuitry is placed in low power

mode; the analog output is configured as high impedance outputs or provides a 100 kΩ load to ground, depending on

how the power-down mode is configured. The serial interface remains active during power-down.

SPI/I²C

Interface Select Input Pin. When this input is low, I²C mode is selected. When this input is high, SPI mode is selected.

SCLK/SCL

Interface Clock Input Pin. In SPI-compatible serial interface mode, this pin acts as a serial clock input. It operates at clock

speeds up to 50 MHz.

I²C mode: In I²C mode, this pin performs the SCL function, clocking data into the device. Data transfer rate in I²C mode is

compatible with both 100 kHz and 400 kHz operating modes.

DIN/SDA

Interface Data Input Pin.

SPI/I²C = 1: This pin acts as the serial data input. Data must be valid on the falling edge of SCLK.

SPI/I²C = 0, I²C mode: In I²C mode, this pin is the serial data pin (SDA) operating as an open drain input/output.

TEST

NC

Test pin (AD5392 only). This pin is used for production testing. For normal operation, this pin should not be connected.

No Connect. These pins have no internal connection.

Exposed Pad

(LFCSP only)

This pad should be connected to the ground plane.

Rev. E | Page 17 of 44

AD5390/AD5391/AD5392

Data Sheet

TERMINOLOGY

Relative Accuracy or Endpoint Linearity (INL)

A measure of the maximum deviation from a straight line

passing through the endpoints of the DAC transfer function.

It is measured after adjusting for zero-scale error and full-scale

error and is expressed in least significant bits (LSBs).

DC Output Impedance

The effective output source resistance. It is dominated by

package lead resistance.

Output Voltage Settling Time

The amount of time it takes for the output of a DAC to settle

to a specified level for a ¼ to ¾ full-scale input change. It is

Differential Nonlinearity (DNL)

The difference between the measured change and the ideal

1 LSB change between any two adjacent codes. A specified

differential nonlinearity of 1 LSB maximum ensures mono-

tonicity.

measured from the rising edge of

.

BUSY

Digital-to-Analog Glitch Energy

The amount of energy injected into the analog output at the

major code transition. It is specified as the area of the glitch in

nV-s. It is measured by toggling the DAC register data between

0x1FFF and 0x2000.

Zero-Scale Error

The error in the DAC output voltage when all 0s are loaded

into the DAC register. Ideally, with all 0s loaded to the DAC

and m = all 1s, c = 2ⁿ⁻¹, VOUT_(Zero-Scale)= 0 V.

DAC-to-DAC Crosstalk

The glitch impulse that appears at the output of one DAC due to

both the digital change and subsequent analog output change at

another DAC. The victim channel is loaded with midscale, and

DAC-to-DAC crosstalk is specified in nV-s.

Zero-scale error is a measure of the difference between VOUT

(actual) and VOUT (ideal) expressed in mV. It is mainly caused

by offsets in the output amplifier.

Offset Error

Digital Crosstalk

A measure of the difference between VOUT (actual) and VOUT

(ideal) expressed in mV in the linear region of the transfer

function. Offset error is measured on the AD539x-5 with code

32 loaded in the DAC register and with code 64 loaded in the

DAC register on the AD539x-3.

The glitch impulse transferred to the output of one converter

due to a change in the DAC register code of another converter

is defined as the digital crosstalk and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity

on the device’s digital inputs can be capacitively coupled both

across and through the device to show up as noise on the VOUT

pins. It can also be coupled along the supply and ground lines.

This noise is digital feedthrough.

Gain Error

The deviation in slope of the DAC transfer characteristic from

ideal and is expressed in % FSR with the DAC output unloaded.

Gain error is specified in the linear region of the output range

between VOUT = 10 mV and VOUT = AV_DD− 50 mV.

Output Noise Spectral Density

DC Crosstalk

This is a measure of internally generated random noise. Random

noise is characterized as a spectral density (voltage per √Hz).

It is measured by loading all DACs to midscale and measuring

noise at the output. It is measured in nV/(Hz)^1/2in a 1 Hz

bandwidth at 10 kHz.

The dc change in the output level of one DAC at midscale in

response to a full-scale code (all 0s to all 1s and vice versa) and

the output change of all other DACs. It is expressed in LSBs.

Rev. E | Page 18 of 44

Data Sheet

AD5390/AD5391/AD5392

TYPICAL PERFORMANCE CHARACTERISTICS

1.00

0.75

0.50

0.25

0

2.0

AV

= DV = 5.5V

DD

VREF = 2.5V

= 25°C

1.5

T

A

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.25

–0.50

–0.75

–1.00

0

512

1024

1536

2048

2560

3072

3584

4096

0

4096

8192

12288

16384

INPUT CODE

Figure 14. Typical AD5391-5 INL Plot

Figure 11. AD5390-5/AD5392-5 Typical INL Plot

1.00

0.75

0.50

0.25

0

2.0

AV

= DV = 3V

DD

VREF = 1.25V

1.5

1.0

T

= 25°C

A

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.25

–0.50

–0.75

–1.00

0

512

1024

1536

2048

2560

3072

3584

4096

0

4096

8192

12288

16384

INPUT CODE

Figure 12. AD5390-3/AD5392-3 INL Plot

Figure 15. Typical AD5391-3 INL Plot

40

14

12

10

8

AV

= 5.5V

AV

= 5V

DD

REFIN = 2.5V

= 25°C

REFOUT = 2.5V

TEMP. RANGE = 25°C TO 85°C

SAMPLE SIZE = 162

T

35

30

25

20

15

10

5

A

6

4

2

0

–2

–1

0

1

2

–5.0 –4.0 –3.0 –2.0 –1.0

0

1.0 2.0 3.0 4.0 5.0

INL ERROR DISTRIBUTION (LSB)

–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5

REFERENCE DRIFT (ppm/°C)

Figure 13. AD5390/AD5392 INL Histogram Plot

Figure 16. AD539x REFOUT Temperature Coefficient

Rev. E | Page 19 of 44

AD5390/AD5391/AD5392

Data Sheet

6

5

FULL SCALE

BUSY

AV

= DV = 5V

DD

VREF = 2.5V

3/4 SCALE

4

T = 25°C

A

MIDSCALE

3

2

1/4 SCALE

VOUT

AV

1

= DV = 5V

ZERO SCALE

DD

VREF = 2.5V

0

T

= 25°C

A

–1

–40 –20 –10

–5

–2

0

2

5

10

20

40

CURRENT (mA)

Figure 17. AD539x Exiting Soft Power-Down

Figure 20. AD539x-5 Source and Sink Capability

0.20

0.15

0.10

0.05

0

AV

= 5V

DD

VREF = 2.5V

= 25°C

T

A

PD

ERROR AT ZERO SINKING CURRENT

–0.05

–0.10

–0.15

–0.20

VOUT

(V –VOUT) AT FULL-SCALE SOURCING CURRENT

DD

AV

= DV = 5V

DD

VREF = 2.5V

= 25°C

T

A

0

0.25

0.50

0.75

1.00

/I

1.25

1.50

1.75

2.00

I

(mA)

SOURCE SINK

Figure 18. AD539x Exiting Hardware Power-Down

Figure 21. Headroom at Rails vs. Source/Sink Current

2.510

2.505

2.500

2.995

2.990

AV

= DV = 5V

DD

VREF = 2.5V

T

= 25°C

A

VDD

VOUT

0

2

4

6

8

10

12

TIME (µs)

Figure 19. AD539x Power-Up Transient

Figure 22. AD539x-5 Glitch Impulse Energy

Rev. E | Page 20 of 44

Data Sheet

AD5390/AD5391/AD5392

1.260

DVDD = 5.5V

V

T

= DVDD

= DGND

= 25°C

IH

IL

A

10

8

1.255

1.250

1.245

6

4

2

0

1.240

0

0.5

0.6

0.7

DI

0.8

0.9

1.0

2

4

6

8

10

12

(mA)

DD

TIME (µs)

Figure 23. AD539x-3 Glitch Impulse

Figure 26. AD539x DI_DDHistogram

2.456

2.455

2.454

2.453

2.452

2.451

2.450

2.449

AV

= DV = 5V

DD

VREF = 2.5V

T

= 25°C

A

LDAC

14ns/SAMPLE NUMBER

VOUT

AV

= DV = 5V

DD

VREF = 2.5V

T

= 25°C

A

0

50 100 150 200 250 300 350 400 450 500 550

SAMPLE NUMBER

Figure 27. AD539x Adjacent Channel Crosstalk

Figure 24. AD539x Slew Rate Boost Off

600

500

400

300

200

100

0

AV

= 5V

DD

= 25°C

T

A

REFOUT DECOUPLED

WITH 100nF CAPACITOR

LDAC

REFOUT = 2.5V

VOUT

REFOUT = 1.25V

AV

= DV = 5V

DD

VREF = 2.5V

T

= 25°C

A

100

1k

10k

100k

FREQUENCY (Hz)

Figure 25. AD539x Slew Rate Boost On

Figure 28. AD539x REFOUT Noise Spectral Density

Rev. E | Page 21 of 44

AD5390/AD5391/AD5392

Data Sheet

6

5

AV

= DV = 3V

DD

AV

= DV = 5V

DD

= 25°C

VREF = 1.25V

T

A

T

= 25°C

DAC LOADED WITH MIDSCALE

EXTERNAL REFERENCE

Y AXIS = 5µV/DIV

A

X AXIS = 100ms/DIV

4

3/4 SCALE

FULL SCALE

3

MIDSCALE

2

1

0

ZERO SCALE

–5

1/4 SCALE

–1

–40 –20 –10

–2

0

2

5

10

20

40

CURRENT (mA)

Figure 30. AD539x-3 Source and Sink Current Capability

Figure 29. 0.1 Hz to 10 Hz Output Noise Plot

Rev. E | Page 22 of 44

Data Sheet

AD5390/AD5391/AD5392

FUNCTIONAL DESCRIPTION

The digital input transfer function for each DAC can be

represented as

DAC ARCHITECTURE

The AD5390/AD5391 are complete single-supply, 16-channel,

voltage output DACs offering a resolution of 14 bits and 12 bits,

respectively. The AD5392 is a complete single-supply, 8-channel,

voltage output DAC offering 14-bit resolution. All devices are

available in a 64-lead LFCSP and 52-lead LQFP, and feature

serial interfaces. This family includes an internal select-able

1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the

buffered reference inputs (alternatively, an external reference

can be used to drive these inputs). All channels have an on-chip

output amplifier with rail-to-rail output capable of driving a

5 kΩ load in parallel with a 200 pF capacitance.

x2 =

where:

(

m+2

)

/2ⁿ

)

×x1+

(

c −2ⁿ⁻¹

)

x2 is the data-word loaded to the resistor-string DAC.

x1 is the 12-bit and 14-bit data-word written to the DAC input

register.

m is the 12-bit and 14-bit gain coefficient (default is all 0x3FFE

on the AD5390/AD5392 and 0xFFE on the AD5391). The LSB

of the gain coefficient is zero.

n = DAC resolution (n = 14 for the AD5390/AD5392 and

n = 12 for the AD5391).

The architecture of a single DAC channel consists of a 12-bit

and 14-bit resistor-string DAC followed by an output buffer

amplifier operating at a gain of 2. This resistor-string architecture

guarantees DAC monotonicity. The 12-bit and 14-bit binary

digital code loaded to the DAC register determines at what

node on the string the voltage is tapped off before being fed to

the output amplifier. Each channel on these devices contains

independent offset and gain control registers, allowing the user

to digitally trim offset and gain.

c is the 12-bit and 14-bit offset coefficient (default is 0x2000 on

the AD5390/AD5392 and 0x800 on the AD5391).

The complete transfer function for these devices can be

represented as

VOUT = 2×VREF × x2/2ⁿ

where:

x2 is the data-word loaded to the resistor-string DAC.

V

_REFis the reference voltage applied to the REFIN/REFOUT pin

AVDD

VREF

on the DAC when an external reference is used (2.5 V for specified

performance on the AD539x-5 products and 1.25 V on the

AD539x-3 products).

x1 INPUT

REG

DAC

REG

14-BIT

DAC

INPUT

DATA

m REG

c REG

x2

VOUT

R

Figure 31. Single-Channel Architecture

These registers let the user calibrate out errors in the complete

signal chain including the DAC using the internal m and c

registers, which hold the correction factors. All channels are

double-buffered, allowing synchronous updating of all channels

using the

pin. Figure 31 shows a block diagram of a

LDAC

single channel on the AD5390/AD5391/AD5392.

Rev. E | Page 23 of 44

AD5390/AD5391/AD5392

Data Sheet

AD5391

DATA DECODING

The AD5391 contains an internal 12-bit data bus. The input

data is decoded depending on the value loaded to the REG1 and

REG0 bits of the input serial register. The input data from the

serial input register is loaded into the addressed DAC input

register, offset (c) register, or gain (m) register. The format data

and the offset (c) and gain (m) register contents are shown in

Table 14 to Table 16.

AD5390/AD5392

The AD5390/AD5392 contain an internal 14-bit data bus.

The input data is decoded depending on the data loaded to

the REG1 and REG0 bits of the input serial register. This is

shown in Table 10.

Data from the serial input register is loaded into the addressed

DAC input register, offset (c) register, or gain (m) register. The

format data, and the offset (c) and gain (m) register contents

are shown in Table 11 to Table 13.

Table 14. AD5391 DAC Data Format (REG1 = 1, REG0 = 1)

DB11 to DB0

DAC Output (V)

2 V_REF× (4095/4096)

2 V_REF× (4094/4096)

2 V_REF× (2049/4096)

2 V_REF× (2048/4096)

2 V_REF× (2047/4096)

2 V_REF× (1/4096)

0

1111

0000

1111

0000

1111

1110

0001

0000

1111

0001

0000

Table 10. Register Selection

1111

REG1

REG0

Register Selected

1000

1

0

1

0

1

0

Input data register (x1)

Offset register (c)

Gain register (m)

1000

0111

0000

Special function registers (SFRs)

0000

Table 11. AD5390/AD5392 DAC Data Format

(REG1 = 1, REG0 = 1)

Table 15. AD5391 Offset Data Format (REG1 = 1, REG0 = 0)

DB11 to DB0

Offset (LSB)

+2047

+2046

+1

DB13 to DB0

DAC Output (V)

1111

0000

1111

0000

1111

1110

0001

0000

1111

0001

0000

11 1111

10 0000

01 1111

00 0000

1111

1110

0001

0000

1111

0001

0000

2 V_REF× (16383/16384)

2 V_REF× (16382/16384)

2 V_REF× (8193/16384)

2 V_REF× (8192/16384)

2 V_REF× (8191/16384)

2 V_REF× (1/16384)

0

1111

0000

1111

0000

1000

+0

0111

–1

0000

–2047

–2048

Table 16. AD5391 Gain Data Format (REG1 = 0, REG0 = 1)

Table 12. AD5390/AD5392 Offset Data Format

(REG1 = 1, REG0 = 0)

DB11 to DB0

Gain Factor

1111

1011

0111

0011

1111

0000

1110

0000

1

DB13 to DB0

Offset (LSB)

+8191

+8190

+1

0.75

0.5

0.25

0

111111

100000

1111

0000

1111

0000

1111

1110

0001

0000

1111

0001

0000

100000

+0

011111

–1

000000

–8191

–8192

Table 13. AD5390/AD5392 Gain Data Format

(REG1 = 0, REG0 = 1)

DB13 to DB0

Gain Factor

11 1111

10 1111

01 1111

00 1111

1111

0000

1110

0000

1

0.75

0.5

0.25

0

00 0000

Rev. E | Page 24 of 44

Data Sheet

AD5390/AD5391/AD5392

INTERFACES

The AD5390/AD5391/AD5392 contain a serial interface that

Logic 1 pin to configure this mode of operation. The serial

interface control pins are described in Table 17.

can be programmed to be DSP-, SPI-, and MICROWIRE-

compatible, or I²C-compatible. The SPI/

the interface mode.

pin is used to select

2

I C

Table 17. Serial Interface Control Pins

Description

To minimize both the power consumption of the device and the

on-chip digital noise, the interface fully powers up only when the

device is being written to, that is, on the falling edge of

SYNC, DIN, SCLK Standard 3-wire interface pins.

DCEN

SDO

Selects standalone mode or daisy-chain mode.

Data out pin for daisy-chain mode.

.

SYNC

DSP-, SPI-, AND MICROWIRE-COMPATIBLE SERIAL

INTERFACE

Figure 2 to Figure 4 show timing diagrams for a serial write to

the AD5390/AD5391/AD5392 in both standalone and daisy-

chain mode. The 24-bit data-word format for the serial interface

is shown in Table 18 to Table 20. Descriptions of the bits follow

in Table 21.

The serial interface can be operated with a minimum of three

wires in standalone mode or four wires in daisy-chain mode.

Daisy-chaining allows many devices to be cascaded together to

2

increase system channel count. The SPI/

pin is tied to a

I C

Table 18. AD5390 16-Channel, 14-Bit DAC Serial Input Register Configuration

MSB

LSB

A

/B

W

R/

0

A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Table 19. AD5391 16-Channel, 12-Bit DAC Serial Input Register Configuration

MSB

LSB

A

/B

W

R/

0

A3 A2 A1 A0 REG1 REG0 DB11

DB10

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X

Table 20. AD5392 8-Channel, 14-Bit DAC Serial Input Register Configuration

MSB

LSB

A

/B

W

R/

0

A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Table 21. Serial Input Register Configuration Bit Descriptions

Bit

Description

A/B

When toggle mode is enabled, this bit selects whether the data write is to the A or B register. With toggle mode disabled, this

bit should be set to zero to select the A data register.

R/W

The read or write control bit.

A3 to A0

Used to address the input channels.

REG1 and

REG0

Select the register to which data is written, as outlined in Table 10.

DB13 to

DB0

X

Contain the input data-word.

Don’t care condition.

Rev. E | Page 25 of 44

AD5390/AD5391/AD5392

Data Sheet

Standalone Mode

The serial clock can be either a continuous or a gated clock. A

continuous SCLK source can be used only if the

held low for the correct number of clock cycles. In gated clock

mode, a burst clock containing the exact number of clock cycles

can be

SYNC

By connecting the daisy-chain enable (DCEN) pin low, stand-

alone mode is enabled. The serial interface works with both a

continuous and a noncontinuous serial clock. The first falling

must be used and

taken high after the final clock to latch

SYNC

edge of

starts the write cycle and resets a counter that

SYNC

the data.

counts the number of serial clocks to ensure that the correct

number of bits is shifted into the serial shift register. Any

Readback Mode

further edges on

(except for a falling edge) are ignored

SYNC

Readback mode is invoked by setting the R/ bit = 1 in the serial

W

until 24 bits are clocked in. Once 24 bits have been shifted in,

the SCLK is ignored. For another serial transfer to take place,

input register write sequence. With R/ = 1, Bit A3 to Bit A0

W

in association with Bits REG1 and REG0 select the register to

be read. The remaining data bits in the write sequence are don’t

care bits. During the next SPI write, the data appearing on the

SDO output contains the data from the previously addressed

register. For a read of a single register, the NOP command can be

used in clocking out the data from the selected register on SDO.

the counter must be reset by the falling edge of

.

SYNC

Daisy-Chain Mode

For systems that contain several devices, the SDO pin can be

used to daisy-chain the devices together. This daisy-chain mode

can be useful in system diagnostics and for reducing the number

of serial interface lines.

The readback diagram in Figure 32 shows the readback sequence.

For example, to read back the m register of Channel 0 on the

AD539x, the following sequence should be implemented:

By connecting the DCEN pin high, daisy-chain mode is

enabled. The first falling edge of

starts the write cycle.

SYNC

The SCLK is continuously applied to the input shift register

when is low. If more than 24 clock pulses are applied,

First, write 0x404XXX to the AD539x input register. This

configures the AD539x for read mode with the m register of

Channel 0 selected. Note that all data bits, DB13 to DB0, are

don’t care bits.

SYNC

the data ripples out of the shift register and appears on the

SDO line. This data is clocked out on the rising edge of SCLK

and is valid on the falling edge. By connecting the SDO of the

first device to the DIN input on the next device in the chain,

a multidevice interface is constructed. For each device in the

system, 24 clock pulses are required. Therefore, the total

number of clock cycles must equal 24N where N is the total

number of AD539x devices in the chain.

Follow this with a second write, a NOP condition, and 0x000000.

During this write, the data from the m register is clocked out on

the DOUT line, that is, data clocked out contains the data from

the m register in Bit DB13 to Bit DB0, and the top 10 bits con-

tain the address information as previously written. In readback

mode, the

signal must frame the data. Data is clocked out

SYNC

When the serial transfer to all devices is complete,

is

SYNC

on the rising edge of SCLK and is valid on the falling edge of

the SCLK signal. If the SCLK idles high between the write and

read operations of a readback, the first bit of data is clocked out

taken high. This latches the input data in each device in the

daisy chain and prevents any further data from being clocked

into the input shift register.

on the falling edge of

.

SYNC

If

is taken high before 24 clocks are clocked into the part,

SYNC

it is considered a bad frame and the data is discarded.

SCLK

24

48

SYNC

DIN

DB23

DB0

DB23

DB0

INPUT WORD SPECIFIES REGISTER TO BE READ

NOP CONDITION

SDO

DB23

DB0

DB23

DB0

UNDEFINED

SELECTED REGISTER DATA CLOCKED OUT

Figure 32. Readback Operation

Rev. E | Page 26 of 44

Data Sheet

AD5390/AD5391/AD5392

I²C SERIAL INTERFACE

Repeated START Condition

The AD5390/AD5391/AD5392 feature an I²C-compatible

2-wire interface consisting of a serial data line (SDA) and a

serial clock line (SCL). SDA and SCL facilitate communication

between the DACs and the master at rates up to 400 kHz.

Figure 6 shows the 2-wire interface timing diagram.

A repeated START (Sr) condition may indicate a change of data

direction on the bus. Sr may be used when the bus master is

writing to several I²C devices and does not want to relinquish

control of the bus.

Acknowledge Bit (ACK)

When selecting the I²C operating mode by configuring the

The acknowledge bit (ACK) is the ninth bit attached to any 8-bit

data-word. An ACK is always generated by the receiving device.

The AD539x devices generate an ACK when receiving an address

or data by pulling SDA low during the ninth clock period.

2

SPI/

pin to Logic 0, the device is connected to the I²C bus

I C

as a slave device, that is, no clock is generated by the device.

The AD5390/AD5391/AD5392 have a 7-bit slave address 1010 1

(AD1)(AD0). The five MSBs are hard-coded and the two LSBs

are determined by the state of the AD1 and AD0 pins. The

hardware configuration facility for the AD1 and AD0 pins

allows four of these devices to be configured on the bus.

Monitoring the ACK allows for detection of unsuccessful data

transfers. An unsuccessful data transfer occurs if a receiving

device is busy or if a system fault has occurred. In the event of

an unsuccessful data transfer, the bus master should reattempt

communication.

I²C Data Transfer

One data bit is transferred during each SCL clock cycle. The

data on SDA must remain stable during the high period of the

SCL clock pulse. Changes in SDA while SCL is high are control

signals that configure START and STOP conditions. Both SDA

and SCL are pulled high by the external pull-up resistors when

the I²C bus is not busy.

AD539X Slave Addresses

A bus master initiates communication with a slave device by

issuing a START condition followed by the 7-bit slave address.

When idle, the AD539x device waits for a START condition

followed by its slave address. The LSB of the address word is

the read/write (R/ ) bit. The AD539x devices are receive

W

START and STOP Conditions

devices only and R/ = 0 when communicating with them.

W

A master device initiates communication by issuing a START

condition. A START condition is a high-to-low transition on

SDA with SCL high. A STOP condition is a low-to-high trans-

ition on SDA, while SCL is high. A START condition from the

master signals the beginning of a transmission to the AD539x.

The STOP condition frees the bus. If a repeated START

condition (Sr) is generated instead of a STOP condition, the

bus remains active.

After receiving the proper address 1010 1(AD1) (AD0), the

AD539x issues an ACK by pulling SDA low for one clock cycle.

The AD539x has four user-programmable addresses determined

by the AD1 and AD0 bits.

Rev. E | Page 27 of 44

AD5390/AD5391/AD5392

Data Sheet

I²C WRITE OPERATION

There are three specific modes in which data can be written to

the AD539x family of DACs.

DAC to be addressed and is also acknowledged by the DAC.

Address Bits A3 to A0 address all channels on the AD5390/

AD5391. Address Bits A2 to A0 address all channels on the

AD5392. Address Bit A3 is a zero on the AD5392. Two bytes

of data are then written to the DAC, as shown in Figure 33.

A STOP condition follows. This lets the user update a single

channel within the AD539x at any time and requires four bytes

of data to be transferred from the master.

4-BYTE MODE

When writing to the AD539x DACs, begin with an address byte

W

(R/ = 0), after which the DAC acknowledges that it is prepared

to receive data by pulling SDA low. The address byte is followed

by the pointer byte. This addresses the specific channel in the

SCL

AD1

AD0

R/W

A/B

0

A3

A2

A1

A0

1

0

1

0

1

SDA

START

ACK

BY

MSB

ACK

BY

CONVERTER

CONDITION

BY

ADDRESS BYTE

POINTER BYTE

CONVERTER

MASTER

SCL

SDA

REG1 REG0 DB13 DB12 DB11 DB10 DB9

MOST SIGNIFICANT DATA BYTE

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

ACK

BY

ACK

BY

STOP

CONDITION

BY

LEAST SIGNIFICANT DATA BYTE

CONVERTER

MASTER

Figure 33. AD5390/AD5392 4-Byte Mode I²C Write Operation

SCL

SDA

AD1

AD0

R/W

A/B

0

A3

A2

A1

A0

1

0

1

0

1

START

ACK

BY

MSB

ACK

BY

CONVERTER

CONDITION

BY

ADDRESS BYTE

POINTER BYTE

CONVERTER

MASTER

SCL

SDA

REG1 REG0 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

ACK

BY

CONVERTER

ACK

BY

CONVERTER

STOP

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

CONDITION

BY

MASTER

Figure 34. AD5391 4-Byte Mode I²C Write Operation

Rev. E | Page 28 of 44

Data Sheet

AD5390/AD5391/AD5392

3-BYTE MODE

The 3-byte mode lets the user update more than one channel in

a write sequence without having to write the device address byte

each time. The device address byte is required only once and

subsequent channel updates require the pointer byte and the

data bytes. In 3-byte mode, the user begins with an address byte

on the AD5392. Address Bit A3 is a zero on the AD5392. This is

then followed by the two data bytes. REG1 and REG0 determine

the register to be updated.

If a STOP condition is not sent following the data bytes,

another channel can be updated by sending a new pointer

byte followed by the data bytes. This mode requires only three

bytes to be sent to update any channel once the device has

been initially addressed and reduces the software overhead in

updating the AD539x channels. A STOP condition at any time

exits this mode. Figure 35 shows a typical configuration.

(R/ = 0) after which the DAC acknowledges that it is prepared

W

to receive data by pulling SDA low. The address byte is followed

by the pointer byte; this addresses the specific channel in the

DAC to be addressed and is also acknowledged by the DAC.

Address Bits A3 to A0 address all channels on the

AD5390/AD5391. Address Bits A2 to A0 address all channels

SCL

1

0

1

0

1

AD1

AD0

R/W

A/B

0

A3

A2

A1

A0

SDA

START

ACK

BY

MSB

ACK

BY

CONVERTER

CONDITION

BY

ADDRESS BYTE

POINTER BYTE FOR CHANNEL N

CONVERTER

MASTER

SCL

SDA

REG1 REG0 MSB

LSB

MSB

LSB

ACK

BY

CONVERTER

ACK

BY

CONVERTER

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

DATA FOR CHANNEL N

SCL

SDA

0

A3

A2

A1

A0

MSB

ACK

BY

CONVERTER

POINTER BYTE FOR CHANNEL NEXT CHANNEL

SCL

SDA

REG1 REG0 MSB

MOST SIGNIFICANT DATA BYTE

LSB

MSB

LSB

ACK

BY

ACK

BY

STOP

CONDITION

BY

LEAST SIGNIFICANT DATA BYTE

CONVERTER

MASTER

DATA FOR CHANNEL NEXT CHANNEL

Figure 35. 3-Byte Mode I²C Write Operation

Rev. E | Page 29 of 44

AD5390/AD5391/AD5392

Data Sheet

2-BYTE MODE

The 2-byte mode lets the user update channels sequentially

following initialization of this mode. The device address byte is

required only once and the address pointer is configured for

autoincrement or burst mode.

The REG0 and REG1 bits in the data byte determine the register

to be updated. In this mode, following the initialization, only

the two data bytes are required to update a channel. The

channel address automatically increments from Address 0 to

the final address and then returns to the normal 3-byte mode

of operation. This mode allows transmission of data to all

channels in one block and reduces the software overhead in

configuring all channels. A STOP condition at any time exits

this mode. Toggle mode of operation is not supported in

2-byte mode. Figure 36 shows a typical configuration.

The user must begin with an address byte (R/ = 0), after

W

which the DAC acknowledges that it is prepared to receive data

by pulling SDA low. The address byte is followed by a specific

pointer byte (0xFF), which initiates the burst mode of opera-

tion. The address pointer initializes to Channel 0 and the data

following the pointer is loaded to Channel 0. The address

pointer automatically increments to the next address.

SCL

1

0

1

0

1

AD1

AD0

R/W

A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1

SDA

START

CONDITION

BY

ACK

BY

MSB

ACK

BY

CONVERTER

ADDRESS BYTE

POINTER BYTE

CONVERTER

MASTER

SCL

SDA

REG1 REG0 MSB

MOST SIGNIFICANT DATA BYTE

LSB

MSB

LSB

ACK

BY

ACK

BY

CONVERTER

LEAST SIGNIFICANT DATA BYTE

CONVERTER

CHANNEL 0 DATA

SCL

SDA

REG1 REG0 MSB

MOST SIGNIFICANT DATA BYTE

LSB

MSB

LSB

ACK

BY

ACK

BY

CONVERTER

LEAST SIGNIFICANT DATA BYTE

CONVERTER

CHANNEL 1 DATA

SCL

SDA

REG1 REG0 MSB

MOST SIGNIFICANT DATA BYTE

LSB

MSB

LSB

ACK

BY

ACK

BY

CONVERTER

STOP

CONDITION

BY

LEAST SIGNIFICANT DATA BYTE

CONVERTER

MASTER

CHANNEL N DATA FOLLOWED BY STOP

Figure 36. 2-Byte Mode I²C Write Operation

Rev. E | Page 30 of 44

Data Sheet

AD5390/AD5391/AD5392

Soft Power-Down

AD539x ON-CHIP SPECIAL FUNCTION REGISTERS

REG1 = REG0 = 0, A3 to A0 = 1000

DB13 to DB0 = Don’t Care

The AD539x family of parts contains a number of special

function registers (SFRs) as shown in Table 22. SFRs are

addressed with REG1 = 0 and REG0 = 0 and are decoded

using Address Bit A3 to Bit A0.

Executing this instruction performs a global power-down,

which puts all channels into a low power mode, reducing analog

current to 1 µA maximum and digital power consumption to

20 µA maximum. In power-down mode, the output amplifier

can be configured as a high impedance output or can provide a

100 kΩ load to ground. The contents of all internal registers are

retained in power-down mode.

Table 22. SFR Register Functions (REG1 = 0, REG0 = 0)

R/

A3

A2

A1

A0

Function

W

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NOP (no operation)

Write CLR code

Soft CLR

Soft power-down

Soft power-up

Control register write

Control register read

Monitor channel

Soft reset

Soft Power-Up

REG1 = REG0 = 0, A3 to A0 =1001

DB13 to DB0 = Don’t Care

This instruction is used to power up the output amplifiers and

the internal references. The time to exit power-down mode is

8 µs. The hardware power-down and software functions are

internally combined in a digital OR function.

Soft Reset

SFR Commands

REG1 = REG0 = 0, A5 to A0 = 001111

DB13 to DB0 = Don’t Care

NOP (No Operation)

REG1 = REG0 = 0, A3 to A0 = 0000

This instruction is used to implement a software reset. All

internal registers are reset to their default values, which

correspond to m at full scale and c at zero scale. The contents

of the DAC registers are cleared, setting all analog outputs to

0 V. The soft reset activation time is 135 µs maximum.

Performs no operation, but is useful in readback mode to clock

out data on SDO for diagnostic purposes.

during a NOP operation.

outputs a low

BUSY

Write CLR Code

REG1 = REG0 = 0, A3 to A0 = 0001

DB13 to DB0 = Contain the CLR data

Monitor Channel

REG1 = REG0 = 0, A3 to A0 = 01010

DB13 to DB8 = Contain data to address the channel to be

monitored

Bringing the

line low or exercising the soft clear function

CLR

loads the contents of the DAC registers with the data contained

in the user-configurable CLR register and sets VOUT 0 to

VOUT 15, accordingly. This can be very useful not only for

setting up a specific output voltage in a clear condition but for

calibration purposes. For calibration, the user can load full scale

or zero scale to the clear code register and then issue a hardware

or software clear to load this code to all DACs, removing the

need for individual writes to all DACs. Default on power-up

is all zeros.

A monitor function is provided on all devices. This feature,

consisting of a multiplexer addressed via the interface, allows

any channel output to be routed to the MON_OUT pin for

monitoring using an external ADC. In addition to monitoring

all output channels, two external inputs are also provided,

allowing the user to monitor signals external to the AD539x.

The channel monitor function must be enabled in the control

register before any channels are routed to the MON_OUT pin.

On the AD5390 and AD5392 14-bit parts, DB13 to DB8 contain

the channel address for the monitored channel. On the AD5391

12-bit part, DB11 to DB6 contain the channel address for the

channel to be monitored. Selecting Address 63 three-states the

MON_OUT pin.

Soft CLR

REG1 = REG0 = 0, A3 to A0 = 0010

DB13 to DB0 = Don’t Care

Executing this instruction performs the CLR, which is

functionally the same as that provided by the external CLR pin.

The DAC outputs are loaded with the data in the CLR code

register. The time taken to execute fully the SOFT CLR is

20 µs on the AD5390/AD5391 and 15 µs on the AD5392. It

The channel monitor decoding for the AD5390/AD5392 is

shown in Table 23 and the monitor decoding for the AD5391 is

shown in Table 24.

is indicated by the

low time.

BUSY

Rev. E | Page 31 of 44

AD5390/AD5391/AD5392

Data Sheet

Table 23. AD5390/AD5392 Channel Monitor Decoding

MON_OUT MON_OUT

REG1 REG0 A3

A2

A1

A0

DB13 DB12 DB11 DB10 DB9

DB8

DB7 to DB0

(AD5390)

(AD5392)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

VOUT 0

VOUT 1

VOUT 2

VOUT 3

VOUT 4

VOUT 5

VOUT 6

VOUT 7

VOUT 8

VOUT 9

VOUT 10

VOUT 11

VOUT 12

VOUT 13

VOUT 14

VOUT 15

MON_IN 1

MON_IN 2

VOUT 0

VOUT 1

VOUT 2

VOUT 3

VOUT 4

VOUT 5

VOUT 6

VOUT 7

MON_IN 1

MON_IN 2

Three-state Three-state

Table 24. AD5391 Channel Monitor Decoding

REG1 REG0 A3 DB11 DB10 DB9

A2

0

A1

1

A0

0

DB8

0

1

0

1

.

DB7

0

1

0

1

0

1

0

1

0

1

.

DB6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

.

DB5 to DB0

MON_OUT (AD5391)

VOUT 0

VOUT 1

VOUT 2

VOUT 3

VOUT 4

VOUT 5

VOUT 6

VOUT 7

0

1

0

1

0

1

0

1

0

.

X

VOUT 8

VOUT 9

VOUT 10

VOUT 11

VOUT 12

VOUT 13

VOUT 14

VOUT 15

MON_IN 1

MON_IN 2

Undefined

Three-state

1

0

1

Rev. E | Page 32 of 44

Data Sheet

AD5390/AD5391/AD5392

CONTROL REGISTER WRITE

Table 25 shows the control register contents for the AD5390 and the AD5392. Table 26 provides bit descriptions. Note that REG1 = REG0 = 0,

A3 to A0 = 1100, and DB13 to DB0 contain the control register data.

Table 25. AD5390/AD5392 Control Register Contents

MSB

LSB

CR13

CR12

CR11

CR10

CR9

CR8

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

Table 26. AD5390 and AD5392 Bit Descriptions

Bit

Description

CR13

Power-Down Status. This bit is used to configure the output amplifier state in power–down mode.

CR13 = 1: Amplifier output is high impedance (default on power-up).

CR13 = 0: Amplifier output is 100 kΩ to ground.

CR12

CR11

REF Select. This bit selects the operating internal reference for the AD539x. CR12 is programmed as follows:

CR12 = 1: Internal reference is 2.5 V (AD5390-2/AD5392-5 default). Recommended operating reference for AD539x-5.

CR12 = 0: Internal reference is 1.25 V (AD5390-3/AD5392-3 default). Recommended operating reference for AD5390-3 and

AD5392-3.

Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate and is

configured as follows:

CR11 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing

the power dissipation.

CR11 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the

overall power consumption.

CR10

CR9

Internal/External Reference. This bit determines if the DAC uses its internal reference or an external reference.

CR10 = 1: Internal reference enabled. Reference output depends on data loaded to CR12.

CR10 = 0: External reference selected (default on power-up).

Channel Monitor Enable (see Table 23).

CR9 = 1: Monitor enabled (default on power-up). This enables the channel monitor function. Following a write to the

monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin.

CR9 = 0: Monitor disabled. When monitor is disabled, the MON_OUT pin is three-stated.

CR8

Thermal Monitor Function. When enabled, this function is used to monitor the internal die temperature of the

AD5390/AD5392. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This

function can be used to protect the device when the power dissipation of the device may be exceeded, if a number of

output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers if the die

temperature has dropped below 130°C.

CR8 = 1: Thermal monitor enabled.

CR8 = 0: Thermal monitor disabled (default on power-up).

CR7 to CR4

CR3 to CR2

Don’t Care.

Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register

for each DAC. Control Register Bits CR3 and CR2 are used to enable individual groups of eight channels for operation in

toggle mode on the AD5390 and AD5392, as follows:

CR3

CR2

Group 1 Channel 8 to Channel 15

Group 0 Channel 0 to Channel 7

CR2 is the only active bit on the AD5392. Logic 1 written to any bit enables a group of channels and Logic 0 disables a

group. LDAC is used to toggle between the two registers.

CR1 to CR0

Don’t Care.

Rev. E | Page 33 of 44

AD5390/AD5391/AD5392

Data Sheet

Table 27 shows the control register contents of the AD5391. Table 28 provides bit descriptions. Note that REG1 = REG0 = 0,

A3 to A0 = 1100, and DB13 to DB0 contain the control register data.

Table 27. AD5391 Control Register Contents

MSB

LSB

CR11

CR10

CR9

CR8

CR7

CR6

CR5

CR4

CR3

CR2

CR1

CR0

Table 28. AD5391 Bit Descriptions

Bit

Description

CR11

Power-Down Status. This bit is used to configure the output amplifier state in power-down mode.

CR11 = 1: Amplifier output is high impedance (default on power-up).

CR11 = 0: Amplifier output is 100 kΩ to ground.

CR10

CR9

REF Select. This bit selects the operating internal reference for the AD5391. CR10 is programmed as follows:

CR10 = 1: Internal reference is 2.5 V (AD5391-5 default). Recommended operating reference for AD5391-5.

CR10 = 0: Internal reference is 1.25 V (AD5391-3 default). Recommended operating reference for AD5391-3.

Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate. This bit is

configured as follows:

CR9 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing

the power dissipation.

CR9 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall

power consumption.

CR8

CR7

Internal/External Reference. This bits determines if the DAC uses its internal reference or an external reference.

CR8 = 1: Internal reference enabled. Reference output depends on data loaded to CR10.

CR8 = 0: External reference selected (default on power-up).

Channel Monitor Enable (see Table 24).

CR7 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in

the SFR register, the selected channel output is routed to the MON_OUT pin.

CR7 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated.

CR6

Thermal Monitor Function. When enabled, this function is used to monitor the internal die temperature of the AD5391,

when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function

can be used to protect the device in cases where the power dissipation of the device may be exceeded, if a number of

output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers if the die temperature

has dropped below 130°C.

CR6 = 1: Thermal monitor enabled.

CR6 = 0: Thermal monitor disabled (default on power-up).

CR5 to CR2

CR1 to CR0

Don’t Care.

Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register for

each DAC. Control Register Bit CR1 and Bit CR0 are used to enable individual groups of eight channels for operation in

toggle mode on the AD5391, as follows:

CR1

CR0

Group 1 Channel 8 to Channel 15

Group 0 Channel 0 to Channel 7

Logic 1 written to any bit enables a group of channels and Logic 0 disables a group. LDAC is used to toggle between the two

registers.

Rev. E | Page 34 of 44

Data Sheet

AD5390/AD5391/AD5392

HARDWARE FUNCTIONS

RESET FUNCTION

POWER-ON RESET

Bringing the

line low resets the contents of all internal

The AD539x products contain a power-on reset generator

and state machine. The power-on reset resets all registers to a

predefined state, and the analog outputs are configured as high

RESET

registers to their power-on reset state.

is a negative edge-

RESET

sensitive input. The default corresponds to m at full scale and

c at zero scale. The contents of all DAC registers are cleared by

setting the outputs to 0 V. This sequence takes 270 µs maximum.

impedance outputs. The

pin goes low during the power-

BUSY

on reset sequence, preventing data writes to the device.

The falling edge of

initiates the reset process.

goes

RESET

low for the duration, returning high when

BUSY

is complete.

POWER-DOWN

RESET

is low, all interfaces are disabled and all

The AD539x products contain a global power-down feature that

puts all channels into a low power mode, reducing the analog

power consumption to 1 µA maximum and the digital power

consumption to 20 µA maximum. In power-down mode, the

output amplifier can be configured as a high impedance output

or to provide a 100 kΩ load to ground. The contents of all

internal registers are retained in power-down mode. When

exiting power-down, the settling time of the amplifier elapses

before the outputs settle to their correct value.

While

BUSY

pulses are ignored. When

LDAC

returns high, the part resumes

BUSY

normal operation, and the status of the

until the next falling edge is detected.

pin is ignored

RESET

ASYNCHRONOUS CLEAR FUNCTION

is negative-edge-triggered and

goes low for the

CLR

duration of the

BUSY

execution. Bringing the

line low

CLR

clears the contents of the DAC registers to the data contained in

the user-configurable register and sets the analog outputs

MICROPROCESSOR INTERFACING

AD539x to MC68HC11

CLR

accordingly. This function can be used in system calibration

to load zero scale and full scale to all channels together. The

execution time for a

CLR

15 µs on the AD5392.

The serial peripheral interface (SPI) on the MC68HC11 is

configured for master mode (MSTR = 1), clock polarity bit

(CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is

configured by writing to the SPI control register (SPCR)—see

the 68HC11 User Manual. SCK of the MC68HC11 drives the

SCLK of the AD539x, the MOSI output drives the serial data

line (DIN) of the AD539x, and the MISO input is driven from

is 20 µs on the AD5390/AD5391 and

AND

FUNCTIONS

LDAC

BUSY

is a digital CMOS output indicating the status of the

BUSY

AD539x devices.

goes low during internal calculations

BUSY

is taken low while

D

_OUT. The

signal is derived from a port line (PC7). When

SYNC

data is being transmitted to the AD539x, the

of x2 data. If

is low, this event

BUSY

input permanently low

LDAC

is stored. The user can hold the

line is taken

SYNC

LDAC

and, in this case, the DAC outputs update immediately

after goes high. also goes low during a power-on

low (PC7). Data appearing on the MOSI output is valid on the

falling edge of SCK. Serial data from the MC8HC11 is trans-

mitted in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle.

BUSY

reset and when a falling edge is detected on the

pin.

RESET

During this time, all interfaces are disabled and any events

on

DV

DD

LDAC

AD539x

MC68HC11

are ignored.

RESET

The AD539x products contain an extra feature whereby a DAC

register is not updated unless its x2 register has been written

MISO

SDO

DIN

to since the last time

was brought low. Normally,

LDAC

is brought low, the DAC registers are filled with

MOSI

when

LDAC

SCK

PC7

SCLK

SYNC

the contents of the x2 registers. However, these devices update

the DAC register only if the x2 data has changed, thereby

removing unnecessary digital crosstalk.

2

SPI/I C

Figure 37. AD539x-MC68HC11 Interface

Rev. E | Page 35 of 44

AD5390/AD5391/AD5392

Data Sheet

DV

DD

AD539x to PIC16C6x/7x

AD539x

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit = 0. This is done

by writing to the synchronous serial port control register

(SSPCON)—see the PIC16/17 Microcontroller User Manual.

8xC51

RESET

2

SPI/I C

DV

DD

In Figure 38, I/O port RA1 is used to pulse

and enable

SYNC

the serial port of the AD539x. This microcontroller transfers

only eight bits of data during each serial transfer operation;

therefore, three consecutive read/write operations are needed,

depending on the mode. Figure 38 shows the connection

diagram.

SDO

RxD

DIN

TxD

P1.1

SCLK

SYNC

DV

DD

Figure 39. AD539x to 8051 Interface

AD539x

PIC16C6x/7x

AD539x to ADSP2101

RESET

Figure 40 shows a serial interface between the AD539x and

the ADSP2101. The ADSP2101 should be set up to operate in

the SPORT transmit alternate framing mode. The ADSP2101

SPORT is programmed through the SPORT control register and

should be configured as follows: internal clock operation, active

low framing, and 16-bit word length. Transmission is initiated

by writing a word to the Tx register after the SPORT has been

enabled.

2

SPI/I C

SDI/RC4

SDO/RC5

SCK/RC3

RA1

SDO

DIN

SCLK

SYNC

DV

DD

AD539x

Figure 38. AD539x to PIC16C6x/7x Interface

ADSP2101

RESET

AD539x to 8051

2

SPI/I C

The AD539x requires a clock synchronized to the serial data.

The 8051 serial interface must, therefore, be operated in Mode 0.

In this mode, serial data enters and exits through RxD and a

shift clock is output on TxD. Figure 39 shows how the 8051 is

connected to the AD539x. Because the AD539x shifts data out

on the rising edge of the shift clock and latches data in on the

falling edge, the shift clock must be inverted. The AD539x

requires its data with the MSB first. Because the 8051 outputs

the LSB first, the transmit routine must take this into account.

DR

SDO

DIN

DT

SCK

SCLK

TFS

RFS

SYNC

Figure 40. AD539x to ADSP2101 Interface

Rev. E | Page 36 of 44

Data Sheet

AD5390/AD5391/AD5392

APPLICATION INFORMATION

Suitable external references for the AD539x-3 include the

ADR280 1.2 V reference. The reference should be decoupled at

the REFOUT/REFIN pin of the device with a 0.1 µF capacitor.

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful

consideration of the power supply and ground return layout

helps to ensure the rated performance. The printed circuit

board on which the AD539x is mounted should be designed so

that the analog and digital sections are separated and confined

to certain areas of the board. If the AD539x is in a system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point only. The star ground

point should be established as close as possible to the device.

AV

DV

DD

0.1µF

10µF

0.1µF

ADR431/

ADR421

AV

DV

DD

REFOUT/REFIN

VOUT 0

0.1µF

For supplies with multiple pins (AV_DD, AV_CC), it is recom-

mended to tie those pins together. The AD539x should have

ample supply bypassing of 10 µF in parallel with 0.1 µF on each

supply located as close to the package as possible—ideally right

up against the device. The 10 µF capacitors are the tantalum

bead type. The 0.1 µF capacitor should have low effective series

resistance (ESR) and effective series inductance (ESI), such as

the common ceramic types that provide a low impedance path

to ground at high frequencies, to handle transient currents due

to internal logic switching.

AD539x

REF_GND

VOUT 15

DAC_GND SIGNAL_GND AGND DGND

Figure 41. Typical Configuration with External Reference

Figure 42 shows a typical configuration when using the internal

reference. On power-up, the AD539x defaults to an external

reference; therefore, the internal reference needs to be configured

and turned on via a write to the AD539x control register. On the

AD5390/AD5392, Control Register Bit CR12 lets the user choose

the reference voltage; Bit CR10 is used to select the internal

reference. It is recommended to use the 2.5 V reference when

AV_DD= 5 V, and the 1.25 V reference when AV_DD= 3 V. On the

AD5391, Control Register Bit CR10 lets the user choose the ref-

erence voltage; Bit CR8 is used to select the internal reference.

The power supply lines of the AD539x should use as large a

trace as possible to provide low impedance paths and reduce

the effects of glitches on the power supply line. Fast switching

signals such as clocks should be shielded with digital ground

to avoid radiating noise to other parts of the board, and should

never run near the reference inputs. A ground line routed

between the DIN and SCLK lines helps reduce crosstalk

between them (not required on a multilayer board, because

there is a separate ground plane, but separating the lines helps).

AV

DV

DD

0.1µF

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough through the

board. A micro-strip technique is by far the best, but not always

possible with a double-sided board. In this technique, the

component side of the board is dedicated to ground plane,

while signal traces are placed on the soldered side.

10µF

0.1µF

AV

DV

DD

REFOUT/REFIN

VOUT 0

0.1µF

AD539x

REF_GND

TYPICAL CONFIGURATION CIRCUIT

VOUT 15

Figure 41 shows a typical configuration for the AD539x when

configured for use with an external reference. In the circuit

shown, all AGND, SIGNAL_GND, and DAC_GND pins are

tied together to a common AGND. AGND and DGND are

connected together at the AD539x device. On power-up,

the AD539x defaults to external reference operation. All

AV_DDlines are connected together and driven from the same

5 V source. It is recommended to decouple close to the device

with a 0.1 µF ceramic and a 10 µF tantalum capacitor. In this

application, the reference for the AD539x-5 is provided

externally from either an ADR421 or ADR431 2.5 V reference.

DAC_GND SIGNAL_GND AGND DGND

Figure 42. Typical Configuration with Internal Reference.

(Digital Connections Omitted for Clarity)

The AD539x contains an internal power-on reset circuit with a

10 ms brown-out time. If the power supply ramp rate exceeds

10 ms, the user should reset the AD539x as part of the initiali-

zation process to ensure the calibration data is loaded correctly

into the device.

Rev. E | Page 37 of 44

AD5390/AD5391/AD5392

Data Sheet

AD539x MONITOR FUNCTION

The AD5390 contains a channel monitor function consisting

of a multiplexer addressed via the interface, allowing any

channel output to be routed to this pin for monitoring using

an external ADC. The channel monitor function must be

enabled in the control register before any channels are routed

to the MON_OUT pin.

3. Load data to all B registers.

4. Apply

.

LDAC

The

is used to switch between the A and B registers in

LDAC

determining the analog output. The first

configures the

LDAC

output to reflect the data in the A registers. This mode offers

significant advantages if the user wants to generate a square

wave at the output on all channels, as could be required to drive

a liquid-crystal-based, variable optical attenuator.

Table 23 and Table 24 contain the decoding information

required to route any channel on the AD5390, AD5391, and

AD5392 to the MON_OUT pin. Selecting Channel Address 63

three-states the MON_OUT pin. The AD539x family also

contains two monitor input pins called MON_IN 1 and

MON_IN 2. The user can connect external signals to these

pins, which under software control can be multiplexed to

MON_OUT for monitoring purposes. Figure 43 shows a typical

monitoring circuit implemented using a 12-bit SAR ADC in a

6-lead SOT package. The external reference input is connected

to MON_IN 1 to allow it to be easily monitored. The controller

output port selects the channel to be monitored, and the input

port reads the converted data from the ADC.

Configuring the AD5390, for example, the user writes to the

control register and sets CR3 = 1 and CR2 = 1, enabling the two

groups of eight for toggle mode operation. The user must then

load data to all 16 A registers and B registers. Toggling the

sets the output values to reflect the data in the A and B registers,

LDAC

and the frequency of the

determines the frequency of the

LDAC

square wave output. The first

loads the contents of the A

LDAC

registers to the DAC registers. Toggle mode is disabled via the

control register; the first following the disabling of the

LDAC

toggle mode updates the outputs with the data contained in the

A registers.

AV

DD

DIN

SYNC

SCLK

DATA

REGISTER

A

REFOUT/REFIN

AD780/

ADR431

OUTPUT PORT

AD5390

AV

DD

MON_IN1

DAC

REGISTER

VOUT

AD7476 CS

SCLK

14-BIT DAC

INPUT PORT

VOUT 0

MON_OUT

VIN

SDATA

GND

DATA

INPUT

DATA

REGISTER

CONTROLLER

AGND

B

VOUT 15

DAC_GND SIGNAL_GND

LDAC

CONTROL INPUT

A/B

Figure 44. Toggle Mode Function

Figure 43. Typical Channel Monitoring Circuit

THERMAL MONITOR FUNCTION

TOGGLE MODE FUNCTION

The AD539x family has a temperature shutdown function to

protect the chip in case multiple outputs are shorted. The short-

circuit current of each output amplifier is typically 40 mA.

Operating the AD539x at 5 V leads to a power dissipation of

200 mW/shorted amplifier. With five channels shorted, this

leads to an extra watt of power dissipation. For the 52-lead

L QF P, t h e θ_JAis typically 44°C/W.

The toggle mode function allows an output signal to be

generated using the LDAC control signal that switches between

two DAC data registers. This function is configured using the

SFR control register, as follows: A write with REG1 = REG0 = 0,

A3 to A0 = 1100 specifies a control register write. The toggle

mode function is enabled in groups of eight channels using Bit

CR3 and Bit CR2 in the AD5390/AD5392 control register and

using Bit CR1 and Bit CR0 in the AD5391 control register. (See

the Control Register Write section.) Figure 44 shows a block

diagram of the toggle mode implementation. Each DAC

channel on the AD539x contains an A and a B data register.

Note that the B registers can be loaded only when toggle mode

is enabled.

The thermal monitor is enabled by the user using CR8 in the

AD5390/AD5392 control register and CR6 in the AD5391

control register. The output amplifiers on the AD539x are

automatically powered down if the die temperature exceeds

approximately 130°C. After a thermal shutdown has occurred,

the user can re-enable the part by executing a soft power-up if

the temperature has dropped below 130°C or by turning off the

thermal monitor function via the control register.

To configure the AD539x for toggle mode of operation, the

sequence of events is as follows:

1. Enable toggle mode for the required channels via the

control register.

2. Load data to all A registers.

Rev. E | Page 38 of 44

Data Sheet

AD5390/AD5391/AD5392

Power Amplifier Control

0.1µF

Multistage power amplifier designs require a large number of

setpoints in the operation and control of the output stage. The

AD539x are ideal for these applications because of their small

size (LFCSP) and the integration of 8 and 16 channels, offering

12- and 14-bit resolution. Figure 45 shows a typical transmitter

architecture, in which the AD539x DACs can be used in the

following control circuits: I_BIAScontrol, average power control

(APC), peak power control (PPC), transmit gain control (TGC),

and audio level control (ALC). DACs are also required for

variable voltage attenuators, phase shifter control, and dc-

setpoint control in the overall amplifier design.

2.5V

REFERENCE

2R

4R

±10V

RANGE

R

±5V

RANGE

R

VOUT 3

VOUT 0

1/4 OP747/

1/4 OP4177

1/4 OP747/

1/4 OP4177

R

4R

AD539x-5

2R

0V TO 5V

RANGE

0V TO 10V

RANGE

VOUT 1

VOUT 4

1/4 OP747/

1/4 OP4177

I SINK

R

VOUT 2

R

1/4 OP747/

1/4 OP4177

PHASE

SHIFT

I

BIAS

R1

Figure 46. Output Configurations for Process Control Applications

Optical Transceivers

POWER

AMPLIFIER

The AD539x-3 family of products are ideally suited to optical

transceiver applications. In 300-pin MSA applications, for

example, digital-to-analog converters are required to control the

laser power, APD bias, and modulator amplitude. Diagnostic

information is required as analog outputs from the module. The

AD539x-3 products offer a combination of 8/16 channels, a

resolution of 12/14 bits in a 64-lead LFCSP, and operate from a

supply voltage of 2.7 V to 5.5 V supply with internal reference.

The AD539x-3 parts also feature I²C-compatible and SPI inter-

faces, making them ideal components for use in these applications.

Figure 47 shows a typical configuration in an optical transceiver

application.

AUDIO

SOURCE

50Ω

LOAD

EXCITER

ALC

PPC

APC

TGC

Figure 45. Multistage Power Amplifier Control

Process Control Applications

The AD539x-5 family is ideal for process control applications

because it offers a combination of 8 and 16 channels and 12-bit

and 14-bit resolution. These applications generally require

output voltage ranges of 0 V to 5 V 5 V, 0 V to 10 V 10 V,

and current sink and source functions. The AD539x-5 products

operate from a single 5 V supply and, therefore, require external

signal conditioning to achieve the output ranges described here.

Figure 46 shows configurations to achieve these output ranges.

The key advantages of using AD539x-5 products in these

applications are small package size, pin compatibility with the

ability to upgrade from 12 to 14 bits, integrated on-chip 2.5 V

reference with 10 ppm/°C maximum temperature coefficient,

and excellent accuracy specifications. The AD539x-5 family

contains an offset and gain register for each channel, so users

can perform system-level calibration on a per-channel basis.

3V

CONTROLLER

SDA

SCL

DV

AV

DD

SDA

2

I

C

BUS

SCL

VLSRBIAS

VLSRPWRMON

VXLOPMON

REFOUT/REFIN

AD539x-3

PIN/APD IRXP

AND TIA

AV

REFIN

DD

IMODMON

IMPD

IBIASMON

I

BIAS

10G LDD

AND

LASER

AIN

MUX

12-BIT

ADC

IMOD

AD7994

TIAs

Figure 47. Optical Transceiver using the AD539x-3

Rev. E | Page 39 of 44

AD5390/AD5391/AD5392

OUTLINE DIMENSIONS

Data Sheet

9.10

9.00 SQ

8.90

0.60 MAX

0.60

MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

8.85

8.75 SQ

8.65

EXPOSED

PAD

0.50

BSC

7.25

7.10 SQ

6.95

0.50

0.40

0.30

33

32

16

17

0.25 MIN

BOTTOM VIEW

7.50 REF

TOP VIEW

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 48. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm x 9 mm Body, Very Thin Quad

(CP-64-3)

Dimensions shown in millimeters

12.20

12.00 SQ

11.80

0.75

0.60

0.45

1.60

MAX

52

40

39

1

PIN 1

10.20

10.00 SQ

9.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

13

27

3.5°

0.15

0.05

14

26

0°

SEATING

0.10

COPLANARITY

0.38

0.32

0.22

PLANE

VIEW A

0.65

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BCC

Figure 49. 52-Lead Low Profile Quad Flat Package [LQFP]

(ST-52)

Dimensions shown in millimeters

Rev. E | Page 40 of 44

Data Sheet

AD5390/AD5391/AD5392

ORDERING GUIDE

Temperature

Range

Output

Channels Error (LSBs)

Linearity

Package

Description

Package

Option

Model¹

Resolution AV_DD

2.7 V to 3.6 V

AD5390BCPZ-3

AD5390BCPZ-3-REEL

AD5390BCPZ-3-REEL7

AD5390BCPZ-5

AD5390BCPZ-5-REEL

AD5390BCPZ-5-REEL7

AD5390BSTZ-3

14-bit

12-bit

14-bit

16

8

4

3

4

3

1

4

3

4

3

64-Lead LFCSP_VQ

52-Lead LQFP

CP-64-3

ST-52

−40°C to +85°C

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

2.7 V to 3.6 V

4.5 V to 5.5 V

AD5390BSTZ-5

52-Lead LQFP

ST-52

AD5391BCPZ-3

AD5391BCPZ-5

AD5391BCPZ-5-REEL

AD5391BCPZ-5-REEL7

AD5391BSTZ-3

64-Lead LFCSP_VQ

52-Lead LQFP

CP-64-3

ST-52

AD5391BSTZ-5

52-Lead LQFP

ST-52

AD5392BCPZ-3

AD5392BCPZ-5

AD5392BSTZ-3

64-Lead LFCSP_VQ

52-Lead LQFP

CP-64-3

ST-52

8

AD5392BSTZ-5

8

52-Lead LQFP

ST-52

EVAL–AD5390EBZ

EVAL–AD5391EBZ

EVAL–AD5392EBZ

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. E | Page 41 of 44

AD5390/AD5391/AD5392

NOTES

Data Sheet

Rev. E | Page 42 of 44

Data Sheet

NOTES

AD5390/AD5391/AD5392

Rev. E | Page 43 of 44

AD5390/AD5391/AD5392

NOTES

Data Sheet

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D03773-0-6/12(E)

Rev. E | Page 44 of 44


型号：	AD5391BCPZ-3
厂家：	ADI
描述：	8-/16-Channel, 3 V/5 V, Serial Input, Single-Supply, 12-/14-Bit Voltage Output 8 / 16通道， 3 V / 5 V ，串行输入，单电源， 12位/ 14位电压输出转换器数模转换器
文件：	总44页 (文件大小：1493K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5391BCPZ-3 [ADI]

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AD5391BCPZ-5-REEL

AD5391BCPZ-5-REEL7

AD5391BST-3

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AD5391BST-5

AD5391BST-5-REEL

AD5391BSTZ-3

AD5391BSTZ-5

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AD5392

AD5392BCP