AD5391 [ADI]
8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs; 8 / 16通道， 3 V / 5 V ，串行输入，单电源， 12位/ 14位电压输出DAC
| 型号： | AD5391 |
| 厂家： | 
ADI |
| 描述： | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| 文件： | 总44页 (文件大小：1446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-/16-Channel, 3 V/5 V, Serial Input, Single-
Supply, 12-/14-Bit Voltage Output DACs
AD5390/AD5391/AD5392
FEATURES
INTEGRATED FUNCTIONS
AD5390: 16-channel, 14-bit voltage output DAC
AD5391: 16-channel, 12-bit voltage output DAC
AD5392: 8-channel, 14-bit voltage output DAC
Guaranteed monotonic
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
INL: 1 LSB max (AD5391)
3 LSB max (AD5390-5/AD5392-5)
4 LSB max (AD5390-3/AD5392-3)
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: −40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
APPLICATIONS
Instrumentation and industrial control
Power amplifier control
Level setting (ATE)
Package types:
Control systems
64-lead LFCSP (9 mm × 9 mm)
52-lead LQFP (10 mm × 10 mm)
User interfaces:
Microelectromechanical systems (MEMs)
Variable optical attenuators (VOAs)
Optical transceivers (MSA 300, XFP)
Serial SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
(featuring data readback)
I2C®-compatible interface
FUNCTIONAL BLOCK DIAGRAM
DV
DD
(×
2)
DGND (
×
2)
AV
DD
(
×2)
AGND (
×
2)
DAC_GND (
×2)
REF_GND
REFOUT/REFIN SIGNAL_GND (
×2)
1.25V/2.5V
REFERENCE
AD5390
2
SPI/I C
INPUT
REG
0
DAC
REG
0
14
14
14
14
14
14
DAC 0
DCEN/AD1
VOUT 0
14
14
m REG0
c REG0
DIN/SDA
SCLK/SCL
SYNC/AD0
SDO
R
R
STATE
R
R
INTERFACE MACHINE
CONTROL
LOGIC
AND
CONTROL
LOGIC
INPUT
REG
1
DAC
REG
1
14
14
DAC 1
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
14
14
m REG1
c REG1
BUSY
PD
INPUT
REG
6
DAC
REG
6
14
14
14
14
14
14
14
14
DAC 6
CLR
POWER-ON
RESET
14
14
RESET
m REG6
c REG6
R
R
R
R
V
0
V 15
IN
IN
INPUT
DAC
REG
7
REG
7
DAC 7
VOUT 7
VOUT 8
14
14
MON_IN1
MON_IN2
m REG7
c REG7
MUX
×
2
VOUT 15
LDAC
MON_OUT
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5390/AD5391/AD5392
TABLE OF CONTENTS
General Description......................................................................... 3
AD5390-5/AD5391-5/AD5392-5 Specifications.......................... 4
AD5390-5/AD5391-5/AD5392-5 AC Characteristics................. 6
AD5390-3/AD5391-3/AD5392-3 Specifications.......................... 7
AD5390-3/AD5391-3/AD5392-3 AC Characteristics................. 9
I2C Write Operation ....................................................................... 28
4-Byte Mode................................................................................ 28
3-Byte Mode................................................................................ 29
2-Byte Mode................................................................................ 30
AD539x On-Chip Special Function Registers........................ 31
Control Register Write............................................................... 33
Hardware Functions....................................................................... 35
Reset Function............................................................................ 35
Asynchronous Clear Function.................................................. 35
Timing Characteristics: Serial SPI-, QSPI-, Microwire-, and
DSP-Compatible Interface............................................................. 10
Timing Characteristics: I2C Serial Interface................................ 13
Absolute Maximum Ratings.......................................................... 14
ESD Caution................................................................................ 14
Pin Configuraton and Function Descriptions............................ 15
Terminology .................................................................................... 18
Typical Performance Characteristics ........................................... 19
Functional Description .................................................................. 23
DAC Architecture—General..................................................... 23
Data Decoding—AD5390/AD5392......................................... 24
Data Decoding—AD5391 ......................................................... 24
Interfaces.......................................................................................... 25
DSP-, SPI-, and MICROWIRE-Compatible Serial Interface 25
I2C Serial Interface.......................................................................... 27
I2C Data Transfer........................................................................ 27
START and STOP Conditions .................................................. 27
Repeated START Condition...................................................... 27
Acknowledge Bit (ACK) ............................................................ 27
and
Functions...................................................... 35
LDAC
BUSY
Power-On Reset.......................................................................... 35
Power-Down ............................................................................... 35
Microprocessor Interfacing....................................................... 35
Application Information................................................................ 37
Power Supply Decoupling ......................................................... 37
Typical Configuration Circuit .................................................. 37
AD539x Monitor Function ....................................................... 38
Toggle Mode Function............................................................... 38
Thermal Monitor Function....................................................... 38
Outline Dimensions....................................................................... 40
Ordering Guide .......................................................................... 41
REVISION HISTORY
10/04: Data Sheet Changed from Rev. 0 to Rev. A
Changes to Figure 37...................................................................... 36
Changes to Figure 38...................................................................... 36
Changes to Ordering Guide.......................................................... 41
Changes to Features.......................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 6
Changes to Table 4............................................................................ 7
Changes to Figure 36...................................................................... 35
4/04—Revision 0: Initial Version
Rev. A | Page 2 of 44
AD5390/AD5391/AD5392
GENERAL DESCRIPTION
with SPI, QSPI, MICROWIRE, and DSP interface standards
and an I2C-compatible interface supporting a 400 kHz data
transfer rate.
The AD5390/AD5391 are complete single-supply, 16-channel,
14-bit and 12-bit DACs, respectively. The AD5392 is a complete
single-supply, 8-channel, 14-bit DAC. Devices are available both
in 64-lead LFCSP and 52-lead LQFP packages. All channels
have an on-chip output amplifier with rail-to-rail operation. All
devices include an internal 1.25/2.5 V, 10 ppm/°C reference, an
on-chip channel monitor function that multiplexes the analog
outputs to a common MON_OUT pin for external monitoring,
and an output amplifier boost mode that optimizes the output
amplifier slew rate.
An input register followed by a DAC register provides double-
buffering, allowing DAC outputs to be updated independently
or simultaneously using the
input. Each channel has a
LDAC
programmable gain and offset adjust register, letting the user
fully calibrate any DAC channel.
Power consumption is typically 0.25 mA per channel.
The AD5390/AD5391/AD5392 contain a 3-wire serial interface
with interface speeds in excess of 30 MHz that are compatible
Table 1. Additional High Channel Count, Low Voltage, Single-Supply DACs in Portfolio
Output
Channels
Linearity
Error (LSB) Package Description
Model
Resolution AVDD Range
Package Option
ST-100
ST-100
BC-100
BC-100
ST-100
ST-100
ST-100
ST-100
ST-100
AD5380BST-5
AD5380BST-3
AD5384BBC-5 14 Bits
AD5384BBC-3 14 Bits
AD5381BST-5
AD5381BST-3
AD5382BST-5
AD5382BST-3
AD5383BST-5
AD5383BST-3
14 Bits
14 Bits
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
40
40
40
40
40
40
32
32
32
32
4
4
4
4
1
1
4
4
1
1
100-Lead LQFP
100-Lead LQFP
100-Lead CSPBGA
100-Lead CSPBGA
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
12 Bits
12 Bits
14 Bits
14 Bits
12 Bits
12 Bits
ST-100
Rev. A | Page 3 of 44
AD5390/AD5391/AD5392
AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external.
All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
AD5390-5
1
AD5391-5
1
Parameter
AD5392-51
Unit
Test Conditions/Comments
ACCURACY
Resolution
14
12
1
1
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Offset Error
3
−1/+2
4
LSB max
LSB max
mV max
Guaranteed monotonic over temperature.
Measured at code 32 in the linear region.
4
4
4
mV max
Offset Error TC
Gain Error
5
5
µV/°C typ
% FSR max
% FSR max
ppm FSR/°C typ
LSB max
0.024
0.06
2
0.024
0.06
2
At 25°C TMIN to TMAX.
Gain Temperature Coefficient2
DC Crosstalk
REFERENCE INPUT/OUTPUT
Reference Input
2
0.5
0.5
2
Reference Input Voltage
2.5
2.5
V
1% for specified performance,
AVDD = 2 × REFIN + 50 mV.
DC Input Impedance
Input Current
1
1
1
1
MΩ min
µA max
Typically 100 MΩ.
Typically 30 nA.
Reference Range
1 V to
1 V to AVDD/2
V min/max
AVDD/2
Reference Output 3
Enabled via internal/external bit in control
register. REF select bit in control register
selects the reference voltage.
Output Voltage
Reference TC
2.495/2.505 2.495/2.505
V min/max
V min/max
ppm max
ppm max
kΩ typ
At ambient, optimized for 2.5 V operation.
At ambient when 1.25 V reference is selected.
Temperature range: 25°C to 85°C.
1.22/1.28
1.22/1.28
10
15
10
15
Temperature range: −40°C to +85°C.
Output Impedance
2.2
2.2
OUTPUT CHARACTERISTICS
Output Voltage Range4
Short-Circuit Current
Load Current
2
0/AVDD
40
1
0/AVDD
40
1
V min/max
mA max
mA max
Capacitive Load Stability
RL = ∞
200
1,000
0.5
200
1,000
0.5
pF max
pF max
Ω max
RL = 5 kΩ
DC Output Impedance
MONITOR OUTPUT PIN
Output Impedance
500
100
500
100
Ω typ
nA typ
Three-State Leakage Current
LOGIC INPUTS
2
DVDD = 2.7 V to 5.5 V.
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
2
2
V min
0.8
10
10
0.8
10
10
V max
µA max
pF max
Total for all pins. TA = TMIN to TMAX
.
Pin Capacitance
Rev. A | Page 4 of 44
AD5390/AD5391/AD5392
AD5390-5
1
AD5391-5
1
Parameter
AD5392-51
Unit
Test Conditions/Comments
LOGIC INPUTS (SCL, SDA Only)
VIH, Input High Voltage
VIL, Input Low Voltage
IIN, Input Leakage Current
VHYST, Input Hysteresis
CIN, Input Capacitance
Glitch Rejection
0.7 DVDD
0.3 DVDD
1
0.05 DVDD
8
50
0.7 DVDD
0.3 DVDD
1
0.05 DVDD
8
50
V min
SMBus-compatible at DVDD < 3.6 V.
SMBus-compatible at DVDD < 3.6 V.
V max
µA max
V min
pF typ
ns max
Input filtering suppresses noise spikes of
<50 ns.
LOGIC OUTPUTS (BUSY, SDO)
Output Low Voltage
2
0.4
DVDD − 1
0.4
DVDD − 1
V max
V min
DVDD = 5 V 10%, sinking 200 µA.
DVDD = 5 V 10%, SDO only, sourcing
200 µA.
Output High Voltage
Output Low Voltage
Output High Voltage
0.4
DVDD − 0.5
0.4
DVDD − 0.5
V max
V min
DVDD = 2.7 V to 3.6 V, sinking 200 µA.
DVDD = 2.7 V to 3.6 V SDO only, sourcing
200 µA.
High Impedance Leakage Current
High Impedance Output
Capacitance
1
5
1
5
µA max
pF typ
LOGIC OUTPUT (SDA)
2
VOL, Output Low Voltage
0.4
0.6
1
0.4
0.6
1
V max
V max
µA max
pF typ
ISINK = 3 mA.
ISINK = 6 mA.
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
AVDD
8
8
4.5/5.5
2.7/5.5
4.5/5.5
2.7/5.5
V min/max
V min/max
DVDD
Power Supply Sensitivity
∆Midscale/∆AVDD
AIDD
2
−85
−85
dB typ
0.375
0.375
mA/channel
max
Outputs unloaded; boost off;
0.25 mA/channel typ.
AIDD
0.475
0.475
mA/channel
max
Outputs unloaded; boost on;
0.325 mA/channel typ.
DIDD
1
1
20
35
1
1
20
35
mA max
µA max
µA max
mW max
VIH = DVDD, VIL = DGND.
Typically 200 nA.
Typically 3 µA.
AD5390/AD5391 with outputs unloaded;
AVDD = DVDD = 5 V; boost off.
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
20
20
mW max
AD5392 with outputs unloaded;
AVDD = DVDD = 5 V, boost off.
1 AD539x-5 products are calibrated with a 2.5 V reference. Temperature range for all versions: −40°C to +85°C.
2 Guaranteed by characterization, not production tested.
3 Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-5 products with a reference of 1.25 V leads to a degradation in
performance accuracy.
4 Accuracy guaranteed from VOUT = 10 mV to AVDD − 50 mV.
Rev. A | Page 5 of 44
AD5390/AD5391/AD5392
AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.
Table 3. AD5390-5/AD5391-5/AD5392-5 AC Characteristics1
Parameter
All
1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
AD5390/AD5392
8
10
6
µs typ
µs max
µs typ
¼ scale to ¾ scale change settling to 1 LSB.
¼ scale to ¾ scale change settling to 1 LSB.
AD5391
8
3
2
12
15
100
1
0.8
0.1
µs max
V/µs typ
V/µs typ
nV-s typ
mV typ
dB typ
nV-s typ
nV-s typ
nV-s typ
Slew rate2
Boost mode on.
Boost mode off.
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
See Terminology section.
See Terminology section.
Effect of input bus activity on DAC output under test.
Output Noise (0.1 Hz to 10 Hz)
15
40
µV p-p typ
µV p-p typ
External reference midscale loaded to DAC.
Internal reference midscale loaded to DAC.
Output Noise Spectral Density
@ 1 kHz
@ 10 kHz
150
100
nV/(Hz)1/2 typ
nV/(Hz)1/2 typ
1 Guaranteed by characterization, not production tested.
2 The slew rate can be adjusted via the current boost control bit in the DAC control register.
Rev. A | Page 6 of 44
AD5390/AD5391/AD5392
AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS
AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications TMIN to TMAX, unless
otherwise noted.
Table 4.
AD5390-31
AD5392-3
AD5391-3
1
Parameter
1
Unit
Test Conditions/Comments
ACCURACY
Resolution
14
12
1
1
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Offset Error
4
−1/+2
4
LSB max
LSB max
mV max
Guaranteed monotonic over temperature.
Measured at code 64 in the linear region.
At 25°C.
4
4
4
mV max
Offset Error TC
Gain Error
5
5
µV/°C typ
% FSR max
% FSR max
ppm FSR/°C typ
mV max
0.024
0.1
2
0.024
0.1
2
TMIN to TMAX
.
Gain Temperature Coefficient
DC Crosstalk
2
0.5
0.5
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output3
1.25
1
1
1.25
1
1
V
1% for specified performance.
Typically 100 MΩ.
Typically 30 nA.
MΩ min
µA max
V min/max
1 V to AVDD/2
1 V to AVDD/2
Enabled via internal/external bit in control
register. REF select bit in control register
selects the reference voltage.
Output Voltage
Reference TC
1.245/1.255
2.47/2.53
10
15
2.2
1.245/1.255
2.47/2.53
10
15
2.2
V min/max
V min/max
ppm max
ppm max
kΩ typ
At ambient. Optimized for 1.25 V operation.
At ambient when 2.5 V reference is selected.
Temperature range: 25°C to 85°C.
Temperature range: −40°C to +85°C.
Output Impedance
OUTPUT CHARACTERISTICS
Output Voltage Range4
Short-Circuit Current
Load Current
2
0/AVDD
40
1
0/AVDD
40
1
V min/max
mA max
mA max
Capacitive Load Stability
RL = ∞
RL = 5 kΩ
200
1,000
0.5
200
1,000
0.5
pF max
pF max
Ω max
DC Output Impedance
MONITOR OUTPUT PIN
Output Impedance
Three-State Leakage Current
LOGIC INPUTS
2
500
100
500
100
Ω typ
nA typ
2
DVDD = 2.7 V to 5.5 V.
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
2
2
V min
0.8
10
10
0.8
10
10
V max
µA max
pF max
Total for all pins. TA = TMIN to TMAX
.
Pin Capacitance
Logic Inputs (SCL, SDA Only)
VIH, Input High Voltage
VIL, Input Low Voltage
IIN, Input Leakage Current
VHYST, Input Hysteresis
0.7 DVDD
0.3 DVDD
1
0.7 DVDD
0.3 DVDD
1
V min
V max
µA max
V min
SMBus-compatible at DVDD < 3.6 V.
SMBus-compatible at DVDD < 3.6 V.
0.05 DVDD
0.05 DVDD
Rev. A | Page 7 of 44
AD5390/AD5391/AD5392
AD5390-31
AD5392-3
AD5391-3
1
Parameter
1
Unit
Test Conditions/Comments
Glitch Rejection
50
50
ns max
Input filtering suppresses noise spikes <50 ns.
Logic Outputs (BUSY, SDO)
Output Low Voltage
2
0.4
DVDD − 0.5
0.4
DVDD − 0.5
V max
V min
DVDD = 2.7 V to 5.5 V, sinking 200 µA.
DVDD = 2.7 V to 3.6 V, SDO only,
sourcing 200 µA.
Output High Voltage
DVDD − 0.1
DVDD − 0.1
V min
DVDD = 4.5 V to 5.5 V, SDO only,
sourcing 200 µA.
High Impedance Leakage
Current
High Impedance Output
Capacitance
1
5
1
5
µA max
pF typ
Logic Output (SDA)
2
VOL, Output Low Voltage
0.4
0.6
1
0.4
0.6
1
V max
V max
µA max
pF typ
ISINK = 3 mA.
ISINK = 6 mA.
Three-State Leakage Current
Three-State Output
Capacitance
8
8
POWER REQUIREMENTS
AVDD
DVDD
2.7/3.6
2.7/5.5
2.7/3.6
2.7/5.5
V min/max
V min/max
Power Supply Sensitivity
∆Midscale/∆AVDD
AIDD
2
−85
−85
dB typ
0.375
0.375
mA/channel
max
Outputs unloaded; boost off;
0.25 mA/channel typ.
AIDD
0.475
0.475
mA/channel
max
Outputs unloaded; boost on;
0.325 mA/channel typ.
DIDD
1
1
20
21
1
1
20
21
mA max
µA max
µA max
mW max
VIH = DVDD, VIL = DGND.
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
AD5390/AD5391 with outputs unloaded;
AVDD = DVDD = 3 V; boost off.
12
12
mW max
AD5392 with outputs unloaded;
AVDD = DVDD = 3 V; boost off.
1 AD539x-3 products are calibrated with a 1.25 V reference. Temperature range for all versions: −40°C to +85°C.
2 Guaranteed by characterization, not production tested.
3 Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-3 products with a reference of 2.5 V leads to a degradation in
performance accuracy.
4 Accuracy guaranteed from VOUT = 39 mV to AVDD − 50 mV.
Rev. A | Page 8 of 44
AD5390/AD5391/AD5392
AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS
AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; CL = 200 pF to AGND.
Table 5. AD5390-3/AD5391-3/AD5392-3 AC Characteristics1
Parameter
All
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
AD5390/AD5392
8
10
6
µs typ
µs max
µs typ
¼ scale to ¾ scale change settling to 1 LSB.
¼ scale to ¾ scale change settling to 1 LSB.
AD5391
8
3
2
µs max
Slew Rate2
V/µs typ
V/µs typ
nV-s typ
mV typ
dB typ
nV-s typ
nV-s typ
nV-s typ
µV p-p typ
µV p-p typ
Boost mode on.
Boost mode off.
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
12
15
100
1
0.8
0.1
15
40
See Terminology section.
See Terminology section.
Effect of input bus activity on DAC output under test.
External reference midscale loaded to DAC.
Internal reference midscale loaded to DAC.
OUTPUT NOISE (0.1 Hz to 10 Hz)
Output Noise Spectral Density
@ 1 kHz
@ 10 kHz
150
100
nV/(Hz)1/2 typ
nV/(Hz)1/2 typ
1 Guaranteed by design and characterization, not production tested.
2 The slew rate can be programmed via the current boost control bit in the AD539x control registers.
Rev. A | Page 9 of 44
AD5390/AD5391/AD5392
TIMING CHARACTERISTICS:
SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE
DVDD = 2 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 6. 3-Wire Serial Interface1
Parameter2, 3
Limit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
13
33
10
50
5
4.5
30
670
20
20
100
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
µs typ
µs typ
ns min
µs max
ns max
ns min
ns min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC falling edge
Minimum SYNC low time
4
t5
t6
4
t7
Minimum SYNC high time
t7A
t8
t9
Minimum SYNC high time in readback mode
Data setup time
Data hold time
24th SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
t10
t11
t12
t13
t14
t15
t16
t17
t17
t18
t19
t20
t21
t22
t23
4
4
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time, AD5390/AD5392
DAC output settling time, AD5391
CLR pulse width low
100
8
6
20
12
20
5
CLR pulse activation time
5
4
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
4
4
8
20
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, Figure 4, and Figure 5.
4 Standalone mode only.
5 Daisy-chain mode only.
Rev. A | Page 10 of 44
AD5390/AD5391/AD5392
t1
SCLK
SYNC
24
48
t22
t3
t2
t7
t21
t4
t8
t9
DB23
DB0 DB23
DB0
DIN
SDO
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N+1
t20
DB23
DB0
t23
UNDEFINED
INPUT WORD FOR DAC N
t13
LDAC
Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)
t1
SCLK
SYNC
24
24
1
2
t3
t2
t4
t5
t7
t6
t8
t9
DB23
DIN
DB0
t10
BUSY
t11
t13
t12
1
LDAC
t17
t14
t15
1
V
OUT
t13
t17
2
2
LDAC
t16
V
OUT
t18
CLR
t19
V
OUT
1
2
LDAC ACTIVE DURING BUSY
LDAC ACTIVE DURING BUSY
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
Rev. A | Page 11 of 44
AD5390/AD5391/AD5392
SCLK
24
48
t7A
SYNC
DB0
DB23'
DB23
DB0
DB23
DIN
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
SDO
DB0
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
I
200µA
OL
TO
OUTPUT
PIN
V
V
OR
OH (MIN)
OL (MAX)
C
50pF
L
I
OH
200µA
Figure 5. Load Circuit for Digital Output Timing
Rev. A | Page 12 of 44
AD5390/AD5391/AD5392
TIMING CHARACTERISTICS: I2C SERIAL INTERFACE
Guaranteed by design and characterization, not production tested. DVDD = 2.7 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.
All specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter1
Limit at TMIN, TMAX
Unit
Description
FSCL
t1
t2
t3
t4
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1 CB
400
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT data hold time
t5
t6
2
tHD, DAT data hold time
t7
t8
t9
t10
tSU, STA setup time for repeated start
tSU, STO stop condition setup time
tBUF, bus free time between a stop and a start condition
tF, fall time of SDA when transmitting
tR, rise time of SCL and SDA when receiving (CMOS-compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS-compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
t11
3
CB
1 See Figure 6.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal)
to bridge the undefined region of SCL’s falling edge.
3 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 DVDD and 0.7 DVDD
.
SDA
t9
t11
t4
t3
t10
SCL
t4
t6
t2
t5
t7
t8
t1
REPEATED
START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 6. I2C Interface Timing Diagram
Rev. A | Page 13 of 44
AD5390/AD5391/AD5392
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 8.
Parameter
AVDD to AGND
DVDD to DGND
Digital Inputs to DGND
Digital Outputs to DGND
VREF to AGND
Stresses above absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to +7 V
REFOUT to AGND
−0.3 V to +7 V
AGND to DGND
VOUTX to AGND
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
64-Lead LFCSP Package, θJA
52-lLad LQFP Package, θJA
−40°C to +85°C
−65°C to +150°C
150°C
22°C/W
38°C/W
Reflow Soldering Peak
Temperature
230°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 14 of 44
AD5390/AD5391/AD5392
PIN CONFIGURATON AND FUNCTION DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
CLR
NC
1
2
39 LDAC
38 BUSY
37 RESET
1
2
48 NC
47 BUSY
46 RESET
45 NC
44 NC
43 NC
42 NC
41 NC
40 NC
39 NC
38 NC
PIN 1
INDICATOR
NC
NC
3
NC
NC
3
PIN 1
INDICATOR
4
36
35
34
33
32
31
30
29
28
27
REF_GND
REFOUT/REFIN
SIGNAL_GND 1
DAC_GND 1
NC
NC
NC
NC
AV
4
NC
5
5
NC
AD5390/
6
NC
6
AD5390/
7
REF_GND
REFOUT/REFIN
SIGNAL_GND 1
DAC_GND 1
AD5391
7
8
AD5391
TOP VIEW
(Not to Scale)
9
8
AV
1
2
DD
DD
10
11
12
13
14
15
TOP VIEW
9
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
AGND 2
AV
DD
1
(Not to Scale)
10
11
12
13
VOUT 15
VOUT 0
VOUT 1
VOUT 2
VOUT 3
37 AV
2
DD
36 AGND 2
35 VOUT 15
34 VOUT 14
33 VOUT 13
VOUT 14
VOUT 13
VOUT 4 16
SIGNAL_GND 2
14 15 16 17 18 19 20 21 22 23 24 25 26
NC = NO CONNECT
NC = NO CONNECT
Figure 7. AD5390/AD5391 LFCSP Pin Configuration
Figure 9. AD5390/AD5391 LQFP Pin Configuration
52 51 50 49 48 47 46 45 44 43 42 41 40
CLR
1
2
39 LDAC
NC
NC
38 BUSY
37 RESET
36 NC
1
2
48 NC
47 BUSY
46 RESET
45 NC
44 NC
43 NC
42 NC
41 NC
40 NC
39 NC
38 NC
37 NC
36 NC
35 NC
34 NC
33 NC
PIN 1
INDICATOR
NC
3
NC
NC
PIN 1
INDICATOR
3
REF_GND
4
4
NC
5
35
34
33
32
31
30
29
28
REFOUT/REFIN
SIGNAL_GND 1
DAC_GND 1
NC
NC
NC
NC
NC
NC
NC
NC
5
NC
6
NC
6
AD5392
7
REF_GND
REFOUT/REFIN
SIGNAL_GND 1
DAC_GND 1
7
AD5392
TOP VIEW
TOP VIEW
8
9
(Not to Scale)
8
AV
1
DD
10
11
12
13
14
15
9
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
(Not to Scale)
AV
1
DD
10
11
12
13
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4 16
27 SIGNAL_GND 2
14 15 16 17 18 19 20 21 22 23 24 25 26
NC = NO CONNECT
NC = NO CONNECT
Figure 8. AD5392 LFCSP Pin Configuration
Figure 10. AD5392 LQFP Pin Configuration
Rev. A | Page 15 of 44
AD5390/AD5391/AD5392
Table 9. Pin Function Descriptions
Mnemonic
Function
VOUTX
Buffered Analog Outputs for Channel X. Each analog output is driven by a rail-to-rail output amplifier operating at a gain
of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.
SIGNAL_GND (1, Analog Ground Reference Points for each group of eight output channels. All SIGNAL_GND pins are tied together
2)
internally and should be connected to the AGND plane as close as possible to the AD539x.
DAC_GND (1, 2)
Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DACs.
These pins should be connected to the AGND plane.
AGND (1, 2)
AVDD (1, 2)
Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be
connected externally to the AGND plane.
Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins should be decoupled with 0.1 uF
ceramic capacitors and 10 µF tantalum capacitors. Operating range is 5 V 10%.
DGND
DVDD
Ground for All Digital Circuitry.
Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. Recommended that these pins be decoupled with
0.1 µF ceramic capacitors and 10 µF tantalum capacitors to DGND.
REF_GND
Ground Reference Point for the Internal Reference. Connect to AGND.
REFOUT/REFIN
The AD539x contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference
output. If the application necessitates the use of an external reference, it can be applied to this pin and the internal
reference disabled via the control register. The default for this pin is a reference input.
MON_OUT
Analog Output Pin. When the monitor function is enabled on the AD5390/AD5391, the MON_OUT acts as the output of
a 16-to-1 channel multiplexer, which can be programmed to multiplex any channel output to the MON_OUT pin. When
the monitor function is enabled on the AD5392, the MON_OUT acts as the output of an 8-to-1 channel multiplexer that
can be programmed to multiplex any channel output to the MON_OUT pin. The MON_OUT pin output impedance is
typically 500 Ω and is intended to drive a high input impedance such as that exhibited by SAR ADC inputs.
MON_IN (1, 2)
Monitor Input Pins. The AD539x contains two monitor input pins to which the user can connect input signals (within the
maximum ratings of the device) for monitoring purposes. Any of the signals applied to the MON_IN pins along with the
output channels can be switched to the MON_OUT pin via software. An external ADC, for example, can be used to
monitor these signals.
SYNC/AD0
DCEN/AD1
Serial Interface Pin.This is the frame synchronization input signal for the serial interface. When taken low, the internal
counter is enabled to count the required number of clocks before the addressed register is updated.
In I2C mode, AD0 acts as a hardware address pin.
Interface Control Pin. Operation is determined by the interface select bit SPI/I2C.
Serial Interface Mode: Daisy-Chain Select Input (level-sensitive, active high). When high, this pin enables daisy-chain
operation to allow a number of devices to be cascaded together.
I2C Mode: This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for
this device on the I2C bus.
SDO
Serial Data Output. Three-statable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data
is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.
BUSY
Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During
this time, the user can continue writing new data to further the x1, c, and m registers (these are stored in a FIFO), but no
further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low this event is
stored. BUSY also goes low during power-on reset and when the RESET pin is low. During this time the interface is
disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low.
LDAC
Load DAC Logic Input (active low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers
are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and
internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes
inactive. However, any events on LDAC during power-on reset or RESET are ignored.
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When
CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of
20 µs (AD5390/91) and 15 µs (AD5392) while all channels are being updated with the CLR code.
RESET
Asynchronous Digital Reset Input (falling edge sensitive). The function of this pin is equivalent to that of the power-on
reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and
x2 registers to their default power-on values. This sequence takes 270 µs max. This falling edge of RESET initiates the
RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all
interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation
and the status of the RESET pin is ignored until the next falling edge is detected.
Rev. A | Page 16 of 44
AD5390/AD5391/AD5392
Mnemonic
Function
PD
Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes
1 µA analog current and 20 µA digital current. In power-down mode, all internal analog circuitry is placed in low power
mode; the analog output is configured as high impedance outputs or provides a 100 kΩ load to ground, depending on
how the power-down mode is configured. The serial interface remains active during power-down.
SPI/I2C
Interface Select Input Pin. When this input is low, I2C mode is selected. When this input is high, SPI mode is selected.
SCLK/SCL
Interface CLOCK Input Pin. In SPI-compatible serial interface mode, this pin acts as a serial clock input. It operates at
clock speeds up to 50 MHz.
I2C mode: In I2C mode, this pin performs the SCL function, clocking data into the device. Data transfer rate in I2C mode is
compatible with both 100 kHz and 400 kHz operating modes.
DIN/SDA
Interface Data Input Pin.
SPI/I2C = 1: This pin acts as the serial data input. Data must be valid on the falling edge of SCLK.
SPI/I2C = 0, I2C mode: In I2C mode, this pin is the serial data pin (SDA) operating as an open drain input/output.
Rev. A | Page 17 of 44
AD5390/AD5391/AD5392
TERMINOLOGY
Relative Accuracy
Output Voltage Settling Time
Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSBs).
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a 1/4 to 3/4 full-scale input change
and measured from the rising edge of
.
BUSY
Digital-to-Analog Glitch Energy
This is the amount of energy injected into the analog output at
the major code transition. It is specified as the area of the glitch
in nV-s. It is measured by toggling the DAC register data
between 0x1FFF and 0x2000.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that
appears at the output of one DAC due to both the digital change
and subsequent analog output change at another DAC. The
victim channel is loaded with midscale, and DAC-to-DAC
crosstalk is specified in nV-s.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register. Ideally, with all 0s loaded to
the DAC and m = all 1s, c = 2n−1, VOUT(Zero Scale) = 0 V.
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. It is mainly caused
by offsets in the output amplifier.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter
is defined as the digital crosstalk and is specified in nV-s.
Offset Error
Offset error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV in the linear region
of the transfer function. Offset error is measured on the
AD539x-5 with code 32 loaded in the DAC register and with
code 64 loaded in the DAC register on the AD539x-3.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Gain Error
Gain error is specified in the linear region of the output range
between VOUT = 10 mV and VOUT = AVDD − 50 mV. It is the
deviation in slope of the DAC transfer characteristic from ideal
and is expressed in % FSR with the DAC output unloaded.
Output Noise Spectral Density
This is a measure of internally generated random noise. Ran-
dom noise is characterized as a spectral density (voltage per
√Hz). It is measured by loading all DACs to midscale and
measuring noise at the output. It is measured in nV/(Hz)1/2 in
a 1 Hz bandwidth at 10 kHz.
DC Crosstalk
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code (all 0s to all 1s and vice versa)
and the output change of all other DACs. It is expressed in LSBs.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
Rev. A | Page 18 of 44
AD5390/AD5391/AD5392
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.00
0.75
0.50
0.25
0
AV = DV = 5.5V
DD DD
VREF = 2.5V
= 25°C
1.5
1.0
T
A
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.25
–0.50
–0.75
–1.00
0
4096
8192
12288
16384
0
512
1024
1536
2048
2560
3072
3584
4096
INPUT CODE
INPUT CODE
Figure 11. AD5390-5/AD5392-5 Typical INL Plot
Figure 14. Typical AD5391-5 INL Plot
2.0
1.5
1.00
0.75
0.50
0.25
0
AV = DV = 3V
DD DD
VREF = 1.25V
T
= 25°C
A
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.25
–0.50
–0.75
–1.00
0
4096
8192
12288
16384
0
512
1024
1536
2048
2560
3072
3584
4096
INPUT CODE
INPUT CODE
Figure 12. AD5390-3/AD5392-5 INL Plot
Figure 15. Typical AD5391-3 INL Plot
40
14
12
10
8
AV = 5.5V
REFIN = 2.5V
DD
AV = 5V
DD
REFOUT = 2.5V
T
= 25°C
TEMP. RANGE = 25°C TO 85°C
SAMPLE SIZE = 162
35
30
25
20
15
10
5
A
6
4
2
0
0
–2
–1
0
1
2
–5.0 –4.0 –3.0 –2.0 –1.0
0
1.0 2.0 3.0 4.0 5.0
INL ERROR DISTRIBUTION (LSB)
–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5
REFERENCE DRIFT (ppm/°C)
Figure 13. AD5390/AD5392 INL Histogram Plot
Figure 16. AD539x REFOUT Temperature Coefficient
Rev. A | Page 19 of 44
AD5390/AD5391/AD5392
6
5
FULL SCALE
WR
BUSY
AV = DV = 5V
DD
DD
VREF = 2.5V
3/4 SCALE
T
= 25°C
4
A
MIDSCALE
3
AV = DV = 5V
DD DD
VREF = 2.5V
2
1/4 SCALE
T
= 25°C
A
EXITS SOFT PD
TO MIDSCALE
VOUT
1
ZERO SCALE
0
–1
–40 –20 –10
–5
–2
0
2
5
10
20
40
CURRENT (mA)
Figure 20. AD539x-5 Source and Sink Capability
Figure 17. AD539x Exiting Soft Power-Down
0.20
0.15
0.10
0.05
0
AV = 5V
DD
VREF = 2.5V
PD
T
= 25°C
A
ERROR AT ZERO SINKING CURRENT
–0.05
–0.10
–0.15
–0.20
(V –VOUT) AT FULL-SCALE SOURCING CURRENT
DD
AV = DV = 5V
DD
DD
VREF = 2.5V
VOUT
T
= 25°C
A
EXITS HARDWARE PD
TO MIDSCALE
0
0.25
0.50
0.75
1.00
/I
1.25
1.50
1.75
2.00
I
(mA)
SOURCE SINK
Figure 18. AD539x Exiting Hardware Power-Down
Figure 21. Headroom at Rails vs. Source/Sink Current
2.539
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
AV = DV = 5V
DD DD
VREF = 2.5V
AV = DV = 5V
VREF = 2.5V
DD
DD
T
= 25°C
A
14ns/SAMPLE NUMBER
1 LSB CHANGE AROUND MIDSCALE
GLITCH IMPULSE = 10nV-s
T
= 25°C
A
POWER SUPPLY RAMP RATE = 10ms
VOUT
AV
DD
0
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 19. AD539x Power-Up Transient
Figure 22. AD539x-5 Glitch Impulse Energy
Rev. A | Page 20 of 44
AD5390/AD5391/AD5392
1.254
1.253
1.252
1.251
1.250
1.249
1.248
1.247
1.246
1.245
DV = 5.5V
DD
AV = DV = 3V
DD DD
VREF = 1.25V
V
V
T
= DV
IH
IL
A
DD
= DGND
= 25
10
8
T
= 25°C
A
°C
14ns/SAMPLE NUMBER
1 LSB CHANGE AROUND MIDSCALE
GLITCH IMPULSE = 5nV-s
6
4
2
0
0.4
0.5
0.6
DI (mA)
0.7
0.8
0.9
0
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
DD
Figure 23. AD539x-3 Glitch Impulse
Figure 26. AD539x DIDD Histogram
2.456
AV = DV = 5V
DD DD
VREF = 2.5V
T
= 25°C
AV = DV = 5V
VREF = 2.5V
2.455
2.454
2.453
2.452
2.451
2.450
2.449
A
DD
DD
14ns/SAMPLE NUMBER
T
= 25°C
A
VOUT
0
50 100 150 200 250 300 350 400 450 500 550
SAMPLE NUMBER
Figure 24. AD539x Slew Rate Boost Off
Figure 27. AD539x Adjacent Channel Crosstalk
600
500
400
300
200
100
0
AV = 5V
DD
T
= 25°C
A
REFOUT DECOUPLED
WITH 100nF CAPACITOR
AV = DV = 5V
DD
DD
VOUT
VREF = 2.5V
= 25°C
T
A
REFOUT = 2.5V
REFOUT = 1.25V
100
1k
10k
100k
FREQUENCY (Hz)
Figure 25. AD539x Slew Rate Boost On
Figure 28. AD539x REFOUT Noise Spectral Density
Rev. A | Page 21 of 44
AD5390/AD5391/AD5392
6
5
AV = DV = 5V
AV = DV = 3V
DD DD
VREF = 1.25V
DD
DD
T
= 25°C
A
DAC LOADED WITH MIDSCALE
EXTERNAL REFERENCE
Y AXIS = 5µV/DIV
T
= 25°C
A
X AXIS = 100ms/DIV
4
3/4 SCALE
FULL SCALE
3
MIDSCALE
2
1
0
ZERO SCALE
–5
1/4 SCALE
–1
–40 –20 –10
–2
0
2
5
10
20
40
CURRENT (mA)
Figure 29. 0.1 Hz to 10 Hz Output Noise Plot
Figure 30. AD539x-3 Source and Sink Current Capability
Rev. A | Page 22 of 44
AD5390/AD5391/AD5392
FUNCTIONAL DESCRIPTION
The digital input transfer function for each DAC can be
represented as
DAC ARCHITECTURE—GENERAL
The AD5390/AD5391 are complete single-supply, 16-channel,
voltage output DACs offering a resolution of 14 bits and 12 bits,
respectively. The AD5392 is a complete single-supply, 8-channel,
voltage output DAC offering 14-bit resolution. All devices are
available in 64-lead LFCSP and 52-lead LQFP packages and
feature serial interfaces. This family includes an internal select-
able 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive
the buffered reference inputs (alternatively, an external refer-
ence can be used to drive these inputs). All channels have an on-
chip output amplifier with rail-to-rail output capable of driving
a 5 kΩ in parallel with a 200 pF load.
x2 =
where:
(m + 2)/2n
)
× x1+
c − 2n−1
x2 is the data-word loaded to the resistor-string DAC.
x1 is the 12-bit and 14-bit data-word written to the DAC input
register.
m is the 12-bit and 14-bit gain coefficient (default is all 0x3FFE
on the AD5390/AD5392 and 0xFFE on the AD5391). The LSB
of the gain coefficient is zero.
The architecture of a single DAC channel consists of a 12-bit
and 14-bit resistor-string DAC followed by an output buffer
amplifier operating at a gain of 2. This resistor-string archi-
tecture guarantees DAC monotonicity. The 12-bit and 14-bit
binary digital code loaded to the DAC register deter-mines at
what node on the string the voltage is tapped off before being
fed to the output amplifier. Each channel on these devices con-
tains independent offset and gain control registers, allowing the
user to digitally trim offset and gain.
n = DAC resolution (n = 14 for the AD5390/AD5392 and
n = 12 for the AD5391).
c is the 12-bit and 14-bit offset coefficient (default is 0x2000 on
the AD5390/AD5392 and 0x800 on the AD5391).
The complete transfer function for these devices can be
represented as
VOUT = 2×VREF × x2/2n
AVDD
VREF
x1 INPUT
REG
where:
DAC
REG
14-BIT
DAC
INPUT
DATA
m REG
c REG
x2
x2 is the data-word loaded to the resistor-string DAC.
VOUT
R
R
V
REF is the reference voltage applied to the REFIN/REFOUT pin
on the DAC when an external reference is used, 2.5 V for
specified performance on the AD539x-5 products and 1.25 V
on the AD539x-3 products.
Figure 31. AD5390/92 Single-Channel Architecture
These registers let the user calibrate out errors in the complete
signal chain including the DAC using the internal m and c
registers, which hold the correction factors. All channels are
double-buffered, allowing synchronous updating of all channels
using the
pin. Figure 31 shows a block diagram of a
LDAC
single channel on the AD5390/AD5391/AD5392.
Rev. A | Page 23 of 44
AD5390/AD5391/AD5392
DATA DECODING—AD5391
DATA DECODING—AD5390/AD5392
The AD5391contains an internal 12-bit data bus. The input
data is decoded depending on the value loaded to the REG1
and REG0 bits of the input serial register. The input data from
the serial input register is loaded into the addressed DAC input
register, offset (c) register, or gain (m) register. The format data
and the offset (c) and gain (m) register contents are shown in
Table 14 to Table 16.
The AD5390/AD5392 contain an internal 14-bit data bus. The
input data is decoded depending on the data loaded to the
REG1 and REG0 bits of the input serial register. This is shown
in Table 10.
Data from the serial input register is loaded into the addressed
DAC input register, offset (c) register, or gain (m) register. The
format data, and the offset (c) and gain (m) register contents are
shown in Table 11 to Table 13.
Table 14. AD5391 DAC Data Format (REG1 = 1, REG0 = 1)
DB11 to DB0
DAC Output (V)
2 VREF × (4095/4096)
2 VREF × (4094/4096)
2 VREF × (2049/4096)
2 VREF × (2048/4096)
2 VREF × (2047/4096)
2 VREF × (1/4096)
0
Table 10. Register Selection
1111
1111
1000
1000
0111
0000
0000
1111
1111
0000
0000
1111
0000
0000
1111
1110
0001
0000
1111
0001
0000
REG1
REG0
Register Selected
1
1
0
0
1
0
1
0
Input data register (x1)
Offset register (c)
Gain register (m)
Special function registers (SFRs)
Table 11. AD5390/AD5392 DAC Data Format
(REG1 = 1, REG0 = 1)
DB13 to DB0
Table 15. AD5391 Offset Data Format (REG1 = 1, REG0 = 0)
DB11 to DB0
DAC Output (V)
Offset (LSB)
+2048
+2047
+1
+0
–1
11 1111
11 1111
10 0000
10 0000
01 1111
00 0000
00 0000
1111
1111
1110
0001
0000
1111
0001
0000
2 VREF × (16383/16384)
2 VREF × (16382/16384)
2 VREF × (8193/16384)
2 VREF × (8192/16384)
2 VREF × (8191/16384)
2 VREF × (1/16384)V
0
1111
1111
1000
1000
0111
0000
0000
1111
1111
0000
0000
1111
0000
0000
1111
1110
0001
0000
1111
0001
0000
1111
0000
0000
1111
0000
0000
–2047
–2048
Table 12. AD5390/AD5392 Offset Data Format
(REG1 = 1, REG0 = 0)
Table 16. AD5391 Gain Data Format (REG1 = 0, REG0 = 1)
DB11 to DB0
Gain Factor
DB13 to DB0
Offset (LSB)
+8192
+8191
+1
1111
1011
0111
0011
1111
1111
1111
1111
0000
1110
1110
1110
1110
0000
1
111111
111111
100000
1111
1111
0000
0000
1111
0000
0000
1111
1110
0001
0000
1111
0001
0000
0.75
0.5
0.25
0
100000
+0
0000
011111
–1
000000
000000
–8191
–8192
Table 13. AD5390/AD5392 Gain Data Format
(REG1 = 0, REG0 = 1)
DB13 to DB0
Gain Factor
11 1111
10 1111
01 1111
00 1111
1111
1111
1111
1111
0000
1110
1110
1110
1110
0000
1
0.75
0.5
0.25
0
00 0000
Rev. A | Page 24 of 44
AD5390/AD5391/AD5392
INTERFACES
Logic 1 pin to configure this mode of operation. The serial
interface control pins are described in Table 17.
The AD5390/AD5391/AD5392 contain a serial interface that
can be programmed to be either DSP-, SPI-, and MICROWIRE-
compatible, or I2C-compatible. The SPI/
the interface mode.
pin is used to select
Table 17. Serial Interface Control Pins
2
I C
Pin
Description
SYNC, DIN, SCLK Standard 3-wire interface pins.
To minimize both the power consumption of the device and
the on-chip digital noise, the interface powers up fully only
when the device is being written to—that is, on the falling
DCEN
SDO
Selects standalone mode or daisy-chain
mode.
Data out pin for daisy-chain mode.
edge of
.
SYNC
Figure 2 to Figure 4 show timing diagrams for a serial write to
the AD5390/AD5391/AD5392 in both standalone and daisy-
chain mode. The 24-bit data-word format for the serial interface
is shown in Table 18 to Table 20. Descriptions of the bits follow
in Table 21.
DSP-, SPI-, AND MICROWIRE-COMPATIBLE SERIAL
INTERFACE
The serial interface can be operated with a minimum of three
wires in standalone mode or four wires in daisy-chain mode.
Daisy-chaining allows many devices to be cascaded together to
2
increase system channel count. The SPI/
pin is tied to a
I C
Table 18. AD5390 16-Channel, 14-Bit DAC Serial Input Register Configuration
MSB
LSB
A
/B
W
R/
0
0
A3
A2
A1
A0
REG1
REG0
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Table 19. AD5391 16-Channel, 12-Bit DAC Serial Input Register Configuration
MSB
LSB
A
/B
W
R/
0
0
A3
A2
A1
A0
REG1
REG0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
Table 20. AD5392 8-Channel, 14-Bit DAC Serial Input Register Configuration
MSB
LSB
DB0
A
/B
W
R/
0
0
0
A2
A1
A0
REG1
REG0
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
Table 21. Serial Input Register Configuration Bit Descriptions
Bit
Description
A/B
When toggle mode is enabled, this bit selects whether the data write is to the A or B register. With toggle mode
disabled, this bit should be set to zero to select the A data register.
R/W
The read or write control bit.
A3 to A0
REG1 and REG0
DB13 to DB0
X
Used to address the input channels.
Select the register to which data is written, as outlined in Table 10.
Contain the input data-word.
Don’t care condition.
Rev. A | Page 25 of 44
AD5390/AD5391/AD5392
If
is taken high before 24 clocks are clocked into the part,
Standalone Mode
SYNC
it is considered a bad frame and the data is discarded.
By connecting the daisy-chain enable (DCEN) pin low,
standalone mode is enabled. The serial interface works with
both a continuous and a noncontinuous serial clock. The first
The serial clock can be either a continuous or a gated clock. A
continuous SCLK source can be used only if the
can be
SYNC
falling edge of
starts the write cycle and resets a counter
SYNC
held low for the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
that counts the number of serial clocks to ensure that the
correct number of bits is shifted into the serial shift register.
must be used and
taken high after the final clock to latch
SYNC
Any further edges on
except for a falling edge are
SYNC
the data.
ignored until 24 bits are clocked in. Once 24 bits have been
shifted in, the SCLK is ignored. For another serial transfer to
take place, the counter must be reset by the falling edge of
Readback Mode
Readback mode is invoked by setting the R/ bit = 1 in the
W
.
SYNC
serial input register write sequence. With R/ = 1, Bits A3 to A0
W
in association with Bits REG1 and REG0 select the register to be
read. The remaining data bits in the write sequence are don’t
care bits. During the next SPI write, the data appearing on the
SDO output contains the data from the previously addressed
register. For a read of a single register, the NOP command can
be used in clocking out the data from the selected register on
SDO.
Daisy-Chain Mode
For systems that contain several devices, the SDO pin can be
used to daisy-chain the devices together. This daisy-chain mode
can be useful in system diagnostics and for reducing the
number of serial interface lines.
By connecting the DCEN pin high, daisy-chain mode is
enabled. The first falling edge of
starts the write cycle.
SYNC
The SCLK is continuously applied to the input shift register
when is low. If more than 24 clock pulses are applied,
The readback diagram in Figure 32 shows the readback
sequence. For example, to read back the m register of Channel 0
on the AD539x, the following sequence should be implemented.
First, write 0x404XXX to the AD539x input register. This
configures the AD539x for read mode with the m register of
Channel 0 selected. Note that all Data Bits DB13 to DB0 are
don’t care bits. Follow this with a second write, a NOP
condition, and 0x000000. During this write, the data from the m
register is clocked out on the DOUT line—that is, data clocked
out contains the data from the m register in Bits DB13 to DB0,
and the top 10 bits contain the address information as
SYNC
the data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting the SDO of the first
device to the DIN input on the next device in the chain, a
multidevice interface is constructed. For each device in the
system, 24 clock pulses are required. Therefore, the total
number of clock cycles must equal 24N where N is the total
number of AD539x devices in the chain.
previously written. In readback mode, the
signal must
SYNC
When the serial transfer to all devices is complete,
is
SYNC
frame the data. Data is clocked out on the rising edge of SCLK
and is valid on the falling edge of the SCLK signal. If the SCLK
idles high between the write and read operations of a readback,
then the first bit of data is clocked out on the falling edge of
taken high. This latches the input data in each device in the
daisy chain and prevents any further data from being clocked
into the input shift register.
.
SYNC
SCLK
24
48
SYNC
DIN
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES REGISTER TO BE READ
NOP CONDITION
SDO
DB23
DB0
DB23
DB0
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
Figure 32. AD539x Readback Operation
Rev. A | Page 26 of 44
AD5390/AD5391/AD5392
I2C SERIAL INTERFACE
The AD5390/AD5391/AD5392 products feature an I2C-
compatible 2-wire interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facilitate
communication between the DACs and the master at rates up
to 400 kHz. Figure 4 shows the 2-wire interface timing diagram.
REPEATED START CONDITION
A repeated START (Sr) condition may indicate a change of data
direction on the bus. Sr may be used when the bus master is
writing to several I2C devices and does not want to relinquish
control of the bus.
When selecting the I2C operating mode by configuring the
ACKNOWLEDGE BIT (ACK)
pin to Logic 0, the device is connected to the I2C bus
2
SPI/
I C
The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data-word. An ACK is always generated by the receiving
device. The AD539x devices generate an ACK when receiving
an address or data by pulling SDA low during the ninth clock
period.
as a slave device (that is, no clock is generated by the device).
The AD5390/AD5391/AD5392 have a 7-bit slave address
1010 1(AD1)(AD0). The five MSBs are hard-coded and the
two LSBs are determined by the state of the AD1 and AD0
pins. The hardware configuration facility for the AD1 and AD0
pins allows four of these devices to be configured on the bus.
Monitoring the ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should reattempt
communication.
I2C DATA TRANSFER
One data bit is transferred during each SCL clock cycle. The
data on SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are control
signals that configure START and STOP Conditions. Both SDA
and SCL are pulled high by the external pull-up resistors when
the I2C bus is not busy.
AD539x SLAVE ADDRESSES
A bus master initiates communication with a slave device by
issuing a START condition followed by the 7-bit slave address.
When idle, the AD539x device waits for a START condition
followed by its slave address. The LSB of the address word is the
START AND STOP CONDITIONS
A master device initiates communication by issuing a START
condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA, while SCL is high. A START condition from
the master signals the beginning of a transmission to the
AD539x. The STOP condition frees the bus. If a repeated
START condition (Sr) is generated instead of a STOP condition,
the bus remains active.
read/write (R/ ) bit. The AD539x devices are receive devices
W
only, and R/ = 0 when communicating with them. After
W
receiving the proper address 1010 1(AD1) (AD0), the AD539x
issues an ACK by pulling SDA low for one clock cycle. The
AD539x has four user-programmable addresses determined by
the AD1 and AD0 bits.
Rev. A | Page 27 of 44
AD5390/AD5391/AD5392
I2C WRITE OPERATION
in the DAC to be addressed and is also acknowledged by the
DAC. Address Bits A3 to A0 address all channels on the
AD5390/AD5391. Address Bits A2 to A0 address all channels on
the AD5392. Address Bit A3 is a zero on the AD5392. Two bytes
of data then are written to the DAC, as shown in Figure 33. A
STOP condition follows. This lets the user update a single
channel within the AD539x at any time and requires four bytes
of data to be transferred from the master.
There are three specific modes in which data can be written to
the AD539x family of DACs.
4-BYTE MODE
When writing to the AD539x DACs, begin with an address byte
(R/W = 0), after which the DAC acknowledges that it is pre-
pared to receive data by pulling SDA low. The address byte is
followed by the pointer byte; this addresses the specific channel
SCL
AD1
AD0
R/W
0
0
0
0
A3
A2
A1
A0
1
0
1
0
1
SDA
START
CONDITION
BY
ACK
BY
CONVERTER
MSB
ACK
BY
CONVERTER
ADDRESS BYTE
POINTER BYTE
MASTER
SCL
SDA
REG1 REG0 MSB
MOST SIGNIFICANT DATA BYTE
LSB
MSB
LSB
ACK
BY
ACK
BY
CONVERTER
STOP
CONDITION
BY
LEAST SIGNIFICANT DATA BYTE
CONVERTER
MASTER
Figure 33. The 4-Byte Mode I2C Write Operation
Rev. A | Page 28 of 44
AD5390/AD5391/AD5392
AD5390/AD5391. Address Bits A2 to A0 address all channels on
the AD5392. Address Bit A3 is a zero on the AD5392. This is
then followed by the two data bytes. REG1 and REG0 determine
the register to be updated.
3-BYTE MODE
The 3-byte mode lets the user update more than one channel in
a write sequence without having to write the device address byte
each time. The device address byte is required only once and
subsequent channel updates require the pointer byte and the
data bytes. In 3-byte mode, the user begins with an address byte
If a STOP condition is not sent following the data bytes,
another channel can be updated by sending a new pointer
byte followed by the data bytes. This mode requires only three
bytes to be sent to update any channel once the device has
been addressed initially and reduces the software overhead in
updating the AD539x channels. A STOP condition at any time
exits this mode. Figure 34 shows a typical configuration.
(R/ = 0) after which the DAC acknowledges that it is
W
prepared to receive data by pulling SDA low. The address byte is
followed by the pointer byte; this addresses the specific channel
in the DAC to be addressed and is also acknowledged by the
DAC. Address Bits A3 to A0 address all channels on the
SCL
1
0
1
0
1
AD1
AD0
R/W
0
0
0
0
A3
A2
A1
A0
SDA
START
CONDITION
BY
ACK
BY
CONVERTER
MSB
ACK
BY
CONVERTER
ADDRESS BYTE
POINTER BYTE FOR CHANNEL N
MASTER
SCL
SDA
REG1 REG0 MSB
LSB
MSB
LSB
ACK
BY
ACK
BY
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
CONVERTER
CONVERTER
DATA FOR CHANNEL N
SCL
SDA
0
0
0
0
A3
A2
A1
A0
MSB
ACK
BY
CONVERTER
POINTER BYTE FOR CHANNEL NEXT CHANNEL
SCL
SDA
REG1 REG0 MSB
MOST SIGNIFICANT DATA BYTE
LSB
MSB
LSB
ACK
BY
ACK
BY
CONVERTER
STOP
CONDITION
BY
LEAST SIGNIFICANT DATA BYTE
CONVERTER
MASTER
DATA FOR CHANNEL NEXT CHANNEL
Figure 34. The 3-Byte Mode I2C Write Operation
Rev. A | Page 29 of 44
AD5390/AD5391/AD5392
2-BYTE MODE
The REG0 and REG1 bits in the data byte determine the register
to be updated. In this mode, following the initialization, only the
two data bytes are required to update a channel. The channel
address automatically increments from Address 0 to the final
address and then returns to the normal 3-byte mode of opera-
tion. This mode allows transmission of data to all channels in
one block and reduces the software overhead in configuring all
channels. A STOP condition at any time exits this mode. Toggle
mode of operation is not supported in 2-byte mode. Figure 35
shows a typical configuration.
The 2-byte mode lets the user update channels sequentially
following initialization of this mode. The device address byte is
required only once and the address pointer is configured for
autoincrement or burst mode.
The user must begin with an address byte (R/ = 0), after
W
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte is followed by a specific
pointer byte (0xFF), which initiates the burst mode of
operation. The address pointer initializes to Channel 0 and the
data following the pointer is loaded to Channel 0. The address
pointer automatically increments to the next address.
.
SCL
1
0
1
0
1
AD1
AD0
R/W
A7=1 A6=1 A5=1
MSB
A4=1 A3=1 A2=1
POINTER BYTE
A1=1 A0=1
SDA
START
CONDITION
BY
ACK
BY
ACK
BY
ADDRESS BYTE
CONVERTER
CONVERTER
MASTER
SCL
SDA
REG1 REG0 MSB
MOST SIGNIFICANT DATA BYTE
LSB
MSB
LSB
ACK
BY
ACK
BY
LEAST SIGNIFICANT DATA BYTE
CONVERTER
CONVERTER
CHANNEL 0 DATA
SCL
SDA
REG1 REG0 MSB
MOST SIGNIFICANT DATA BYTE
LSB
MSB
LSB
ACK
BY
ACK
BY
LEAST SIGNIFICANT DATA BYTE
CONVERTER
CONVERTER
CHANNEL 1 DATA
SCL
SDA
REG1 REG0 MSB
MOST SIGNIFICANT DATA BYTE
LSB
MSB
LSB
ACK
BY
ACK
BY
STOP
CONDITION
BY
LEAST SIGNIFICANT DATA BYTE
CONVERTER
CONVERTER
MASTER
CHANNEL N DATA FOLLOWED BY STOP
Figure 35. 2-Byte Mode I2C Write Operation
Rev. A | Page 30 of 44
AD5390/AD5391/AD5392
Soft Power-Down
REG1 = REG0 = 0, A3–A0 =1000
DB13–DB0 = Don’t Care.
AD539x ON-CHIP SPECIAL FUNCTION REGISTERS
The AD539x family of parts contains a number of special
function registers (SFRs) as shown in Table 22. SFRs are
addressed with REG1 = 0 and REG0 = 0 and are decoded using
Address Bits A3–A0.
Executing this instruction performs a global power-down,
which puts all channels into a low power mode, reducing analog
current to 1 µA maximum and digital power consumption to
20 µA maximum. In power-down mode, the output amplifier
can be configured as a high impedance output or can provide a
100 kΩ load to ground. The contents of all internal registers are
retained in power-down mode.
Table 22. SFR Register Functions (REG1 = 0, REG0 = 0)
R/ W
A3
A2
A1
A0
Function
X
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
NOP (no operation)
Write CLR code
Soft CLR
Soft power-down
Soft power-up
Control register write
Control register read
Monitor channel
Soft reset
Soft Power-Up
REG1 = REG0 = 0, A3–A0 =1001
DB13–DB0 = Don’t Care.
This instruction is used to power up the output amplifiers and
the internal references. The time to exit power-down mode is
8 µs. The hardware power-down and software functions are
internally combined in a digital OR function.
SFR Commands
NOP (No Operation)
REG1 = REG0 = 0, A3–A0 = 0000
Soft Reset
REG1 = REG0 = 0, A5–A0 = 001111
DB13–DB0 = Don’t Care.
Performs no operation, but is useful in readback mode to clock
This instruction is used to implement a software reset. All
internal registers are reset to their default values, which
correspond to m at full scale and c at zero scale. The contents
of the DAC registers are cleared, setting all analog outputs to
0 V. The soft reset activation time is 135 µs maximum.
out data on SDO for diagnostic purposes.
outputs a low
BUSY
during a NOP operation.
Write CLR Code
REG1 = REG0 = 0, A3–A0 = 0001
DB13–DB0 = Contain the CLR data.
Monitor Channel
REG1 = REG0 = 0, A3–A0 = 01010
DB13–DB8 = Contain data to address the channel to be
monitored.
Bringing the
line low or exercising the soft clear function
CLR
loads the contents of the DAC registers with the data contained
in the user-configurable CLR register and sets VOUT0 to
VOUT15, accordingly. This can be very useful not only for
setting up a specific output voltage in a clear condition but for
calibration purposes. For calibration, the user can load full scale
or zero scale to the clear code register and then issue a hardware
or software clear to load this code to all DACs, removing the
need for individual writes to all DACs. Default on power-up is
all zeros.
A monitor function is provided on all devices. This feature,
consisting of a multiplexer addressed via the interface, allows
any channel output to be routed to the MON_OUT pin for
monitoring using an external ADC. In addition to monitoring
all output channels, two external inputs are also provided,
allowing the user to monitor signals external to the AD539x.
The channel monitor function must be enabled in the control
register before any channels are routed to the MON_OUT pin.
On the AD5390 and AD5392 14-bit parts, DB13 to DB8 contain
the channel address for the monitored channel. On the AD5391
12-bit part, DB11 to DB6 contain the channel address for the
channel to be monitored. Selecting Address 63 three-states the
MON_OUT pin.
Soft CLR
REG1 = REG0 = 0, A3–A0 = 0010
DB13–DB0 = Don’t Care.
Executing this instruction performs the CLR, which is
functionally the same as that provided by the external CLR pin.
The DAC outputs are loaded with the data in the CLR code
register. The time taken to execute fully the SOFT CLR is
20 µs on the AD5390/AD5391 and 15 µs on the AD5392, and is
The channel monitor decoding for the AD5390/AD5392 is
shown in Table 23 and the monitor decoding for the AD5391 is
shown in Table 24.
indicated by the
low time.
BUSY
Rev. A | Page 31 of 44
AD5390/AD5391/AD5392
Table 23. AD5390/AD5392 Channel Monitor Decoding
MON_OUT
REG1 REG0 A3 A2 A1 A0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 to DB0 (AD5390)
MON_OUT
(AD5392)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
VOUT 8
VOUT 9
VOUT 10
VOUT 11
VOUT 12
VOUT 13
VOUT 14
VOUT 15
MON_IN1
MON_IN2
Three-state
MON_IN1
MON_IN2
Three-state
Table 24. AD5391 Channel Monitor Decoding
MON_OUT
(AD5391)
REG1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
REG0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DB9
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
.
DB8
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
.
DB7
DB6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
.
DB5 to DB0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VOUT 0
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VOUT 5
VOUT 6
VOUT 7
VOUT 8
VOUT 9
VOUT 10
VOUT 11
VOUT 12
VOUT 13
VOUT 14
VOUT 15
MON_IN1
MON_IN2
Undefined
Undefined
Undefined
Three-state
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
1
Rev. A | Page 32 of 44
AD5390/AD5391/AD5392
CONTROL REGISTER WRITE
Table 25 shows the control register contents for the AD5390 and the AD5392. Table 26 provides bit descriptions. Note that
REG1 = REG0 = 0, A3–A0 = 1100, and DB13–DB0 contain the control register data.
Table 25. AD5390/AD5392 Control Register Contents
MSB
LSB
CR13
CR12
CR11
CR10
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
Table 26. AD5390 and AD5392 Bit Descriptions
Bit
Description
CR13
Power-Down Status. This bit is used to configure the output amplifier state in power–down mode.
CR13 = 1: Amplifier output is high impedance (default on power-up).
CR13 = 0: Amplifier output is 100 kΩ to ground.
CR12
CR11
REF Select. This bit selects the operating internal reference for the AD539x. CR12 is programmed as follows:
CR12 = 1: Internal reference is 2.5 V (AD5390/AD5392-5 default). Recommended operating reference for AD539x-5.
CR12 = 0: Internal reference is 1.25 V (AD5390/AD5392-3 default). Recommended operating reference for AD5390-3 and
AD5392-3.
Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate and is
configured as follows:
CR11 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing
the power dissipation.
CR11 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the
overall power consumption.
CR10
CR9
Internal/External Reference. This bit determines if the DAC uses its internal reference or an external reference.
CR10 = 1: Internal reference enabled. Reference output depends on data loaded to CR12.
CR10 = 0: External reference selected (default on power-up).
Channel Monitor Enable (see Table 23).
CR9 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in the SFR
register, the selected channel output is routed to the MON_OUT pin.
CR9 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated.
CR8
Thermal Monitor Function. This function is used to monitor the internal die temperature of the AD5390/AD5392, when
enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function
can be used to protect the device in cases where the power dissipation of the device may be exceeded, if a number of
output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers, if the die
temperature has dropped below 130°C.
CR8 = 1: Thermal monitor enabled.
CR8 = 0: Thermal monitor disabled (default on power-up).
CR7 to CR4
CR3 to CR2
Don’t Care.
Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register
for each DAC. Control Register Bits CR3 and CR2 are used to enable individual groups of eight channels for operation in
toggle mode on the AD5390 and AD5392, as follows:
CR3 Group 1 Channels 8 to 15
CR2 Group 0 Channels 0 to 7
CR2 is the only active bit on the AD5392. Logic 1 written to any bit enables a group of channels, and Logic 0 disables a
group. LDAC is used to toggle between the two registers.
CR1 and CR0
Don’t care.
Rev. A | Page 33 of 44
AD5390/AD5391/AD5392
Table 27 shows the control register contents of the AD5391. Table 28 provides bit descriptions. Note that REG1 = REG0 = 0,
A3–A0 = 1100, and DB13–DB0 contain the control register data.
Table 27. AD5391 Control Register Contents
MSB
LSB
CR11
CR10
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
Table 28. AD5391 Bit Descriptions
Bit
Description
CR11
Power-Down Status. This bit is used to configure the output amplifier state in power-down mode.
CR11 = 1: Amplifier output is high impedance (default on power-up).
CR11 = 0: Amplifier output is 100 kΩ to ground.
CR10
CR9
REF Select. This bit selects the operating internal reference for the AD5391. CR10 is programmed as follows:
CR10 = 1: Internal reference is 2.5 V (AD5391-5 default). Recommended operating reference for AD5391-5.
CR10 = 0: Internal reference is 1.25 V (AD5391-3 default). Recommended operating reference for AD5391-3.
Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate. This bit is
configured as follows:
CR9 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing
the power dissipation.
CR9 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall
power consumption.
CR8
CR7
Internal/External Reference. This bits determines if the DAC uses its internal reference or an external reference.
CR8 = 1: Internal reference enabled. Reference output depends on data loaded to CR10.
CR8 = 0: External reference selected (default on power-up).
Channel Monitor Enable (see Table 24).
CR7 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in
the SFR register, the selected channel output is routed to the MON_OUT pin.
CR7 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated.
CR6
Thermal Monitor Function. This function is used to monitor the internal die temperature of the AD5391, when enabled.
The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function can be
used to protect the device in cases where the power dissipation of the device may be exceeded, if a number of output
channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers if the die temperature
has dropped below 130°C.
CR6 = 1: Thermal monitor enabled.
CR6 = 0: Thermal monitor disabled (default on power-up).
CR5 to CR2
CR1 to CR0
Don’t care.
Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register for
each DAC. Control Register Bits CR3 and CR2 are used to enable individual groups of eight channels for operation in toggle
mode on the AD5391, as follows:
CR1 Group 1 Channels 8-15
CR0 Group 0 Channels 0 to 7
Logic 1 written to any bit enables a group of channels, and Logic 0 disables a group. LDAC is used to toggle between
the two registers.
Rev. A | Page 34 of 44
AD5390/AD5391/AD5392
HARDWARE FUNCTIONS
RESET FUNCTION
POWER-ON RESET
Bringing the
registers to their power-on reset state.
sensitive input. The default corresponds to m at full scale and
c at zero scale. The contents of all DAC registers are cleared
setting the outputs to 0 V. This sequence takes 270 µs maximum.
line low resets the contents of all internal
The AD539x products contain a power-on reset generator and
state machine. The power-on reset resets all registers to a
predefined state, and the analog outputs are configured as high
RESET
is a negative edge-
RESET
impedance outputs. The
pin goes low during the power-
BUSY
on reset sequence, preventing data writes to the device.
The falling edge of
initiates the reset process.
goes
RESET
BUSY
POWER-DOWN
low for the duration, returning high when
is complete.
RESET
is low, all interfaces are disabled and all
The AD539x products contain a global power-down feature that
puts all channels into a low power mode, reducing the analog
power consumption to 1 µA maximum and the digital power
consumption to 20 µA maximum. In power-down mode, the
output amplifier can be configured as a high impedance output
or provide a 100 kΩ load to ground. The contents of all internal
registers are retained in power-down mode. When exiting
power-down, the settling time of the amplifier elapses before
the outputs settle to their correct value.
While
BUSY
LDAC
pulses are ignored. When
normal operation, and the status of the
until the next falling edge is detected.
returns high, the part resumes
BUSY
pin is ignored
RESET
ASYNCHRONOUS CLEAR FUNCTION
is negative-edge-triggered and
goes low for the
CLR
BUSY
duration of the
execution. Bringing the
line low clears
CLR
CLR
the contents of the DAC registers to the data contained in the
user-configurable register and sets the analog outputs
MICROPROCESSOR INTERFACING
AD539x to MC68HC11
CLR
accordingly. This function can be used in system calibration to
load zero scale and full scale to all channels together. The
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), clock polarity bit
(CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the MC68HC11 drives the
SCLK of the AD539x, the MOSI output drives the serial data
line (DIN) of the AD539x, and the MISO input is driven from
execution time for a
is 20 µs on the AD5390/AD5391 and
CLR
15 µs on the AD5392.
AND
FUNCTIONS
LDAC
BUSY
is a digital CMOS output indicating the status of the
BUSY
AD539x devices.
goes low during internal calculations
BUSY
DOUT. The
signal is derived from a port line (PC7). When
SYNC
of x2 data. If
is taken low while
is low, this event
LDAC
BUSY
data is being transmitted to the AD539x, the
line is taken
SYNC
is stored. The user can hold the
input permanently low
LDAC
and, in this case, the DAC outputs update immediately after
goes high. also goes low during a power-on reset
low (PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the MC8HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle.
BUSY
BUSY
and when a falling edge is detected on the
this time, all interfaces are disabled and any events on
are ignored.
pin. During
RESET
LDAC
DV
DD
AD539x
SER/PAR
RESET
The AD539x products contain an extra feature whereby a DAC
register is not updated unless its x2 register has been written to
MC68HC11
since the last time
was brought low. Normally, when
LDAC
MISO
SDO
DIN
is brought low, the DAC registers are filled with the
LDAC
MOSI
contents of the x2 registers. However, these devices update the
DAC register only if the x2 data has changed, thereby removing
unnecessary digital crosstalk.
SCK
PC7
SCLK
SYNC
2
SPI/1 C
Figure 36. AD539x-MC68HC11 Interface
Rev. A | Page 35 of 44
AD5390/AD5391/AD5392
DV
DD
AD539x to PIC16C6x/7x
AD539x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done by
writing to the synchronous serial port control register
SER/PAR
8xC51
RESET
2
SPI/1 C
(SSPCON). See the PIC16/17 Microcontroller User Manual.
DV
DD
In Figure 27, I/O port RA1 is used to pulse
and enable
SYNC
the serial port of the AD539x. This microcontroller transfers
only eight bits of data during each serial transfer operation;
therefore, three consecutive read/write operations are needed,
depending on the mode. Figure 37 shows the connection
diagram.
SDO
RxD
DIN
TxD
P1.1
SCLK
SYNC
DV
DD
Figure 38. AD539x to 8051 Interface
AD539x
PIC16C6x/7x
SER/PAR
AD539x to ADSP2101/ADSP2103
RESET
Figure 39 shows a serial interface between the AD539x and the
ADSP2101/ADSP2103. The ADSP2101/ADSP2103 should be
set up to operate in the SPORT transmit alternate framing
mode. The ADSP2101/ADSP2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled.
2
SPI/1 C
SDI/RC4
SDO/RC5
SCK/RC3
RA1
SDO
DIN
SCLK
SYNC
Figure 37. AD539x to PIC16C6X/7X Interface
DV
DD
AD539x
ADSP2101/
ADSP2103
AD539x to 8051
RESET
The AD539x requires a clock synchronized to the serial data.
The 8051 serial interface must, therefore, be operated in mode 0.
In this mode, serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 38 shows how the 8051 is
connected to the AD539x. Because the AD539x shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD539x
requires its data with the MSB first. Because the 8051 outputs
the LSB first, the transmit routine must take this into account.
2
SPI/I C
DR
SDO
DIN
DT
SCK
SCLK
TFS
RFS
SYNC
Figure 39. AD539x to ADSP2101/ADSP2103 Interface
Rev. A | Page 36 of 44
AD5390/AD5391/AD5392
APPLICATION INFORMATION
reference. The reference should be decoupled at the
REFOUT/REFIN pin of the device with a 0.1 µF capacitor.
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
AV
DV
DD
DD
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD539x is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD539x is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
0.1µF
10µF
0.1µF
AV
DV
DD
DD
REFOUT/REFIN
VOUT 0
0.1µF
AD539x
For supplies with multiple pins (AVDD, AVCC), it is recom-
mended to tie those pins together. The AD539x should have
ample supply bypassing of 10 µF in parallel with 0.1 µF on each
supply located as close to the package as possible—ideally right
up against the device. The 10 µF capacitors are the tantalum
bead type. The 0.1 µF capacitor should have low effective series
resistance (ESR) and effective series inductance (ESI), such as
the common ceramic types that provide a low impedance path
to ground at high frequencies, to handle transient currents due
to internal logic switching.
REF_GND
VOUT 31
DAC_GND SIGNAL_GND AGND DGND
Figure 40. Typical Configuration with External Reference
Figure 41 shows a typical configuration when using the internal
reference. On power-up, the AD539x defaults to an external
reference; therefore, the internal reference needs to be config-
ured and turned on via a write to the AD539x control register.
On the AD5390/AD5392 Control Register Bit CR12 lets the
user choose the reference voltage; Bit CR10 is used to select the
internal reference. It is recommended to use the 2.5 V reference
when AVDD = 5 V, and the 1.25 V reference when AVDD = 3 V. On
the AD5391, Control Register Bit CR10 lets the user choose the
reference voltage; Bit CR8 is used to select the internal
reference.
The power supply lines of the AD539x should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the DIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board, because
there is a separate ground plane, but separating the lines helps).
AV
DV
DD
DD
0.1µF
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane, while signal traces are
placed on the soldered side.
10µF
0.1µF
ADR431/
ADR421
AV
DV
DD
DD
REFOUT/REFIN
VOUT 0
0.1µF
AD539x
REF_GND
VOUT 31
DAC_GND SIGNAL_GND AGND DGND
TYPICAL CONFIGURATION CIRCUIT
Figure 40 shows a typical configuration for the AD539x-5 when
configured for use with an external reference. In the circuit
shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied
together to a common AGND. AGND and DGND are
Figure 41. Typical Configuration with Internal Reference
connected together at the AD539x device. On power-up, the
AD539x defaults to external reference operation. All AVDD lines
are connected together and driven from the same 5 V source. It
is recommended to decouple close to the device with a 0.1 µF
ceramic and a 10 µF tantalum capacitor. In this application, the
reference for the AD539x-5 is provided externally from either
an ADR421 or ADR431 2.5 V reference. Suitable external
references for the AD539x-3 include the ADR280 1.2 V
Rev. A | Page 37 of 44
AD5390/AD5391/AD5392
To configure the AD539x for toggle mode of operation, the
sequence of events is as follows:
Digital connections have been omitted for clarity. The AD539x
contains an internal power-on reset circuit with a 10 ms brown-
out time. If the power supply ramp rate exceeds 10 ms, the user
should reset the AD539x as part of the initialization process to
ensure the calibration data is loaded correctly into the device.
1. Enable toggle mode for the required channels via the
control register.
2. Load data to A registers.
3. Load data to B registers.
AD539x MONITOR FUNCTION
4. Apply
.
LDAC
The AD5390 contains a channel monitor function consisting of
a multiplexer addressed via the interface, allowing any channel
output to be routed to this pin for monitoring using an external
ADC. The channel monitor function must be enabled in the
control register before any channels are routed to the
MON_OUT pin.
The
is used to switch between the A and B registers in
LDAC
determining the analog output. The first
configures the
LDAC
output to reflect the data in the A registers. This mode offers
significant advantages, if the user wants to generate a square
wave at the output on all channels as might be required to drive
a liquid-crystal-based, variable optical attenuator. Configuring
the AD5390, for example, the user writes to the control register
and sets CR3 = 1 and CR2 = 1, enabling the two groups of eight
for toggle mode operation. The user must then load data to all
Table 23 and Table 24 contain the decoding information
required to route any channel on the AD5390, AD5391, and
AD5392 to the MON_OUT pin. Selecting Channel Address 63
three-states the MON_OUT pin. The AD539x family also
contains two monitor input pins called MON_IN1 and
MON_IN2. The user can connect external signals to these
pins, which under software control can be multiplexed to
MON_OUT for monitoring purposes. Figure 42 shows a typical
monitoring circuit implemented using a 12-bit SAR ADC in a
6-lead SOT package. The external reference input is connected
to MON_IN1 to allow it to be easily monitored. The controller
output port selects the channel to be monitored, and the input
port reads the converted data from the ADC.
16 A registers and B registers. Toggling the
sets the out-
LDAC
put values to reflect the data in the A and B registers, and the
frequency of the determines the frequency of the square
LDAC
wave output. The first
loads the contents of the A regis-
LDAC
ters to the DAC registers. Toggle mode is disabled via the
control register; the first following the disabling of the
LDAC
toggle mode updates the outputs with the data contained in the
A registers.
THERMAL MONITOR FUNCTION
The AD539x family has a temperature shutdown function to
protect the chip in case multiple outputs are shorted. The short-
circuit current of each output amplifier is typically 40 mA.
Operating the AD539x at 5 V leads to a power dissipation of
200 mW/shorted amplifier. With five channels shorted, this
leads to an extra watt of power dissipation. For the 52-lead
LQFP, the θJA is typically 44°C/W.
AV
DD
DIN
REFOUT/REFIN
AD780/
ADR431
OUTPUT PORT
SYNC
SCLK
AD5390
MON_IN1
AV
DD
AD7476 CS
SCLK
INPUT PORT
MON_OUT
VIN
VOUT 0
SDATA
GND
CONTROLLER
AGND
VOUT 15
DAC_GND SIGNAL GND
The thermal monitor is enabled by the user using CR8 in the
AD5390/AD5392 control register and by CR6 in the AD5391
control register. The output amplifiers on the AD539x are
automatically powered down if the die temperature exceeds
approximately 130°C. After a thermal shutdown has occurred,
the user can re-enable the part by executing a soft power-up if
the temperature has dropped below 130°C or by turning off the
thermal monitor function via the control register.
Figure 42. Typical Channel Monitoring Circuit
TOGGLE MODE FUNCTION
The toggle mode function allows an output signal to be
generated using the LDAC control signal that switches between
two DAC data registers. This function is configured using the
SFR control register, as follows. A write with REG1 = REG0 = 0,
A3–A0 = 1100 specifies a control register write. The toggle
mode function is enabled in groups of eight channels using Bits
CR3 and CR2 in the AD5390/AD5392 control register and
using Bits CR1 and CR0 in the AD5391 control register. (See
the Control Register Write section.) Figure 43 shows a block
diagram of the toggle mode implementation. Each DAC
channel on the AD539x contains an A and a B data register.
Note that the B registers can be loaded only when toggle mode
is enabled.
DATA
REGISTER
A
DAC
REGISTER
VOUT
14-BIT DAC
DATA
REGISTER
B
INPUT
REGISTER
INPUT
DATA
LDAC
CONTROL INPUT
A/B
Figure 43. Toggle Mode Function
Rev. A | Page 38 of 44
AD5390/AD5391/AD5392
Power Amplifier Control
0.1µF
Multistage power amplifier designs require a large number of
setpoints in the operation and control of the output stage. The
AD539x are ideal for these applications because of their small
size (LFCSP package) and the integration of 8 and 16 channels,
offering 12- and 14-bit resolution. Figure 44 shows a typical
transmitter architecture, in which the AD539x DACs can be
used in the following control circuits: IBIAS control, average
power control (APC), peak power control (PPC), transmit gain
control (TGC), and audio level control (ALC). DACs are also
required for variable voltage attenuators, phase shifter control,
and dc-setpoint control in the overall amplifier design.
2.5V
REFERENCE
2R
4R
±10V
RANGE
R
R
±5V
RANGE
R
VOUT 3
VOUT 0
1/4 OP747/
1/4 OP4177
1/4 OP747/
1/4 OP4177
R
4R
AD539x-5
2R
0V–5V
RANGE
0V–10V
RANGE
VOUT 1
VOUT 4
1/4 OP747/
1/4 OP4177
I SINK
R
VOUT 2
R
1/4 OP747/
1/4 OP4177
PHASE
SHIFT
I
BIAS
R1
Figure 45. Output Configurations for Process
Control Applications
Optical Transceivers
POWER
AMPLIFIER
AUDIO
SOURCE
50Ω
LOAD
EXCITER
The AD539x-3 family of products are ideally suited to optical
transceiver applications. In 300 pin MSA applications, for
example, digital-to-analog converters are required to control the
laser power, APD bias, modulator amplitude and diagnostic
information is required as analog outputs from the module. The
AD539x offering a combination of 8/16 channels, resolution of
12/14-bits in a 64 lead LFCSP package, operating from a supply
voltage of 2.7 V to 5.5 V supply with internal reference and
featuring I2C-compatible and SPI interface, make it an ideal
component for use in these applications. Figure 46 shows a
typical configuration in an optical transceiver application.
ALC
PPC
APC
TGC
Figure 44. Multistage Power Amplifier Control
Process Control Applications
The AD539x-5 family is ideal for process control applications
because it offers a combination of 8 and 16 channels and 12-bit
and 14-bit resolution. These applications generally require
output voltage ranges of 0 V to 5 V 5 V, 0 V to 10 V 10 V, and
current sink and source functions. The AD539x-5 products
operate from a single 5 V supply and, therefore, require external
signal conditioning to achieve the output ranges described here.
Figure 45 shows configurations to achieve these output ranges.
The key advantages of using AD539x products in these
3V
CONTROLLER
SDA
SCL
DV
AV
DD
DD
SDA
2
I
C
BUS
SCL
VLSRBIAS
VLSRPWRMON
REFOUT/REFIN
AD539x-3
PIN/APD IRXP
AND TIA
VXLOPMON
AV
DD
REFIN
IMODMON
IMPD
IBIASMON
I
BIAS
10G LDD
AND
LASER
AIN
MUX
12-BIT
ADC
IMOD
AD7994
applications are small package size, pin compatibility with the
ability to upgrade from 12 to 14 bits, integrated on-chip 2.5 V
reference with 10 ppm/°C maximum temperature coefficient,
and excellent accuracy specifications. The AD539x family
contains an offset and gain register for each channel, so users
can perform system-level calibration on a per-channel basis.
TIAs
Figure 46. Optical Transceiver using the AD539x-3
Rev. A | Page 39 of 44
AD5390/AD5391/AD5392
OUTLINE DIMENSIONS
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
PIN 1
0.60 MAX
INDICATOR
49
48
64
1
PIN 1
INDICATOR
6.35
6.20 SQ*
6.05
TOP
8.75
BSC SQ
BOTTOM
VIEW
VIEW
0.45
0.40
0.35
33
32
16
17
7.50 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.50 BSC
*
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 47. 64-Lead Lead Frame Chip Scale Package [LFCSP]
9 mm x 9 mm Body (CP-64-2)
(Dimensions shown in millimeters)
0.75
0.60
0.45
12.00 BSC
1.60
MAX
SQ
52
40
39
1
SEATING
PLANE
PIN 1
TOP VIEW
(PINS DOWN)
10.00
BSC SQ
10°
6°
2°
1.45
1.40
1.35
0.20
0.09
7°
VIEW A
13
27
14
26
3.5°
0°
0.38
0.32
0.22
0.15
0.05
0.65
BSC
SEATING
PLANE
0.10 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BCC
Figure 48. 52-Lead Low Profile Quad Flat Package [LQFP]
(ST-52)
(Dimensions shown in millimeters)
Rev. A | Page 40 of 44
AD5390/AD5391/AD5392
ORDERING GUIDE
Temperature
Range
Output
Channels Error (LSBs)
Linearity
Package
Description
Package
Option
Model
Resolution AVDD
2.7 V to 3.6 V
AD5390BCP-3
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
12-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
14-bit
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
8
4
4
4
3
3
3
4
4
3
3
1
1
1
1
1
1
1
1
1
1
4
4
4
3
3
3
4
4
3
3
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
52-lead LQFP
52-lead LQFP
52-lead LQFP
52-lead LQFP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
52-lead LQFP
52-lead LQFP
52-lead LQFP
52-lead LQFP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
64-lead LFCSP
52-lead LQFP
52-lead LQFP
52-lead LQFP
52-lead LQFP
CP-64-2
CP-64-2
CP-64-2
CP-64-2
CP-64-2
CP-64-2
ST-52
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
AD5390BCP-3-REEL
AD5390BCP-3-REEL7
AD5390BCP-5
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
AD5390BCP-5-REEL
AD5390BCP-5-REEL7
AD5390BST-3
AD5390BST-3-REEL
AD5390BST-5
ST-52
ST-52
AD5390BST-5-REEL
AD5391BCP-3
ST-52
CP-64-2
CP-64-2
CP-64-2
CP-64-2
CP-64-2
CP-64-2
ST-52
AD5391BCP-3-REEL
AD5391BCP-3-REEL7
AD5391BCP-5
AD5391BCP-5-REEL
AD5391BCP-5-REEL7
AD5391BST-3
AD5391BST-3-REEL
AD5391BST-5
ST-52
ST-52
AD5391BST-5-REEL
AD5392BCP-3
ST-52
CP-64-2
CP-64-2
CP-64-2
CP-64-2
CP-64-2
CP-64-2
ST-52
AD5392BCP-3-REEL
AD5392BCP-3-REEL7
AD5392BCP-5
8
8
8
AD5392BCP-5-REEL
AD5392BCP-5-REEL7
AD5392BST-3
8
8
8
AD5392BST-3-REEL
AD5392BST-5
8
ST-52
8
ST-52
AD5392BST-5-REEL
Eval–AD5390EB
8
ST-52
AD5390
Evaluation Board
Eval–AD5391EB
Eval–AD5392EB
AD5391
Evaluation Board
AD5392
Evaluation Board
Rev. A | Page 41 of 44
AD5390/AD5391/AD5392
NOTES
Rev. A | Page 42 of 44
AD5390/AD5391/AD5392
NOTES
Rev. A | Page 43 of 44
AD5390/AD5391/AD5392
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03773-0--10/04(A)
Rev. A | Page 44 of 44
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