AD5398BCPZ-WP [ADI]
120 mA, Current Sinking, 10-Bit, I2C DAC; 120毫安，吸收电流， 10位， I2C DAC
| 型号： | AD5398BCPZ-WP |
| 厂家： | 
ADI |
| 描述： | 120 mA, Current Sinking, 10-Bit, I2C DAC |
| 文件： | 总16页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
120 mA, Current Sinking, 10-Bit, I2C DAC
AD5398
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
120 mA current sink
DD
6
Available in 8-lead LFCSP package
2-wire (I2C®-compatible) serial interface
10-bit resolution
POWER-ON
REFERENCE
RESET
AD5398
Integrated current sense resistor
2.7 V to 5.5 V power supply
Guaranteed monotonic over all codes
Power-down to 0.5 μA typical
Internal reference
Ultralow noise preamplifier
Power-down function
Power-on reset
3
4
SDA
SCL
10-BIT
2
I C SERIAL
8
I
SINK
CURRENT
INTERFACE
OUTPUT DAC
R
SENSE
3.3Ω
R
PD
1
5
2
7
DGND
DGND
AGND
Figure 1.
CONSUMER APPLICATIONS
Lens autofocus
Image stabilization
Optical zoom
Shutters
Iris/exposure
Neutral density filter NDFs
Lens covers
Camera phones
Digital still cameras
Camera modules
Digital video cameras (DVCs)/camcorders
Camera-enabled devices
Security cameras
GENERAL DESCRIPTION
The AD5398 is a single 10-bit DAC with 120 mA output
current sink capability. It features an internal reference and
operates from a single 2.7 V to 5.5 V supply. The DAC is
controlled via a 2-wire (I2C-compatible) serial interface that
operates at clock rates up to 400 kHz.
The AD5398 incorporates a power-on reset circuit, which
ensures that the DAC output powers up to 0 V and remains
there until a valid write takes place. It has a power-down
feature that reduces the current consumption of the device to
1 μA max.
Web/PC cameras
The AD5398 is designed for autofocus, image stabilization,
and optical zoom applications in camera phones, digital still
cameras, and camcorders.
INDUSTRIAL APPLICATIONS
Heater control
Fan control
Cooler (Peltier) control
Solenoid control
The AD5398 also has many industrial applications, such as
controlling temperature, light, and movement, over the range
Valve control
−40°C to +85°C without derating.
Linear actuator control
Light control
Current loop control
The I2C address range for the AD5398 is 0x18 to 0x1F
inclusive.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD5398
TABLE OF CONTENTS
Specifications..................................................................................... 3
Theory of Operation ...................................................................... 10
Serial Interface............................................................................ 10
I2C Bus Operation ...................................................................... 10
Data Format ................................................................................ 10
Power Supply Bypassing and Grounding................................ 11
Applications..................................................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
AC Specifications.......................................................................... 4
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Terminology ...................................................................................... 9
REVISION HISTORY
7/05—Rev. 0 to Rev. A
Changes to Table 4............................................................................ 5
Deleted Figure 21............................................................................ 13
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide .......................................................... 14
12/04—Revision 0: Initial Version
Rev. A | Page 2 of 16
AD5398
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD; all specifications TMIN to TMAX
,
unless otherwise noted.
Table 1.
B Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC PERFORMANCE
VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V with
reduced performance
Resolution
Relative Accuracy2
Differential Nonlinearity2, 3
Zero Code Error2,
Offset Error @ Code 162
Gain Error2
Offset Error Drift4, 5
Gain Error Drift2, 5
10
1.5
Bits
LSB
LSB
mA
mA
117 μA/LSB
4
1
Guaranteed monotonic over all codes
All 0s loaded to DAC
4
0
1
0.5
5
0.6
0.5
% of FSR @ 25°C
μA/ºC
LSB/ºC
10
0.2
OUTPUT CHARACTERISTICS
Minimum Sink Current4
Maximum Sink Current
3
120
mA
mA
VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V but
specified maximum sink current might not be achieved
Output Current During PD
Output Compliance5
80
20
nA
V
PD = 1
0.6
VDD
Output voltage range over which max sink current is
available
To 10% of FS, coming out of power-down mode; VDD = 5 V
Power-Up Time
μs
LOGIC INPUTS (PD)5
Input Current
1
0.8
μA
V
V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
LOGIC INPUTS (SCL, SDA)5
Input Low Voltage, VINL
Input High Voltage, VINH
Input Leakage Current IIN
Input Hysteresis, VHYST
Digital Input Capacitance, CIN
Glitch Rejection6
VDD = 2.7 V to 5.5 V
VDD = 2.7 V to 5.5 V
0.7 VDD
3
6
pF
−0.3
0.7 VDD
0.3 VDD
VDD + 0.3
1
V
V
μA
V
pF
ns
VIN = 0 V to VDD
0.05 VDD
50
Pulse width of spike suppressed
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (Normal Mode)
VDD = 2.7 V to 5.5 V
IDD specification is valid for all DAC codes.
VIH = VDD, VIL = GND, VDD = 5.5 V
2.5
2.3
0.5
4
3
1
mA
mA
μA
V
DD = 2.7 V to 4.5 V
V
IH = VDD, VIL = GND, VDD = 4.5 V
IDD (Power-Down Mode)
VIH = VDD, VIL = GND
1 Temperature range is as follows: B Version: –40°C to +85°C.
2 See the Terminology section.
3 Linearity is tested using a reduced code range: Codes 32 to 1023.
4 To achieve near zero output current, use the power-down feature.
5 Guaranteed by design and characterization; not production tested.
6 Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
Rev. A | Page 3 of 16
AD5398
AC SPECIFICATIONS
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD, unless otherwise noted.
Table 2.
B Version1, 2
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Output Current Settling Time
250
μs
VDD = 5 V, RL = 25 Ω, LL = 680 μH
¼ scale to ¾ scale change (0x100 to 0x300)
Slew Rate
Major Code Change Glitch Impulse
Digital Feedthrough3
0.3
0.15
0.06
mA/μs
nA-s
nA-s
1 LSB change around major carry
1 Temperature range is as follows: B Version: –40°C to +85°C.
2 Guaranteed by design and characterization; not production tested.
3 See the Terminology section.
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Version
Limit at TMIN, TMAX
Parameter1
Unit
Description
fSCL
t1
t2
t3
t4
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
t5
t6
2
t7
t8
t9
t10
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus free time between a stop condition and a start condition
tR, rise time of both SCL and SDA when receiving
May be CMOS driven
t11
250
300
20 + 0.1 Cb
tF, fall time of SDA when receiving
tF, fall time of both SCL and SDA when transmitting
3
Cb
400
Capacitive load for each bus line
1 Guaranteed by design and characterization; not production tested.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
3 Cb is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.
SDA
t3
t4
t9
t10
t11
SCL
t2
t7
t1
t8
t4
t6
t5
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. A | Page 4 of 16
AD5398
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1
Table 4.
Stresses above those listed under Absolute Maximum Ratings
Parameter
Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
VDD to AGND
–0.3 V to +7 V
VDD to DGND
AGND to DGND
SCL, SDA to DGND
PD to DGND
–0.3 V to VDD + 0.3 V
–0.3 V to +0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
ISINK to AGND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
LFCSP Power Dissipation
θJA Thermal Impedance2
Mounted on 2-Layer Board
Mounted on 4-Layer Board
Lead Temperature, Soldering
Max Peak Reflow Temperature3
–40°C to +85°C
–65°C to +150°C
150°C
(TJ max – TA)/θJA
84°C/W
48°C/W
260°C ( 5°C)
1 Transient currents of up to 100 mA do not cause SCR latch-up.
2 To achieve the optimum θJA, it is recommended that the AD5398 is soldered on a
4-layer board. The AD5398 comes in an 8-lead LFCSP package with an exposed
paddle that should be connected to the same potential as the AD5398 DGND pin.
3 As per Jedec J-STD-020C.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 16
AD5398
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PD
DGND
SDA
1
2
3
4
8
7
6
5
I
SINK
AD5398
AGND
TOP VIEW
V
DD
(Not to Scale)
SCL
DGND
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
PD
DGND
SDA
SCL
DGND
VDD
Power Down. Asynchronous power-down signal.
Digital Ground Pin.
I2C Interface Signal.
I2C Interface Signal.
Digital Ground Pin.
Digital Supply Voltage.
Analog Ground Pin.
Output Current Sink.
AGND
ISINK
Rev. A | Page 6 of 16
AD5398
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
VERT = 50μs/DIV
INL V = 3.8V
DD
TEMP = 25°C
1.5
1.0
0.5
0
3
HORIZ = 468μA/DIV
–0.5
CH3
M50.0μs
CODE
Figure 4. Typical INL Plot
Figure 7. Settling Time for a 4-LSB Step (VDD = 3.6 V)
0.6
0.5
0.4
0.3
0.2
0.1
0
DNL V = 3.8V
DD
TEMP = 25°C
VERT = 2μA/DIV
4.8μA p-p
1
–0.1
–0.2
–0.3
HORIZ = 2s/DIV
CH1
M2.0s
CODE
Figure 5. Typical DNL Plot
Figure 8. 0.1 Hz to 10 Hz Noise Plot (VDD = 3.6 V)
92.0
91.5
91.0
90.5
90.0
89.5
89.0
88.5
88.0
0.14
I
@ +25°C
OUT
0.12
0.10
0.08
0.06
0.04
0.02
0
I
@ –40°C
OUT
I
@ +85°C
OUT
–6
–6
–6
–6
–6
250.0
–6 –6
300.0 333.1
53.5
100.0
150.0
200.0
TIME
CODE
Figure 6. ¼ to ¾ Scale Settling Time (VDD = 3.6 V)
Figure 9. Sink Current vs. Code vs. Temperature (VDD = 3.6 V)
Rev. A | Page 7 of 16
AD5398
2000
1800
1600
1400
1200
1000
800
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
= 3.6V
DD
V
= 4.5V
DD
V
= 3.8V
DD
600
400
200
0
10
–40 –30 –20 –10
0
15 25 35 45 55 65 75 85
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY
Figure 10. AC Power Supply Rejection (VDD = 3.6 V)
Figure 13. Zero Code Error vs. Supply Voltage vs. Temperature
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.5
V
= 4.5V
DD
1.0
0.5
POSITIVE INL (V = 3.8V) POSITIVE INL (V = 4.5V)
DD DD
V
= 3.8V
DD
0
POSITIVE INL (V = 3.6V)
DD
–0.5
–1.0
–1.5
–2.0
NEGATIVE INL (V = 3.6V)
DD
NEGATIVE INL (V = 3.8V)
DD
–0.5
–1.0
V
= 3.6V
DD
NEGATIVE INL (V = 4.5V)
DD
–40 –30 –20 –10
0
15 25 35 45 55 65 75 85
–40 –30 –20 –10
0
15 25 35 45 55 65 75 85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. INL vs. Temperature vs. Supply
Figure 14. Full-Scale Error vs. Temperature vs. Supply
1.0
0.8
0.6
POSITIVE DNL (V = 3.6V)
DD
0.4
POSITIVE DNL (V = 4.5V)
DD
0.2
0
POSITIVE DNL (V = 3.8V)
DD
NEGATIVE DNL (V = 3.8V)
DD
–0.2
–0.4
–0.6
–0.8
–1.0
NEGATIVE DNL (V = 4.5V)
DD
NEGATIVE DNL (V = 3.6V)
DD
–40 –30 –20 –10
0
15 25 35 45 55 65 75 85
TEMPERATURE (°C)
Figure 12. DNL vs. Temperature vs. Supply
Rev. A | Page 8 of 16
AD5398
TERMINOLOGY
Relative Accuracy
Gain Error Drift
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSB, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 4.
This is a measurement of the change in gain error with changes
in temperature. It is expressed in LSB/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nA-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot is shown in Figure 5.
Digital Feedthrough
Digital feedthrough is a measurement of the impulse injected
into the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nA-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally the
output is 0 mA. The zero-code error is always positive in the
AD5398 because the output of the DAC cannot go below 0 mA.
This is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in mA.
Offset Error
Offset error is a measurement of the difference between ISINK
(actual) and IOUT (ideal) in the linear region of the transfer
function, expressed in mA. Offset error is measured on the
AD5398 with Code 16 loaded into the DAC register.
Gain Error
This is a measurement of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percent of the full-scale range.
Offset Error Drift
This is a measurement of the change in offset error with a
change in temperature. It is expressed in μV/°C.
Rev. A | Page 9 of 16
AD5398
THEORY OF OPERATION
The AD5398 is a fully integrated 10-bit DAC with 120 mA
output current sink capability and is intended for driving voice
coil actuators in applications such as lens autofocus, image sta-
bilization, and optical zoom. The circuit diagram is shown in
Figure 15. A 10-bit current output DAC coupled with Resistor R
generates the voltage that drives the noninverting input of the
operational amplifier. This voltage also appears across the RSENSE
resistor and generates the sink current required to drive the
voice coil.
When the bus is idle, SCL and SDA are both high. The master
device initiates a serial bus operation by generating a start
condition, which is defined as a high-to-low transition on the
SDA low while SCL is high. The slave device connected to the
bus responds to the start condition and shifts in the next eight
data bits under control of the serial clock. These eight data bits
consist of a 7-bit address, plus a read/write bit, which is 0 if data
is to be written to a device, and 1 if data is to be read from a
device. Each slave device on an I2C bus must have a unique
address. The address of the AD5398 is 0001100; however,
0001101, 0001110, and 0001111 address the part because the
last two bits are unused/don’t care (see Figure 17 and Figure 18).
Since the address plus R/W bit always equals eight bits of data,
another way of looking at it is that the write address of the
AD5398 is 0001 1000 (0x18) and the read address is 0001 1001
(0x19). Again, Bit 6 and Bit 7 of the address are unused, and
therefore the write addresses can also be 0x1A, 0x1C, and 0x1E,
and the read address can be 0x1B, 0x1D, and 0x1F (see Figure 17
and Figure 18).
Resistors R and RSENSE are interleaved and matched. Therefore,
the temperature coefficient and any nonlinearities over tem-
perature are matched and the output drift over temperature is
minimized. Diode D1 is an output protection diode.
V
BAT
V
DD
6
VOICE
POWER-ON
RESET
REFERENCE
COIL
AD5398
ACTUATOR
D1
SDA
SCL
3
4
10-BIT
2
I C SERIAL
8
CURRENT
INTERFACE
I
At the end of the address data, after the R/W bit, the slave
device that recognizes its own address responds by generating
an acknowledge (ACK) condition. This is defined as the slave
device pulling SDA low while SCL is low before the ninth clock
pulse, and keeping it low during the ninth clock pulse. Upon
receiving ACK, the master device can clock data into the
AD5398 in a write operation, or it can clock it out in a read
operation. Data must change only during the low period of the
clock, because SDA transitions during the high period define a
start condition as described previously, or a stop condition as
described in the Data Format section.
OUTPUT DAC
SINK
R
SENSE
3.3Ω
R
1
PD
5
2
7
AGND
DGND
DGND
Figure 15. Block Diagram Showing Connection to Voice Coil
SERIAL INTERFACE
The AD5398 is controlled using the industry-standard I2C
2-wire serial protocol. Data can be written to the DAC, or read
back from it, at data rates up to 400 kHz. After a read operation
the contents of the input register are reset to all zeros.
I2C data is divided into blocks of eight bits, and the slave
generates an ACK at the end of each block. Since the AD5398
requires 10 bits of data, two data-words must be written to it
when a write operation, or read back from it when a read
operation. At the end of a read or write operation, the AD5398
acknowledges the second data byte. The master generates a stop
condition, defined as a low-to-high transition on SDA while
SCL is high, to end the transaction.
I2C BUS OPERATION
An I2C bus operates with one or more master devices that
generate the serial clock (SCL), and read/write data on the serial
data line (SDA) to/from slave devices such as the AD5398. All
devices on an I2C bus have their SCL pin connected to the SDA
line and their SCL pin connected to the SCL line. I2C devices
can only pull the bus lines low; pulling high is achieved by pull-
up resistors RP. The value of RP depends on the data rate, bus
capacitance, and the maximum load current that the I2C device
can sink (3 mA for a standard device).
DATA FORMAT
Data is written to the AD5398 high byte first, MSB first, and is
shifted into the 16-bit input register. After all data is shifted in,
data from the input register is transferred to the DAC register.
V
DD
Because the DAC requires only 10 bits of data, not all bits of the
input register data are used. The MSB is reserved for an active-
high, software-controlled, power-down function. Bit 14 is
unused; Bit 13 to Bit 4 are DAC data; Bit 9 to Bit 0 and Bit 3
to Bit 0 are unused.
R
R
P
P
SDA
SCL
2
2
2
I C MASTER
DEVICE
I C SLAVE
I C SLAVE
AD5398
DEVICE
DEVICE
During a read operation, data is read back in the same bit order.
Figure 16. Typical I2C Bus
Rev. A | Page 10 of 16
AD5398
1
0
9
1
1
9
SCL
SDA
0
0
1
1
X
X
R/W
PD
X
D9 D8 D7 D6 D5 D4
D3 D2 D1 D0
X
X
X
X
START BY
MASTER
ACK BY
AD5398
ACK BY
AD5398
ACK BY STOP BY
AD5398 MASTER
FRAME 1
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
SERIAL BUS
ADDRESS BYTE
Figure 17. Write Operation
1
0
9
1
1
9
SCL
SDA
0
0
1
1
X
X
R/W
PD
X
D9 D8 D7 D6 D5 D4
D3 D2 D1 D0
X
X
X
X
START BY
MASTER
ACK BY
AD5398
ACK BY
AD5398
ACK BY STOP BY
AD5398 MASTER
FRAME 1
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
SERIAL BUS
ADDRESS BYTE
Figure 18. Read Operation
Table 6. Data Format 1
Serial Data-Words High Byte
Low Byte
Serial Data Bits
Input Register
Function
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
R15 R14 R13 R12 R11 R10 R9
PD D9 D8 D7 D6 D5
R8
D4
R7
D3
R6
D2
R5
D1
R4
D0
R3
X
R2
X
R1
X
R0
X
X
1 PD = soft power-down; X = unused/don’t care; D9 to D0 = DAC data
POWER SUPPLY BYPASSING AND GROUNDING
V
BAT
When accuracy is important in an application, it is beneficial to
consider power supply and ground return layout on the PCB.
The PCB for the AD5398 should have separate analog and
digital power supply sections. Where shared AGND and DGND
is necessary, the connection of grounds should be made at only
one point, as close as possible to the AD5398.
VOICE
COIL
ACTUATOR
L
C
V
C
R
C
TRACE
RESISTANCE
R
T
V
V
T
8
Special attention should be paid to the layout of the AGND
return path and track between the voice coil motor and ISINK to
minimize any series resistance. Figure 19 shows the output
current sink of the AD5398 and illustrates the importance of
reducing the effective series impedance of AGND, and the track
resistance between the motor and ISINK. The voice coil is
modeled as inductor LC and resistor RC. The current through
the voice coil is effectively a dc current that results in a voltage
drop, VC, when the AD5398 is sinking current; the effect of any
series inductance is minimal. The maximum voltage drop
allowed across RSENSE is 400 mV, and the minimum drain to
source voltage of Q1 is 200 mV. This means that the AD5398
output has a compliance voltage of 600 mV. If VDROP falls below
600 mV, the output transistor, Q1, can no longer operate
properly and ISINK might not be maintained as a constant.
I
SINK
Q1
R
SENSE
3.3Ω
DROP
7
AGND
GROUND
R
G
RESISTANCE
V
G
GROUND
INDUCTANCE
L
G
Figure 19. Effect of PCB Trace Resistance and Inductance
Rev. A | Page 11 of 16
AD5398
As the current increases through the voice coil, VC increases
and VDROP decreases and eventually approaches the minimum
specified compliance voltage of 600 mV. The ground return
path is modeled by the components RG and LG, and the track
resistance between the voice coil and the AD5398 is modeled as
RT. The inductive effects of LG influence RSENSE and RC equally,
and because the current is maintained as a constant, it is not as
critical as the purely resistive component of the ground return
path. When the maximum sink current is flowing through the
motor, the resistive elements, RT and RG, might have an impact
on the voltage headroom of Q1 and could, in turn, limit the
maximum value of RC because of voltage compliance.
For this reason it is important to minimize any series impedance
on both the ground return path and interconnect between the
AD5398 and the motor.
The power supply of the AD5398 should be decoupled with
0.1 μF and 10 μF capacitors. These capacitors should be kept as
physically close as possible, with the 0.1 μF capacitor serving as
a local bypass capacitor, and therefore should be located as close
as possible to the VDD pin. The 10 μF capacitor should be a
tantalum bead-type; the 0.1 μF capacitor should be a ceramic
type with a low effective series resistance and effective series
inductance. The 0.1 μF capacitor provides a low impedance path
to ground for high transient currents.
For example,
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching digital
signals should be shielded from other parts of the board by
digital ground. Avoid crossover of digital and analog signals if
possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is to use a multilayer board with ground and power
planes, where the component side of the board is dedicated to
the ground plane only and the signal traces are placed on the
solder side. However, this is not always possible with a
2-layer board.
VBAT = 3.6 V
RG = 0.5 Ω
RT = 0.5 Ω
ISINK = 120 mA
VDROP = 600 mV (the compliance voltage)
Then the largest value of resistance of the voice coil, RC, is
VBAT −[VDROP +(ISINK ×RT )+(ISINK ×RG)]
RC =
=
ISINK
The exposed paddle on the AD5398 should be soldered to
ground to ensure the best possible thermal performance. The
thermal impedance of the AD5398 LFCSP package is 48°C/W
when soldered in a 4-layer board. It is defined in the Absolute
Maximum Ratings Section.
3.6 V −[600 mV +2×(120 mA×0.5 ꢀ)]
= 24 ꢀ
120 mA
Rev. A | Page 12 of 16
AD5398
APPLICATIONS
The AD5398 is designed to drive both spring preloaded and
nonspring linear motors used in applications such as lens auto-
focus, image stabilization, or optical zoom. The operation
principle of the spring preloaded motor is that the lens position
is controlled by the balancing of a voice coil and spring. Figure 20
shows the transfer curve of a typical spring preloaded linear
motor for autofocus. The key points of this transfer function are
displacement or stroke, which is the actual distance the lens
moves in mm, and the current through the motor in mA.
0.5
0.4
0.3
0.2
0.1
0
START
CURRENT
A start current is associated with spring preloaded linear
motors, which is effectively a threshold current that must be
exceeded for any displacement in the lens to occur. The start
current is usually 20 mA or greater; the rated stroke or
displacement is usually 0.25 mm to 0.4 mm; and the slope of
the transfer curve is approximately 10 μm/mA or less.
0
10
20
30
40
50
60
70
80
90 100 110 120
SINK CURRENT (mA)
Figure 20. Spring Preloaded Voice Coil Stroke vs. Sink Current
The AD5398 is designed to sink up to 120 mA, which is more
than adequate for available commercial linear motors or voice
coils. Another factor that makes the AD5398 the ideal solution
for these applications is the monotonicity of the device, which
ensures that lens positioning is repeatable for the application of
a given digital word.
Figure 21 shows a typical application circuit for the AD5398.
V
V
CC
DD
+
+
0.1μF
10μF
10μF
0.1μF
6
POWER-DOWN
VOICE
POWER-ON
RESET
RESET
1
REFERENCE
COIL
AD5398
ACTUATOR
V
DD
R
R
P
P
SDA
SCL
10-BIT
3
4
2
I C SERIAL
8
CURRENT
INTERFACE
OUTPUT DAC
2
2
2
R
I C MASTER
DEVICE
I C SLAVE
I C SLAVE
SENSE
3.3Ω
R
DEVICE
DEVICE
5
2
7
Figure 21. Typical Application Circuit
Rev. A | Page 13 of 16
AD5398
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
8
PIN 1
INDICATOR
1
PIN 1
INDICATOR
1.89
1.74
1.59
2.75
BSC SQ
TOP
VIEW
1.50
REF
0.50
BSC
4
5
1.60
1.45
1.30
0.70 MAX
0.65TYP
12° MAX
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 22. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5398BCPZ-REEL1
AD5398BCPZ-REEL71
AD5398BCPZ-WP1
EVAL-AD5398EB
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
8-Lead LFCSP_VD
8-Lead LFCSP_VD
8-Lead LFCSP_VD
Evaluation Board
Package Option
CP-8-2
CP-8-2
–40°C to +85°C
CP-8-2
1 Z = Pb-free part.
Rev. A | Page 14 of 16
AD5398
NOTES
Rev. A | Page 15 of 16
AD5398
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05034–0–7/05(A)
Rev. A | Page 16 of 16
相关型号：
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IC SERIAL INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, PDSO10, MICRO, SOIC-10, Digital to Analog Converter
ADI
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