AD5444YRM [ADI]
12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface; 12位/ 14位，高带宽乘法数模转换器，串行接口
| 型号： | AD5444YRM |
| 厂家： | 
ADI |
| 描述： | 12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface |
| 文件： | 总28页 (文件大小：726K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-/14-Bit High Bandwidth
Multiplying DACs with Serial Interface
Data Sheet
AD5444/AD5446
FEATURES
GENERAL DESCRIPTION
12 MHz multiplying bandwidth
INL of 0.5 LSB at 12 bits
Pin-compatible 12-/14-bit current output DAC
2.5 V to 5.5 V supply operation
10-lead MSOP package
10 V reference input
50 MHz serial interface
2.7 MSPS update rate
The AD5444/AD54461 are CMOS 12-bit and 14-bit, current
output, digital-to-analog converters (DACs). Operating from a
single 2.5 V to 5.5 V power supply, these devices are suited for
battery-powered and other applications.
As a result of the CMOS submicron manufacturing process,
these parts offer excellent 4-quadrant multiplication char-
acteristics of up to 12 MHz.
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. On power-up, the internal shift register and
latches are filled with 0s, and the DAC output is at zero scale.
Extended temperature range: −40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detection
0.4 µA typical current consumption
Guaranteed monotonic
The applied external reference input voltage (VREF) determines
the full-scale output current. These parts can handle 10 V
inputs on the reference, despite operating from a single-supply
power supply of 2.5 V to 5.5 V. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage output
when combined with an external current-to-voltage precision
amplifier. The AD5444/AD5446 DACs are available in small
10-lead MSOP packages, which are pin-compatible with the
AD5425/AD5426/AD5432/AD5443 family of DACs.
APPLICATIONS
Portable, battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
The EV-AD5443/46/53SDZ board is available for evaluating
DAC performance. For more information, see the UG-327
evaluation board user guide.
Ultrasound
Gain, offset, and voltage trimming
Automotive radar
1 US Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
V
V
REF
DD
R
FB
R
AD5444/
AD5446
I
I
1
2
OUT
12-BIT
R-2R DAC
OUT
DAC REGISTER
INPUT LATCH
POWER-ON
RESET
SYNC
SCLK
SDIN
CONTROL LOGIC AND
INPUT SHIFT REGISTER
SDO
GND
Figure 1.
Rev. E
Document Feedback
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5444/AD5446
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Section................................................................................ 15
Circuit Operation....................................................................... 15
Single-Supply Applications ....................................................... 17
Adding Gain................................................................................ 17
Divider or Programmable Gain Element................................ 17
Amplifier Selection .................................................................... 18
Reference Selection .................................................................... 18
Serial Interface ................................................................................ 20
Microprocessor Interfacing....................................................... 21
PCB Layout and Power Supply Decoupling................................ 23
Overview of AD54xx and AD55xx Current Output Devices... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 14
General Description....................................................................... 15
REVISION HISTORY
6/13—Rev. D to Rev. E
4/05—Rev. 0 to Rev. A
Changes to General Description Section ...................................... 1
Change to Figure 46 and Figure 47 .............................................. 21
Changes to Ordering Guide .......................................................... 25
Added AD5446 ...................................................................Universal
Changes to Features ..........................................................................1
Changes to General Description .....................................................1
Changes to Specifications.................................................................3
Inserted Figure 7; Renumbered Sequentially.................................9
Inserted Figure 9; Renumbered Sequentially.................................9
Inserted Figure 13; Renumbered Sequentially ........................... 10
Changes to Figure 22...................................................................... 11
Changes to Figure 23...................................................................... 11
Changes to Serial Interface............................................................ 20
Changes to Figure 44...................................................................... 20
Changes to Figure 45...................................................................... 20
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide.......................................................... 28
4/12—Rev. C to Rev. D
Changes to General Description Section ...................................... 1
Deleted Evaluation Board for the DAC Section......................... 23
Deleted Power Supplies for the Evaluation Board Section ....... 23
Deleted Figure 54; Renumbered Sequentially ............................ 24
Deleted Figure 55 and Figure 56................................................... 25
Updated Outline Dimensions....................................................... 25
Changes to Ordering Guide .......................................................... 25
Deleted Figure 57............................................................................ 26
4/07—Rev. B to Rev. C
Changes to Table 9.......................................................................... 19
Changes to Ordering Guide .......................................................... 28
Changes to Features.......................................................................... 1
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Figure 22...................................................................... 10
Changes to Figure 23...................................................................... 10
Changes to Table 9.......................................................................... 19
Changes to Table 12........................................................................ 27
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide .......................................................... 28
10/04—Revision 0: Initial Version
Rev. E | Page 2 of 28
Data Sheet
AD5444/AD5446
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX
,
unless otherwise noted. DC performance measured with OP177, and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
AD5444
Resolution
Relative Accuracy
Differential Nonlinearity
Total Unadjusted Error (TUE)
Gain Error
12
0.5
1
1
0.5
Bits
LSB
LSB
LSB
LSB
Guaranteed monotonic
AD5446
Resolution
14
Bits
Relative Accuracy
2
LSB
Differential Nonlinearity
Total Unadjusted Error (TUE)
Gain Error
−1/+2
4
2.5
LSB
LSB
LSB
ppm FSR/°C
nA
Guaranteed monotonic
Gain Error Temperature Coefficient1
2
Output Leakage Current
1
Data = 0x0000, TA = 25°C, IOUT1
10
nA
Data = 0x0000, TA = −40°C to +125°C, IOUT1
REFERENCE INPUT1
Reference Input Range
VREF Input Resistance
RFB Feedback Resistance
Input Capacitance
10
9
9
V
kΩ
kΩ
7
7
11
11
Input resistance TC = −50 ppm/°C
Input resistance TC = −50 ppm/°C
Zero-Scale Code
Full-Scale Code
18
18
22
22
pF
pF
DIGITAL INPUTS/OUTPUTS1
Input High Voltage, VIH
2.0
1.7
V
V
VDD = 3.6 V to 5 V
VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
Input Leakage Current, IIL
Input Capacitance
0.8
0.7
V
V
V
V
V
V
nA
nA
pF
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD − 1
VDD − 0.5
VDD = 4.5 V to 5 V, ISOURCE = 200 µA
VDD = 2.5 V to 3.6 V, ISOURCE = 200 µA
VDD = 4.5 V to 5 V, ISINK = 200 µA
VDD = 2.5 V to 3.6 V, ISINK = 200 µA
TA = 25°C
0.4
0.4
1
10
10
TA = −40°C to +125°C
Rev. E | Page 3 of 28
AD5444/AD5446
Data Sheet
Parameter
Min
Typ
Max
Unit
Conditions
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth
Multiplying Feedthrough Error
12
MHz
VREF = 3.5 V, DAC loaded with all 1s
VREF = 3.5 V, DAC loaded with all 0s
72
64
44
dB
dB
dB
100 kHz
1 MHz
10 MHz
Output Voltage Settling Time
VREF = 10 V, RLOAD = 100 Ω, DAC latch alternately
loaded with 0s and 1s
Measured to 1 mV of FS
Measured to 4 mV of FS
Measured to 16 mV of FS
Digital Delay
10%-to-90% Settling Time
Digital-to-Analog Glitch Impulse
Output Capacitance
100
24
16
20
10
2
110
40
33
40
30
ns
ns
ns
ns
ns
nV-s
Interface delay time
Rise and fall time, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
IOUT
1
13
28
18
5
pF
pF
pF
pF
DAC latches loaded with all 0s
DAC latches loaded with all 1s
DAC latches loaded with all 0s
DAC latches loaded with all 1s
IOUT
2
Digital Feedthrough
0.5
nV-s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 3.5 V p-p, all 1s loaded, f = 1 kHz
Clock = 1 MHz, VREF = 3.5 V
Analog THD
Digital THD
83
dB
50 kHz fOUT
20 kHz fOUT
Output Noise Spectral Density
SFDR Performance (Wide Band)
50 kHz fOUT
71
77
25
dB
dB
nV/√Hz
@ 1 kHz
Clock = 10 MHz, VREF = 3.5 V
78
74
dB
dB
20 kHz fOUT
SFDR Performance (Narrow Band)
50 kHz fOUT
20 kHz fOUT
Clock = 1 MHz, VREF = 3.5 V
87
85
79
dB
dB
dB
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range, VDD
Supply Current, IDD
f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V
2.5
5.5
10
0.6
0.001
V
0.4
µA
µA
%/%
TA = −40°C to +125°C, logic inputs = 0 V or VDD
TA = 25°C, logic inputs = 0 V or VDD
∆VDD = 5%
Power Supply Sensitivity1
1 Guaranteed by design and characterization; not subject to production test.
Rev. E | Page 4 of 28
Data Sheet
AD5444/AD5446
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
REF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted.
V
Table 2.
V
DD = 4.5 V to
VDD = 2.5 V to
5.5 V
Parameter1
5.5 V
50
20
8
Unit
Conditions/Comments
fSCLK
t1
t2
50
20
8
MHz max Maximum clock frequency.
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MSPS
SCLK cycle time.
SCLK high time.
SCLK low time.
SYNC falling edge to SCLK active edge setup time.
Data setup time.
Data hold time.
SYNC rising edge to SCLK active edge setup time
Minimum SYNC high time.
t3
t4
8
8
8
8
t5
t6
t7
5
4.5
5
5
4.5
5
t8
30
23
2.7
30
30
2.7
t9
SCLK active edge to SDO valid.
Consists of cycle time, SYNC high time, data setup time and output
voltage settling time.
Update Rate
1 Guaranteed by design and characterization; not subject to production test.
t1
SCLK
t2
t3
t4
t7
SYNC
t8
t6
t5
DB15
DB0
SDIN
Figure 2. Standalone Timing Diagram
t1
SCLK
SYNC
SDIN
t2
t3
t7
t8
t4
t6
t5
DB15
DB0
DB15 (N)
DB0 (N)
(N + 1)
(N + 1)
t9
SDO
DB15 (N)
DB0 (N)
NOTES
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain Timing Diagram
Rev. E | Page 5 of 28
AD5444/AD5446
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VDD to GND
VREF, RFB to GND
IOUT1, IOUT2 to GND
Logic Inputs and Outputs1
Input Current (All Pins Except Supplies)
Operating Temperature Range
Extended (Y Version)
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
10 mA
Only one absolute maximum rating can be applied at any one
time.
−40°C to +125°C
I
200µA
OL
Storage Temperature Range
Junction Temperature
10-lead MSOP θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
−65°C to +150°C
150°C
206°C/W
300°C
TO
OUTPUT
PIN
V
+V
2
OH (MIN)
OL (MAX)
C
20pF
L
I
200µA
OH
235°C
Figure 4. Load Circuit for SDO Timing Specifications
1
SYNC
Overvoltages at SCLK,
, and SDIN are clamped by internal diodes.
ESD CAUTION
Rev. E | Page 6 of 28
Data Sheet
AD5444/AD5446
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
10
R
I
1
FB
OUT
AD5444/
AD5446
9
V
I
2
REF
DD
OUT
8
GND
V
TOP VIEW
(Not to Scale)
7
SCLK
SDIN
SDO
6
SYNC
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
IOUT
IOUT
GND
SCLK
1
2
DAC Current Output.
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
Ground Pin.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked
into the shift register on the rising edge of SCLK.
5
6
SDIN
SYNC
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.
By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow
the user to change the active edge to the rising edge.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low,
data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising
edge of SYNC.
7
SDO
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to data loaded to the shift register.
8
9
10
VDD
VREF
RFB
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input.
DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.
Rev. E | Page 7 of 28
AD5444/AD5446
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
2.0
1.6
T
V
V
= 25°C
= 10V
A
T
= 25°C
A
0.4
0.3
0.2
REF
V
V
= 10V
REF
= 5V
= 5V
DD
DD
1.2
0.8
0.1
0.4
0
0
–0.1
–0.2
–0.3
–0.4
–0.8
–1.2
–1.6
–2.0
–0.4
–0.5
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
0
512
1024
1536
2048
2560
3072
3584
4096
CODE
Figure 6. INL vs. Code (12-Bit DAC)
Figure 9. DNL vs. Code (14-Bit DAC)
2.0
1.00
0.75
0.50
0.25
0
T
V
V
= 25°C
= 10V
A
T
= 25°C
A
1.6
1.2
REF
V
= 5V
DD
AD5444
= 5V
DD
MAX INL
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0
MIN INL
–0.25
–0.50
–0.75
–1.00
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
2
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE (V)
Figure 10. INL vs. Reference Voltage
Figure 7. INL vs. Code (14-Bit DAC)
1.0
0.8
0.6
0.4
2.0
1.5
T
V
V
= 25°C
T
= 25°C
= 5V
A
A
V
= 10V
DD
AD5444
REF
= 5V
DD
1.0
MAX DNL
MIN DNL
0.5
0.2
0
0
–0.2
–0.5
–1.0
–1.5
–2.0
–0.4
–0.6
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
2
3
4
5
6
7
8
9
10
CODE
REFERENCE VOLTAGE (V)
Figure 8. DNL vs. Code (12-Bit DAC)
Figure 11. DNL vs. Reference Voltage
Rev. E | Page 8 of 28
Data Sheet
AD5444/AD5446
1.0
0.3
0.2
V
= 10V
REF
T
V
V
= 25°C
A
0.8
0.6
0.4
= 10V
REF
= 5V
DD
0.1
V
= 3V
DD
0.2
V
= 5V
0
DD
0
–0.2
–0.4
–0.6
–0.1
–0.2
–0.3
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
–60 –40 –20
0
20
40
60
80
100 120 140
CODE
TEMPERATURE (°C)
Figure 15. Gain Error vs. Temperature
Figure 12. TUE vs. Code (12-Bit DAC)
2.0
2.0
1.5
T
V
V
= 25°C
A
T
= 25°C
A
= 10V
1.6
1.2
REF
= 5V
V
= 5V
DD
AD5444
DD
1.0
0.8
0.5
0.4
0
0
–0.4
–0.8
–1.2
–1.6
–2.0
–0.5
–1.0
–1.5
–2.0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
2
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE (V)
Figure 13. TUE vs. Code (14-Bit DAC)
Figure 16. Gain Error vs. Reference Voltage
2.0
1.5
1.0
0.5
0
2.0
T
= 25°C
= 5V
A
V
DD
AD5444
I
1, V = 5V
OUT DD
1.6
1.2
0.8
MAX TUE
I
1, V = 3V
OUT DD
MIN TUE
–0.5
–1.0
–1.5
–2.0
0.4
0
2
3
4
5
6
7
8
9
10
–40
–20
0
20
40
60
80
100
120
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
Figure 17. IOUT1 Leakage Current vs. Temperature
Figure 14. TUE vs. Reference Voltage
Rev. E | Page 9 of 28
AD5444/AD5446
Data Sheet
2.5
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
= 25°C
A
T
= 25°C
A
V
IH
V
IL
2.0
1.5
V
= 5V
DD
1.0
0.5
0
V
= 3V
2
DD
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
1
3
4
5
INPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 18. Supply Current vs. Logic Input Voltage
Figure 21. Threshold Voltage vs. Supply Voltage
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
0
T
= 25°C
A
ALL 1s
ALL 0s
LOADING
ZS TO FS
ALL ON
DB13
–10
–20
–30
–40
–50
–60
–70
–80
DB12
DB11
DB10
V
= 5V
DD
DB9
DB8
DB7
DB6
DB5
DB4
DB3
V
= 3V
DD
V
V
C
= 5V
DD
= ±3.5V
REF
DB2
= 1.8pF
COMP
AD8038 AMPLIFIER
10k
100k
1M
10M 100M
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 22. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 19. Supply Current vs. Temperature
0.6
0.4
6
5
4
3
2
1
0
T
= 25°C
A
AD5444
LOADING 0101 0101 0101
0.2
0
–0.2
–0.4
–0.6
V
= 5V
DD
T
V
= 25°C
= 5V
–0.8
–1.0
–1.2
A
DD
V
= ±3.5V
REF
C
= 1.8pF
COMP
AD8038 AMPLIFIER
V
= 3V
DD
1
10
100
1k
10k
100k
1M
10M
10k 100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. Supply Current vs. Update Rate
Figure 23. Reference Multiplying Bandwidth vs. Frequency—All 1s Loaded
Rev. E | Page 10 of 28
Data Sheet
AD5444/AD5446
3
10
0
T
V
= 25°C
= 3V
A
T
V
= 25°C
A
DD
= 5V
DD
AD8038 AMPLIFIER
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–3
–6
–9
FULL SCALE
ZERO SCALE
V
V
V
V
V
= ±2V, AD8038 C
= ±2V, AD8038 C
= ±15V, AD8038 C
= ±15V, AD8038 C
= ±15V, AD8038 C
= 1pF
= 1.5pF
REF
REF
REF
REF
REF
COMP
COMP
= 1pF
= 1.5pF
= 1.8pF
COMP
COMP
COMP
1
10
100
1k
10k
100k
1M
10M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27. Power Supply Rejection Ratio vs. Frequency
Figure 24. Reference Multiplying Bandwidth vs. Frequency
and Compensation Capacitor
–60
–65
–70
–75
–80
–85
–90
0.08
0.06
0.04
0.02
0
T
V
V
= 25°C
= 5V
A
V
= 5V
DD
T
V
= 25°C
= 0V
A
DD
0x7FF TO 0x800
NRG = 2.154nV-s
= ±3.5V
REF
REF
AD8038 AMP
= 1.8pF
C
COMP
V
= 3V
DD
0x7FF TO 0x800
NRG = 1.794nV-s
V
= 5V
DD
–0.02
–0.04
–0.06
0x800 TO 0x7FF
NRG = 0.694nV-s
V
= 5V
0x800 TO 0x7FF
NRG = 0.694nV-s
DD
50
75
100
125
150
175
200
225
250
100
1k
10k
100k
FREQUENCY (Hz)
TIME (ns)
Figure 25. Midscale Transition, VREF = 0 V
Figure 28. THD + Noise vs. Frequency
100
80
60
40
20
0
–1.66
–1.68
–1.70
–1.72
–1.74
–1.76
–1.78
–1.80
V
= 5V
DD
T
V
= 25°C
= 3.5V
A
0x7FF TO 0x800
NRG = 2.154nV-s
MCLK = 200kHz
MCLK = 500kHz
REF
AD8038 AMP
= 1.8pF
C
COMP
V
= 3V
DD
MCLK = 1MHz
0x7FF TO 0x800
NRG = 1.794nV-s
V
= 5V
DD
0x800 TO 0x7FF
NRG = 0.694nV-s
= 5V
T
V
= 25°C
A
V
DD
= 3.5V
REF
0x800 TO 0x7FF
NRG = 0.694nV-s
AD8038 AMP
50
75
100
125
150
175
200
225
250
0
10
20
30
40
50
TIME (ns)
fOUT (kHz)
Figure 29. Wideband SFDR vs. fOUT Frequency
Figure 26. Midscale Transition, VREF = 3.5 V
Rev. E | Page 11 of 28
AD5444/AD5446
Data Sheet
0
0
–20
T
V
V
= 25°C
= 5V
T
V
V
= 25°C
= 5V
A
A
DD
DD
= 3.5V
= 3.5V
REF
REF
–20
AD8038 AMP
AD8038 AMP
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
100k
200k
300k
400k
500k
10k
15k
20k
25k
30k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. Wideband SFDR , fOUT = 20 kHz, Clock = 1 MHz
Figure 32. Narrow-Band SFDR, fOUT = 20 kHz, Clock = 1 MHz
0
0
T
V
V
= 25°C
= 5V
T
V
V
= 25°C
= 5V
A
A
DD
DD
= 3.5V
= 3.5V
REF
REF
–20
–20
–40
AD8038 AMP
AD8038 AMP
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
100k
200k
300k
400k
500k
30k
40k
50k
60k
70k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 1 MHz
Figure 33. Narrow-Band SFDR, fOUT = 50 kHz, Clock = 1 MHz
Rev. E | Page 12 of 28
Data Sheet
AD5444/AD5446
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
80
70
60
50
40
30
20
10
0
T
V
= 25°C
= 3.5V
A
T
= 25°C
A
REF
AD8038 AMP
AD8038 AMP
FULL SCALE
LOADED TO DAC
MIDSCALE
LOADED TO DAC
ZERO SCALE
LOADED TO DAC
–100
10k
100
1k
10k
100k
1M
15k
20k
25k
30k
35k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 34. Narrow-Band IMD, fOUT = 20 kHz and 25 kHz, Clock = 1 MHz
Figure 36. Output Noise Spectral Density
0
T
= 25°C
A
V
= 3.5V
REF
AD8038 AMP
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
100k
200k
300k
400k
500k
FREQUENCY (Hz)
Figure 35. Wideband IMD, fOUT = 20 kHz and 25 kHz, Clock = 1 MHz
Rev. E | Page 13 of 28
AD5444/AD5446
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity
Digital Feedthrough
Relative accuracy or integral nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero scale and full scale and is normally expressed
in LSBs or as a percentage of full-scale reading.
When the device is not selected, high frequency logic activ-
ity on the device’s digital inputs can be capacitively coupled
through the device to show up as noise on the IOUT1 and IOUT
pins and, subsequently, into the following circuitry. This noise is
digital feedthrough.
2
Differential Nonlinearity
Multiplying Feedthrough Error
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of −1 LSB maximum
over the operating temperature range ensures monotonicity.
Multiplying feedthrough error is due to capacitive feedthrough
from the DAC reference input to the DAC IOUT1 line, when all
0s are loaded to the DAC.
Total Harmonic Distortion (THD)
Gain Error
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics, such as second
to fifth, are included.
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For this
DAC, ideal maximum output is VREF − 1 LSB. Gain error of the
DAC is adjustable to zero with external resistance.
2
2
2
2
V2 +V3 +V4 +V5
THD = 20 log
Output Leakage Current
V1
Output leakage current is current that flows in the DAC ladder
switches when the ladder is turned off. For the IOUT1 line, it can
be measured by loading all 0s to the DAC and measuring the
Digital Intermodulation Distortion
Second-order intermodulation (IMD) measurements are the
relative magnitudes of the fa and fb tones digitally generated by
the DAC and the second-order products at 2fa − fb and 2fb − fa.
I
OUT1 current. Minimum current flows in the IOUT2 line when
the DAC is loaded with all 1s.
Compliance Voltage Range
Output Capacitance
The maximum range of (output) terminal voltage for which
the device provides the specified characteristics.
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
Spurious-Free Dynamic Range (SFDR)
The amount of time it takes for the output to settle to a speci-
fied level for a full-scale input change. For this device, it is
specified with a 100 Ω resistor to ground. The settling time
The usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling
rate or fS/2). Narrow-band SFDR is a measure of SFDR over
an arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.
SYNC
specification includes the digital delay from the
edge to the full-scale output change.
rising
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either picoamps per second
or nanovolts per second, depending upon whether the glitch is
measured as a current or voltage signal.
Rev. E | Page 14 of 28
Data Sheet
AD5444/AD5446
GENERAL DESCRIPTION
CIRCUIT OPERATION
Unipolar Mode
DAC SECTION
The AD5444/AD5446 are 12-bit and 14-bit current output
DACs consisting of segmented (4 bits), inverting R– 2R ladder
configurations. A simplified diagram for the 12-bit AD5444
is shown in Figure 37.
Using a single op amp, the AD5444/AD5446 can easily be
configured to provide 2-quadrant multiplying operation or
a unipolar output voltage swing, as shown in Figure 38.
R
R
R
When an output amplifier is connected in unipolar mode, the
output voltage is given by
V
REF
2R
S1
2R
S2
2R
S3
2R
2R
R
S12
D
R
VOUT
VREF
FB
OUT
OUT
2n
I
I
1
2
where:
DAC DATA LATCHES
AND DRIVERS
D is the fractional representation of the digital word loaded to
the DAC:
Figure 37. Simplified Ladder
D = 0 to 4095 (12-bit AD5444)
D = 0 to 16383 (14-bit AD5446)
The feedback resistor (RFB) has a value of R. The value of R is
typically 9 kΩ (7 kΩ minimum, 11 kΩ maximum). If IOUT1 is
kept at the same potential as GND, a constant current flows in
each ladder leg, regardless of digital input code. Therefore, the
input resistance presented at VREF is always constant and nomi-
nally of value R. The DAC output (IOUT1) is code-dependent,
producing various resistances and capacitances. The external
amplifier choice should take into account the variation in
impedance generated by the DAC on the amplifiers inverting
input node.
n is the number of bits.
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
This DAC is designed to operate with either negative or positive
reference voltages. The VDD power pin is used by the internal
digital logic only to drive the on and off states of the DAC
switches. The DAC is also designed to accommodate ac refer-
ence input signals in the range of −10 V to +10 V. With a fixed
+10 V reference, the circuit shown in Figure 38 provides a
unipolar 0 V to −10 V output voltage swing. When VIN is an
ac signal, the circuit performs 2-quadrant multiplication.
Access is provided to the VREF, RFB, and both IOUT terminals of
the DAC, making the device extremely versatile and allowing it
to be configured in several different operating modes. For
example, the device provides unipolar output mode, 4-quadrant
multiplication in bipolar mode, and single-supply mode of
operation. Note that a matching switch is used in series with the
internal RFB. Power must be applied to VDD to achieve continuity
when measuring RFB.
Table 5 shows the relationship between digital code and
expected output voltage for unipolar operation.
Table 5. Unipolar Code
Digital Input
Analog Output (V)
−VREF (4095/4096)
−VREF (2048/4096) = −VREF/2
−VREF (1/4096)
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
−VREF (0/4096) = 0
V
V
DD
R2
C1
R
DD
FB
I
1
2
OUT
AD5444/
AD5446
V
V
A1
REF
REF
I
R1
OUT
V
= 0V TO –V
REF
OUT
SYNC SCLK SDIN
AGND
MICROCONTROLLER
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 38. Unipolar Operation
Rev. E | Page 15 of 28
AD5444/AD5446
Data Sheet
Bipolar Operation
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation.
In some applications, it may be necessary to generate a full
4-quadrant multiplying operation, or a bipolar output swing.
This can easily be accomplished by using another external
amplifier and some external resistors, as shown in Figure 39.
In this circuit, the second amplifier (A2) provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage results in a full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (VOUT = −VREF) to midscale
Table 6. Bipolar Code
Digital Input
Analog Output (V)
+VREF (2047/2048)
0
−VREF (2047/2048)
−VREF (0/2048)
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
Stability
In the current-to-voltage (I-to-V) configuration, the IOUT1of the
DAC and the inverting node of the op amp must be connected
as closely as possible, and proper PCB layout techniques must
be employed. Because every code change corresponds to a step
function, gain peaking can occur if the op amp has limited GBP
and excessive parasitic capacitance exists at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response that can cause ringing or instability in the closed-loop
applications circuit.
(VOUT − 0 V) to full scale (VOUT = +VREF
)
D
VOUT = V
×
−V
REF
REF
2n−1
where:
D is the fractional representation of the digital word loaded
to the DAC:
D = 0 to 4095 (12-bit AD5444)
D = 0 to 16383 (14-bit AD5446)
An optional compensation capacitor (C1) can be added in
parallel with RFB for stability, as shown in Figure 38 and
Figure 39. Too small a value for C1 can produce ringing at
the output, while too large a value can adversely affect the
settling time. C1 should be found empirically, but 1 pF to
2 pF is generally adequate for the compensation.
n is the resolution of the DAC.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
R3
20kΩ
V
V
DD
R2
R5
20kΩ
C1
R
DD
FB
R4
10kΩ
R1
I
1
OUT
AD5444/
AD5446
V
V
±10V
A1
REF
REF
A2
I
2
OUT
V
= –V
REF
TO +V
REF
SYNC SCLK SDIN
OUT
AGND
NOTES
MICROCONTROLLER
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC.
OUT
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 39. Bipolar Operation (4-Quadrant Multiplication)
Rev. E | Page 16 of 28
Data Sheet
AD5444/AD5446
V
= +5V
DD
SINGLE-SUPPLY APPLICATIONS
Voltage Switching Mode of Operation
ADR03
V
V
IN
OUT
GND
Figure 40 shows the AD5444/AD5446 DACs operating in the
voltage switching mode. The reference voltage (VIN) is applied
to the IOUT1 pin, IOUT2 is connected to AGND, and the output
voltage is available at the VREF terminal. In this configuration,
a positive reference voltage results in a positive output voltage,
making single-supply operation possible. The output from
the DAC is voltage at a constant impedance (the DAC ladder
resistance). Therefore, an op amp is necessary to buffer the
output voltage. The reference input no longer sees a constant
input impedance but rather one that varies with code, so the
voltage input should be driven from a low impedance source.
+5V
–5V
C1
V
R
FB
DD
I
I
1
2
OUT
–2.5V
V
REF
OUT
V
= 0V TO +2.5V
OUT
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 41. Positive Voltage Output with Minimum Components
ADDING GAIN
In applications in which the output voltage is required to be
greater than VIN, gain can be added with an additional external
amplifier, or it can be achieved in a single stage. It is important
to take into consideration the effect of the temperature coeffi-
cients of the DAC’s thin film resistors. Simply placing a resistor
in series with the RFB resistor can cause mismatches in the
temperature coefficients and result in larger gain temperature
coefficient errors. Instead, increase the gain of the circuit by
using the recommended configuration shown in Figure 42.
R1, R2, and R3 should all have similar temperature coefficients,
but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits where gains
of greater than 1 are required.
V
DD
R1
R2
R
V
FB
DD
V
OUT
V
V
I
1
IN
REF
OUT
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 40. Single-Supply Voltage Switching Mode Operation
It is important to note that, with this configuration, VIN is lim-
ited to low voltages, because the switches in the DAC ladder do
not have the same source-drain drive voltage. As a result, their
on resistance differs, which degrades the integral linearity of the
DAC. In addition, VIN must not go negative by more than 0.3 V,
or an internal diode turns on, exceeding the maximum ratings
of the device. In this type of application, the full range of the
multiplying capability of the DAC is lost.
V
DD
C1
V
R
FB
DD
I
I
1
2
OUT
R1
V
V
IN
V
REF
OUT
OUT
R3
R2
GND
R2 + R3
R2
GAIN =
Positive Output Voltage
R2R3
R2 + R3
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier because
of the resistor’s tolerance errors. To generate a negative reference,
the reference can be level-shifted by an op amp such that the
R1 =
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 42. Increasing Gain of Current Output DAC
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and RFB is used as the input
resistor, as shown in Figure 43, then the output voltage is
inversely proportional to the digital input fraction, D.
VOUT and GND pins of the reference become the virtual ground
and −2.5 V, respectively, as shown in Figure 41.
For D = 1 − 2−n, the output voltage is
V
OUT = −VIN/D = −VIN/(1 − 2−n)
Rev. E | Page 17 of 28
AD5444/AD5446
Data Sheet
V
V
DD
DD
The input bias current of an op amp also generates an offset
V
IN
at the voltage output as a result of the bias current flowing
in the feedback resistor, RFB. Most op amps have input bias
currents low enough to prevent any significant errors in
12-bit applications.
R
FB
V
I
1
REF
OUT
GND
Common-mode rejection of the op amp is important in voltage
switching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-bit, 10-bit, and 12-bit
resolutions.
V
OUT
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage switching
DAC circuit is determined largely by the output op amp. To
obtain minimum settling time in this configuration, it is impor-
tant to minimize capacitance at the VREF node (voltage output
node in this application) of the DAC. This is done by using low
input, capacitance buffer amplifiers and careful board design.
Figure 43. Current-Steering DAC Used as a Divider
or Programmable Gain Element
As D is reduced, the output voltage increases. For small values
of the digital fraction (D), it is important to ensure that the
amplifier does not saturate and the required accuracy is met.
For example, an 8-bit DAC driven with the binary code 0x10
(0001 0000), that is, 16 decimal, in the circuit of Figure 43,
should cause the output voltage to be 16 × VIN. However, if the
DAC has a linearity specification of 0.5 LSB, then D can, in
fact, have a weight in the range of 15.5/256 to 16.5/256, so the
possible output voltage is in the range 15.5 VIN to 16.5 VIN. This
is an error of 3%, even though the DAC itself has a maximum
error of 0.2%.
Most single-supply circuits include ground as part of the analog
signal range, which, in turn, requires an amplifier that can handle
rail-to-rail signals. A large range of single-supply amplifiers is
available from Analog Devices, Inc. (see Table 8 and Table 9 for
suitable suggestions).
REFERENCE SELECTION
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction (D) of the current into the VREF terminal
is routed to the IOUT1 terminal, the output voltage has to change,
as follows:
When selecting a reference for use with the AD5444/AD5446
current output DAC, pay attention to the output voltage tem-
perature coefficient specification. This parameter affects not
only the full-scale error but can also affect the linearity (INL
and DNL) performance. The reference temperature coefficient
should be consistent with the system accuracy specifications.
For example, an 8-bit system required to hold its overall speci-
fication to within 1 LSB over the temperature range 0°C to 50°C
dictates that the maximum system drift with temperature
should be less than 78 ppm/°C.
Output Error Voltage due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R equal to 10 kΩ, and a gain
(1/D) of 16, the error voltage is 1.6 mV.
A 12-bit system with the same temperature range to overall
specification within 2 LSBs requires a maximum drift of
10 ppm/°C. By choosing a precision reference with low output
temperature coefficient, this error source can be minimized.
Table 7 suggests some of the dc references available from
Analog Devices that are suitable for use with this range of
current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is
an amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code-dependent output resistance
of the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed upon the desired change
in output between the two codes and gives rise to a differential
linearity error, which, if large enough, can cause the DAC to be
nonmonotonic.
Rev. E | Page 18 of 28
Data Sheet
AD5444/AD5446
Table 7. Suitable Analog Devices Precision References
Initial Tolerance
Part No. Output Voltage (V) Accuracy (%)
Temperature Drift
Coefficient (ppm/°C)
ISS (mA) Output Noise (µV p-p)
Package
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
TSOT-23, SC70
SOIC-8
SOIC-8
TSOT-23
TSOT-23
ADR01
ADR01
ADR02
ADR02
ADR03
ADR03
ADR06
ADR06
ADR431 2.5
ADR435
ADR391 2.5
ADR395
10
10
5
0.05
0.05
0.06
0.06
0.10
0.10
0.10
0.10
0.04
0.04
0.16
0.10
3
9
3
9
3
9
3
9
3
3
9
9
1
1
1
1
20
20
10
10
6
5
2.5
2.5
3
1
1
6
1
1
0.8
0.8
0.12
0.12
10
10
3.5
8
5
8
3
5
5
Table 8. Suitable Analog Devices Precision Op Amps
Part No. Supply Voltage (V) VOS (Max) (µV) IB (Max) (nA) 0.1 Hz to 10 Hz Noise (µV p-p) Supply Current (µA) Package
OP97
2 to 20
2.5 to 15
2.7 to 5
1.8 to 6
2.7 to 6
25
60
5
50
5
0.1
2
0.05
0.001
0.1
0.5
0.4
1
2.3
0.5
600
500
975
50
SOIC-8
OP1177
AD8551
AD8603
AD8628
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
850
TSOT, SOIC-8
Table 9. Suitable Analog Devices High Speed Op Amps
BW @ ACL
(Typ) (MHz)
Slew Rate
(Typ) (V/µs)
Part No. Supply Voltage (V)
VOS (Max) (µV)
1500
1000
3000
10,000
IB (Max) (nA)
0.006
10500
750
Package
AD8065
AD8021
AD8038
AD9631
5 to 24
2.25 to 12
3 to 12
145
490
350
320
180
120
425
1300
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC70-5
SOIC-8
3 to 6
7000
Rev. E | Page 19 of 28
AD5444/AD5446
Data Sheet
SERIAL INTERFACE
The AD5444/AD5446 have an easy-to-use, 3-wire interface that
is compatible with SPI, QSPI, MICROWIRE, and DSP inter-
face standards. Data is written to the device in 16-bit words.
This 16-bit word consists of two control bits, 12 data bits or
14 data bits, as shown in Figure 44 and Figure 45. The AD5446
uses all 14 bits of DAC data while AD5444 uses 12 bits and
ignores the 2 LSBs.
SYNC
high
After the falling edge of the 16th SCLK pulse, bring
to transfer data from the input shift register to the DAC register.
Daisy-Chain Mode
Daisy-chain mode is the default power-on mode. To disable
the daisy-chain function, write 01 to the control word. In daisy-
chain mode, the internal gating on the SCLK is disabled. The
SCLK is continuously applied to the input shift register when
Control Bit C1 and Control Bit C0 allow the user to load and
update the new DAC code and to change the active clock edge.
By default, the shift register clocks data on the falling edge, but
this can be changed via the control bits. If changed, the DAC
core is inoperative until the next data frame. A power cycle
resets this back to the default condition. On-chip, power-on
reset circuitry ensures the device powers on with zero scale
loaded to the DAC register and the IOUT line.
SYNC
is low. If more than 16 clock pulses are applied, the data
ripples out of the shift register and appears on the SDO line.
This data is clocked out on the rising edge of the SCLK (this
is the default; use the control word to change the active edge)
and is valid for the next device on the falling edge (default).
By connecting this line to the SDIN input on the next device in
the chain, a multidevice interface is constructed. Sixteen clock
pulses are required for each device in the system. Therefore, the
total number of clock cycles must equal 16 N, where N is the
number of devices in the chain.
Table 10. DAC Control Bits
C1
C0
Function Implemented
Load and update (power-on default)
Disable SDO
0
0
0
1
SYNC
When the serial transfer to all devices is complete,
should be taken high. This prevents any further data from
being clocked into the shift register. A burst clock containing
the exact number of clock cycles can be used, and
taken high some time later. After the rising edge of
is automatically transferred from each device’s input register to
the addressed DAC.
1
0
No operation
1
1
Clock data to shift register on rising edge
SYNC
can be
SYNC
, data
SYNC
Function
SYNC
is an edge-triggered input that acts as a frame synchroni-
zation signal. Data can be transferred into the device only while
When the control bits = 10, the device is in no operation mode.
This can be useful in daisy-chain applications where the user
does not want to change the settings of a particular DAC in the
chain. Simply write 10 to the control bits for that DAC and the
following data bits are ignored.
SYNC
SYNC
is low. To start the serial data transfer,
should be
SYNC
taken low, observing the minimum
falling to the SCLK
falling edge setup time, t4. To minimize the power consumption
of the device, the interface powers up fully only when the device
SYNC
is being written to, that is, on the falling edge of
The SCLK and DIN input buffers are powered down on the
SYNC
.
rising edge of
.
DB15 (MSB)
DB0 (LSB)
C1 C0
DB9 DB8 DB7 DB6 DB5 DB4
DATA BITS
DB1 DB0
DB3 DB2
X
X
DB11 DB10
CONTROL BITS
Figure 44. AD5444 12-Bit Input Shift Register Contents
DB15 (MSB)
DB0 (LSB)
DB3 DB2 DB1 DB0
DB5 DB4
C1
C0
DB11 DB10 DB9 DB8 DB7 DB6
DATA BITS
DB13 DB12
CONTROL BITS
Figure 45. AD5446 14-Bit Input Shift Register Contents
Rev. E | Page 20 of 28
Data Sheet
AD5444/AD5446
Table 11. SPORT Control Register Setup
MICROPROCESSOR INTERFACING
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
Setting
Description
Microprocessor interfacing to the AD5444/AD5446 DAC is
through a serial bus that uses standard protocol compatible
with microcontrollers and DSP processors. The communica-
tions channel is a 3-wire interface consisting of a clock signal, a
data signal, and a synchronization signal. The AD5444/AD5446
requires a 16-bit word, with the default being data valid on the
falling edge of SCLK, but this can be changed using the control
bits in the data-word.
1
1
00
1
1
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
ITFS
1
SLEN
1111
ADSP-BF5xx to AD5444/AD5446 Interface
ADSP-21xx to AD5444/AD5446 Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the ADSP-BF5xx
and the AD5444/AD5446 DAC is shown in Figure 48. In this
configuration, data is transferred through the MOSI (master
The ADSP-21xx family of DSPs is easily interfaced to the
AD5444/AD5446 DAC without the need for extra glue logic.
Figure 46 is an example of an SPI interface between the DAC
and the ADSP-2191M. SCK of the DSP drives the serial clock
SYNC
line, SCLK.
SPIxSEL
is driven from one of the port lines, in this
SYNC
output/slave input) pin.
is driven by the SPI chip select
case
.
pin, which is a reconfigured programmable flag pin.
AD5444/
AD5446*
ADSP-2191M*
ADSP-BF5xx*
AD5444/AD5446*
SYNC
SDIN
SCLK
SPIxSEL
MOSI
SYNC
SDIN
SCLK
SPIxSEL
MOSI
SCK
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. ADSP-2191M SPI to AD5444/AD5446 Interface
Figure 48. ADSP-BF5xx to AD5444/AD5446 Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 47. In this interface example, SPORT0 is used to trans-
fer data to the DAC shift register. Transmission is initiated by
writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSP serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 49. When the SPORT is
enabled, initiate transmission by writing a word to the Tx register.
The data is clocked out on each rising edge of the DSPs serial
clock and clocked into the DAC input shift register on the
falling edge of its SCLK. The DAC output is updated by using
the transmit frame synchronization (TFS) line to provide a
SYNC
DAC output takes place on the rising edge of the
signal.
ADSP-2101/
ADSP-2191M*
AD5444/AD5446*
SYNC
signal.
TFS
SYNC
ADSP-BF5xx*
TFS
AD5444/AD5446*
DT
SDIN
SYNC
SCLK
SCLK
DT
SDIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 47. ADSP-2101/ADSP-2191M to
AD5444/AD5446 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 49. ADSP-BF5xx to AD5444/AD5446 Interface
Communication between two devices at a given clock speed
is possible when the following specifications are compatible:
frame sync delay and frame sync setup-and-hold, data delay
and data setup-and-hold, and SCLK width. The DAC inter-
SYNC
face expects a t4 (
falling edge to SCLK falling edge setup
time) of 13 ns minimum. See the ADSP-21xx User Manual for
information on clock and frame sync frequencies for the
SPORT register.
Table 11 shows the setup for the SPORT control register.
Rev. E | Page 21 of 28
AD5444/AD5446
Data Sheet
80C51/80L51 to AD5444/AD5446 Interface
MC68HC11*
AD5444/AD5446*
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 50. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, while RxD drives the serial data line,
SDIN. P1.1 is a bit-programmable pin on the serial port and
PC7
SCK
SYNC
SCLK
SDIN
MOSI
SYNC
is used to drive
. When data is to be transmitted to the
*ADDITIONAL PINS OMITTED FOR CLARITY
switch, P1.1 is taken low. The 80C51/80L51 transmits data only
in 8-bit bytes; therefore, only eight falling clock edges occur in
the transmit cycle. To load data correctly to the DAC, P1.1 is
left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data.
Figure 51. MC68HC11 to AD5444/AD5446 Interface
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
SYNC
the MC68HC11, and, with
low, the shift register clocks
data out on the rising edges of SCLK.
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge. As a result, no glue
logic is required between the DAC and microcontroller inter-
face. P1.1 is taken high following the completion of this cycle.
The 80C51/80L51 provides the LSB of its SBUF register as the
first bit in the data stream. The DAC input register requires its
data with the MSB as the first bit received. The transmit routine
should take this into account.
MICROWIRE to AD5444/AD5446 Interface
Figure 52 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC SCLK.
MICROWIRE*
AD5444/AD5446*
SK
SO
CS
SCLK
SDIN
SYNC
AD5444/AD5446*
SCLK
8051*
TxD
RxD
P1.1
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 52. MICROWIRE to AD5444/AD5446 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 50. 80C51/80L51 to AD5444/AD5446 Interface
PIC16C6x/7x to AD5444/AD5446 Interface
MC68HC11 Interface to AD5444/AD5446 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON); see the PIC16/17 Microcontroller User Manual.
Figure 51 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface, the MOSI
output drives the serial data line (SDIN) of the AD5444/AD5446.
SYNC
In this example, I/O port RA1 is used to provide a
signal and enable the serial port of the DAC. This micro-
controller transfers only eight bits of data during each serial
transfer operation; therefore, two consecutive write operations
are required. Figure 53 shows the connection diagram.
SYNC
The
signal is derived from a port line (PC7). When data
SYNC
PIC16C6x/7x*
AD5444/AD5446*
is being transmitted to the AD5444/AD5446, the
line is
SCK/RC3
SDI/RC4
RA1
SCLK
SDIN
SYNC
taken low (PC7). Data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
To load data to the DAC, PC7 is left low after the first eight bits
are transferred, and a second serial write operation is performed
to the DAC. PC7 is taken high at the end of this procedure.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 53. PIC16C6x/7x to AD5444/AD5446 Interface
Rev. E | Page 22 of 28
Data Sheet
AD5444/AD5446
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit boards on
which the AD5444/AD5446 are mounted should be designed
so the analog and digital sections are separated and confined to
certain areas of the board. If the DACs are in systems in which
multiple devices require a AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the devices.
A microstrip technique, by far the best, is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane, while signal
traces are placed on the solder side.
It is good practice to employ compact, minimum lead-length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close
to the device as possible.
The DAC should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the pack-
age as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR)
and effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on oppo-
site sides of the board should run at right angles to each other.
This reduces the effects of feedthrough throughout the board.
Rev. E | Page 23 of 28
AD5444/AD5446
Data Sheet
OVERVIEW OF AD54xx AND AD55xx CURRENT OUTPUT DEVICES
Table 12.
Part Number
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5405
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
Resolution (Bits)
Number of DACs
INL (LSB) Interface Package1
Features
8
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
0.25
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
0.25
1
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
RU-16, CP-20
RM-10
RU-20
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
12 MHz BW, 50 MHz serial
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial interface
10 MHz BW, 50 MHz serial
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 17 ns CS pulse width
10 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
12 MHz BW, 50 MHz serial
8
8
8
8
RU-10
UJ-8
RM-10
RU-20, CP-20
RU-16
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
RU-24
UJ-8
RM-10
RM-10
RU-24
0.5
1
1
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
CP-40
1
RU-20, CP-20
RU-24
1
1
0.5
1
2
1
RU-16
UJ-8, RM-8
RM-10
UJ-8, RM-8
RM-8
12 MHz BW, 50 MHz serial
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
4 MHz BW, 50 MHz serial clock
4 MHz BW, 20 ns WR pulse width
1
RU-28
1
1
RM-8
RU-38
2
2
RM-8
RU-28
Parallel
Serial
Parallel
2
2
RU-16
RU-38
1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. E | Page 24 of 28
Data Sheet
AD5444/AD5446
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 54. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Resolution (Bits) INL (LSB) Temperature Range Package Description Package Option Branding
AD5444YRM
12
12
12
12
12
12
14
14
14
14
14
0.5
0.5
0.5
0.5
0.5
0.5
2
2
2
2
2
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Evaluation Board
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
D27
D27
D27
D6X
D6X
D6X
D28
D28
D28
D7Z
D7Z
AD5444YRM-REEL
AD5444YRM-REEL7
AD5444YRMZ
AD5444YRMZ-REEL
AD5444YRMZ-REEL7
AD5446YRM
AD5446YRM-REEL
AD5446YRM-REEL7
AD5446YRMZ
AD5446YRMZ-RL7
EV-AD5443/46/53SDZ
1 Z = RoHS Compliant Part.
Rev. E | Page 25 of 28
AD5444/AD5446
NOTES
Data Sheet
Rev. E | Page 26 of 28
Data Sheet
NOTES
AD5444/AD5446
Rev. E | Page 27 of 28
AD5444/AD5446
NOTES
Data Sheet
©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04588-0-6/13(E)
Rev. E | Page 28 of 28
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