AD5445 [ADI]
8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface; 8位/ 10位/ 12位，高带宽，乘法DAC ，并行接口
| 型号： | AD5445 |
| 厂家： | 
ADI |
| 描述： | 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface |
| 文件： | 总24页 (文件大小：884K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-/10-/12-Bit, High Bandwidth,
Multiplying DACs with Parallel Interface
AD5424/AD5433/AD5445*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2.5 V to 5.5 V Supply Operation
Fast Parallel Interface (17 ns Write Cycle)
10 MHz Multiplying Bandwidth
V
V
REF
DD
R
FB
AD5424/
AD5433/
AD5445
R
I
1
OUT
ꢀ10 V Reference Input
8-/10-/12-BIT
R-2R DAC
I
2
OUT
Extended Temperature Range –40ꢁC to +125ꢁC
20-Lead TSSOP and Chip Scale (4 mm ꢂ 4 mm) Packages
8-, 10-, and 12-Bit Current Output DACs
Upgrades to AD7524/AD7533/AD7545
Pin Compatible 8-, 10-, and 12-Bit DACs in Chip Scale
Guaranteed Monotonic
POWER-ON
RESET
DAC REGISTER
INPUT LATCH
CS
R/W
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Readback Function
0.4 ꢃA Typical Power Consumption
DB7/DB9/DB11
DB0
GND
DATA
INPUTS
APPLICATIONS
Portable Battery-Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, Offset, and Voltage Trimming
GENERAL DESCRIPTION
The AD5424/AD5433/AD5445 are CMOS 8-, 10-, and 12-bit
current output digital-to-analog converters (DACs), respectively.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage output
when combined with an external I-to-V precision amplifier.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to battery-powered applications and many
other applications.
While these devices are upgrades of AD7524/AD7533/AD7545
in multiplying bandwidth performance, they have a latched
interface and cannot be used in transparent mode.
These DACs utilize data readback allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s and the DAC
outputs are at zero scale.
The AD5424 is available in small 20-lead LFCSP and 16-lead
TSSOP packages, while the AD5433/AD5445 DACs are avail-
able in small 20-lead LFCSP and TSSOP packages.
As a result of manufacture on a CMOS submicron process, they
offer excellent 4-quadrant multiplication characteristics, with
large signal multiplying bandwidths of up to 10 MHz.
*U.S. Patent No. 5,689,257
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD5424/AD5433/AD5445–SPECIFICATIONS1
(VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP1177,
AC performance with AD8038, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
AD5424
Resolution
8
Bits
Relative Accuracy
Differential Nonlinearity
AD5433
0.25 LSB
0.5
LSB
Guaranteed monotonic
Guaranteed monotonic
Resolution
10
Bits
Relative Accuracy
Differential Nonlinearity
AD5445
0.5
1
LSB
LSB
Resolution
12
1
Bits
LSB
Relative Accuracy
Differential Nonlinearity
Gain Error
–1/+2 LSB
10
Guaranteed monotonic
mV
ppm FSR/ЊC
nA
nA
Gain Error Temperature Coefficient2
Output Leakage Current2
5
10
20
Data = 0x0000, TA = 25ЊC, IOUT1
Data = 0x0000, IOUT
1
REFERENCE INPUT2
Reference Input Range
10
10
10
V
kΩ
kΩ
V
REF Input Resistance
8
8
12
12
Input resistance TC = –50 ppm/ЊC
Input resistance TC = –50 ppm/ЊC
RFB Resistance
Input Capacitance
Code 0
3
5
6
8
pF
pF
Code 4095
DIGITAL INPUTS/OUTPUT2
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIL
Input Capacitance
1.7
V
V
A
pF
0.6
1
10
4
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
0.4
0.4
V
V
ISINK = 200 µA
VDD – 1
ISOURCE = 200 µA
V
V
ISINK = 200 µA
ISOURCE = 200 µA
VDD – 0.5
DYNAMIC PERFORMANCE2
Reference Multiplying Bandwidth
Output Voltage Settling Time
AD5424
AD5433
AD5445
Digital Delay
10% to 90% Settling Time
Digital to Analog Glitch Impulse
Multiplying Feedthrough Error
10
MHz
VREF = 3.5 V; DAC loaded all 1s
VREF = 10 V, RLOAD = 100 Ω, CLOAD = 15 pF
Measured to 16 mV of full scale
Measured to 4 mV of full scale
Measured to 1 mV of full scale
Interface delay time
Rise and Fall time, VREF = 10 V, RLOAD = 100 Ω
1 LSB change around major carry, VREF = 0 V
DAC latch loaded with all 0s. VREF
Reference = 1 MHz
Reference = 10 MHz
30
35
80
20
15
2
60
70
120
40
30
ns
ns
ns
ns
ns
nV-s
= 3.5 V
70
48
dB
dB
–2–
REV. 0
AD5424/AD5433/AD5445
Parameter
Min
Typ
Max
Unit
Conditions
Output Capacitance
I
OUT2
22
10
12
25
1
25
12
17
30
pF
pF
pF
pF
All 0s loaded
All 1s loaded
All 0s loaded
All 1s loaded
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
VREF = 3.5 V pk-pk; all 1s loaded, f = 100 kHz
IOUT
1
Digital Feedthrough
nV-s
Total Harmonic Distortion
Digital THD
–81
dB
Clock = 10 MHz
50 kHz fOUT
Output Noise Spectral Density
SFDR Performance (Wide Band)
Clock = 10 MHz
500 kHz fOUT
65
25
dB
nV√Hz
@ 1 kHz
AD5445, 65k codes, VREF = 3.5 V
55
63
65
dB
dB
dB
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
50
60
62
dB
dB
dB
50 kHz fOUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz fOUT
AD5445, 65k codes, VREF = 3.5 V
73
80
87
dB
dB
dB
100 kHz fOUT
50 kHz fOUT
Clock = 25 MHz
500 kHz fOUT
100 kHz fOUT
70
75
80
dB
dB
dB
50 kHz fOUT
Intermodulation Distortion
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz
f1 = 40 kHz, f2 = 50 kHz
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz
f1 = 40 kHz, f2 = 50 kHz
AD5445, 65k codes, VREF = 3.5 V
65
72
dB
dB
51
65
dB
dB
POWER REQUIREMENTS
Power Supply Range
IDD
2.5
5.5
0.6
5
V
A
A
TA = 25ЊC, logic inputs = 0 V or VDD
Logic inputs = 0 V or VDD
0.4
NOTES
1Temperature range is as follows: Y version: –40ЊC to +125ЊC.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
AD5424/AD5433/AD5445
TIMING CHARACTERISTICS1, 2
(VREF = 5 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted.)
Parameter
VDD = 2.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
Unit
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
0
0
10
6
0
5
9
20
40
5
0
0
10
6
0
5
7
10
20
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
R/W to CS setup time
R/W to CS hold time
CS low time (write cycle)
Data setup time
Data hold time
R/W high to CS low
CS min high time
Data access time
ns max
ns typ
t9
Bus relinquish time
10
10
ns max
NOTES
1See Figure 1. Temperature range is as follows: Y version: –40ЊC to +125ЊC. Guaranteed by design and characterization, not subject to production test.
2All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measured with load
circuit in Figure 2.
Specifications subject to change without notice.
t2
t6
t2
t1
R/W
t7
t3
t4
DATA VALID
CS
t8
t9
t5
DATA
DATA VALID
Figure 1. Timing Diagram
–4–
REV. 0
AD5424/AD5433/AD5445
ABSOLUTE MAXIMUM RATINGS1
(TA = 25ЊC, unless otherwise noted.)
I
200ꢃA
OL
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VREF, RFB to GND . . . . . . . . . . . . . . . . . . . . . . –12 V to +12 V
IOUT1, IOUT2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Logic Inputs and Output2 . . . . . . . . . . . –0.3 V to VDD +0.3 V
Operating Temperature Range
TO
OUTPUT
PIN
V
+ V
2
OH (MIN)
OL (MAX)
C
50pF
L
I
200ꢃA
OH
Extended Industrial (Y Version) . . . . . . . . –40ЊC to +125ЊC
Storage Temperature Range . . . . . . . . . . . . . –65ЊC to +150ЊC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150ЊC
16-Lead TSSOP JA Thermal Impedance . . . . . . . . . 150ЊC/W
20-Lead TSSOP JA Thermal Impedance . . . . . . . . . 143ЊC/W
20-Lead LFCSP JA Thermal Impedance . . . . . . . . . 135ЊC/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300ЊC
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235ЊC
Figure 2. Load Circuit for Data Output Timing Specifications
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2 Overvoltages at DBx, CS, and R/W, will be clamped by internal diodes.
ORDERING GUIDE
Resolution INL
Temperature
Range
Package
Option
Model
(Bits)
(LSB)
Package Description
AD5424YRU
8
8
8
8
8
8
10
10
0.25
0.25
0.25
0.25
0.25
0.25
0.5
0.5
0.5
0.5
0.5
0.5
1
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
–40ЊC to +125ЊC
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
LFCSP (Chip Scale Package)
LFCSP (Chip Scale Package)
LFCSP (Chip Scale Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
LFCSP (Chip Scale Package)
LFCSP (Chip Scale Package)
LFCSP (Chip Scale Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
TSSOP (Thin Shrink Small Outline Package)
LFCSP (Chip Scale Package)
LFCSP (Chip Scale Package)
LFCSP (Chip Scale Package)
RU-16
RU-20
RU-20
CP-20
CP-20
CP-20
RU-20
RU-20
RU-20
CP-20
CP-20
CP-20
RU-20
RU-20
RU-20
CP-20
CP-20
CP-20
AD5424YRU-REEL
AD5424YRU-REEL7
AD5424YCP
AD5424YCP-REEL
AD5424YCP-REEL7
AD5433YRU
AD5433YRU-REEL
AD5433YRU-REEL7 10
AD5433YCP
AD5433YCP-REEL
AD5433YCP-REEL7 10
AD5445YRU
AD5445YRU-REEL
AD5445YRU-REEL7 12
AD5445YCP
AD5445YCP-REEL
AD5445YCP-REEL7 12
EVAL-AD5424EB
10
10
12
12
1
1
1
1
12
12
1
Evaluation Kit
EVAL-AD5433EB
EVAL-AD5445EB
Evaluation Kit
Evaluation Kit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5424/AD5433/AD5445 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
AD5424/AD5433/AD5445
PIN CONFIGURATIONS
TSSOP
LFCSP
I
1
2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT
R
FB
I
AD5424
V
REF
OUT
(Not to Scale)
GND
DB7
DB6
DB5
DB4
DB3
V
DD
GND
DB7
DB6
DB5
DB4
1
2
3
4
5
15 R/W
14 CS
13 NC
12 NC
11 NC
PIN 1
R/W
INDICATOR
CS
AD5424
TOP VIEW
DB0 (LSB)
DB1
DB2
NC = NO CONNECT
AD5424 PIN FUNCTION DESCRIPTIONS
Pin No.
TSSOP
LFCSP Mnemonic
Function
1
19
I
I
OUT1
OUT2
DAC Current Output.
2
20
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
1
GND
DB7–DB0
NC
Ground
4–11
2–9
10–13
14
Parallel Data Bits 7 to 0.
No Internal Connection.
12
13
CS
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input
latch or to read data from the DAC register. Rising edge of CS loads data.
15
R/W
Read/Write. When low, used in conjunction with CS to load parallel data. When high, use
with CS to readback contents of DAC register.
14
15
16
16
17
18
VDD
VREF
RFB
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
–6–
REV. 0
AD5424/AD5433/AD5445
PIN CONFIGURATIONS
TSSOP
LFCSP
I
1
2
1
2
20
19
18
17
16
OUT
R
FB
I
V
AD5433
OUT
REF
(Not to Scale)
GND
DB9
DB8
DB7
DB6
DB5
DB4
DB3
3
V
DD
GND
1
2
3
4
5
4
15 R/W
14 CS
13 NC
12 NC
11 DB0
R/W
PIN 1
DB9
DB8
DB7
DB6
INDICATOR
5
CS
AD5433
TOP VIEW
6
15 NC
7
14
NC
8
DB0 (LSB)
DB1
13
12
9
10
11 DB2
NC = NO CONNECT
NC = NO CONNECT
AD5433 PIN FUNCTION DESCRIPTIONS
Pin No.
TSSOP
LFCSP Mnemonic Function
1
19
IOUT
OUT2
GND
1
DAC Current Output.
2
20
I
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
Ground
3
1
4–13
14, 15
16
2–11
12, 13
14
DB9–DB0 Parallel Data Bits 9 to 0.
NC
Not Internally Connected.
CS
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input
latch or to read data from the DAC register. Rising edge of CS loads data.
17
15
R/W
Read/Write. When low, used in conjunction with CS to load parallel data. When high, use
with CS to readback contents of DAC register.
18
19
20
16
17
18
VDD
VREF
RFB
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
REV. 0
–7–
AD5424/AD5433/AD5445
PIN CONFIGURATIONS
TSSOP
LFCSP
I
1
2
1
2
20
19
18
17
16
15
14
OUT
R
FB
I
V
OUT
AD5445
REF
(Not to Scale)
GND
3
V
DD
GND
DB11
DB10
DB9
1
2
3
4
5
15 R/W
14 CS
13 DB0
12 DB1
11 DB2
PIN 1
DB11
DB10
DB9
DB8
DB7
DB6
DB5
4
R/W
INDICATOR
AD5445
TOP VIEW
5
CS
DB8
6
DB0 (LSB)
DB1
7
8
13 DB2
9
12
11
DB3
DB4
10
AD5445 PIN FUNCTION DESCRIPTIONS
Pin No.
TSSOP
LFCSP Mnemonic
Function
1
19
20
1
IOUT
1
DAC Current Output.
2
I
OUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
GND
Ground Pin.
4–15
16
2–13
14
DB11–DB0
CS
Parallel Data Bits 11 to 0.
Chip Select Input. Active low. Rising edge of CS loads data. Used in conjunction with R/W to
load parallel data to the input latch or to read data from the DAC register.
17
15
R/W
Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with
CS to readback contents of DAC register.
18
19
20
16
17
18
VDD
VREF
RFB
Positive Power Supply Input. These parts can be operated from a supply of +2.5 V to +5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
–8–
REV. 0
Typical Performance Characteristics–AD5424/AD5433/AD5445
0.20
0.15
0.10
0.05
0
1.0
0.5
T
V
V
= 25ꢁC
T
V
V
= 25ꢁC
T = 25ꢁC
A
A
A
0.8
0.4
= 10V
= 5V
= 10V
= 5V
V
= 10V
REF
REF
REF
V
= 5V
DD
DD
DD
0.6
0.3
0.4
0.2
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.05
–0.10
–0.15
–0.20
0
50
100
CODE
150
200
250
0
200
400 600
CODE
800
1000
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
TPC 2. INL vs. Code (10-Bit DAC)
TPC 1. INL vs. Code (8-Bit DAC)
TPC 3. INL vs. Code (12-Bit DAC)
0.5
0.20
1.0
T
V
V
= 25ꢁC
T
V
V
T
V
V
A
A
A
0.4
0.3
0.8
0.6
= 10V
= 5V
REF
0.15
0.10
0.05
0
DD
0.2
0.4
0.1
0.2
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.2
–0.4
–0.6
–0.8
–1.0
–0.05
–0.10
–0.15
–0.20
0
200
400
600
CODE
800
1000
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
250
0
200
50
150
CODE
100
TPC 6. DNL vs. Code (12-Bit DAC)
TPC 4. DNL vs. Code (8-Bit DAC)
TPC 5. DNL vs. Code (10-Bit DAC)
5
4
0.6
0.5
–0.40
T
V
V
= 25ꢁC
A
= 10V
= 5V
REF
DD
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
3
2
V
= 5V
DD
0.4
MAX INL
0.3
1
0.2
T
V
V
= 25ꢁC
0
A
= 10V
= 5V
0.1
0
REF
DD
–1
–2
–3
–4
–5
V
= 2.5V
DD
MIN INL
MIN DNL
–0.1
–0.2
–0.3
V
= 10V
REF
2
3
4
5
6
7
8
9
10
–60 –40 –20
0
20 40 60 80 100 120 140
2
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE
REFERENCE VOLTAGE
TEMPERATURE (ꢁC)
TPC 7. INL vs. Reference Voltage,
AD5445
TPC 8. DNL vs. Reference Voltage,
AD5445
TPC 9. Gain Error vs. Temperature
REV. 0
–9–
AD5424/AD5433/AD5445
0.5
0.4
2.0
4
3
T
V
V
= 25ꢁC
T
V
V
= 25ꢁC
A
A
MAX DNL
= 2.5V
= 3V
1.5
= 0V
REF
REF
= 3V AND 5V
DD
T
V
V
= 25ꢁC
0.3
DD
A
2
= 0V
= 3V
MAX INL
1.0
0.5
REF
GAIN ERROR
MAX INL
MAX DNL
0.2
DD
1
0.1
0
0
0
MIN DNL
–1
–2
–3
–4
–5
–0.1
–0.2
–0.3
–0.4
–0.5
OFFSET ERROR
–0.5
–1.0
–1.5
–2.0
MIN INL
MIN DNL
MIN INL
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
(V)
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
(V)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
(V)
V
V
V
BIAS
BIAS
BIAS
TPC 11. Linearity vs. VBIAS Voltage
Applied to IOUT2, AD5445
TPC 10. Linearity vs. VBIAS Voltage
Applied to IOUT2, AD5445
TPC 12. Gain and Offset Errors
vs. VBIAS Voltage Applied to IOUT
2
3
0.5
0.4
0.3
4
T
V
V
= 25ꢁC
A
MAX INL
T
V
V
= 25ꢁC
A
= 0V
= 5V
REF
DD
= 2.5V
= 5V
3
2
REF
2
1
DD
MAX DNL
GAIN ERROR
0.2
0.1
1
MAX DNL
0
0
0
MAX INL
MIN DNL
–1
–2
–3
–4
–5
–0.1
–0.2
–0.3
–0.4
–0.5
OFFSET ERROR
–1
–2
–3
MIN INL
T
V
V
= 25ꢁC
A
= 2.5V
REF
= 3V AND 5V
MIN DNL
1.5
DD
MIN INL
0.5
1.0
2.5
2.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
(V)
0.5
1.0
1.5
2.0
V
(V)
V
V
(V)
BIAS
BIAS
BIAS
TPC 14. Linearity vs. VBIAS Voltage
Applied to IOUT2, AD5445
TPC 15. Linearity vs. VBIAS Voltage
Applied to IOUT2, AD5445
TPC 13. Gain and Offset Errors
vs. VBIAS Voltage Applied to IOUT
2
0.50
8
1.6
1.4
1.2
T = 25ꢁC
A
T
= 25ꢁC
A
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
7
6
5
4
3
2
1
0
V
= 5V
DD
I
V
5V
OUT1 DD
ALL 0s
ALL 1s
1.0
0.8
0.6
0.4
0.2
0
V
= 5V
DD
V
= 2.5V
DD
ALL 1s
ALL 0s
I
V
3V
OUT1 DD
V
= 3V
DD
V
= 2.5V
DD
–40
–60
–20
0
20 40 60 80 100 120 140
C)
–40 –20
0
20 40 60 80 100 120
TEMPERATURE ( C)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
0
0.5 1.0
TEMPERATURE (
ꢁ
ꢁ
TPC 17. IOUT1 Leakage Cur-
rent vs. Temperature
TPC 18. Supply Current vs.
Temperature
TPC 16. Supply Current vs. Logic
Input Voltage (Driving DB0–DB11,
All Other Digital Inputs @ Supplies)
–10–
REV. 0
AD5424/AD5433/AD5445
14
12
10
8
6
0
–6
0.2
T
= 25ꢁC
ALL ON
DB11
DB10
DB9
A
T
= 25ꢁC
A
LOADING
ZS TO FS
LOADING ZS TO FS
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
0
–0.2
–0.4
V
= 5V
DD
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
6
V
= 3V
DD
T
V
V
= 25ꢁC
A
T
V
= 25ꢁC
4
A
= 5V
DD
= 5V
V
= 2.5V
DD
DD
= ꢀ3.5V
V
= ꢀ3.5V
INPUT
= 1.8pF
REF
–0.6
–0.8
REF
C
= 1.8pF
COMP
2
C
COMP
AD8038 AMPLIFIER
AD5445 DAC
AD8038 AMPLIFIER
AD5445 DAC
ALL OFF
0
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
TPC 19. Supply Current vs.
Update Rate
TPC 20. Reference Multiplying
Bandwidth vs. Frequency and
Code
TPC 21. Reference Multiplying
Bandwidth—All Ones Loaded
3
–1.68
0.045
T
V
= 25ꢁC
T
V
= 25ꢁC
T
V
= 25ꢁC
A
A
A
7FF TO 800H
= 5V
7FF TO 800H
= 5V
= 3.5V
= 5V
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
= 0V
REF
DD
REF
–1.69
–1.70
–1.71
–1.72
–1.73
–1.74
–1.75
–1.76
–1.77
AD8038 AMPLIFIER
C
AD5445
AD8038 AMPLIFIER
= 1.8pF
V
DD
= 1.8pF
C
COMP
COMP
V
DD
0
–3
–6
–9
V
= 3V
DD
V
= 3V
DD
800 TO 7FFH
800 TO 7FFH
V
= 5V
DD
V
= 3V
DD
V
= 3V
DD
V
V
V
V
V
=
=
=
=
=
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
2V, AD8038 C 1.47pF
C
2V, AD8038 C 1pF
0.15V, AD8038 C 1pF
0.15V, AD8038 C 1.47pF
REF
REF
REF
REF
REF
C
C
–0.005
–0.010
C
V
= 5V
DD
3.51V, AD8038 C 1.8pF
C
0
20 40 60 80 100 120 140 160 180 200
TIME (ns)
10k
100k
1M
10M
100M
0
20 40 60 80 100 120 140 160 180 200
TIME (ns)
FREQUENCY (Hz)
TPC 22. Reference Multiplying
Bandwidth vs. Frequency and
Compensation Capacitor
TPC 23. Midscale Transition,
VREF = 0 V
TPC 24. Midscale Transition,
VREF = 3.5 V
20
100
–60
T
V
= 25ꢁC
T
V
= 25ꢁC
T
V
V
= 25ꢁC
A
A
A
= 3V
= 3.5V
= 3V
DD
DD
REF
MCLK = 1MHz
0
–20
AMP = AD8038
AD8038 AMPLIFIER
AD5445
= 3.5 V p-p
REF
–65
–70
–75
–80
–85
–90
80
60
40
20
0
MCLK = 200kHz
MCLK = 0.5MHz
–40
–60
FULL SCALE
–80
ZERO SCALE
–100
–120
1
10
100
1k
10k 100k 1M 10M
1
10
100
1k
10k
100k
1M
0
20 40 60 80 100 120 140 160 180 200
fOUT (kHz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TPC 25. Power Supply
Rejection vs. Frequency
TPC 26. THD and Noise vs.
Frequency
TPC 27. Wideband SFDR vs.
fOUT Frequency
REV. 0
–11–
AD5424/AD5433/AD5445
90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
= 25ꢁC
T
V
= 25ꢁC
A
A
MCLK = 5MHz
80
= 5V
= 5V
DD
DD
MCLK = 10MHz
AMP = AD8038
AD5445
65k CODES
AMP = AD8038
AD5445
65k CODES
70
60
50
MCLK = 25MHz
40
30
20
T
V
= 25ꢁC
A
= 3.5V
REF
10
0
AD8038 AMPLIFIER
AD5445
0
2
4
6
8
10
12
0
100 200 300 400 500 600 700 800 900 1000
fOUT (kHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 29. Wideband SFDR,
fOUT = 100 kHz, Clock = 25 MHz
TPC 30. Wideband SFDR,
TPC 28. Wideband SFDR vs.
OUT Frequency
f
OUT = 500 kHz, Clock = 10 MHz
f
0
20
0
0
T = 25ꢁC
A
DD
AMP = AD8038
AD5445
65k CODES
T
V
= 25ꢁC
T
V
= 25ꢁC
A
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V = 3V
= 3V
= 5V
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
DD
AMP = AD8038
AD5445
65k CODES
AMP = AD8038
AD5445
65k CODES
–20
–40
–60
–80
–100
–120
50 60 70 80 90 100 110 120 130 140 150
FREQUENCY (MHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz)
250 300 350 400 450 500 550 600 650 700 750
FREQUENCY (kHz)
TPC 31. Wideband SFDR,
fOUT = 50 kHz, Clock = 10 MHz
TPC 32. Narrow-Band Spectral
Response, fOUT = 500 kHz,
Clock = 25 MHz
TPC 33. Narrow-Band SFDR,
fOUT = 100 kHz, MCLK = 25 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
0
T
V
= 25ꢁC
T
V
= 25ꢁC
T = 25ꢁC
A
DD
AMP = AD8038
AD5445
65k CODES
A
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= 3V
= 3V
V
= 5V
DD
DD
AMP = AD8038
AD5445
65k CODES
AMP = AD8038
AD5445
65k CODES
MCLK 10MHz
5V
V
DD
200 250 300 350 400 450 500 550 600 650 700
FREQUENCY (MHz)
70 75 80 85 90 95 100 105 110 115 120
FREQUENCY (MHz)
20 25 30 35 40 45 50 55 60 65 70
FREQUENCY (MHz)
TPC 34. Narrow-Band IMD,
fOUT = 400 kHz, 500 kHz,
Clock = 10 MHz
TPC 35. Narrow-Band IMD,
fOUT = 90 kHz, 100 kHz,
Clock = 10 MHz
TPC 36. Narrow-Band IMD,
fOUT = 40 kHz, 50 kHz,
Clock = 10 MHz
–12–
REV. 0
AD5424/AD5433/AD5445
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
= 25ꢁC
T = 25ꢁC
A
DD
AMP = AD8038
AD5445
65k CODES
A
= 5V
V
= 5V
DD
AMP = AD8038
AD5445
65k CODES
0
50 100 150 200 250 300 350 400
FREQUENCY (kHz)
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
TPC 37. Wideband IMD, fOUT
=
TPC 38. Wideband IMD, fOUT
=
90 kHz, 100 kHz, Clock = 25 MHz
60 kHz, 50 kHz, Clock = 10 MHz
REV. 0
–13–
AD5424/AD5433/AD5445
TERMINOLOGY
Digital Feedthrough
Relative Accuracy
When the device is not selected, high frequency logic activity on
the device digital inputs may be capacitively coupled through the
device to show up as noise on the IOUT pins and subsequently
into the following circuitry. This noise is digital feedthrough.
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for 0 and full scale and is normally expressed in LSBs
or as a percentage of full-scale reading.
Multiplying Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded to the DAC.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of –1 LSB max over
the operating temperature range ensures monotonicity.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms
sum of the harmonics of the DAC output to the fundamental
value is the THD. Usually only the lower order harmonics are
included, such as second to fifth.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is VREF – 1 LSB. Gain error of
the DACs is adjustable to 0 with external resistance.
V22 +V32 +V4 +V52
2
(
)
THD = 20log
V
1
Output Leakage Current
Digital Intermodulation Distortion
Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the IOUT1 terminal, it
can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s.
Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones generated digi-
tally by the DAC and the second-order products at 2fa – fb and
2fb – fa.
Spurious-Free Dynamic Range (SFDR)
Output Capacitance
It is the usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the mea-
sure of difference in amplitude between the fundamental and
the largest harmonically or nonharmonically related spur from
dc to full Nyquist bandwidth (half the DAC sampling rate, or
fS/2). Narrow band SFDR is a measure of SFDR over an arbi-
trary window size, in this case 50% of the fundamental. Digital
SFDR is a measure of the usable dynamic range of the DAC
when the signal is digitally generated sine wave.
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full scale input change. For these devices, it
is specified with a 100 Ω resistor to ground.
The settling time specification includes the digital delay from
CS rising edge to the full-scale output change.
Digital to Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal.
–14–
REV. 0
AD5424/AD5433/AD5445
DAC SECTION
CIRCUIT OPERATION
The AD5424, AD5433, and AD5445 are 8-, 10- and 12-bit
current output DACs consisting of a standard inverting R-2R
ladder configuration. A simplified diagram for the 8-bit AD5424
is shown in Figure 3. The matching feedback resistor RFB has a
value of R. The value of R is typically 10 kΩ (minimum 8 kΩ
and maximum 12 kΩ). If IOUT1 and IOUT2 are kept at the same
potential, a constant current flows in each ladder leg, regardless
of digital input code. Therefore, the input resistance presented
at VREF is always constant and nominally of resistance value R.
The DAC output (IOUT) is code-dependent, producing various
resistances and capacitances. External amplifier choice should
take into account the variation in impedance generated by the
DAC on the amplifiers inverting input node.
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing as shown in Figure 4.
V
DD
R2
C1
V
R
DD
FB
I
1
OUT
V
AD5424/
V
A1
REF
REFAD5433/AD5445
I
2
R1
OUT
V
=
OUT
0 TO –V
REF
GND
R/W CS
AGND
DATA
R
R
R
INPUTS
V
REF
NOTES
2R
S1
2R
S2
2R
S3
2R
S8
2R
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF – 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
R
R
A
FB
I
1
OUT
Figure 4. Unipolar Operation
I
2
OUT
DAC DATA LATCHES
AND DRIVERS
When an output amplifier is connected in unipolar mode, the
output voltage is given by
Figure 3. Simplified Ladder
D
VOUT = –VREF
×
2n
Access is provided to the VREF, RFB, IOUT1 and IOUT2 terminals
of the DAC, making the device extremely versatile and allowing it
to be configured in several different operating modes, for example,
to provide a unipolar output, 4-quadrant multiplication in bipo-
lar mode or in single-supply modes of operation. Note that a
matching switch is used in series with the internal RFB feedback
resistor. If users attempt to measure RFB, power must be applied
to VDD to achieve continuity.
where D is the fractional representation of the digital word loaded
to the DAC and n is the resolution of the DAC.
D = 0 to 255 (8-Bit AD5424)
= 0 to 1023 (10-Bit AD5433)
= 0 to 4095 (12-Bit AD5445)
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
PARALLEL INTERFACE
These DACs are designed to operate with either negative or
positive reference voltages. The VDD power pin is only used
by the internal digital logic to drive the DAC switches’ on
and off states.
Data is loaded to the AD5424/33/45 in the format of an 8-, 10-, or
12-bit parallel word. Control lines CS and R/W allow data to be
written to or read from the DAC register. A write event takes place
when CS and R/W are brought low, data available on the data
lines fills the shift register, and the rising edge of CS latches the
data and transfers the latched data-word to the DAC register.
The DAC latches are not transparent, thus a write sequence must
consist of a falling and rising edge on CS to ensure data is loaded
to the DAC register and its analog equivalent reflected on the
DAC output.
These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 4 will
give a unipolar 0 V to –10 V output voltage swing. When VIN is
an ac signal, the circuit performs 2-quadrant multiplication.
Table I shows the relationship between digital code and expected
output voltage for unipolar operation. (AD5424, 8-bit device).
A read event takes place when R/W is held high and CS is brought
low. Now data is loaded from the DAC register back to the input
register and out onto the data line where it can be read back to
the controller for verification or diagnostic purposes.
Table I. Unipolar Code Table
Digital Input
Analog Output (V)
1111 1111
1000 0000
0000 0001
0000 0000
–VREF (255/256)
–VREF (128/256) = –VREF/2
–VREF (1/256)
–VREF (0/256) = 0
REV. 0
–15–
AD5424/AD5433/AD5445
R3
10kꢄ
R2
V
DD
R5
20kꢄ
C1
R
V
FB
DD
R4
R1
10kꢄ
I
1
2
OUT
V
ꢀ10V
REF
A1
V
AD5424/
AD5433/AD5445
REF
I
OUT
A2
V
= –V
TO +V
OUT
REF REF
R/W CS
GND
AGND
DATA
INPUTS
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V = 0 V WITH CODE 10000000 LOADED TO DAC.
OUT
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
3. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED IF A1/A2 IS
A HIGH SPEED AMPLIFIER.
Figure 5. Bipolar Operation (4-Quadrant Multiplication)
Bipolar Operation
Stability
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing. This
can be easily accomplished by using another external amplifier and
some external resistors as shown in Figure 5. In this circuit, the
second amplifier A2 provides a gain of 2. Biasing the external
amplifier with an offset from the reference voltage results in full
4-quadrant multiplying operation. The transfer function of this
circuit shows that both negative and positive output voltages
are created as the input data (D) is incremented from code
zero (VOUT = –VREF) to midscale (VOUT = 0 V ) to full scale
(VOUT = +VREF).
In the I-to-V configuration, the IOUT of the DAC and the invert-
ing node of the op amp must be connected as close as possible,
and proper PCB layout techniques must be employed. Since
every code change corresponds to a step function, gain peaking
may occur if the op amp has limited GBP and there is excessive
parasitic capacitance at the inverting node. This parasitic capaci-
tance introduces a pole into the open-loop response, which can
cause ringing or instability in closed-loop applications.
An optional compensation capacitor, C1, can be added in parallel
with RFB for stability as shown in Figures 4 and 5. Too small a
value of C1 can produce ringing at the output, while too large
a value can adversely affect the settling time. C1 should be
found empirically but 1 pF to 2 pF is generally adequate
for compensation.
VOUT = VREF × D 2n−1 −VREF
(
)
where D is the fractional representation of the digital word loaded
to the DAC and n is the resolution of the DAC.
D = 0 to 255 (8-Bit AD5424)
= 0 to 1023 (10-Bit AD5433)
= 0 to 4095 (12-Bit AD5445)
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
Table II shows the relationship between digital code and the
expected output voltage for bipolar operation (AD5426, 8-bit
device).
Table II. Bipolar Code Table
Digital Input
Analog Output (V)
1111 1111
1000 0000
0000 0001
0000 0000
+VREF (127/128)
0
–VREF (127/128)
–VREF (128/128)
–16–
REV. 0
AD5424/AD5433/AD5445
V
SINGLE-SUPPLY APPLICATIONS
DD
R1
R2
Current Mode Operation
Figure 6 shows a typical circuit for operation with a single 2.5 V to
5 V supply. In the current mode circuit of Figure 6, IOUT2 and
hence IOUT1 is biased positive by the amount applied to VBIAS. In
this configuration, the output voltage is given by
R
V
FB
DD
V
I
1
A1
IN
V
OUT
OUT
V
DAC
REF
I
2
OUT
GND
VOUT = D × R RDAC × V
−VIN +V
(
)
(
)
{
}
FB
BIAS
BIAS
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
As D varies from 0 to 255 (AD5424), 1023 (AD5433), or
4095 (AD5445), the output voltage varies from VOUT = VBIAS
to VOUT = 2 VBIAS – VIN.
Figure 7. Single-Supply Voltage Switching Mode Operation
V
BIAS should be a low impedance source capable of sinking and
sourcing all possible variations in current at the IOUT2 terminal.
POSITIVE OUTPUT VOLTAGE
V
DD
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages. In order to achieve a positive
voltage output, an applied negative reference to the input of the
DAC is preferred over the output inversion through an inverting
amplifier because of the resistor tolerance errors. To generate a
negative reference, the reference can be level shifted by an op
amp such that the VOUT and GND pins of the reference become
the virtual ground and –2.5 V respectively, as shown in Figure 8.
C1
R
V
FB
DD
I
1
2
OUT
V
A1
DAC
GND
REF
I
OUT
V
OUT
V
IN
V
= 5V
DD
ADR03
V
BIAS
V
V
IN
OUT
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
+5V
C1
R
V
FB
DD
–2.5V
I
1
8-/10-/12-BIT DAC
OUT
Figure 6. Single-Supply Current Mode Operation
V
I
2
REF
OUT
V
=
OUT
0 TO +2.5V
1/2 AD8552
–5V
GND
Voltage Switching Mode of Operation
1/2 AD8552
Figure 7 shows these DACs operating in the voltage-switching
mode. The reference voltage, VIN, is applied to the IOUT1 pin;
IOUT2 is connected to AGND; and the output voltage is avail-
able at the VREF terminal. In this configuration, a positive
reference voltage results in a positive output voltage making
single-supply operation possible. The output from the DAC is
voltage at a constant impedance (the DAC ladder resistance),
thus an op amp is necessary to buffer the output voltage. The
reference input no longer sees a constant input impedance, but
one that varies with code. So, the voltage input should be driven
from a low impedance source.
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 8. Positive Voltage Output with Minimum
of Components
It is important to note that VIN is limited to low voltages be-
cause the switches in the DAC ladder no longer have the same
source-drain drive voltage. As a result, their on resistance dif-
fers, which degrades the linearity of the DAC. See TPCs 10–15.
Also, VIN must not go negative by more than 0.3 V or an inter-
nal diode will turn on, exceeding the max ratings of the device.
In this type of application, the full range of multiplying capabil-
ity of the DAC is lost.
REV. 0
–17–
AD5424/AD5433/AD5445
ADDING GAIN
resistor as shown in Figure 10, then the output voltage is inversely
proportional to the digital input fraction D. For D = 1 – 2n the
output voltage is
In applications where the output voltage is required to be greater
than VIN, gain can be added with an additional external amplifier or
it can also be achieved in a single stage. It is important to consider
the effect of temperature coefficients of the thin film resistors of
the DAC. Simply placing a resistor in series with the RFB resistor
will cause mismatches in the temperature coefficients resulting in
larger gain temperature coefficient errors. Instead, the circuit of
Figure 9 is a recommended method of increasing the gain of the
circuit. R1, R2, and R3 should all have similar temperature coef-
ficients, but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits where gains of
great than 1 are required.
VOUT = −VIN D = −VIN 1− 2−n
(
)
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
10H (00010000), i.e., 16 decimal, in the circuit of Figure 10
should cause the output voltage to be 16ϫ VIN. However, if the
DAC has a linearity specification of 0.5 LSB then D can in
fact have the weight anywhere in the range 15.5/256 to 16.5/256
so that the possible output voltage will be in the range 15.5 VIN to
16.5 VIN—an error of +3% even though the DAC itself has a
maximum error of 0.2%.
V
DD
C1
R
V
FB
DD
V
R1
DD
I
1
2
OUT
8-/10-/12-BIT DAC
V
IN
V
V
IN
OUT
V
I
REF
OUT
R3
R2
R
V
DD
GND
FB
GAIN = R2 + R3
R2
I
1
OUT
V
REF
I
2
OUT
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
R1 = R2R3
R2 + R3
GND
Figure 9. Increasing Gain of Current Output DAC
V
OUT
USING DACS AS A DIVIDER OR A PROGRAMMABLE
GAIN ELEMENT
NOTE
ADDITIONAL PINS OMITTED FOR CLARITY
Current steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and RFB is used as the input
Figure 10. Current Steering DAC Used as a Divider
or Programmable Gain Element
Table III. Suitable ADI Precision References Recommended for Use with AD5424/AD5433/AD5445 DACs
Part No.
Output Voltage
Initial Tolerance
Temperature Drift
0.1 Hz to 10 Hz Noise
Package
ADR01
ADR02
ADR03
ADR425
10 V
5 V
2.5 V
5 V
0.1%
0.1%
0.2%
0.04%
3 ppm/°C
3 ppm/°C
3 ppm/°C
3 ppm/°C
20 V p-p
10 V p-p
10 V p-p
3.4 V p-p
SC70, TSOT, SOIC
SC70, TSOT, SOIC
SC70, TSOT, SOIC
MSOP, SOIC
Table IV. Some Precision ADI Op Amps Suitable for Use with AD5424/AD5433/AD5445 DACs
Part No.
Max Supply Voltage (V)
VOS (max) (ꢃV)
IB (max) (nA)
GBP (MHz)
Slew Rate (V/ꢃs)
OP97
OP1177
AD8551
20
18
6
25
60
5
0.1
2
0.05
0.9
1.3
1.5
0.2
0.7
0.4
Table V. Some High Speed ADI Op Amps Suitable for Use with AD5424/AD5433/AD5445 DACs
Max Supply Voltage
(V)
BW @ ACL
(MHz)
Slew Rate
(V/ꢃs)
VOS (max)
(ꢃV)
IB (max)
(nA)
Part No.
AD8065
AD8021
AD8038
AD9631
12
12
5
145
200
350
320
180
100
425
1300
1500
1000
3000
10000
0.01
1000
0.75
7000
5
–18–
REV. 0
AD5424/AD5433/AD5445
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Since only a fraction D of the current into the VREF terminal is
routed to the IOUT1 terminal, the output voltage has to change
as follows:
rail-to-rail signals; there is a large range of single-supply amplifiers
available from Analog Devices.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5424/AD5433/AD5445 is mounted should be designed so
that the analog and digital sections are separated, and confined
to certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
Output Error Voltage Due to DAC Leakage = (Leakage ϫ R)/D
where R is the DAC resistance at the VREF terminal. For a DAC
leakage current of 10 nA, R = 10 kΩ and a gain (i.e., 1/D) of 16
the error voltage is 1.6 mV.
REFERENCE SELECTION
When selecting a reference for use with the AD5424 series of
current output DACs, pay attention to the references output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature coeffi-
cient should be consistent with the system accuracy specifications.
For example, an 8-bit system required to hold its overall specifi-
cation to within 1 LSB over the temperature range 0ЊC to 50ЊC
dictates that the maximum system drift with temperature should
be less than 78 ppm/ЊC. A 12-bit system with the same tempera-
ture range to overall specification within 2 LSBs requires a
maximum drift of 10 ppm/ЊC. By choosing a precision reference
with low output temperature coefficient this error source can be
minimized. Table III suggests some references available from
Analog Devices that are suitable for use with this range of cur-
rent output DACs.
These DACs should have ample supply bypassing of 10 F in
parallel with 0.1 F on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 F capaci-
tor should have low effective series resistance (ESR) and effective
series inductance (ESI), like the common ceramic types that
provide a low impedance path to ground at high frequencies, to
handle transient currents due to internal logic switching. Low
ESR 1 F to 10 F tantalum or electrolytic capacitors should
also be applied at the supplies to minimize transient disturbance
and filter out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the board,
and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micros-
trip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane, while signal traces are
placed on the solder side.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
The input offset voltage of an op amp is multiplied by the vari-
able gain (due to the code dependent output resistance of the
DAC) of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity error,
which if large enough, could cause the DAC to be nonmonotonic.
In general, the input offset voltage should be <1/4 LSB to ensure
monotonic behavior when stepping through codes.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize on high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
EVALUATION BOARD FOR THE AD5424/AD5433/AD5445
The board consists of a 12-bit AD5445 and a current to voltage
amplifier AD8065. Included on the evaluation board is a 10 V
reference ADR01. An external reference may also be applied via
an SMB input.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor RFB. Most op amps have input bias currents
low enough to prevent any significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in voltage
switching circuits since it produces a code dependent error at the
voltage output of the circuit. Most op amps have adequate common
mode rejection for use at 8-, 10-, and 12-bit resolution.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows
the user to write a code to the device.
Provided the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage switching
DAC circuit is determined largely by the output op amp. To
obtain minimum settling time in this configuration, it is important
to minimize capacitance at the VREF node (voltage output node
in this application) of the DAC. This is done by using low
inputs capacitance buffer amplifiers and careful board design.
OPERATING THE EVALUATION BOARD
Power Supplies
The board requires 12 V, and +5 V supplies. The +12 V VDD
and VSS are used to power the output amplifier, while the +5 V
is used to power the DAC (VDD1) and transceivers (VCC).
Both supplies are decoupled to their respective ground plane
with 10 F tantalum and 0.1 F ceramic capacitors.
Link1 (LK1) is provided to allow selection between the on-board
reference (ADR01) or an external reference applied through J2.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can handle
REV. 0
–19–
AD5424/AD5433/AD5445
Figure 11. Evaluation Board Schematic
–20–
REV. 0
AD5424/AD5433/AD5445
P1
C1
R2
R4
C12
DB11
DB9
DB7
DB5
DB3
DB1
U3
DB10
DB8
DB6
DB4
DB2
DB0
U1
J1
OUTPUT
U5
C2
TP1
C7
R5
R1
C6
C5
C4
C3
C8
U2
LK1
CS
RW
EXT
VREF
U4
J4
J2
J3
R3
C18
C14
C16
CS
R/W
C19
C17
C13
C15
P2
C20
EVAL-AD5424/
AD5433/AD5445EB
Figure 12. Silkscreen—Component Side View
REV. 0
–21–
AD5424/AD5433/AD5445
Table VI. Bill of Materials for AD5424/AD5433/AD5445 Evaluation Board
Name
Part Description
Value
Tolerance
PCB Decal
Stock Code
C1, C2, C4,
C6, C8
C10, C12, C13,
C15
X7R Ceramic Capacitor
X7R Ceramic Capacitor
0.1 F
0.1 F
10%
10%
0603
0603
FEC 499-675
FEC 499-675
C3, C5, C9,
C11, C14
C17, C19
Tantalum Capacitor – Taj Series
X7R Ceramic Capacitor
10 F 20 V 10%
0.1 F 10%
10 F 10 V 10%
CAP\TAJ_B
0603
CAP\TAJ_A
0603
TESTPOINT
TESTPOINT
SMB
LINK-3P-
36WAY
FEC 197-427
FEC 499-675
FEC 197-130
C16, C18, C20 Tantalum Capacitor – Taj Series
C7
CS
DB0–DB11
J1–J4
LK1
P1
P2
R1
X7R Ceramic Capacitor
TESTPOINT
Red Testpoint
4.7 pF
10%
FEC 240-345 (Pack)
FEC 240-345 (Pack)
FEC 310-682
FEC 511-717 and 150-411
FEC 147-753
SMB Socket
3-Pin Header (3 ϫ 1)
36-Pin Centronics Connector
6-Pin Terminal Block
0.063 W Resistor
CON\POWER6 FEC 151-792
0603
Not Inserted
R2, R3, R4, R5 0.063 W Resistor
RW, TP1, TP2 Red Testpoint
10 kΩ
1%
0603
FEC 911-355
FEC 240-345 (Pack)
AD5445BRU
ADR01AR
AD8065AR
TESTPOINT
TSSOP20
SO8NB
U1
AD5445
ADR425/ADR01/ADR02/ADR03
AD8065
U2*
U3*
SO8NB
U4
U5
74ABT543
74ABT543
Rubber Stick-on Feet
TSSOP24
TSSOP24
Fairchild 74ABT543CMTC
Fairchild 74ABT543CMTC
FEC 148-922
Each Corner
*See section on Amplifier and Reference Selection
FEC - Farnell Electronic Components, Units 4 and 5 Gofton Court, Jamestown Road, Finglas, Dublin 11, Ireland. Tel. Int +353 (0)1 8309277
www.farnell.com
–22–
REV. 0
AD5424/AD5433/AD5445
Overview of AD54xx Devices
tS max Interface Package
Part No.
Resolution
No. DACs INL
Features
AD5403*
8
2
0.25 60 ns
Parallel
CP-40
10 MHz Bandwidth,
10 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
AD5410*
AD5413*
AD5424
AD5425
8
8
8
8
1
2
1
1
0.25 100 ns Serial
0.25 100 ns Serial
RU-16
RU-24
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
0.25 60 ns
Parallel
RU-16, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
0.25 100 ns Serial
0.25 100 ns Serial
RM-10
Byte Load, 10 MHz Bandwidth,
50 MHz Serial
AD5426
AD5428
8
8
1
2
RM-10
RU-20
10 MHz Bandwidth, 50 MHz Serial
0.25 60 ns
Parallel
10 MHz Bandwidth,
17 ns CS Pulse Width
AD5429
AD5450
AD5404*
8
2
1
2
0.25 100 ns Serial
0.25 100 ns Serial
RU-10
RJ-8
10 MHz Bandwidth, 50 MHz Serial
10 MHz Bandwidth, 50 MHz Serial
8
10
0.5
70 ns
Parallel
CP-40
10 MHz Bandwidth,
17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
AD5411*
AD5414*
10
10
1
2
0.5
0.5
110 ns Serial
110 ns Serial
110 ns Serial
RU-16
RU-24
RM-10
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5432
AD5433
10
10
1
1
0.5
0.5
10 MHz Bandwidth, 50 MHz Serial
70 ns
Parallel
RU-20, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5439
AD5440
10
10
2
2
0.5
0.5
110 ns Serial
70 ns Parallel
RU-16
RU-24
10 MHz Bandwidth, 50 MHz Serial
10 MHz Bandwidth,
17 ns CS Pulse Width
AD5451
AD5405
10
12
1
2
0.25 110 ns Serial
RJ-8
10 MHz Bandwidth, 50 MHz Serial
1
120 ns Parallel
CP-40
10 MHz Bandwidth,
17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
AD5412*
AD5415
12
12
1
2
1
1
160 ns Serial
160 ns Serial
RU-16
RU-24
RM-10
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5443
AD5445
12
12
1
1
1
1
160 ns Serial
10 MHz Bandwidth, 50 MHz Serial
120 ns Parallel
RU-20, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5447
AD5449
12
12
2
2
1
1
120 ns Parallel
160 ns Serial
RU-24
RU-16
10 MHz Bandwidth,
17 ns CS Pulse Width
10 MHz Bandwidth,
17 ns CS Pulse Width
AD5452
AD5453
12
14
1
1
0.5
2
160 ns Serial
180 ns Serial
RJ-8, RM-8
RJ-8, RM-8
10 MHz Bandwidth, 50 MHz Serial
10 MHz Bandwidth, 50 MHz Serial
*Future parts, contact factory for availability
REV. 0
–23–
AD5424/AD5433/AD5445
OUTLINE DIMENSIONS
16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Dimensions shown in millimeters
5.10
5.00
4.90
6.60
6.50
6.40
16
9
8
20
11
10
4.50
4.40
4.30
6.40
BSC
4.50
4.40
4.30
1
6.40 BSC
1
PIN 1
1.20
MAX
PIN 1
0.65
BSC
0.15
0.05
0.20
0.09
1.20
0.75
0.60
0.45
MAX
0.15
0.05
0.20
0.09
8ꢁ
0ꢁ
0.30
0.19
0.65
BSC
0.75
0.60
0.45
SEATING
PLANE
8ꢁ
0ꢁ
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
COMPLIANT TO JEDEC STANDARDS MO-153AC
20-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-20)
Dimensions shown in millimeters
0.60
MAX
4.0
BSC SQ
0.60
MAX
16
15
20
1
5
PIN 1
2.25
2.10 SQ
1.95
INDICATOR
TOP
BOTTOM
VIEW
3.75
VIEW
BSC SQ
11
10
0.75
0.55
0.35
6
0.25 MIN
0.80 MAX
0.65 NOM
0.30
0.23
0.18
12ꢁ MAX
1.00
0.90
0.80
0.05
0.02
0.00
0.20
REF
SEATING
PLANE
COPLANARITY
0.08
0.50
BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
–24–
REV. 0
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