AD5541A_技术文档

2.7 V to 5.5 V, Serial-Input, Voltage-Output,

16-/12-Bit nanoDACs in LFCSP

Preliminary Technical Data

AD5541A/AD5542A/AD5512A

range of −40°C to 105°C.

FEATURES

Low power, 1 LSB INL nanoDACs

AD5541A: 16 bits

FUNCTIONAL BLOCK DIAGRAMS

AD5542A: 16 bits

AD5512A: 12 bits

2.7 V to 5.5 V single-supply operation

Low glitch: 0.5 nV-s

Unbuffered voltage output capable of driving 60 kΩ loads

directly

V_LOGICpin provides 1.8 V digital interface capability

Hardware CLR and LDAC functions

50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface

standards

Power-on reset clears DAC output to zeroscale and midscale

Schmitt trigger inputs

Figure 1. AD5541A

Available in 3 mm × 3 mm 16-LFCSP, 10-LFCSP, and 8-LFCSP

Also available in10-MSOP and 16-TSSOP

APPLICATIONS

Automatic test equipment

Precision Source-measure Instruments

Data Acquisition Systems

Medical Instrumentation

Aerospace Instrumentation

Communications Infrastructure equipment

Industrial Control

Figure 2. AD5541A-1

GENERAL DESCRIPTION

The AD5541A/AD5542A/AD5512A¹are single, 16-/16-/12-bit,

serial input, unbuffered voltage output digital-to-analog conver-

ters (DACs) that operate from a single 2.7 V to 5.5 V supply.

The AD5541A/AD5542A/AD5512A utilize a versatile 3-wire

interface that is compatible with a 50 MHz SPI, QSPI™,

MICROWIRE™, and DSP interface standards.

These DACs provide 16-/12-bit performance without any adjust-

ments. The DAC output is unbuffered, which reduces power

consumption and offset errors contributed to by an output buffer.

The AD5542A/AD5512A can be operated in bipolar mode, which

generates a

V_REFoutput swing. The AD5542A/AD5512A also

includes Kelvin sense connections for the reference and analog

ground pins to reduce layout sensitivity.

Figure 3. AD5542A

The AD5541A is available in 10-lead 3 mm × 3 mm LFCSP and

10-lead MSSOP. The AD5541A-1 is available in 8-lead 3 mm ×

3 mm LFCSP. The AD5542A/AD5512A are available in 16-lead

3 mm × 3 mm LFCSP and the AD5542A is also available in

16-lead TSSOP. The AD5542A-1 is available in 10-lead LFCSP.

The AD5541A and AD5542A are specified over a temperature

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5541A/AD5542A/AD5512A

Preliminary Technical Data

Figure 4.

¹All references to the AD5541A/AD5542A/AD5512A incorporate all models (see Ordering Guide) including the AD5541A-1/AD5542A-1 unless specified.

Rev. PrA| Page 2 of 24

Preliminary Technical Data

AD5541A/AD5542A/AD5512AA

TABLE OF CONTENTS

Features...............................................................................................1

Bipolar Output Operation .........................................................14

Output Amplifier Selection .......................................................14

Force Sense Amplifier Selection ...............................................14

Reference and Ground ...............................................................14

Power-On Reset...........................................................................15

Power Supply and Reference Bypassing...................................15

Microprocessor Interfacing ...........................................................16

AD5541/AD5542 to ADSP-2101/ADSP-2103 Interface........16

AD5541/AD5542 to 68HC11/68L11 Interface .......................16

AD5541/AD5542 to MICROWIRE Interface.........................16

AD5541/AD5542 to 80C51/80L51 Interface...........................16

Applications Information...............................................................17

Optocoupler Interface ................................................................17

Decoding Multiple AD5541/AD5542s.....................................17

Outline Dimensions........................................................................18

Ordering Guide ...........................................................................21

Applications .......................................................................................1

General Description..........................................................................1

Functional Block Diagrams .............................................................1

Revision History................................................................................3

Specifications .....................................................................................4

Timing Characteristics .................................................................5

Absolute Maximum Ratings ............................................................6

ESD Caution ..................................................................................6

Pin Configurations and Function Descriptions............................7

Typical Performance Characteristics..............................................9

Terminology.....................................................................................12

Theory of Operation.......................................................................13

Digital-to-Analog Section..........................................................13

Serial Interface.............................................................................13

Unipolar Output Operation.......................................................13

REVISION HISTORY

Rev. PrA | Page 3 of 24

AD5541A/AD5542A/AD5512A

SPECIFICATIONS

Preliminary Technical Data

V_DD= 2.7 V to 5.5V, V_REF= 2.5 V, AGND = DGND = 0 V. −40°C < T_A< +105°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Condition

STATIC PERFORMANCE

AD5541A/AD5542A

Resolution

16

Bits

LSB

Relative Accuracy (INL)

±0.5

±1.0

±2.0

±4.0

±1.0

±1.5

L, C grades

B, J grades

A grade

Guaranteed monotonic

J grade

Differential Nonlinearity (DNL)

AD5512A

Resolution

12

Bits

Relative Accuracy (INL)

Differential Nonlinearity (DNL)

Gain Error

±1.0

±5

LSB

ppm/°C

LSB

−1.5

T_A= 25°C

±±

Gain Error Temperature Coefficient

Zero Code Error

±0.1

0.3

±1

±2

Zero Code Temperature Coefficient

AD5542A/AD5512A

±0.05

ppm/°C

Bipolar Resistor Matching

1.000

±0.0015

±1

Ω/Ω

%

LSB

R_FB/R_INV, typically R_FB= R_INV= 28 kΩ

Ratio error

T_A= 25°C

TBD

±5

Bipolar Zero Offset Error

±±

LSB

Bipolar Zero Temperature Coefficient

OUTPUT CHARACTERISTICS

±0.2

ppm/°C

Output Voltage Range

0

V_REF− 1 LSB

V

Unipolar operation

−V_REF

+V_REF− 1 LSB

V

μs

V/μs

nV-sec

kΩ

AD5542 bipolar operation

To 1/2 LSB of FS, C_L= 10 pF

C_L= 10 pF, measured from 0% to 63%

1 LSB change around the major carry

All 1s loaded to DAC, V_REF= 2.5 V

Tolerance typically 20%

Output Voltage Settling Time

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Feedthrough

1

25

0.5

0.2

6.25

DAC Output Impedance

Power Supply Rejection Ratio

DAC REFERENCE INPUT

Reference Input Range

Reference Input Resistance¹

±1.0

V_DD

LSB

∆V_DD± 10%

2.0

9

±.5

V

kΩ

Unipolar operation

AD5542, bipolar operation

LOGIC INPUTS

Input Current

±1

0.8

μA

V

pF

V

Input Low Voltage, V_INL

Input High Voltage, V_INH

Input Capacitance²

Hysteresis Voltage²

REFERENCE

V_DD= 2.± V to 5.5 V

V_DD= 4.5 V to 5.5 V

V_DD= 2.± V to 3.6 V

2.0

1.8

10

0.15

Reference −3 dB Bandwidth

Reference Feedthrough

THD

Signal-to-Noise Ratio

Reference Input Capacitance

1.3

1

TBD

92

±5

120

MHz

mV p-p

dB

pF

All 1s loaded

All 0s loaded, V_REF= 1 V p-p at 100 kHz

Code 0x0000

Code 0xFFFF

pF

Rev. PrA | Page 4 of 24

Preliminary Technical Data

AD5541A/AD5542A/AD5512AA

Parameter

Min

Typ

Max

Unit

Test Condition

POWER REQUIREMENTS

V_DD

I_DD

V_LOGIC

2.±

1.8

5.5

TBD

5.5

V

µA

V

200

I_LOGIC

200

1.5

TBD

µA

mW

Power Dissipation

¹Reference input resistance is code-dependent, minimum at 0x8555.

²Guaranteed by design, not subject to production test.

TIMING CHARACTERISTICS

V_LOGIC= 1.8 V to 5.5 V V, V_DD= 5V, V_REF= 2.5 V, V_INH= 90% of V_LOGIC, V_INL= 10% of V_LOGIC, AGND = DGND = 0 V; −40°C < T_A< +105°C,

unless otherwise noted.

Table 2.

Parameter^{1, 2}

Limit

50

20

10

5

Unit

Description

f_SCLK

t₁

t₂

MHz max

ns min

SCLK cycle frequency

SCLK cycle time

SCLK high time

t₃

SCLK low time

t₄

CS low to SCLK high setup

CS high to SCLK high setup

SCLK high to CS low hold time

SCLK high to CS high hold time

Data setup time

t₅

±

t₆

15

10

±

t_±

t₈

t₉

5

Data hold time (V_INH= 90% of V_DD, V_INL= 10% of V_DD)

Data hold time (V_INH= 3V, V_INL= 0 V)

LDAC pulsewidth

t₉

5

t₁₀

t₁₁

t₁₂

t₁₃

15

CS high to LDAC low setup

CS high time between active periods

CLR pulsewidth

¹Guaranteed by design and characterization. Not production tested

²All input signals are specified with t_R= t_F= 1 ns/V and timed from a voltage level of (V_INL+ V_INH)/2.

Figure 5. Timing Diagram

Rev. PrA | Page 5 of 24

AD5541A/AD5542A/AD5512A

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3.

Parameter

Rating

V_DDto AGND

−0.3 V to +6 V

Digital Input Voltage to DGND

V_OUTto AGND

AGND, AGNDF, AGNDS to DGND

−0.3 V to V_DD+ 0.3 V

−0.3 V to +0.3 V

Input Current to Any Pin Except Supplies ±10 mA

Operating Temperature Range

ESD CAUTION

Industrial (A, B, C Versions)

Commercial (J, L Versions)

Storage Temperature Range

Maximum Junction Temperature (T_Jmax)

Package Power Dissipation

Thermal Impedance, θ_JA

SOIC (R-8)

−40°C to +85°C

0°C to ±0°C

−65°C to +150°C

150°C

(T_Jmax − T_A)/θ_JA

149.5°C/W

104.5°C/W

SOIC (R-14)

Lead Temperature, Soldering

Peak Temperature¹

260°C

¹As per JEDEC Standard 20.

Rev. PrA | Page 6 of 24

Preliminary Technical Data

AD5541A/AD5542A/AD5512AA

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

CS

1

2

3

4

8

7

6

5

GND

VDD

VOUT

CLR

VDD

VOUT

AGND

REF

1

2

3

4

5

10 VLOGIC

AD5541A-1

TO P VIEW

(Not to Scale)

9

8

7

6

DGND

LDAC

DIN

AD5541A

TO P VIEW

(Not to Scale)

SCLK

DIN

CS

SCLK

NC = NO CO NNECT

Figure 6. AD5541A-1 8-Lead LFCSP Pin Configuration

Figure 8. AD5541A 10-Lead LFCSP Pin Configuration

VDD

VOUT

AGND

REF

1

2

3

4

5

10 VLOGIC

9

8

7

6

DGND

LDAC

DIN

AD5541A

V

1

2

3

4

8

7

6

5

V

DD

O UT

TOP VIEW

(Not to Scale)

AD5541A

AG ND

REF

CS

DG ND

DIN

TO P VIEW

(Not to Scale)

CS

SCLK

NC = NO CONNECT

Figure 9. AD5541A 10-Lead MSOP Pin Configuration

Figure 7. AD5541A 8-Lead SOIC Pin Configuration

Table 4. AD5541A Pin Function Descriptions

Pin No.

8-Lead

LFCSP

8-Lead 10-Lead 10-Lead

SOIC

LFCSP

MSOP

Mnemonic Description

6

1

2

3

2

3

4

2

3

4

VOUT

AGND

REF

Analog Output Voltage from the DAC.

Ground Reference Point for Analog Circuitry.

Voltage Reference Input for the DAC. Connect to an external 2.5 V reference.

Reference can range from 2 V to V_DD.

1

CS

2

3

4

5

6

5

6

Logic Input Signal. The chip select signal is used to frame the serial data input.

SCLK

Clock Input. Data is clocked into the input register on the rising edge of SCLK.

Duty cycle must be between 40% and 60%.

4

6

±

DIN

Serial Data Input. This device accepts 16-bit words. Data is clocked into the

input register on the rising edge of SCLK.

±

8

9

1

9

1

DGND

VDD

Digital Ground. Ground reference for digital circuitry.

Analog Supply Voltage, 5 V ± 10%.

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is

low, all LDAC pulses are ignored. When CLR is activated, the input register and

the DAC register are cleared to the model selectable midscale or zeroscale .

Logic Power Supply.

±

5

CLR

10

8

10

8

VLOGIC

LDAC

LDAC Input. When this input is taken low, the DAC register is simultaneously

updated with the contents of the input register.

Rev. PrA | Page ± of 24

AD5541A/AD5542A/AD5512A

Preliminary Technical Data

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

RFB

VDD

VLOGIC

INV

VOUT

AGNDF

AGNDS

REFS

REFF

NC

AD5542A

TO P VIEW

(Not to Scale)

DGND

LDAC

CLR

DIN

CS

SCLK

NC = NO CO NNECT

Figure 10. AD5542A-1 10-Lead LFCSP Pin Configuration

Figure 12. AD5542A 16-Lead TSSOP Pin Configuration

RFB

1

2

3

4

5

6

7

14

V

DD

1

VOUT

12 DGND

11 LDAC

10 CLR

V

13 INV

O UT

AD5542A

AGNDF 2

AGNDS 3

AG NDF

12 DG ND

11 LDAC

10 DIN

AD5542A

AD5512A

TOP

AG NDS

REFS

REFF

CS

TO P VIEW

VIEW

(Not to Scale)

4

9

DIN

REFS

9

8

NC

SCLK

NC = NO CO NNECT

(Not to Scale)

NC = NO CO NNECT

Figure 11. AD5542 14-Lead SOIC Pin Configuration

Figure 13. AD5542A 16-Lead LFCSP Pin Configuration

Table 5. AD5542A/AD5512A Pin Function Descriptions

Pin No.

10-Lead 14-Lead 16-Lead

16-Lead

LFCSP

SOIC

TSSOP

Mnemonic Description

8

1

16

RFB

Feedback Resistor Pin. In bipolar mode, connect this pin to the external op

amp output.

6

2

3

4

5

2

3

4

5

1

2

3

4

VOUT

Analog Output Voltage from the DAC.

Ground Reference Point for Analog Circuitry (Force).

Ground Reference Point for Analog Circuitry (Sense).

Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V

reference. Reference can range from 2 V to V_DD.

AGNDF

AGNDS

REFS

6

5

REFF

Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V

reference. Reference can range from 2 V to V_DD.

Logic Input Signal. The chip select signal is used to frame the serial data

input.

Clock Input. Data is clocked into the input register on the rising edge of SCLK.

Duty cycle must be between 40% and 60%.

CS

2

3

±

8

9

6

8

SCLK

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR

is low, all LDAC pulses are ignored. When CLR is activated, the input register

and the DAC register are cleared to the model selectable midscale or

zeroscale .

Serial Data Input. This device accepts 16-bit words. Data is clocked into the

input register on the rising edge of SCLK.

CLR

5

4

11

10

11

10

12

9

DIN

11

LDAC

LDAC Input. When this input is taken low, the DAC register is simultaneously

updated with the contents of the input register.

12

13

14

12

13

DGND

INV

Digital Ground. Ground reference for digital circuitry.

Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin

to external op amps inverting input in bipolar mode.

Analog Supply Voltage, 5 V ± 10%.

Logic Power Supply.

±

9

14

16

15

14

VDD

VLOGIC

Rev. PrA | Page 8 of 24

Preliminary Technical Data

AD5541A/AD5542A/AD5512AA

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 14. Integral Nonlinearity vs. Code

Figure 17. Differential Nonlinearity vs. Code

Figure 15. Integral Nonlinearity vs. Temperature

Figure 18. Differential Nonlinearity vs. Temperature

Figure 16. Linearity Error vs. Supply Voltage

Figure 19. Linearity Error vs. Reference Voltage

Rev. PrA | Page 9 of 24

AD5541A/AD5542A/AD5512A

Preliminary Technical Data

Figure 20. Gain Error vs. Temperature

Figure 21. Supply Current vs. Temperature

Figure 22. Supply Current vs. Digital Input Voltage

Figure 23. Zero-Code Error vs. Temperature

Figure 24. Supply Current vs. Reference Voltage or Supply Voltage

Figure 25. Reference Current vs. Code

Rev. PrA | Page 10 of 24

Preliminary Technical Data

AD5541A/AD5542A/AD5512AA

Figure 26. Digital Feedthrough

Figure 28. Large Signal Settling Time

Figure 27. Digital-to-Analog Glitch Impulse

Figure 29. Small Signal Settling Time

Rev. PrA | Page 11 of 24

AD5541A/AD5542A/AD5512A

TERMINOLOGY

Preliminary Technical Data

Digital-to-Analog Glitch Impulse

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or INL is a measure of the

maximum deviation, in LSBs, from a straight line passing

through the endpoints of the DAC transfer function. A typical

INL vs. code plot is shown in Figure 14.

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-sec

and is measured when the digital input code is changed by

1 LSB at the major carry transition. A digital-to-analog glitch

impulse plot is shown in Figure 27.

Differential Nonlinearity (DNL)

DNL is the difference between the measured change and the

ideal 1 LSB change between any two adjacent codes. A specified

differential nonlinearity of 1 LSB maximum ensures mono-

tonicity. A typical DNL vs. code plot is shown in Figure 17.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC, but it is measured when the DAC output is not updated.

Gain Error

CS

is held high while the CLK and DIN signals are toggled. It

Gain error is the difference between the actual and ideal analog

output range, expressed as a percent of the full-scale range.

It is the deviation in slope of the DAC transfer characteristic

from ideal.

is specified in nV-sec and is measured with a full-scale code

change on the data bus, that is, from all 0s to all 1s and vice

versa. A typical digital feedthrough plot is shown in Figure 26.

Power Supply Rejection Ratio (PSRR)

Gain Error Temperature Coefficient

PSRR indicates how the output of the DAC is affected by changes

in the power supply voltage. Power-supply rejection ratio is

quoted in terms of percent change in output per percent change

in V_DDfor full-scale output of the DAC. V_DDis varied by 10%.

Gain error temperature coefficient is a measure of the change

in gain error with changes in temperature. It is expressed in

ppm/°C.

Zero Code Error

Zero code error is a measure of the output error when zero code

is loaded to the DAC register.

Reference Feedthrough

Reference feedthrough is a measure of the feedthrough from the

_REFinput to the DAC output when the DAC is loaded with all

0s. A 100 kHz, 1 V p-p is applied to V_REF. Reference feedthrough

V

Zero Code Temperature Coefficient

This is a measure of the change in zero code error with a change

in temperature. It is expressed in mV/°C.

is expressed in mV p-p.

Rev. PrA | Page 12 of 24

Preliminary Technical Data

AD5541A/AD5542A/AD5512AA

THEORY OF OPERATION

The AD5541A/AD5542A/AD5512A are single, 16-bit, serial

input, voltage output DACs. They operate from a single supply

ranging from 2.7 V to 5 V and consume typically 300 µA with a

supply of 5 V. Data is written to these devices in a 16-bit word

format,

SERIAL INTERFACE

The AD5541/AD5542 are controlled by a versatile 3- or 4-wire

serial interface that operates at clock rates up to 25 MHz and is

compatible with SPI, QSPI, MICROWIRE, and DSP interface

standards. The timing diagram is shown in Figure 5. Input data

via a 3- or 4-wire serial interface. To ensure a known power-up

state, these parts are designed with a power-on reset function.

In unipolar mode, the output is reset to 0 V; in bipolar mode,

the AD5542 output is set to −V_REF. Kelvin sense connections for

the reference and analog ground are included on the AD5542.

CS

is framed by the chip select input, . After a high-to-low

CS

transition on , data is shifted synchronously and latched into

the input register on the rising edge of the serial clock, SCLK.

Data is loaded MSB first in 16-bit words. After 16 data bits have

been loaded into the serial input register, a low-to-high transition

DIGITAL-TO-ANALOG SECTION

CS

on transfers the contents of the shift register to the DAC. Data

CS

can be loaded to the part only while

is low.

function that allows the DAC latch

LDAC CS

The DAC architecture consists of two matched DAC sections.

A simplified circuit diagram is shown in Figure 30. The DAC

architecture of the AD5541/AD5542 is segmented. The four

MSBs of the 16-bit data-word are decoded to drive 15 switches,

E1 to E15. Each switch connects one of 15 matched resistors to

either AGND or V_REF. The remaining 12 bits of the data-word

drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder

network.

LDAC

The AD5542 has an

to be updated asynchronously by bringing

LDAC

low after

should be maintained high while data is written

LDAC

goes high.

to the shift register. Alternatively,

nently low to update the DAC synchronously. With

can be tied perma-

LDAC

tied

CS

permanently low, the rising edge of loads the data to the DAC.

R

UNIPOLAR OUTPUT OPERATION

V

OUT

These DACs are capable of driving unbuffered loads of 60 kΩ.

Unbuffered operation results in low supply current, typically

300 μA, and a low offset error. The AD5541 provides a unipolar

output swing ranging from 0 V to V_REF. The AD5542 can be

configured to output both unipolar and bipolar voltages. Figure 31

shows a typical unipolar output voltage circuit. The code table

for this mode of operation is shown in Table 6.

2R

S0

2R . . . . .

S1 . . . . .

2R

E1

2R . . . . .

E2 . . . . .

2R

E15

S11

V

REF

FOUR MSBs DECODED

INTO 15 EQUAL SEGMENTS

12-BIT R-2R LADDER

5V

2.5V

Figure 30. DAC Architecture

10µF

0.1µF

With this type of DAC configuration, the output impedance

is independent of code, while the input impedance seen by

the reference is heavily code dependent. The output voltage is

dependent on the reference voltage, as shown in the following

equation:

0.1µF

SERIAL

INTERFACE

V

REF(REFF*) REFS*

DD

AD820/

OP196

CS

UNIPOLAR

OUTPUT

DIN

AD5541/AD5542

OUT

V_REF× D

SCLK

LDAC*

V_OUT

where:

=

EXTERNAL

OP AMP

2^N

DGND

AGND

*AD5542 ONLY.

D is the decimal data-word loaded to the DAC register.

N is the resolution of the DAC.

Figure 31. Unipolar Output

Table 6. Unipolar Code Table

For a reference of 2.5 V, the equation simplifies to the following:

DAC Latch Contents

MSB

2.5 × D

LSB

Analog Output

V_REF× (65,535/65,536)

V_OUT

=

65,536

1111 1111 1111 1111

1000 0000 0000 0000

0000 0000 0000 0001

0000 0000 0000 0000

V_REF× (32,±68/65,536) = ½ V_REF

V_REF× (1/65,536)

0 V

This gives a V_OUTof 1.25 V with midscale loaded, and 2.5 V

with full-scale loaded to the DAC.

The LSB size is V_REF/65,536.

Rev. PrA | Page 13 of 24

AD5541A/AD5542A/AD5512A

Preliminary Technical Data

Assuming a perfect reference, the unipolar worst-case output

voltage can be calculated from the following equation:

Assuming a perfect reference, the worst-case bipolar output

voltage can be calculated from the following equation:

D

[

(

V_{OUT −UNI}+ V_OS

)

(

2 + RD

)

− V_REF

(

1 + RD

)

]

V_OUT−UNI

=

×

(

V_REF+ V_GE+ V_ZSE+ INL

)

V_OUT−BIP

=

2¹⁶

1 +

(

2 + RD

)

A

where:

_OUT−UNIis unipolar mode worst-case output.

D is code loaded to DAC.

_REFis reference voltage applied to the part.

_GEis gain error in volts.

_ZSEis zero scale error in volts.

INL is integral nonlinearity in volts.

where:

V

_OUT-BIPis the bipolar mode worst-case output

_OUT−UNIis the unipolar mode worst-case output.

_OSis the external op amp input offset voltage.

RD is the R_FBand R_INVresistor matching error.

A is the op amp open-loop gain.

V

OUTPUT AMPLIFIER SELECTION

BIPOLAR OUTPUT OPERATION

For bipolar mode, a precision amplifier should be used and

supplied from a dual power supply. This provides the V_REF

output. In a single-supply application, selection of a suitable op

amp may be more difficult as the output swing of the amplifier

does not usually include the negative rail, in this case, AGND.

This can result in some degradation of the specified performance

unless the application does not use codes near zero.

With the aid of an external op amp, the AD5542 can be confi-

gured to provide a bipolar voltage output. A typical circuit of

such operation is shown in Figure 32. The matched bipolar

offset resistors, R_FBand R_INV, are connected to an external op

amp to achieve this bipolar output swing, typically R_FB= R_INV

28 kΩ. Table 7 shows the transfer function for this output

operating mode. Also provided on the AD5542 are a set of

Kelvin connections to the analog ground inputs.

=

The selected op amp needs to have a very low-offset voltage (the

DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need

for output offset trims. Input bias current should also be very

low because the bias current, multiplied by the DAC output

impedance (approximately 6 kΩ), adds to the zero code error.

Rail-to-rail input and output performance is required. For fast

settling, the slew rate of the op amp should not impede the

settling time of the DAC. Output impedance of the DAC is

constant and code-independent, but to minimize gain errors,

the input impedance of the output amplifier should be as high

as possible. The amplifier should also have a 3 dB bandwidth of

1 MHz or greater. The amplifier adds another time constant to

the system, thus increasing the settling time of the output. A

higher 3 dB amplifier bandwidth results in a shorter effective

settling time of the combined DAC and amplifier.

+5V +2.5V

10µF

0.1µF

+5V

RFB

SERIAL

INTERFACE

V

REFF REFS

DD

R

FB

CS

INV

DIN

R

INV

UNIPOLAR

OUTPUT

OUT

SCLK

LDAC

AD5541/AD5542

–5V

EXTERNAL

OP AMP

DGND AGNDF AGNDS

Figure 32. Bipolar Output (AD5542 Only)

Table 7. Bipolar Code Table

DAC Latch Contents

MSB

LSB

Analog Output

FORCE SENSE AMPLIFIER SELECTION

1111 1111 1111 1111

1000 0000 0000 0001

1000 0000 0000 0000

0111 1111 1111 1111

0000 0000 0000 0000

+V_REF× (32,±6±/32,±68)

+V_REF× (1/32,±68)

0 V

−V_REF× (1/32,±68)

−V_REF× (32,±68/32,±68) = −V_REF

Use single-supply, low-noise amplifiers. A low-output impedance

at high frequencies is preferred because the amplifiers need to

be able to handle dynamic currents of up to 20 mA.

REFERENCE AND GROUND

Because the input impedance is code-dependent, the reference

pin should be driven from a low impedance source. The AD5541/

AD5542 operate with a voltage reference ranging from 2 V to

V_DD. References below 2 V result in reduced accuracy. The full-

scale output voltage of the DAC is determined by the reference.

Table 6 and Table 7 outline the analog output voltage or partic-

ular digital codes. For optimum performance, Kelvin sense

connections are provided on the AD5542.

If the application doesn’t require separate force and sense lines,

tie the lines close to the package to minimize voltage drops

between the package leads and the internal die.

Rev. PrA | Page 14 of 24

Preliminary Technical Data

AD5541A/AD5542A/AD5512AA

POWER-ON RESET

POWER SUPPLY AND REFERENCE BYPASSING

The AD5541/AD5542 have a power-on reset function to ensure

that the output is at a known state on power-up. On power-up,

the DAC register contains all 0s until the data is loaded from

the serial register. However, the serial register is not cleared on

power-up, so its contents are undefined. When loading data

initially to the DAC, 16 bits or more should be loaded to prevent

erroneous data appearing on the output. If more than 16 bits are

loaded, the last 16 are kept, and if less than 16 bits are loaded,

bits remain from the previous word. If the AD5541/ AD5542

need to be interfaced with data shorter than 16 bits, the data

should be padded with 0s at the LSBs.

For accurate high-resolution performance, it is recommended

that the reference and supply pins be bypassed with a 10 μF

tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.

Rev. PrA | Page 15 of 24

AD5541A/AD5542A/AD5512A

Preliminary Technical Data

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5541/AD5542 is via a

serial bus that uses standard protocol that is compatible with

DSP processors and microcontrollers. The communications

channel requires a 3- or 4-wire interface consisting of a clock

signal, a data signal and a synchronization signal. The

AD5541/AD5542 require a 16-bit data-word with data valid on

the rising edge of SCLK. The DAC update can be done

automatically when all the data is clocked in or it can be done

AD5541/AD5542 TO MICROWIRE INTERFACE

Figure 35 shows an interface between the AD5541/AD5542

and any MICROWIRE-compatible device. Serial data is shifted

out on the falling edge of the serial clock and into the AD5541/

AD5542 on the rising edge of the serial clock. No glue logic is

required because the DAC clocks data into the input shift

register on the rising edge.

LDAC

under control of the

(AD5542 only).

CS

SO

CS

AD5541/

AD5542*

MICROWIRE*

DIN

AD5541/AD5542 TO ADSP-2101/ADSP-2103

INTERFACE

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 33 shows a serial interface between the AD5541/AD5542

and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103

should be set to operate in the SPORT transmit alternate framing

mode. The ADSP-2101/ADSP-2103 are programmed through

the SPORT control register and should be configured as follows:

internal clock operation, active low framing, 16-bit word length.

Transmission is initiated by writing a word to the Tx register

after the SPORT has been enabled. As the data is clocked out

on each rising edge of the serial clock, an inverter is required

between the DSP and the DAC, because the AD5541/AD5542

clock data in on the falling edge of the SCLK.

Figure 35. AD5541/AD5542 to MICROWIRE Interface

AD5541/AD5542 TO 80C51/80L51 INTERFACE

A serial interface between the AD5541/AD5542 and the 80C51/

80L51 microcontroller is shown in Figure 36. TxD of the micro-

controller drives the SCLK of the AD5541/AD5542, and RxD

drives the serial data line of the DAC. P3.3 is a bit programmable

CS

pin on the serial port that is used to drive

.

The 80C51/80L51 provide the LSB first, whereas the AD5541/

AD5542 expects the MSB of the 16-bit word first. Care should

be taken to ensure the transmit routine takes this into account.

FO

TFS

LDAC**

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is valid on the falling edge of TxD, so the clock

must be inverted as the DAC clocks data into the input shift

register on the rising edge of the serial clock. The 80C51/80L51

transmit data in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. As the DAC requires a 16-bit

word, P3.3 must be left low after the first eight bits are transferred,

CS

AD5541/

AD5542*

ADSP-2101/

ADSP-2103*

DT

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY.

Figure 33. AD5541/AD5542 to ADSP-2101/ADSP-2103 Interface

LDAC

AD5541/AD5542 TO 68HC11/68L11 INTERFACE

and brought high after the second byte is transferred.

on

the AD5542 can also be controlled by the 80C51/ 80L51 serial

port output by using another bit programmable pin, P3.4.

Figure 34 shows a serial interface between the AD5541/AD5542

and the 68HC11/68L11 microcontroller. SCK of the 68HC11/

68L11 drives the SCLK of the DAC, and the MOSI output drives

P3.4

P3.3

RxD

TxD

LDAC**

CS

the serial data line serial DIN. The

signal is driven from one

80C51/

80L51*

CS

AD5541/

AD5542*

of the port lines. The 68HC11/68L11 is configured for master

mode: MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing

on the MOSI output is valid on the rising edge of SCK.

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY.

PC6

PC7

LDAC**

Figure 36. AD5541/AD5542 to 80C51/80L51 Interface

68HC11/

68L11*

CS

AD5541/

AD5542*

MOSI

SCK

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

**AD5542 ONLY.

Figure 34. AD5541/AD5542 to 68HC11/68L11 Interface

Rev. PrA | Page 16 of 24

Preliminary Technical Data

AD5541A/AD5542A/AD5512AA

APPLICATIONS INFORMATION

OPTOCOUPLER INTERFACE

DECODING MULTIPLE AD5541/AD5542s

The digital inputs of the AD5541A/AD5542A/AD5512A are

Schmitt-triggered so that they can accept slow transitions on the

digital input lines. This makes these parts ideal for industrial

applications where it may be necessary to isolate the DAC from

the controller via optocouplers. Figure 37 illustrates such an

interface.

CS

pin of the AD5541/AD5542 can be used to select one of

The

a number of DACs. All devices receive the same serial clock and

CS

serial data, but only one device receives the

signal at any one

time. The DAC addressed is determined by the decoder. There is

some digital feedthrough from the digital input lines. Using a

burst clock minimizes the effects of digital feedthrough on the

analog signal channels. Figure 38 shows a typical circuit.

5V

REGULATOR

AD5541/AD5542

SCLK

0.1µF

POWER

10µF

CS

V

OUT

DIN

V

DD

V

DD

SCLK

10kΩ

V

DD

SCLK

ENABLE

AD5541/AD5542

EN

CS

CODED

ADDRESS

V

DECODER

DGND

OUT

DIN

V

AD5541/AD5542

SCLK

10kΩ

CS

V

AD5541/AD5542

OUT

CS

V

OUT

V

DIN

SCLK

10kΩ

DIN

GND

AD5541/AD5542

CS

V

OUT

DIN

SCLK

Figure 37. AD5541/AD5542 in an Optocoupler Interface

Figure 38. Addressing Multiple AD5541/AD5542s

Rev. PrA | Page 1± of 24

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

5.15

4.90

4.65

3.10

3.00

2.90

1

5

PIN 1

0.50 BSC

0.95

0.85

0.75

1.10 MAX

0.80

0.60

0.40

8°

0°

0.15

0.05

0.33

0.17

SEATING

PLANE

0.23

0.08

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 39. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters.

0.30

0.23

0.18

3.00

BSC SQ

0.50 BSC

10

6

PIN 1 INDEX

AREA

1.74

1.64

1.49

EXPOSED

PAD

(BOTTOM VIEW)

0.50

0.40

0.30

5

1

PIN 1

INDICATOR

(R 0.19)

TOP VIEW

2.48

2.38

2.23

0.80 MAX

0.55 NOM

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SEATING

PLANE

0.20 REF

Figure 40. 10-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-10-9)

Dimensions shown in millimeters.

Rev. PrA | Page 18 of 24

0.35

0.30

0.25

3.00

BSC SQ

0.65 BSC

8

5

4

PIN 1 INDEX

AREA

1.74

1.64

1.49

EXPOSED

PAD

(BOTTOM VIEW)

0.50

0.40

0.30

1

PIN 1

R

INDICATO

(R 0.2)

TOP VIEW

2.48

2.38

2.23

0.80 MAX

0.55 NOM

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SEATING

PLANE

0.20 REF

Figure 41. 8-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-8-3)

Dimensions shown in millimeters.

5.10

5.00

4.90

16

9

4.50

4.40

4.30

6.40

BSC

1

8

PIN 1

1.20

MAX

0.20

0.15

0.05

0.75

0.60

0.45

0.09

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 42. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters.

Rev. PrA | Page 19 of 24

3.10

3.00 SQ

2.90

0.30

0.23

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

13

16

0.50

BSC

1

4

12

EXPOSED

PAD

1.75

1.60 SQ

1.55

9

8

5

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WEED.

Figure 43. 16-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-16-22)

Dimensions shown in millimeters.

Rev. PrA | Page 20 of 24

ORDERING GUIDE

Clear to Code

Package

Description

Package

Option

Model

INL

DNL

Temperature Range

AD5541ABRMZ

AD5541AARMZ

AD5541ABCPZ

AD5541AACPZ

AD5541ABCPZ-1

AD5542ABRUZ

AD5542AARUZ

AD5542ASRUZ

AD5542ABCPZ

AD5542AACPZ

AD5442ABCPZ-1

AD5512AACPZ

±1 LSB

±2 LSB

±1 LSB

±2 LSB

±1 LSB

±2 LSB

±1 LSB

±2 LSB

±1 LSB

Midscale

Zero-scale

Midscale

−40°C to +105°C

−55°C to +125°C

−40°C to +105°C

10-Lead MSOP

10-Lead LFCSP

8-Lead LFCSP

16-Lead TSSOP

16-Lead LFCSP

10-Lead LFCSP

16-Lead LFCSP

RM-10

CP-10-9

CP_8-3

RU-16

CP-16-22

CP-10-9

CP-16-22

Rev. PrA | Page 21 of 24

AD5541A/AD5542A/AD5512A

NOTES

Preliminary Technical Data

Rev. PrA | Page 22 of 24

Preliminary Technical Data

NOTES

AD5541A/AD5542A/AD5512A

Rev. PrA | Page 23 of 24

AD5541A/AD5542A/AD5512A

NOTES

Preliminary Technical Data

registered trademarks are the property of their respective owners.

PR08516-0-12/09(PrA)

Rev. PrA | Page 24 of 24


型号：	AD5541A
厂家：	ADI
描述：	2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDACs in LFCSP 2.7 V至5.5 V ，串行输入，电压输出， 16位/ 12位nanoDACs的LFCSP
文件：	总24页 (文件大小：838K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5541A [ADI]

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AD5541AARMZ

AD5541AARMZ-REEL7

AD5541ABCPZ

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AD5541ABCPZ-1-RL7

AD5541ABCPZ-500RL7

AD5541ABCPZ-REEL7

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AD5541ABRMZ