AD5543CRMZ_技术文档

Current Output/Serial Input,

16-/14-Bit DACs

Data Sheet

AD5543/AD5553

FEATURES

FUNCTIONAL BLOCK DIAGRAM

16-bit resolution AD5543

14-bit resolution AD5553

1 LSB DNL

AD5543/AD5553

R

FB

V

DD

1 LSB INL

Low noise: 12 nV/√Hz

Low power: I_DD= 10 µA

0.5 µs settling time

4Q multiplying reference input

2 mA full-scale current 20%, with V_REF= 10 V

Built-in RFB facilitates voltage conversion

3-wire interface

I

V

DAC

OUT

REF

CS

16 OR 14

CONTROL

LOGIC

DAC

REGISTER

16 OR 14

CLK

SDI

GND

16-BIT/14-BIT SHIFT

REGISTER

Ultracompact 8-lead MSOP and 8-lead SOIC packages

Figure 1.

APPLICATIONS

1.0

0.8

Automatic test equipment

Instrumentation

0.6

Digitally controlled calibration

Industrial control PLCs

0.4

0.2

0

GENERAL DESCRIPTION

–0.2

–0.4

–0.6

–0.8

–1.0

The AD5543/AD5553 are precision 16-/14-bit, low power,

current output, small form factor digital-to-analog converters

(DACs). They are designed to operate from a single 5 V supply

with a 10 V multiplying reference.

The applied external reference, V_REF, determines the full-scale

output current. An internal feedback resistor (R_FB) facilitates the

R-2R and temperature tracking for voltage conversion when

combined with an external op amp.

CODE

Figure 2. Integral Nonlinearity

2

0

A serial-data interface offers high speed, 3-wire microcontroller-

compatible inputs using serial data in (SDI), clock (CLK), and

CS

chip select ( ).

–2

The AD5543/AD5553 are packaged in ultracompact (3 mm ×

4.7 mm) 8-lead MSOP and 8-lead SOIC packages.

–4

–6

–8

–10

–12

–14

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 3. Reference Multiplying Bandwidth

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD5543/AD5553

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications Information.............................................................. 11

Stability ........................................................................................ 11

Positive Voltage Output............................................................. 11

Bipolar Output............................................................................ 11

Programmable Current Source ................................................ 12

Reference Selection .................................................................... 12

Amplifier Selection .................................................................... 12

Evaluation Board ............................................................................ 14

System Development Platform................................................. 14

AD5543/AD5553 to SPORT Interface .................................... 14

Waveform Generator ................................................................. 14

Operating the Evaluation Board .............................................. 14

Bill of Materials........................................................................... 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 20

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Diagrams.......................................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Circuit Operation ............................................................................. 9

DAC Section.................................................................................. 9

Serial Data Interface....................................................................... 10

ESD Protection Circuits............................................................. 10

PCB Layout and Power Supply Bypassing .............................. 10

REVISION HISTORY

1/12—Rev. E to Rev. F

10/09—Rev. B to Rev. C

Added Figure 15, Renumbered Sequentially ................................ 8

Change to Table 9 ........................................................................... 13

Changes to Figure 27...................................................................... 15

Changes to Figure 28...................................................................... 16

Replaced Figure 29, Figure 30, and Figure 31............................. 17

Updated Outline Dimensions..................................................... 14

Changes to Ordering Guide.......................................................... 15

7/09—Rev. A to Rev. B

Updated Format..................................................................Universal

Change to Features Section..............................................................1

Updated Outline Dimensions....................................................... 14

Changes to Ordering Guide.......................................................... 15

2/11—Rev. D to Rev. E

Added Evaluation Board Section ................................................. 14

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide .......................................................... 21

2/03—Rev. 0 to Rev. A

Changes to Ordering Guide.............................................................3

4/10—Rev. C to Rev. D

Changes to Figure 3.......................................................................... 1

Changes to Table 1............................................................................ 3

Moved Timing Diagrams Section .................................................. 4

Moved Table 4 ................................................................................... 6

Delete Figure 13; Renumbered Sequentially................................. 8

Changes to Figure 14........................................................................ 8

Changes to Figure 18........................................................................ 9

Moved Table 5 and Table 6............................................................ 10

Added Reference Selection Section and Amplifier Selection

Section.............................................................................................. 12

Added Table 7, Table 8, and Table 9;

12/02—Revision 0: Initial Version

Renumbered Sequentially.............................................................. 13

Rev. F | Page 2 of 20

Data Sheet

AD5543/AD5553

SPECIFICATIONS

V_DD= 5 V 10%, V_SS= 0 V, I _OUT= virtual GND, GND = 0 V, V_REF= 10 V, T_A= full operating temperature range, unless otherwise noted.

Table 1.

Parameter

Symbol

N

Condition

5 V 10%

Unit

STATIC PERFORMANCE¹

Resolution

1 LSB = V_REF/2¹⁶= 153 µV when V_REF= 10 V (AD5543)

1 LSB = V_REF/2¹⁴= 610 µV when V_REF= 10 V (AD5553)

Grade: AD5553C

16

14

1

Bits

Relative Accuracy

INL

LSB max

nA max

mV typ/max

ppm/°C typ

Grade: AD5543C

Grade: AD5543B

Monotonic

Data = 0x0000, T_A= 25°C

Data = 0x0000, T_A= T_Amaximum

Data = 0xFFFF

1

2

1

Differential Nonlinearity

Output Leakage Current

DNL

I_OUT

10

20

1/ 4

1

Full-Scale Gain Error

Full-Scale Temperature Coefficient²

REFERENCE INPUT

V_REFRange

G_FSE

TCV_FS

V_REF

R_REF

C_REF

−15/+15

V min/max

kΩ typ³

pF typ

Input Resistance

5

Input Capacitance²

ANALOG OUTPUT

Output Current

I_OUT

Data = 0xFFFF for AD5543

Data = 0x3FFF for AD5553

Code dependent

2

mA typ

pF typ

Output Capacitance²

LOGIC INPUTS AND OUTPUT

Logic Input Low Voltage

Logic Input High Voltage

Input Leakage Current

Input Capacitance²

INTERFACE TIMING^{2, 4}

Clock Input Frequency

Clock Width High

C_OUT

200

V_IL

V_IH

I_IL

0.8

2.4

10

V max

V min

µA max

pF max

C_IL

10

See Figure 4 and Figure 5

f_CLK

t_CH

t_CL

t_CSS

t_CSH

t_DS

50

10

0

MHz

ns min

Clock Width Low

CS to Clock Setup

Clock to CS Hold

10

5

10

Data Setup

Data Hold

t_DH

SUPPLY CHARACTERISTICS

Power Supply Range

Positive Supply Current

Power Dissipation

V_{DD RANGE}

I_DD

P_DISS

P_SS

4.5/5.5

10

0.055

0.006

V min/max

µA max

mW max

%/% max

Logic inputs = 0 V

ΔV_DD= 5%

Power Supply Sensitivity

Rev. F | Page 3 of 20

AD5543/AD5553

Data Sheet

Parameter

AC CHARACTERISTICS⁴

Symbol

Condition

5 V 10%

Unit

Output Voltage Settling Time

t_S

To 0.1% of full scale,

0.5

µs typ

Data = 0x0000 to 0xFFFF to 0x0000 for AD5543

Data = 0x0000 to 0x3FFF to 0x0000 for AD5553

V_REF= 100 mV rms, data = 0xFFFF

V_REF= 0 V, data = 0x7FFF to 0x8000 for AD5543

Data = 0x0000, V_REF= 100 mV rms, same channel

C_S= 1 and f_CLK= 1 MHz

Reference Multiplying Bandwidth

DAC Glitch Impulse

Feedthrough Error

Digital Feedthrough

Total Harmonic Distortion

Output Spot Noise Voltage

BW

Q

V_OUT/V_REF

Q

THD

e_N

6.6

7

−83

7

−103

12

MHz typ

nV-sec

dB

nV-sec

dB typ

nV/√Hz

V_REF= 5 V p-p, data = 0xFFFF, f = 1 kHz

f = 1 kHz, BW = 1 Hz

¹All static performance tests (except I_OUT) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 R_FBterminal is

tied to the amplifier output. The +IN op amp is grounded, and the DAC I_OUTis tied to the −IN op amp. Typical values represent average readings measured at 25°C.

²These parameters are guaranteed by design and are not subject to production testing.

³All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where an AD8065 was used.

⁴All input control signals are specified with t_R= t_F= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

TIMING DIAGRAMS

SDI

D15

D14

D13

D12

D11

D10

D9

D8

D1

D0

CLK

t_DS

t_DH

t_CH

t_CL

t_CSS

t_CSH

CS

Figure 4. AD5543 Timing Diagram

SDI

D13

D12

D11

D10

D9

D8

D7

D6

D1

D0

CLK

t_DS

t_DH

t_CH

t_CL

t_CSS

t_CSH

CS

Figure 5. AD5553 Timing Diagram

Rev. F | Page 4 of 20

Data Sheet

AD5543/AD5553

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

V_REFto GND

Logic Inputs to GND

V(I_OUT) to GND

Input Current to Any Pin Except Supplies

Package Power Dissipation

Thermal Resistance, θ_JA

8-Lead Surface Mount (MSOP)

8-Lead Surface Mount (SOIC)

Maximum Junction Temperature (T_{J Max}

Operating Temperature Range

Model B and Model C

−0.3 V to +8 V

−18 V to +18 V

−0.3 V to +8 V

−0.3 V to V_DD+ 0.3 V

50 mA

(T_{J Max}− T_A)/θ_JA

ESD CAUTION

150°C/W

100°C/W

150°C

)

−40°C to +85°C

−65°C to +150°C

Storage Temperature Range

Lead Temperature

R-8, RM-8 (Vapor Phase, 60 sec)

R-8, RM-8 (Infrared, 15 sec)

215°C

220°C

Rev. F | Page 5 of 20

AD5543/AD5553

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK

SDI

1

2

3

4

8

7

6

5

CS

AD5543/

AD5553

V

DD

R

GND

FB

TOP VIEW

(Not to Scale)

V

I

OUT

REF

Figure 6. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

Clock Input. Positive-edge triggered, clocks data into shift register.

1

2

3

4

5

CLK

SDI

R_FB

V_REF

I_OUT

Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored.

Internal Matching Feedback Resistor. This pin connects to an external op amp for voltage output.

DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.

DAC Current Output. This pin connects to the inverting terminal of the external precision I-to-V op amp for

voltage output.

6

7

8

GND

V_DD

CS

Analog and Digital Ground.

Positive Power Supply Input. Specified range of operation at 5 V 10%.

Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge.

See Table 4 for operation.

Table 4. Control-Logic Truth Table

CS

CLK

Serial Shift Register Function

No effect

DAC Register

X

H

Latched

↑+¹

X¹

L

Shift register data advanced one bit

No effect

Shift register data transferred to DAC register

Latched

H

↑+¹

Latched

New data loaded from serial register

¹↑+ = positive logic transition; X = don't care.

Rev. F | Page 6 of 20

Data Sheet

AD5543/AD5553

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.2

–0.4

–0.6

–0.8

–1.0

–0.8

–1.0

0

8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

CODE (Decimal)

0

2048

4096

6144

CODE (Decimal)

8192 10,240 12,288 14,336 16,384

Figure 7. AD5543 Integral Nonlinearity Error

Figure 10. AD5553 Differential Nonlinearity Error

1.5

1.0

0.8

V

A

= 2.5V

REF

= 25°C

T

1.0

0.5

0

0.6

0.4

0.2

INL

0

DNL

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

GE

2

4

6

8

10

0

8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

CODE (Decimal)

SUPPLY VOLTAGE V (V)

DD

Figure 8. AD5543 Differential Nonlinearity Error

Figure 11. Linearity Error vs. VD_D

5

4

3

2

1

0

1.0

0.8

V

A

= 5V

DD

= 25°C

T

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

IH

4.0

4.5

5.0

0

2048

4096

6144

CODE (Decimal)

8192 10,240 12,288 14,336 16,384

LOGIC INPUTVOLTAGEV (V)

Figure 12. Supply Current vs. Logic Input Voltage

Figure 9. AD5553 Integral Nonlinearity Error

Rev. F | Page 7 of 20

AD5543/AD5553

Data Sheet

3.0

2.5

2.0

1.5

1.0

0.5

0

A2

–5V

DLY

67.72µs

0x5555

0x8000

0xFFFF

0x0000

10k

100k

1M

CLOCK FREQUENCY (Hz)

10M

100M

5V

2V

136ns

Figure 16. Settling Time

Figure 13. AD5543 Supply Current vs. Clock Frequency

–3.65

–3.70

90

80

70

60

50

40

30

20

10

0

V

= 5V ± 10%

= 10V

DD

REF

–3.75

–3.80

–3.85

–3.90

–3.95

–4.00

–4.05

–20

–10

0

10

20

30

40

10

100

1k

10k

100k

1M

TIME (ns)

FREQUENCY (Hz)

Figure 14. Power Supply Rejection Ratio (PSRR) vs. Frequency

Figure 17. Midscale Transition and Digital Feedthrough

20

0

–20

–40

–60

–80

–100

–120

–140

–160

0

5

10

15

20

25

FREQUENCY (kHz)

Figure 15. AD5543/AD5553 Analog THD

Rev. F | Page 8 of 20

Data Sheet

AD5543/AD5553

CIRCUIT OPERATION

The AD5543/AD5553 contain 16-/14-bit current output, DACs,

serial input registers, and DAC registers. Both converters use a

3-wire serial data interface.

Note that a matching switch is used in series with the internal

5 kΩ feedback resistor. If users attempt to measure R_FB, power

must be applied to V_DDto achieve continuity.

V

DD

DAC SECTION

R2

The DAC architecture uses a current steering R-2R ladder

design. Figure 18 shows the typical equivalent DAC structure.

The DAC contains a matching feedback resistor for use with an

external op amp (see Figure 19). With RFB and IOUT terminals

connected to the op amp output and inverting node, respectively,

a precision voltage output is achieved as

C1

V

R

DD

FB

I

1

OUT

AD5543/

AD5553

V

REF

A1

REF

R1

GND

V

= 0 TO –V

REF

OUT

SYNC SCLK SDIN

AGND

V

_OUT= −V_REF× D/65,536 (AD5543)

(1)

(2)

µCONTROLLER

NOTES

V_OUT= −V_REF× D/16,384 (AD5553)

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (4pF TO 6pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Note that the output voltage polarity is the opposite of the V_REF

polarity for dc reference voltages.

Figure 19. Voltage Output Configuration

These DACs are designed to operate with either negative or

positive reference voltages. The V_DDpower pin is only used

by the internal logic to drive the on and off states of the DAC

switches.

These DACs are also designed to accommodate ac reference

input signals. The AD5543 accommodates input reference

voltages in the range of −12 V to +12 V. The reference voltage

inputs exhibit a constant nominal input resistance value of 5 kΩ

30%. The DAC output (I_OUT) is code dependent, producing

various resistances and capacitances. External amplifier choice

should take into account the variation in impedance generated

by the AD5543 on the inverting input node of the amplifier.

The feedback resistance, in parallel with the DAC ladder

resistance, dominates output voltage noise. To maintain good

analog performance, power supply bypassing of 0.01 µF to 0.1 µF

ceramic or chip capacitors, in parallel with a 1 µF tantalum

capacitor, is recommended. Due to degradation of PSRR in

frequency, users must avoid using switching power supplies.

V

DD

R

V

FB

REF

2R

R

5kΩ

S1

S2

I

OUT

GND

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY;

SWITCHES S1 AND S2 ARE CLOSED, V MUST BE POWERED.

DD

Figure 18. Equivalent R-2R DAC Circuit

Rev. F | Page 9 of 20

AD5543/AD5553

Data Sheet

SERIAL DATA INTERFACE

V

DD

CS

The AD5543/AD5553 use a 3-wire ( , SDI, CLK) serial data

interface. New serial data is clocked into the serial input register

in a 16-bit data-word format for the AD5543. The MSB is loaded

first. Table 5 defines the 16 data-word bits. Data is placed on the

SDI pin and clocked into the register on the positive clock edge

of CLK, subject to the data setup-and-hold time requirements

that are specified in the interface timing specifications. Only the

last 16 bits clocked into the serial register are interrogated when

DIGITAL

INPUTS

5kΩ

DGND

Figure 20. Equivalent ESD Protection Circuits

PCB LAYOUT AND POWER SUPPLY BYPASSING

CS

the pin is strobed to transfer the serial register data to the DAC

register. Because most microcontrollers output serial data in 8-

bit bytes, two data bytes can be written to the AD5543/AD5553.

It is a good practice to employ compact, minimum lead length

PCB layout design. The leads to the input should be as short as

possible to minimize IR drop and stray inductance.

CS

After loading the serial register, the rising edge of

transfers

the serial register data to the DAC register; during this strobe,

the CLK should not be toggled. For the AD5553, with 16-bit

clock cycles, the two LSBs are ignored.

It is also essential to bypass the power supplies with quality

capacitors for optimum stability. Supply leads to the device

should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic

capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic

capacitors should also be applied at the supplies to minimize

transient disturbance and filter out low frequency ripple.

ESD PROTECTION CIRCUITS

All logic input pins contain back-biased ESD protection Zener

diodes that are connected to ground (DGND) and V_DD, as

shown in Figure 20.

The PCB metal traces between V_REFand R_FBshould also be

matched to minimize gain error.

Table 5. AD5543 Serial Input Register Data Format; Data Loaded MSB-First Format

B15 (MSB)

B14

B13

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0 (LSB)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Table 6. AD5553 Serial Input Register Data Format; Data Loaded MSB-First Format

B13 (MSB)¹

B12

B11

B10

B9

B8

B7

B6

B5

B4

D4

B3

D3

B2

B1

B0 (LSB)

D13

D12

D11

D10

D9

D8

D7

D6

D5

D2

D1

D0

1

CS

A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered are transferred to the DAC register when returns to

logic high.

Rev. F | Page 10 of 20

Data Sheet

AD5543/AD5553

APPLICATIONS INFORMATION

STABILITY

BIPOLAR OUTPUT

V

DD

The AD5543/AD5553 are inherently 2-quadrant multiplying

DACs. That is, they can easily be set up for unipolar output

operation. The full-scale output polarity is the inverse of the

reference input voltage.

U1

C1

V

R

FB

DD

I

V

OUT

REF

V

O

AD8628

In some applications, it may be necessary to generate the full

4-quadrant multiplying capability or a bipolar output swing,

which is easily accomplished by using an additional U4 external

amplifier configured as a summing amplifier (see Figure 23). In

this circuit, the second amplifier, U4, provides a gain of 2 that

increases the output span magnitude to 5 V. Biasing the external

amplifier with a 2.5 V offset from the reference voltage results in a

full 4-quadrant multiplying circuit. The transfer equation of this

circuit shows that both negative and positive output voltages are

created as the input data (D) is incremented from code zero

GND

AD5543/AD5553

U2

Figure 21. Optional Compensation Capacitor for Gain Peaking Prevention

In the I-to-V configuration, the I_OUTof the DAC and the inverting

node of the op amp must be connected as close as possible to

each other, and proper PCB layout technique must be employed.

Because every code change corresponds to a step function, gain

peaking may occur if the op amp has limited GBP and there is

excessive parasitic capacitance at the inverting node.

(V_OUT= −2.5 V) to midscale (V_OUT= 0 V) to full-scale (V_OUT

=

An optional compensation capacitor, C1, can be added for

stability, as shown in Figure 21. C1 should be found empirically,

but 20 pF is generally adequate for the compensation.

+2.5 V).

V

_OUT= (D/32,768 − 1) × V_REF(AD5543)

_OUT= (D/16,384 − 1) × V_REF(AD5553)

(3)

(4)

POSITIVE VOLTAGE OUTPUT

For the AD5543, the resistance tolerance becomes the dominant

error of which users should be aware.

To achieve the positive voltage output, an applied negative

reference to the input of the DAC is preferred over the output

inversion through an inverting amplifier because of the tolerance

errors of the resistors. To generate a negative reference, the

reference can be level-shifted by an op amp such that the VOUT

and GND pins of the reference become the virtual ground and

−2.5 V, respectively (see Figure 22).

R1

R2

10kΩ ± 0.01% 10kΩ ± 0.01%

C2

U4

+5V

V+

+5V

U1

5kΩ ± 0.01%

V

O

R3

ADR03

1/2AD8620

V–

C1

OUT

V

R

FB

+5V

DD

ADR03

I

V

+5V

IN

REF

GND

OUT

GND

U3

–5V

1/2AD8620

–2.5V < V < +2.5V

V

O

IN

OUT

U4

+5V

U1

V

GND

U3

–2.5V

C1

OUT

AD5553 ONLY

V

R

FB

U2

DD

V+

I

1/2AD8620

V–

REF

Figure 23. 4-Quadrant Multiplying Application Circuit

V

O

1/2AD8628

GND

–5V

AD5543/AD5553

U2

0V < V < +2.5V

O

Figure 22. Positive Voltage Output Configuration

Rev. F | Page 11 of 20

AD5543/AD5553

Data Sheet

PROGRAMMABLE CURRENT SOURCE

REFERENCE SELECTION

Figure 24 shows a versatile V-I conversion circuit using an

improved Howland current pump. In addition to the precision

current conversion it provides, this circuit enables a bidirectional

current flow and high voltage compliance. This circuit can be used

in 4 mA to 20 mA current transmitters with up to 500 Ω of load. In

Figure 24, it can be shown that if the resistor network is matched,

the load current is

When selecting a reference for use with the AD55xx series of

current output DACs, pay attention to the output voltage,

temperature coefficient specification of the reference. Choosing

a precision reference with a low output temperature coefficient

minimizes error sources. Table 7 lists some of the references

available from Analog Devices, Inc., that are suitable for use

with this range of current output DACs.

(

R2 + R3 /R1

)

AMPLIFIER SELECTION

I_L

=

×V_REF× D

(5)

R3

The primary requirement for the current-steering mode is an

amplifier with low input bias currents and low input offset

voltage. Because of the code-dependent output resistance of the

DAC, the input offset voltage of an op amp is multiplied by the

variable gain of the circuit. A change in this noise gain between

two adjacent digital fractions produces a step change in the

output voltage due to the amplifier’s input offset voltage. This

output voltage change is superimposed upon the desired change

in output between the two codes and gives rise to a differential

linearity error, which, if large enough, can cause the DAC to be

nonmonotonic.

R3 in theory can be made small to achieve the current needed

within the U3 output current driving capability. This circuit is

versatile such that AD8510 can deliver 20 mA in both directions

and the voltage compliance approaches 15 V, which is limited

mainly by the supply voltages of U3. However, users must pay

attention to the compensation. Without C1, it can be shown

that the output impedance becomes

R1' R3

R2' + R3'

If the resistors are perfectly matched, Z_Ois infinite, which is

(

R1 + R2

)

Z_O

=

(6)

R1

(

)

− R1' R2 + R3

(

)

The input bias current of an op amp also generates an offset at

the voltage output because of the bias current flowing in the

feedback resistor, R_FB.

desirable, and behaves as an ideal current source. On the other

hand, if they are not matched, Z_Ocan be either positive or negative.

Negative can cause oscillation. As a result, C1 is needed to prevent

the oscillation. For critical applications, C1 could be found

empirically but typically falls in the range of a few picofarads (pF).

Common-mode rejection of the op amp is important in voltage-

switching circuits because it produces a code-dependent error

at the voltage output of the circuit.

V

DD

Provided that the DAC switches are driven from true wideband

low impedance sources (V_INand AGND), they settle quickly.

Consequently, the slew rate and settling time of a voltage-

switching DAC circuit is determined largely by the output op

amp. To obtain minimum settling time in this configuration,

minimize capacitance at the V_REFnode (the voltage output node

in this application) of the DAC. This is done by using low input

capacitance buffer amplifiers and careful board design.

U1

R

V

FB

DD

I

V

REF

OUT

REF

R1'

150kΩ

R2'

15kΩ

AD8628

GND

C1

10pF

AD5543/AD5553

U2

V

DD

U3

R3'

50Ω

V+

Analog Devices offers a wide range of amplifiers for both

precision dc and ac applications, as listed in Table 8 and Table 9.

AD8510

V–

R3

50Ω

V

SS

V

L

R1

150kΩ

R2

15kΩ

I

LOAD

L

Figure 24. Programmable Current Source with Bidirectional Current Control

and High Voltage Compliance Capabilities

Rev. F | Page 12 of 20

Data Sheet

AD5543/AD5553

Table 7. Suitable Analog Devices Precision References

Maximum Temperature

Part No. Output Voltage (V) Initial Tolerance (%) Drift (ppm/°C)

I_SS(mA) Output Noise (μV p-p) Package(s)

ADR01

ADR02

ADR03

ADR06

ADR420

ADR421

ADR423

ADR425

ADR431

ADR435

ADR391

ADR395

10

5.0

2.5

3.0

2.048

2.50

3.00

5.00

2.500

5.000

2.5

0.05

0.06

0.1

0.05

0.04

0.16

0.10

3

9

3

9

3

9

3

9

3

9

1

0.5

0.8

0.12

20

10

6

SOIC-8

TSOT-5, SC70-5

SOIC-8

TSOT-5, SC70-5

SOIC-8

TSOT-5, SC70-5

SOIC-8

TSOT-5, SC70-5

SOIC-8, MSOP-8

TSOT-5

6

10

1.75

2

3.4

3.5

8

5

8

5.0

TSOT-5

Table 8. Suitable Analog Devices Precision Op Amps

_OSMaximum I_BMaximum 0.1 Hz to 10 Hz

V

Part No.

Supply Voltage (V) (μV)

(nA)

Noise (μV p-p)

Supply Current (μA) Package(s)

OP97

2 ꢀo 20

2.5 ꢀo 15

5 ꢀo 18

5 ꢀo 15

1.8 ꢀo 5

2.7 ꢀo 5

25

60

75

125

50

65

0.1

2

12

0.5

0.4

0.1

0.077

0.1

2.3

2.4

600

500

2300

3000

2000

40

SOIC-8 , PDIP-8

MSOP-8, SOIC-8

SOIC-8, SOT-23-5

TSOT-5

MSOP-8, SOIC-8

WLCSP-5, SOT-23-5

TSOT-5

OP1177

AD8675

AD8671

ADA4004-1

AD8603

AD8607

AD8605

AD8615

AD8616

90

0.001

40

1000

2000

MSOP-8, SOIC-8

Table 9. Suitable Analog Devices High Speed Op Amps

Part No.

AD8065

AD8066

AD8021

AD8038

ADA4899-1

AD8057

AD8058

AD8061

AD8062

AD9631

Supply Voltage (V) BW @ ACL (MHz)

Slew Rate (V/μs)

V_OS(Max) (μV)

1500

1000

3000

35

5000

6000

I_B(Max) (nA)

0.006

10,500

750

100

500

350

Package(s)

5 ꢀo 24

3 ꢀo 12

5 ꢀo 12

3 ꢀo 12

2.7 ꢀo 8

3 ꢀo 6

145

490

350

600

325

320

180

120

425

310

1000

850

650

1300

SOIC-8, SOT-23-5

SOIC-8, MSOP-8

SOIC-8, SC70-5

LFCSP-8, SOIC-8

SOT-23-5, SOIC-8

SOIC-8, MSOP-8

SOT-23-5, SOIC-8

SOIC-8, MSOP-8

SOIC-8, PDIP-8

6000

10,000

350

7000

Rev. F | Page 13 of 20

AD5543/AD5553

Data Sheet

EVALUATION BOARD

The EVAL-AD5543/EVAL-AD5553 is used in conjunction with

an SDP1Z system development platform board available from

Analog Devices, which is purchased separately from the

evaluation board. The USB-to-SPI communication to the

AD5543 is completed using this Blackfin-based development

board. The software offers a waveform generator.

SPORT_TFS

SPORT_TSCLK

SPORT_DTO

CS

SCLK

SDIN

SYSTEM DEVELOPMENT PLATFORM

ADSP-BF527

AD5543/AD5553

The system development platform (SDP) is a hardware and

software evaluation tool for use in conjunction with product

evaluation boards. The SDP board is based on the Blackfin

BF527 processor with USB connectivity to the PC through a

USB 2.0 high speed port. For more information about this

device, see the system development platform web page.

Figure 25. AD5543/AD5553 to SPORT Interface

WAVEFORM GENERATOR

The evaluation board software offers a waveform generator to

show every change introduced and transmitted to the output.

OPERATING THE EVALUATION BOARD

AD5543/AD5553 TO SPORT INTERFACE

The evaluation board requires 12 V and +5 V supplies. The

+12 V V_DDand V_SSare used to power the output amplifier, while

the +5 V is used to power the DAC (V_DD1).

The Analog Devices SDP has one SPORT serial port. The

SPORT interface is used to control the AD5543/AD5553,

allowing clock frequencies up to 30 MHz.

Figure 26. Evaluation Board Software—Waveform Generator

Rev. F | Page 14 of 20

Data Sheet

AD5543/AD5553

1 2 6

0

+

Figure 27. Schematic of AD5543/AD5553 Evaluation Board

Rev. F | Page 15 of 20

AD5543/AD5553

Data Sheet

BMODE1: PULL UP WITH A 10k RESISTOR TO SET SDP TO BOOT FROM A SPI FLASH ON THE DAUGHTER BOARD

J2

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

61

RESET_IN

UART_RX

GND

NC

BMODE1

UART_TX

GND

62

63

64

BOARD ID EEPROM (24LC64) MUST BE ON I2C BUS 0, ADDRESS IS AT USER DISCRETION

NC

65

SDP

STANDARD

CONNECTOR

NC

66

NC

3.3V_BF

67

NC

U4

68

NC

69

1

2

3

4

8

7

6

5

GND

NC

GND

A0

VCC

WP

SCL

SDA

70

NC

A1

71

NC

TMR_C

A2

VSS

72

*

TMR_D

TMR_B

GPIO7

73

TIMERS

TMR_A

GPIO6

GND

GPIO4

GPIO2

GPIO0

SCL_1

SDA_1

GND

74

24LC64

75

GND

76

GENERAL

INPUT/OUTPUT

GPIO5

77

GPIO3

STATUS

START

78

GPIO1

79

SCL_0

80

I2C

SDA_0

81

GND

82

MAIN I2C BUS (CONNECTED TO BLACKFIN TWI - PULL UP RESISTORS NOT REQUIRED)

SPI_SEL1/SPI_SS

SPI_SEL_C

SPI_SEL_B

GND

SPI_CLK

SPI_MISO

SPI_MOSI

SPI_SEL_A

GND

83

84

SPI

I2C BUS 1 IS COMMON ACROSS BOTH CONNECTORS ON SDP - PULL UP RESISTORS REQUIRED

(CONNECTED TO BLACKFIN GPIO - USE I2C_0 FIRST)

85

86

SPORT_INT

87

*

SPORT_DT3

SPORT_TSCLK

SPORT_DT0

SPORT_TFS

SPORT_RFS

SPORT_DR0

SPORT_RSCLK

GND

SCLK

SDIN

/CS

88

*

SPORT_DT2

89

SPORT

SPORT_DT1

SPORT_DR1

90

91

*

SPORT_DR2

92

SPORT_DR3

93

GND

94

PAR_FS1

PAR_FS3

PAR_A1

PAR_A3

GND

PAR_CLK

PAR_FS2

PAR_A0

PAR_A2

GND

PAR_INT

PAR_WR

PAR_D0

PAR_D2

PAR_D4

GND

PAR_D6

PAR_D8

PAR_D10

PAR_D12

GND

95

96

97

98

99

PAR_CS

PAR_RD

PAR_D1

PAR_D3

PAR_D5

GND

PAR_D7

PAR_D9

PAR_D11

PAR_D13

PAR_D14

GND

PAR_D17

PAR_D19

PAR_D21

PAR_D23

GND

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

PARALLEL

PORT

USB_VBUS

PAR_D15

*

PAR_D16

*

PAR_D18

8

3.3V_BF

*

PAR_D20

7

PAR_D22

6

GND

VIO(+3.3V)

GND

5

VIO: USE TO SET IO VOLTAGE MAX DRAW 20mA

USB_VBUS

GND

NC

VIN

4

VIN: USE THIS PIN TO POWER THE SDP

REQUIRES 4-7V 200mA

3

GND

2

NC

1

*NC ON BLACKFIN SDP

Figure 28. Schematic of SDP Interface

Rev. F | Page 16 of 20

Data Sheet

AD5543/AD5553

Figure 29. Silkscreen—Component Side View (Top Layer)

Figure 30 Component Side Artwork

Figure 31. Solder Side Artwork

Rev. F | Page 17 of 20

AD5543/AD5553

Data Sheet

BILL OF MATERIALS

Table 10.

Name

CS

Part Description

Value

PCB Decal

Testpoint

RTAJ_A

C0603

RTAJ_B

C0603

RTAJ_B

C0603

Part Description

Testpoint

Red testpoint

AGND

C1

C2

C3

C4

C5

C6

C7

C8

Testpoint

Black testpoint

Capacitor+

Capacitor

Capacitor+

Capacitor

Capacitor+

Capacitor

Capacitor+

Capacitor

Ground link

CON\POWER5

SDP-STANDARD-CONN

SMB

10 µF

0.1 µF

5.6 pF

10 µF

0.1 µF

10 µF

0.1 µF

10 µF

0.1 µF

10 µF

0.1 µF

10 V SMD tantalum capacitor

50 V X7R ceramic capacitor

Multilayer ceramic capacitor

16 V tantalum capacitor

50 V X7R ceramic capacitor

16 V tantalum capacitor

50 V X7R ceramic capacitor

16 V tantalum capacitor

50 V X7R ceramic capacitor

RTAJ_B

C0603

C0805

C9

C10

C11

C12

GL1

J1

J2

J3

J4

10 V 10 µF ceramic capacitor 10% X5R 0805

50 V X7R ceramic capacitor

Copper short

C0603

Component link

CON\POWER5

CON-120/FX8-120S-SV

SMB

5-pin terminal block

120-way connector, 0.6 mm pitch, receptacle

Straight PCB mount SMB jack—50 Ω

Red testpoint

Digital-to-analog converter

5 V reference

SMB

Testpoint

AD5543/AD5553

ADR435

SMB

SCLK

SDIN

U1

Testpoint

SO8NB

U2

SO8NB

U3

AD8038

SO8NB

Single op amp 8-pin

U4

24LC64

Testpoint

MTHOLE-3MM

MSO8

64K I2C serial EEPROM MSOP8

Black testpoint

Red testpoint

3 mm NPTH hole

USB_VBUS

VOUT

VREF

X1

Testpoint

MTHOLE-3MM

X2

3 mm NPTH hole

Rev. F | Page 18 of 20

Data Sheet

AD5543/AD5553

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

1

5

4

5.15

4.90

4.65

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.65 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.80

0.55

0.40

0.15

0.05

0.23

0.09

6°

0°

0.40

0.25

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 32. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

5.00 (0.1968)

4.80 (0.1890)

8

1

5

4

6.20 (0.2441)

5.80 (0.2284)

4.00 (0.1574)

3.80 (0.1497)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

BSC

45°

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.10 (0.0040)

8°

0°

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 33. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters and (inches)

Rev. F | Page 19 of 20

AD5543/AD5553

Data Sheet

ORDERING GUIDE

Model^{1, 2}

AD5543CRMZ

AD5543CRMZ-REEL7

AD5543BR

AD5543BRZ

AD5543BRM

AD5543BRM-REEL7

AD5543BRMZ

AD5543BRMZ-REEL7

AD5553CRM

AD5553CRM-REEL7

AD5553CRMZ

INL (LSB)

RES (LSB)

Temperature Range

−40°C to +85°C

Package Description

8-Lead MSOP

8-Lead SOIC_N

8-Lead MSOP

Evaluation Board

Package Option

Branding

DEV

1

2

1

16

14

RM-8

R-8

RM-8

DXB

DXB#

DUC

DUC#

AD5553CRMZ-REEL7

EVAL-AD5543SDZ

¹The AD5543 contains 1040 transistors. The die size measures 55 mil × 73 mil or 4,015 sq. mil.

²Z = RoHS Compliant Part, # denotes RoHS-compliant product may be top or bottom marked.

registered trademarks are the property of their respective owners.

D02917-0-1/12(F)

Rev. F | Page 20 of 20


型号：	AD5543CRMZ
厂家：	ADI
描述：	Current Output/Serial Input, 16-/14-Bit DACs 电流输出/串行输入， 16位/ 14位DAC 转换器数模转换器光电二极管 PC
文件：	总20页 (文件大小：582K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5543CRMZ [ADI]

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