AD5557 [ADI]
Dual Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with 4-Quadrant Resistors; 双路电流输出，并行输入， 16位/ 14位乘法数模转换器与4象限电阻
| 型号： | AD5557 |
| 厂家： | 
ADI |
| 描述： | Dual Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with 4-Quadrant Resistors |
| 文件： | 总20页 (文件大小：652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Current Output, Parallel Input, 16-/14-Bit
Multiplying DACs with 4-Quadrant Resistors
AD5547/AD5557
FEATURES
Dual channel
FUNCTIONAꢀ BꢀOCK DIAGRAM
R
R
V
R
1A
COMA
REFA
OFSA
16-bit resolution: AD5547
14-bit resolution: AD5557
R
FBA
V
DD
2- or 4-quadrant, 4 MHz BW multiplying DAC
1 ꢀSB DNꢀ
1 ꢀSB INꢀ for AD5557, 2 ꢀSB INꢀ for AD5547
Operating supply voltage: 2.7 V to 5.5 V
ꢀow noise: 12 nV/√Hz
DAC A
REGISTER
RS
D0..D15
OR
D0..D13
INPUT
REGISTER
I
DAC A
DAC B
D0–D15
(AD5547)
D0–D13
OUTA
RS
AGNDA
(AD5557)
AGNDB
DAC B
REGISTER
RS
INPUT
REGISTER
ꢀow power: IDD = 10 µA max
0.5 µs settling time
I
OUTB
RS
DAC A
DAC B
WR
Built-in RFB facilitates current-to-voltage conversion
Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V,
or 10 V outputs
2 mA full-scale current 20ꢁ, with VREF = 10 V
Extended automotive operating temperature range:
–40°C to +125°C
R
FBB
R
OFSB
POWER
ON
RESET
A0, A1
ADDR
DECODE
AD5547/AD5557
DGND
RS MSB
LDAC
R
R
V
REFB
1B
COMB
Figure 1.
Selectable zero-scale/midscale power-on presets
Compact TSSOP-38 package
APPꢀICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Digital waveform generation
The built-in 4-quadrant resistors facilitate resistance matching
and temperature tracking, which minimize the numbers of
components needed for multiquadrant applications. In addition,
the feedback resistor (RFB) simplifies the I-V conversion with an
external buffer.
GENERAꢀ DESCRIPTION
The AD5547/AD5557 are dual precision, 16-/14-bit,
multiplying, low power, current-output, parallel input, digital-
to-analog converters. They are designed to operate from single
+5 V supply with 1ꢀ V multiplying references for 4-quadrant
outputs with up to 4 MHz bandwidth.
The AD5547/AD5557 are available in a compact TSSOP-38
package and operate at the extended automotive temperature
range of –4ꢀ°C to +125°C.
VREF
U1
–VREF
C1
R
R
V
R
R
FBA
1A
COMA
REFA
OFSA
C2
ROFS RFB
R1
R2
U2
IOUTA
VOUTA
16-/14-BIT
DAC A
AD5547/AD5557
16/14 DATA
AGNDA
–VREF TO +VREF
POWER-ON
RESET
WR LDAC RS
MSB A0, A1
(ONE CHANNEL SHOWN ONLY)
WR
LDAC
RS
MSB
A0, A1
2
Figure 2. 16/14-Bit 4-Quadrant Multiplying DAC with Minimum of External Components (Only One Channel Shown)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5547/AD5557
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 9
Circuit Operation ........................................................................... 12
D/A Converter Section.............................................................. 12
Digital Section............................................................................. 13
PCB Layout, Power Supply Bypassing, and Ground
Connections................................................................................ 13
Applications..................................................................................... 14
Unipolar Mode ........................................................................... 14
Bipolar Mode .............................................................................. 16
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
Revision ꢀ: Initial Version
Rev. 0 | Page 2 of 20
AD5547/AD5557
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, IOUT = Virtual GND, GND = ꢀ V, VREF = –1ꢀ V to +1ꢀ V, TA = –4ꢀ°C to +125°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter
Symbol
N
Conditions
Min Typ
Max
Unit
STATIC PERFORMANCE1
Resolution
AD5547, 1 LSB = VREF/216 = 153 µV at VREF = 10 V
AD5557, 1 LSB = VREF/214 = 610 µV at VREF = 10 V
Grade: AD5557C
Grade: AD5547B
Monotonic
Data = zero scale, TA = 25°C
Data = zero scale, TA = TA maximum
Data = full scale
Data = full scale
Data = full scale
16
14
Bits
Bits
LSB
LSB
LSB
nA
nA
mV
mV
mV
Relative Accuracy
INL
1
2
1
10
20
4
Differential Nonlinearity
Output Leakage Current
DNL
IOUT
Full-Scale Gain Error
Bipolar Mode Gain Error
Bipolar Mode Zero-Scale Error
Full-Scale Tempco2
GFSE
GE
GZSE
TCVFS
1
1
1
4
3
1
ppm/°C
REFERENCE INPUT
VREF Range
VREF
REF
R1 and R2
∆(R1 to R2)
RFB, ROFS
CREF
–18
4
4
+18
6
6
1.5
12
V
REF Input Resistance
R1 and R2 Resistance
R1-to-R2 Mismatch
Feedback and Offset Resistance
Input Capacitance2
5
5
kΩ
kΩ
Ω
kΩ
pF
0.5
8
10
5
ANALOG OUTPUT
Output Current
IOUT
COUT
Data = full scale
Code dependent
2
200
mA
pF
Output Capacitance2
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
VIL
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
0.8
0.4
V
V
V
V
Logic Input High Voltage
VIH
2.4
2.1
Input Leakage Current
Input Capacitance2
IIL
CIL
10
10
µA
pF
INTERFACE TIMING2, 3
Data to WR Setup Time
tDS
tDH
tWR
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
20
35
0
ns
ns
ns
ns
ns
Data to WR Hold Time
WR Pulse Width
0
20
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
35
20
35
20
35
0
ns
ns
ns
ns
ns
ns
ns
LDAC Pulse Width
RS Pulse Width
tLDAC
tRS
WR to LDAC Delay Time
tLWD
0
SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current
Power Dissipation
VDD RANGE
IDD
PDISS
PSS
2.7
5.5
10
V
µA
Logic inputs = 0 V
Logic inputs = 0 V
∆VDD = 5ꢀ
0.055 mW
0.003 ꢀ/ꢀ
Power Supply Sensitivity
Rev. 0 | Page 3 of 20
AD5547/AD5557
Parameter
AC CHARACTERISTICS4
Symbol
Conditions
Min Typ
Max
Unit
Output Voltage Settling Time
tS
To 0.1ꢀ of full scale, data cycles from zero scale
to full scale to zero scale
0.5
µs
Reference Multiplying BW
DAC Glitch Impulse
Multiplying Feedthrough Error
Digital Feedthrough
BW
Q
VOUT/VREF
QD
VREF = 5 V p-p, data = full scale
VREF = 0 V, midscale to midscale – 1
VREF = 100 mV rms, f = 10 kHz
WR = 1, LDAC toggles at 1 MHz
VREF = 5 V p-p, data = full scale, f = 1 kHz
f = 1 kHz, BW = 1 Hz
4
7
–65
7
MHz
nV-s
dB
nV-s
dB
Total Harmonic Distortion
Output Noise Density
Analog Crosstalk
THD
eN
–85
12
–95
nV/√Hz
dB
CAT
Signal input at Channel A and measure the output
at Channel B, f = 1 kHz
1 All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP97 I-V converter amplifier. The device RFB terminal is tied
to the amplifier output. The OP97’s +IN pin is grounded, and the DAC’s IOUT is tied to the OP97’s –IN pin. Typical values represent average readings measured at 25°C.
2 Guaranteed by design; not subject to production testing.
3 All input control signals are specified with tR = tF = 2.5 ns (10ꢀ to 90ꢀ of 3 V), and are timed from a voltage level of 1.5 V.
4 All ac characteristic tests are performed in a closed-loop system using an AD841 I-V converter amplifier.
tWR
WR
DATA
tDH
tDS
tLWD
LDAC
tLDAC
tRS
RS
Figure 3. AD5547/AD5557 Timing Diagram
Rev. 0 | Page 4 of 20
AD5547/AD5557
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VDD to GND
RFB, ROFS, R1, RCOM, and VREF to GND
Logic Inputs to GND
V(IOUT) to GND
Input Current to Any Pin except Supplies
Thermal Resistance (θJA)1
Maximum Junction Temperature (TJ MAX
Operating Temperature Range
Storage Temperature Range
Lead Temperature
–0.3 V, +8 V
–18 V, 18 V
–0.3 V, +8 V
–0.3 V, VDD + 0.3 V
50 mA
)
150°C
–40°C to +125°C
–65°C to +150°C
1 Package power dissipation = (TJ MAX – TA)/θJA.
Vapor Phase, 60 s
Infrared, 15 s
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 20
AD5547/AD5557
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC
NC
1
2
3
4
5
6
7
8
9
38 D0
37 D1
D1
1
2
3
4
5
6
7
8
9
38 D2
37 D3
36 D4
35 D5
34 D6
33 D7
32 D8
31 D9
30 D10
29 VDD
28 D11
27 D12
26 D13
25 D14
24 D15
D0
36
D2
R
R
OFSA
OFSA
35 D3
34 D4
33 D5
32 D6
31 D7
30 D8
29 VDD
28 D9
27 D10
26 D11
25 D12
24 D13
R
R
FBA
FBA
R
R
1A
COMA
1A
COMA
R
R
V
V
REFA
REFA
I
I
OUTA
OUTA
AD5557
AD5547
AGNDA
AGNDA
DGND 10
TOP VIEW
(Not to Scale)
DGND 10
TOP VIEW
(Not to Scale)
AGNDB 11
AGNDA 11
I
12
13
14
15
16
17
I
12
13
14
15
16
17
OUTB
OUTB
V
V
REFB
REFB
R
R
COMB
COMB
R
R
1B
1B
23
RS
23
RS
R
R
FBB
FBB
22 MSB
21 LDAC
20 A1
22 MSB
21 LDAC
20 A1
R
R
OFSB
OFSB
WR 18
A0 19
WR 18
A0 19
NC = NO CONNECT
Figure 4. AD5547 TSSOP-38 Pin Configuration
Figure 5. AD5557 TSSOP-38 Pin Configuration
Table 3. AD5547 Pin Function Descriptions
Pin No.
Mnemonic Function
1, 2, 24–
D0–D15
Digital Input Data Bits D0 to D15. Signal level must be ≤ VDD + 0.3 V.
28, 30–38
3
ROFSA
Bipolar Offset Resistor A. Accepts up to 18 V. In 2-quadrant mode, ROFSA ties to RFBA. In 4-quadrant mode, ROFSA
ties to R1A and the external reference.
4
5
RFBA
R1A
Internal Matching Feedback Resistor A. Connects to the external op amp for I-V conversion.
4-Quandrant Resistor. In 2-quadrant mode, R1A shorts to the VREFA pin. In 4-quadrant mode, R1A ties to ROFSA. Do
not connect when operating in unipolar mode.
6
7
RCOMA
Center Tap Point of the Two 4-Quadrant Resistors, R1A and R2A. In 4-quadrant mode, RCOMA ties to the inverting
node of the reference amplifier. In 2-quadrant mode, RCOMA shorts to the VREF pin. Do not connect if operating in
unipolar mode.
DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, VREFA is the
reference input with constant input resistance versus code. In 4-quadrant mode, VREFA is driven by the external
reference amplifier.
VREFA
8
IOUTA
DAC A Current Output. Connects to the inverting terminal of external precision I-V op amp for voltage output.
9
AGNDA
DGND
AGNDB
IOUTB
DAC A Analog Ground.
Digital Ground.
DAC B Analog Ground.
10
11
12
13
DAC B Current Output. Connects to inverting terminal of external precision I-V op amp for voltage output.
DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance versus code. If
VREFB
configured with an external op amp for 4-quadrant multiplying, VREFB becomes –VREF
.
14
15
RCOMB
Center Tap Point of the Two 4-Quadrant Resistors, R1B and R2B. In 4-quadrant mode, RCOMB ties to the inverting
node of the reference amplifier. In 2-quadrant mode, RCOMB shorts to the VREF pin. Do not connect if operating in
unipolar mode.
4-Quandrant Resistor. In 2-quadrant mode, R1B shorts to the VREFB pin. In 4-quadrant mode, R1B ties to ROFSB. Do not
connect if operating in unipolar mode.
R1B
16
17
RFBB
ROFSB
Internal Matching Feedback Resistor B. Connects to external op amp for I-V conversion.
Bipolar Offset Resistor B. Accepts up to 18 V. In 2-quadrant mode, ROFSB ties to RFBB. In 4-quadrant mode, ROFSB
ties to R1B and an external reference.
Rev. 0 | Page 6 of 20
AD5547/AD5557
Pin No.
Mnemonic Function
18
WR
Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge.
Signal level must be ≤ VDD + 0.3 V.
19
20
21
22
A0
A1
LDAC
MSB
Address Pin 0. Signal level must be ≤ VDD + 0.3 V.
Address Pin 1. Signal level must be ≤ VDD + 0.3 V.
Digital Input Load DAC Control. Signal level must be ≤ VDD + 0.3 V.
Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The
signal level must be ≤ VDD + 0.3 V.
23
29
RS
Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0, and to midscale if MSB = 1. Signal
level must be ≤ VDD + 0.3 V.
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
VDD
Table 4. AD5557 Pin Function Descriptions
Pin No. Mnemonic Function
1, 2
3
NC
ROFSA
No Connection. Do not connect anything other than dummy pads to these pins.
Bipolar Offset Resistor A. Accepts up to 18 V. In 2-quadrant mode, ROFSA ties to RFBA. In 4-quadrant mode, ROFSA ties
to R1A and the external reference.
4
5
RFBA
R1A
Internal Matching Feedback Resistor A. Connects to the external op amp for I-V conversion.
4-Quandrant Resistor. In 2-quadrant mode, R1A shorts to the VREFA pin. In 4-quadrant mode, R1A ties to ROFSA. Do not
connect when operating in unipolar mode.
6
7
RCOMA
Center Tap Point of the Two 4-Quadrant Resistors, R1A and R2A. In 4-quadrant mode, RCOMA ties to the inverting node
of the reference amplifier. In 2-quadrant mode, RCOMA shorts to the VREF pin. Do not connect if operating in
unipolar mode.
DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, VREFA is the
reference input with constant input resistance versus code. In 4-quadrant mode, VREFA is driven by the external
reference amplifier.
VREFA
8
IOUTA
DAC A Current Output. Connects to the inverting terminal of external precision I-V op amp for voltage output.
9
AGNDA
DGND
AGNDB
IOUTB
DAC A Analog Ground.
Digital Ground.
DAC B Analog Ground.
10
11
12
13
DAC B Current Output. Connects to inverting terminal of external precision I-V op amp for voltage output.
DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance versus code. If configured
VREFB
with an external op amp for 4-quadrant multiplying, VREFB becomes –VREF
.
14
15
RCOMB
Center Tap Point of the Two 4-Quadrant Resistors, R1B and R2B. In 4-quadrant mode, RCOMB ties to the inverting node
of the reference amplifier. In 2-quadrant mode, RCOMB shorts to the VREF pin. Do not connect if operating in
unipolar mode.
4-Quandrant Resistor. In 2-quadrant mode, R1B shorts to the VREFB pin. In 4-quadrant mode, R1B ties to ROFSB. Do not
connect if operating in unipolar mode.
R1B
16
17
RFBB
ROFSB
Internal Matching Feedback Resistor B. Connects to external op amp for I-V conversion.
Bipolar Offset Resistor B. Accepts up to 18 V. In 2-quadrant mode, ROFSB ties to RFBB. In 4-quadrant mode, ROFSB ties
to R1B and an external reference.
18
WR
Write Control Digital Input In, Active Low. Transfers shift register data to the DAC register on the rising edge. Signal
level must be ≤ VDD + 0.3 V.
19
20
21
22
A0
A1
LDAC
MSB
Address Pin 0. Signal level must be ≤ VDD + 0.3 V.
Address Pin 1. Signal level must be ≤ VDD + 0.3 V.
Digital Input Load DAC Control. Signal level must be ≤ VDD + 0.3 V.
Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The signal
level must be ≤ VDD + 0.3 V.
23
RS
Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0, and to midscale if MSB = 1. Signal
level must be ≤ VDD + 0.3 V.
24–28,
30–38
29
D13 to D0
VDD
Digital Input Data Bits D13 to D0. Signal level must be ≤ VDD + 0.3 V.
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
Rev. 0 | Page 7 of 20
AD5547/AD5557
Table 5. Address Decoder Pins
A1
A0
Output Update
DAC A
0
0
0
1
None
1
1
0
1
DAC A and B
DAC B
Table 6. Control Inputs
RS WR
ꢀDAC Register Operation
0
1
1
1
1
X
0
1
0
X
0
1
1
Reset the output to 0 with MSB pin = 0; reset the output to midscale with MSB pin = 1.
Load the input register with data bits.
Load the DAC register with the contents of the input register.
The input and DAC registers are transparent.
When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on
the falling edge of the pulse, and are then loaded into the DAC register on the rising edge of the pulse.
No register operation.
1
1
0
Rev. 0 | Page 8 of 20
AD5547/AD5557
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE (Decimal)
0
2048 4096
6144
8192 10240 12288 14336 16384
CODE (Decimal)
Figure 9. AD5557 Differential Nonlinearity Error
Figure 6. AD5547 Integral Nonlinearity Error
1.0
0.8
1.5
1.0
V
= 2.5V
= 25°C
REF
T
A
0.6
0.4
0.5
0.2
INL
0
0
DNL
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
GE
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE (Decimal)
2
4
6
8
10
SUPPLY VOLTAGE V (V)
DD
Figure 10. Linearity Error vs. VDD
Figure 7. AD5547 Differential Nonlinearity Error
5
4
3
2
1.0
0.8
V
T
= 5V
= 25°C
DD
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
IH
4.0
4.5
5.0
0
2048
4096
6144
8192 10240 12288 14336 16384
LOGIC INPUT VOLTAGE V (V)
CODE (Decimal)
Figure 11. Supply Current vs. Logic Input Voltage
Figure 8. AD5557 Integral Nonlinearity Error
Rev. 0 | Page 9 of 20
AD5547/AD5557
3.0
2.5
2.0
1.5
1.0
0.5
0
LDAC (5V/DIV)
0x5555
0x8000
V
V
= 5V
DD
= 10V
REF
CODES 0x8000 ↔0x7FFF
0xFFFF
0x0000
V
(50mV/DIV)
OUT
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10k
100k
1M
CLOCK FREQUENCY (Hz)
10M
100M
TIME (µs)
Figure 15. AD5547 Midscale Transition and Digital Feedthrough
Figure 12. AD5547 Supply Current vs. Clock Frequency
REF LEVEL
0.000dB
/DIV
12.000dB
MARKER 4 41 677.200Hz
MAG (A/R) –2.939db
90
80
70
60
50
40
30
20
10
0
0xFFFF
0x8000
0x4000
0x2000
0x1000
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
V
V
= 5V ± 10%
REF
DD
–12dB
–24dB
–36dB
–48dB
–60dB
–72dB
–84dB
–96dB
–108dB
= 10V
0x0000
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
START 10.000Hz
STOP 50 000 000.000Hz
Figure 13. Power Supply Rejection Ratio vs. Frequency
Figure 16. AD5547 Unipolar Reference Multiplying Bandwidth
REF LEVEL
0.000dB
/DIV
12.000dB
0
ALL BITS ON
D15 AND D14 ON
D15 AND D13 ON
D15 AND D12 ON
D15 AND D11 ON
D15 AND D10 ON
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
LDAC
1
2
D15 AND D9 ON
D15 AND D8 ON
D15 AND D7 ON
D15 AND D6 ON
D15 AND D5 ON
D15 AND D4 ON
D15 AND D3 ON
D15 AND D2 ON
D15 AND D1 ON
V
OUT
CH1 5.00V CH2 2.00V M 200ns
A CH1 2.70V
B CH1 –6.20V
400.00ns
D15 AND D0 ON
D15 ON
10
100
1k
10k
100k
1M
10M
Figure 14. Settling Time from Full Scale to Zero Scale
START 10.000Hz
STOP 10 000 000.000Hz
Figure 17. AD5547 Bipolar Reference Multiplying Bandwidth (Codes from
Midscale to Full Scale)
Rev. 0 | Page 10 of 20
AD5547/AD5557
REF LEVEL
0.000dB
/DIV
12.000dB
0
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
ALL BITS OFF
D14 ON
D14 AND D13 ON
D14 AND D12 ON
D14 AND D11 ON
D14 AND D10 ON
D14 AND D9 ON
D14 AND D8 ON
D14 AND D7 ON
D14 AND D6 ON
D14 AND D5 ON
D14 AND D4 ON
D14 AND D3 ON
D14 AND D2 ON
D14 AND D1 ON
D14 AND D0 ON
D14 ON
10
100
1k
10k
100k
1M
10M
START 10.000Hz
STOP 10 000 000.000Hz
Figure 18. AD5547 Bipolar Reference Multiplying Bandwidth (Codes from
Midscale to Zero Scale)
Rev. 0 | Page 11 of 20
AD5547/AD5557
CIRCUIT OPERATION
D/A CONVERTER SECTION
the variation of the AD5547/AD5557 output impedance. The
feedback resistance in parallel with the DAC ladder resistance
dominates output voltage noise. To maintain good analog
performance, it is recommended that the power supply is
bypassed with a ꢀ.ꢀ1 µF to ꢀ.1 µF ceramic or chip capacitor in
parallel with a 1 µF tantalum capacitor. Also, to minimize gain
error, PCB metal traces between VREF and RFB should match.
The AD5547/AD5557 are 16-/14-bit, multiplying, current
output, parallel input DACs. The devices operate from a single
2.7 V to 5.5 V supply, and provide both unipolar (ꢀ V to –VREF
or ꢀ V to +VREF), and bipolar ( VREF) output ranges from –18 V
to +18 V references. In addition to the precision conversion RFB
commonly found in current output DACs, there are three addi-
tional precision resistors for 4-quadrant bipolar applications.
Every code change of the DAC corresponds to a step function;
gain peaking at each output step may occur if the op amp has
limited GBP and excessive parasitic capacitance present at the
op amp’s inverting node. A compensation capacitor, therefore,
may be needed between the I-V op amp inverting and output
nodes to smooth the step transition. Such a compensation
capacitor should be found empirically, but a 2ꢀ pF capacitor is
generally adequate for the compensation.
The AD5547/AD5557 consist of two groups of precision R-2R
ladders, which make up the 12/1ꢀ LSBs, respectively. Further-
more, the 4 MSBs are decoded into 15 segments of resistor value
2R. Figure 19 shows the architecture of the 16-bit AD5547. Each
of the 16 segments and the R-2R ladder carries an equally
weighted current of one-sixteenth of full scale. The feedback
resistor RFB and 4-quadrant resistor ROFS have values of 1ꢀ kΩ.
Each 4-quadrant resistor, R1 and R2, equals 5 kΩ. In 4-quadrant
operation, R1, R2, and an external op amp work together to
invert the reference voltage and apply it to the VREF input.
With ROFS and RFB connected as shown in Figure 2, the output
The VDD power is used primarily by the internal logic to drive
the DAC switches. Note that the output precision degrades if the
operating voltage falls below the specified voltage. Users should
also avoid using switching regulators because device power
supply rejection degrades at higher frequencies.
can swing from –VREF to +VREF
.
The reference voltage inputs exhibit a constant input resistance
of 5 kΩ 2ꢀ0. The impedance of IOUT, the DAC output, is code
dependent. External amplifier choice should take into account
V
REF
2R
2R
2R
2R
80kΩ
R2
5kΩ
80kΩ 80kΩ 80kΩ
RCOM
R1
R1
5kΩ
4 MSB
15 SEGMENTS
R
R
R
R
R
R
R
R
40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ 40kΩ
2R 2R 2R 2R 2R 2R 2R 2R 2R
80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ 80kΩ
8-BIT R2R
ROFS
RFB
RA
RB
R
R
R
R
2R
2R
2R
2R
2R
80kΩ 80kΩ 80kΩ 80kΩ 80kΩ
10kΩ 10kΩ
4-BIT R2R
IOUT
AGND
15
8
4
ADDRESS DECODER
LDAC
LDAC
WR
DAC REGISTER
RS
RS
RS
INPUT REGISTER
WR
D15 D14
D0
Figure 19. 16-Bit AD5547 Equivalent R-2R DAC Circuit with Digital Section, One Channel Shown
Rev. 0 | Page 12 of 20
AD5547/AD5557
The voltage reference temperature coefficient and long-term
drift are primary considerations. For example, a 5 V reference
with a TC of 5 ppm/°C means the output changes by 25 µV/°C.
As a result, a reference operating at 55°C contributes an
additional 75ꢀ µV full-scale error.
DIGITAꢀ SECTION
The AD5547/AD5557 have 16-/14-bit parallel inputs. The
devices are double-buffered with 16-/14-bit registers. The dou-
ble-buffered feature allows the simultaneous update of several
AD5547/AD5557s. For the AD5547, the input register is loaded
WR
directly from a 16-bit controller bus when
is brought low.
Similarly, the same 5 V reference with a 5ꢀ ppm long-term
drift means the output may change by 25ꢀ µV over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
The DAC register is updated with data from the input register
when LDAC is brought high. Updating the DAC register
updates the DAC output with the new data (see Figure 19). To
low and LDAC high.
pin resets the part to zero scale if the
MSB pin = ꢀ, and to midscale if the MSB pin = 1.
WR
make both registers transparent, tie
PCB ꢀAYOUT, POWER SUPPꢀY BYPASSING, AND
GROUND CONNECTIONS
RS
The asynchronous
It is a good practice to employ a compact, minimum-lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and VDD, as shown in Figure 2ꢀ. As
a result, the voltage level of the logic input should not be greater
than the supply voltage.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error.
V
DD
It is also essential to bypass the power supply with quality
capacitors for optimum stability. Supply leads to the device
should be bypassed with ꢀ.ꢀ1 µF to ꢀ.1 µF disc or chip ceramic
capacitors. Low ESR 1 µF to 1ꢀ µF tantalum or electrolytic
capacitors should also be applied at the supply in parallel with
the ceramic capacitor to minimize transient disturbance and
filter out low frequency ripple.
DIGITAL
INPUTS
5kΩ
DGND
Figure 20. Equivalent ESD Protection Circuits
To minimize the digital ground bounce, the AD5547/AD5557
DGND terminal should be joined with the AGND terminal at a
single point. Figure 21 illustrates the basic supply-bypassing
configuration and AGND/DGND connection for the
AD5547/AD5557.
Amplifier Selection
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. A 3ꢀ nA input
bias current in the op amp contributes to 1 LSB in the AD5547’s
full-scale error. The OP1177 and AD8628 op amps are good
candidates for the I-V conversion.
V
DD
+
5V
–
C2
C1
Reference Selection
AD5547/AD5557
AGND
1µF
0.1µF
The initial accuracy and rated output of the voltage reference
determine the full-span adjustment. The initial accuracy of the
reference is usually a secondary concern because it can be
trimmed. Figure 26 shows an example of a trimming circuit.
The zero-scale error can also be minimized by standard op amp
nulling techniques.
DGND
Figure 21. Power Supply Bypassing
Rev. 0 | Page 13 of 20
AD5547/AD5557
APPLICATIONS
UNIPOꢀAR MODE
2-Quadrant Multiplying Mode, VOUT = 0 V to –VREF
In this case, the output voltage polarity is opposite the VREF
polarity (see Figure 22). Table 7 shows the negative output
versus code for the AD5547.
The AD5547/AD5557 DAC architecture uses a current-steering
R-2R ladder design that requires an external reference and op
amp to convert the unipolar mode of output voltage to
Table 7. AD5547 Unipolar Mode Negative Output vs. Code
D in Binary
VOUT (V)
V
V
OUT = –VREF × D/65,536 (AD5547)
OUT = –VREF × D/16,384 (AD5557)
(1)
(2)
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
–VREF(65,535/65,536)
–VREF/2
–VREF(1/65,536)
0
where D is the decimal equivalent of the input code.
+5V
2
U3 ADR03
5
C1
1µF
C2
0.1µF
VIN
TRIM
VOUT
GND
6
+2.5V
V
REFA
4
R
R
R
R
FBA
1A
COMA
OFSA
2.2pF
C6
VDD
ROFS
RFB
R1
R2
C3
0.1µF
2.5V
16-/14-BIT
I
OUTA
V
+V
AD5547/AD5557
OUTA
AD8628
–V
AGNDA
U1
–2.5V TO 0V
16/14 DATA
C4
WR LDAC RS MSB A0, A1
0.1µF
C5
WR
LDAC
RS
2
1µF
–5V
MSB
A0, A1
Figure 22. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 to –VREF
Rev. 0 | Page 14 of 20
AD5547/AD5557
Table 8 shows the positive output versus code for the AD5547.
2-Quadrant Multiplying Mode, VOUT = 0 V to +VREF
The AD5547/AD5557 are designed to operate with either
positive or negative reference voltages. As a result, a positive
output can be achieved with an additional op amp, (see
Figure 23); the output becomes
Table 8. AD5547 Unipolar Mode Positive Output vs. Code
D in Binary
VOUT (V)
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
+VREF(65,535/65,536)
+VREF/2
+VREF(1/65,536)
0
V
V
OUT = +VREF × D/65,536 (AD5547)
OUT = +VREF × D/16,384 (AD5557)
(3)
(4)
+5V
C1
2
U3
C2
1µF
U2A
1µF
VIN
5
6
TRIM
VOUT
GND
AD8628
C7
–2.5V
4
ADR03
+2.5V
+5V
1µF
C5 0.1µF
C4
R
R
V
R
R
1A
R1
COMA
REFA
OFSA
FBA
C6
U2B
VDD
ROFS
RFB
R2
C3
0.1µF
I
OUTA
+V
16-/14-BIT
V
OUTA
AD8628
–V
AGNDA
AD5547/AD5557
16/14 DATA
0V TO +2.5V
WR LDAC RS MSB A0, A1
WR
LDAC
RS
2
MSB
A0, A1
Figure 23. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 to +VREF
Rev. 0 | Page 15 of 20
AD5547/AD5557
+15V
2
U3
C1
C2
1µF
0.1µF
VIN
5
6
TRIM
VOUT
GND
U2A
4
ADR01
AD8512
C8
–10V
REFA
+10V
R
R
V
R
R
1A
COMA
OFSA
FBA
+5V
C4 1µF
VDD
ROFS
RFB
+15V
U2B
R1
R2
C9
C5 0.1µF
C3
0.1µF
I
OUTA
AD5547/AD5557
16-/14-BIT
DAC A
+V
VOUT
AD8512
–V
U1
AGNDA
16/14 DATA
–10V TO +10V
C6 0.1µF
C7 1µF
WR
LDAC RS MSB A0, A1
WR
LDAC
RS
2
–15V
MSB
A0, A1
Figure 24. 4-Quadrant Multiplying Mode, VOUT = –VREF to +VREF
BIPOꢀAR MODE
4-Quadrant Multiplying Mode, VOUT = –VREF to +VREF
Table 9. AD5547 Output vs. Code
D in Binary
VOUT
The AD5547/AD5557 contain on-chip all the 4-quadrant
resistors necessary for precision bipolar multiplying operation.
Such a feature minimizes the number of exponent components
to only a voltage reference, dual op amp, and compensation
capacitor (see Figure 24). For example, with a +1ꢀ V reference,
the circuit yields a precision, bipolar –1ꢀ V to +1ꢀ V output.
Table 9 shows some of the results for the 16-bit AD5547.
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+VREF (32,767/32,768)
+VREF (1/32,768)
0
–VREF (1/32,768)
–VREF
V
V
OUT = (D/32768 − 1) × VREF (AD5547)
OUT = (D/16384 − 1) × VREF (AD5557)
(5)
(6)
Rev. 0 | Page 16 of 20
AD5547/AD5557
AC Reference Signal Attenuator
System Calibration
Besides handling the digital waveform decoded from the
parallel input data, the AD5547/AD5557 can also handle low
frequency ac reference signals for signal attenuation, channel
equalization, and waveform generation applications. The
maximum signal range can be up to 18 V (See Figure 25).
The initial accuracy of the system can be adjusted by trimming
the voltage reference ADRꢀx with a digital potentiometer (see
Figure 26). The AD517ꢀ provides a one-time programmable
(OTP), 8-bit adjustment that is ideal and reliable for such
calibration. ADI’s OTP digital potentiometer comes with
programmable software that simplifies factory calibration.
U2A
OP2177
C7
+10V
–10V
+15V
C4
C5 0.1µF
1µF
R
R
R
FBA
R
V
REFA
1A
OFSA
COMA
C6
+5V
R1
U2B
VDD
R2
ROFS
RFB
C1
1µF
C2
0.1µF
I
OUTA
16-/14-BIT
V
+V
AD5547/AD5557
OUTA
OP2177
–V
AGNDA
U1
16/14 DATA
C8 1µF
C9 0.1µF
WR LDAC RS MSB A0, A1
WR
LDAC
RS
2
MSB
–15V
A0, A1
Figure 25. Signal Attenuator with AC Reference
+5V
C1
1µF
2
AD5170
U4
U3
C2
0.1µF
VIN
R3
5
6
10kΩ
TRIM
470kΩ
B
VOUT
GND
U2
R7 1kΩ
AD8628
4
ADR03
–2.5V
C7
+2.5V
+5V
C4
1µF
R
R
R
R
V
REFA
1A
OFSA
FBA
COMA
C6
C5 0.1µF
U2B
R1
VDD
R2
ROFS
RFB
C3
0.1µF
I
OUTA
V
16-/14-BIT
+V
AD5547/AD5557
OUTA
AD8628
–V
AGNDA
U1
0V TO +2.5V
16/14 DATA
WR LDAC RS MSB A0, A1
WR
LDAC
RS
MSB
2
REF 01/AD
A0, A1
Figure 26. Full-Span Calibration
Rev. 0 | Page 17 of 20
AD5547/AD5557
Table 1ꢀ lists the latest DACS available from Analog Devices.
Table 10. ADI Current Output DACs
Model
Bits Outputs Interface
Package
MSOP-10
MSOP-10
SOT23-8
TSSOP-16
TSSOP-16
TSSOP-20
MSOP-10
SOT23-8
TSSOP-20
TSSOP-16
TSSOP-24
MSOP-10
SOT23-8
TSSOP-20
MSOP-10
TSSOP-16
TSSOP-24
TSSOP-24
LFCSP-40
SOT23-8
MSOP-8
Comments
AD5425
AD5426
AD5450
AD5424
AD5429
AD5428
AD5432
AD5451
AD5433
AD5439
AD5440
AD5443
AD5452
AD5445
AD5444
AD5449
AD5415
AD5447
AD5405
AD5453
AD5553
AD5556
AD5446
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
8
1
1
1
1
2
2
1
1
1
2
2
1
1
1
1
2
2
2
2
1
1
1
1
2
2
1
1
2
2
SPI, 8-Bit Load
SPI
Fast 8-bit load; see also AD5426.
See also AD5425 fast load.
See also AD5425 fast load.
8
8
SPI
8
8
Parallel
SPI
8
Parallel
SPI
10
10
10
10
10
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
SPI
Parallel
SPI
Parallel
SPI
SPI
Parallel
SPI
SPI
See also AD5452 and AD5444.
Higher accuracy version of AD5443; see also AD5444.
Higher accuracy version of AD5443; see also AD5452.
Uncommitted resistors.
SPI
Parallel
Parallel
SPI
SPI
Parallel
SPI
SPI
Parallel
SPI
Parallel
SPI
Parallel
Uncommitted resistors.
TSSOP-28
MSOP-10
TSSOP-16
TSSOP-38
MSOP-8
TSSOP-28
TSSOP-16
TSSOP-38
MSOP version of AD5453; compatible with AD5443, AD5432, and AD5426.
Rev. 0 | Page 18 of 20
AD5547/AD5557
OUTLINE DIMENSIONS
9.80
9.70
9.60
38
20
19
4.50
4.40
4.30
6.40 BSC
1
PIN 1
1.20
MAX
0.15
0.05
8°
0°
0.50
BSC
0.27
0.17
0.70
0.60
0.45
SEATING
PLANE
0.20
0.09
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153BD-1
Figure 27. 38-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-38)
Dimension s shown in millimeters
ORDERING GUIDE
Resolution DNꢀ
INꢀ
Temperature
Ordering
Quantity Package Description
Package
Option
Model
(Bits)
(ꢀSB) (ꢀSB) Range
AD5547BRU
16
1
1
1
1
2
2
1
1
–40°C to +125°C 50
–40°C to +125°C 1,000
–40°C to +125°C 50
–40°C to +125°C 1,000
Thin Shrink Small Outline Package (TSSOP) RU-38
Thin Shrink Small Outline Package (TSSOP) RU-38
Thin Shrink Small Outline Package (TSSOP) RU-38
Thin Shrink Small Outline Package (TSSOP) RU-38
AD5547BRU-REEL7 16
AD5557CRU 14
AD5557CRU-REEL7 14
Rev. 0 | Page 19 of 20
AD5547/AD5557
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04452–0–4/04(0)
Rev. 0 | Page 20 of 20
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