AD5612 [ADI]
2.7 V to 5.5 V, <100 uA, 8-/10-/12-Bit nanoDACs with; 2.7 V至5.5 V ， \u003c 100微安， 8位/ 10位/ 12位nanoDACs与
| 型号： | AD5612 |
| 厂家： | 
ADI |
| 描述： | 2.7 V to 5.5 V, <100 uA, 8-/10-/12-Bit nanoDACs with |
| 文件： | 总24页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit nanoDACs® with
I2C®-Compatible Interface, Tiny SC70 Package
AD5602/AD5612/AD5622
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
Single 8-, 10-, 12-bit DACs, 2 LSB INL
6-lead SC70 package
DD
GND
POWER-ON
RESET
Micropower operation: 100 μA max @ 5 V
Power-down to <150 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
AD5602/AD5612/AD5622
REF(+)
DAC
REGISTER
OUTPUT
BUFFER
V
8-/10-/12-BIT
DAC
OUT
I2C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
On-chip output buffer amplifier, rail-to-rail operation
APPLICATIONS
ADDR
SCL SDA
Process control
Figure 1.
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Table 1. Related Devices
Part No.
AD5601/AD5611/AD5621 2.7 V to 5.5 V, <100 μA, 8-, 10-, 12-bit
nanoDAC with SPI® interface in a
Description
tiny SC70 package
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD5602/AD5612/AD5622, members of the nanoDAC
family, are single 8-, 10-, 12-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply, consuming <100 μA
at 5 V. These DACs come in tiny SC70 packages. Each DAC
contains an on-chip precision output amplifier that allows rail-
to-rail output swing to be achieved.
1. Available in a 6-lead SC70 package.
2. Maximum 100 μA power consumption, single-supply
operation. These parts operate from a single 2.7 V to 5.5 V
supply, typically consuming 0.2 mW at 3 V and 0.4 mW at
5 V, making them ideal for battery-powered applications.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/μs.
The AD5602/AD5612/AD5622 use a 2-wire I2C-compatible
serial interface that operates in standard (100 kHz), fast
(400 kHz), and high speed (3.4 MHz) modes.
4. Reference derived from the power supply.
5. Standard, fast, and high speed mode I2C interface.
6. Designed for very low power consumption.
The references for AD5602/AD5612/AD5622 are derived from
the power supply inputs to give the widest dynamic output range.
Each part incorporates a power-on reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place to the device. The parts contain a power-down
feature that reduces the current consumption of the devices to
<150 nA at 3 V and provides software-selectable output loads
while in power-down mode. The parts are put into power-down
mode over the serial interface. The low power consumption of
the AD5602/AD5612/AD5622 in normal operation makes them
ideally suited for use in portable battery-operated equipment. The
typical power consumption is 0.4 mW at 5 V.
7. Power-down capability. When powered down, the DAC
typically consumes <150 nA at 3 V.
8. Power-on reset and brownout detection.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD5602/AD5612/AD5622
TABLE OF CONTENTS
Features .............................................................................................. 1
Resistor String............................................................................. 15
Output Amplifier........................................................................ 15
Serial Interface ................................................................................ 16
Input Register.............................................................................. 16
Power-On Reset.......................................................................... 17
Power-Down Modes .................................................................. 17
Write Operation.......................................................................... 18
Read Operation........................................................................... 19
High Speed Mode....................................................................... 20
Applications..................................................................................... 21
Choosing a Reference as Power Supply................................... 21
Bipolar Operation....................................................................... 21
Power Supply Bypassing and Grounding................................ 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
I2C Timing Specifications............................................................ 4
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
D/A Section................................................................................. 15
REVISION HISTORY
3/06—Rev. A to Rev. B
Changes to Table 2............................................................................ 3
Updates to Outline Dimensions ................................................... 22
Changes to Ordering Guide .......................................................... 23
8/05—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 22
6/05—Revision 0: Initial Version
Rev. B | Page 2 of 24
AD5602/AD5612/AD5622
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A, B, W, Y Versions1
Parameter
STATIC PERFORMANCE
Resolution
AD5602
Min
Typ
Max
Unit
Test Conditions/Comments
DAC output unloaded
Bits
8
AD5612
AD5622
Relative Accuracy2
10
12
AD5602
AD5612
0.5
0.5
4
LSB
LSB
LSB
B, Y versions
B, Y versions
A version
AD5622
2
LSB
B, Y versions
6
1
10
10
LSB
LSB
mV
mV
A, W versions
Guaranteed monotonic by design
All 0s loaded to DAC register
Differential Nonlinearity2
Zero Code Error
Offset Error
Full-Scale Error
Gain Error
Zero Code Error Drift
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS3
Output Voltage Range
Output Voltage Settling Time
Slew Rate
0.5
0.063
0.5
0.0004
5
2
mV
All 1s loaded to DAC register
0.037
% of FSR
μV/°C
ppm of FSR/°C
0
VDD
10
V
μs
V/μs
pF
pF
6
Code ¼ to ¾
0.5
470
1000
120
2
Capacitive Load Stability
RL = ∞
RL = 2 kΩ
Output Noise Spectral Density
Noise
nV/Hz
DAC code = midscale, 10 kHz
DAC code = midscale, 0.1 Hz to 10 Hz
bandwidth
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short Circuit Current
5
nV-s
nV-s
Ω
1 LSB change around major carry
0.2
0.5
15
mA
VDD = 3 V/5 V
LOGIC INPUTS (SDA, SCL)
IIN, Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
VHYST, Input Hysteresis
LOGIC OUTPUTS (OPEN DRAIN)
VOL, Output Low Voltage
1
μA
V
V
pF
V
0.3 × VDD
0.7 × VDD
0.1 × VDD
2
2
0.4
0.6
1
V
V
μA
pF
ISINK = 3 mA
ISINK = 6 mA
Floating-State Leakage Current
Floating-State Output Capacitance
Rev. B | Page 3 of 24
AD5602/AD5612/AD5622
A, B, W, Y Versions1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.7
5.5
V
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
DAC active and excluding load current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
75
60
100
90
μA
μA
0.3
0.15
1
1
μA
μA
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
96
%
ILOAD = 2 mA, VDD = 5 V
1 Temperature ranges for A, B versions: −40°C to +125°C, typical at 25°C.
2 Linearity calculated using a reduced code range 64 to 4032.
3 Guaranteed by design and characterization, not production tested.
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1
Table 3.
Limit at TMIN, TMAX
Parameter
Conditions2
Min
Max
100
400
3.4
Unit
KHz
KHz
MHz
MHz
μs
μs
ns
ns
μs
μs
ns
ns
ns
ns
ns
μs
μs
Description
3
fSCL
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Serial clock frequency
tHIGH, SCL high time
tLOW, SCL low time
1.7
t1
4
Fast mode
0.6
60
120
4.7
1.3
160
320
250
100
10
0
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
t2
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
t3
t4
tSU;DAT, data setup time
tHD;DAT, data hold time
3.45
0.9
Fast mode
0
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
0
0
70
150
ns
ns
μs
μs
ns
μs
μs
ns
t5
t6
t7
4.7
0.6
160
4
0.6
160
4.7
tSU;STA, set-up time for a repeated start condition
tHD;STA, hold time (repeated) start condition
μs
tBUF, bus free time between a stop and a start
condition
Fast mode
1.3
μs
Rev. B | Page 4 of 24
AD5602/AD5612/AD5622
Limit at TMIN, TMAX
Parameter
Conditions2
Min
Max
Unit
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
t8
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
4
0.6
160
tSU;STO, setup time for a stop condition
t9
1000
300
80
160
300
300
80
160
1000
300
40
tRDA, rise time of SDA signal
10
20
t10
t11
t11A
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
10
20
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
10
20
80
1000
tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
Fast mode
300
80
160
300
300
40
80
50
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
10
20
t12
tFCL, fall time of SCL signal
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Fast mode
10
20
0
4
tSP
Pulse width of spike suppressed
High speed mode
0
1 See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the
AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622-2.
2 CB refers to the capacitance on the bus line.
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
TIMING DIAGRAM
t11
t12
t6
t2
t6
SCL
t1
t3
t5
t10
t8
t4
t9
SDA
t7
P
S
S
P
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. B | Page 5 of 24
AD5602/AD5612/AD5622
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
–0.3 V to + 7.0 V
Digital Input Voltage to GND
VOUT to GND
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
Operating Temperature Range
Extended Automotive (W, Y Versions)
Extended Industrial (A, B Versions)
–40°C to +125°C
−40°C to +85°C
–65°C to +160°C
150°C
Storage Temperature Range
Maximum Junction Temperature
SC70 Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
332°C/W
120°C/W
215°C
220°C
2.0 kV
ESD
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 24
AD5602/AD5612/AD5622
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADDR
1
2
3
6
5
4
V
OUT
AD5602/
AD5612/
AD5622
SCL
GND
TOP VIEW
(Not to Scale)
SDA
V
DD
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
ADDR
SCL
SDA
Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6).
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register.
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input register. It
is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
4
5
6
VDD
GND
VOUT
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND.
Ground. The ground reference point for all circuitry on the part.
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Rev. B | Page 7 of 24
AD5602/AD5612/AD5622
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.05
0.04
0.03
0.02
V
T
= 5V
V
T
= 5V
DD
= 25°C
DD
= 25°C
0.8
0.6
0.4
0.2
0
A
A
0.01
0
–0.01
–0.02
–0.03
–0.2
–0.4
–0.6
–0.8
–1.0
–0.04
–0.05
0
500
1000
1500 2000 2500 3000
DAC CODE
3500 4000
0
200
400
DAC CODE
600
800
1000
Figure 4. Typical AD5622 Integral Nonlinearity Error
Figure 7. Typical AD5612 Differential Nonlinearity Error
0.15
0.10
0.05
0
0.06
V
= 5V
V
= 5V
DD
= 25°C
DD
T = 25°C
A
T
A
0.04
0.02
0
–0.05
–0.10
–0.02
–0.04
–0.06
–0.15
–0.20
0
500
1000
1500 2000 2500 3000
DAC CODE
3500 4000
0
50
100
150
200
250
DAC CODE
Figure 5. Typical AD5622 Differential Nonlinearity Error
Figure 8. Typical AD5602 Integral Nonlinearity Error
0.25
0.015
0.010
0.005
0
V
T
= 5V
V
T
= 5V
DD
= 25°C
DD
= 25°C
0.20
0.15
0.10
0.05
0
A
A
–0.05
–0.10
–0.15
–0.005
–0.010
–0.015
–0.20
–0.25
0
200
400
600
800
1000
0
50
100
DAC CODE
150
200
250
DAC CODE
Figure 9. Typical AD5602 Differential Nonlinearity Error
Figure 6. Typical AD5612 Integral Nonlinearity Error
Rev. B | Page 8 of 24
AD5602/AD5612/AD5622
1
0
0.5
V
= 5V
T = 25°C
A
DD
= 25°C
T
A
0.4
0.3
–1
–2
–3
–4
–5
MAX DNL
0.2
0.1
0
–0.1
MIN DNL
–6
–7
–0.2
–0.3
0
500
1000
1500 2000 2500 3000
DAC CODE
3500 4000
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
DD
Figure 10. Typical AD5622 Total Unadjusted Error
Figure 13. AD5622 DNL Error vs. Supply
0.5
0.8
0.6
0.4
0.2
0
T
= 25°C
A
MAX INL
0.4
0.3
MAX INL = 5V
MAX INL = 3V
0.2
0.1
0
–0.2
–0.4
–0.1
MIN INL = 5V
MIN INL = 3V
MIN INL
4.2
–0.2
–0.3
–0.6
–0.8
–40
–20
0
20
40
60
80
100
120
2.7
3.2
3.7
4.7
5.2
TEMPERATURE (°C)
V
(V)
DD
Figure 14. AD5622 INL Error vs. Temperature (3 V/5 V Supply)
Figure 11. AD5622 INL Error vs. Supply
8
0
T
= 25°C
A
MAX TUE = 5V
7
–1
–2
–3
–4
–5
–6
MAX TUE
6
5
MAX TUE = 3V
MIN TUE = 5V
4
3
2
MIN TUE
–7
–8
1
0
MIN TUE = 3V
–40
–20
0
20
40
60
80
100
120
2.7
3.2
3.7
4.2
(V)
4.7
5.2
TEMPERATURE (°C)
V
DD
Figure 15. AD5622 Total Unadjusted Error vs. Temperature (3 V/5 V Supply)
Figure 12. AD5622 Total Unadjusted Error vs. Supply
Rev. B | Page 9 of 24
AD5602/AD5612/AD5622
0.6
1.8
1.6
1.4
1.2
1.0
0.8
0.5
OFFSET ERROR = 3V
0.4
MAX DNL = 5V
0.3
0.2
MAX DNL = 3V
0.1
0
0.6
0.4
OFFSET ERROR = 5V
MIN DNL = 5V
MIN DNL = 3V
–0.1
–0.2
–0.3
0.2
0
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. AD5622 DNL Error vs. Temperature (3 V/5 V Supply)
Figure 19. Offset Error vs. Temperature (3 V/5 V Supply)
4
0.00025
0.00020
0.00015
0.00010
GAIN ERROR = 3V
ZERO CODE ERROR = 3V
ZERO CODE ERROR = 5V
2
0
–2
–4
GAIN ERROR = 5V
FULL-SCALE ERROR = 3V
–6
0.00005
0
–8
FULL-SCALE ERROR = 5V
–10
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. Gain Error vs. Temperature (3 V/5 V Supply)
Figure 17. Zero Code/Full-Scale Error vs. Temperature (3 V/5 V Supply)
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
1
T
= 25°C
A
0
–1
–2
–3
–4
ZERO CODE ERROR
T
= 25°C
A
–5
–6
FULL-SCALE ERROR
–7
–8
2.7
3.2
3.7
4.2
(V)
4.7
5.2
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
V
DD
DD
Figure 18. Zero Code/Full-Scale Error vs. Supply Voltage
Figure 21. Supply Current vs. Supply Voltage
Rev. B | Page 10 of 24
AD5602/AD5612/AD5622
12
10
8
V
V
V
= 3V
V
V
V
= 5V
DD
IH
DD
IH
= V
= V
DD
DD
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
= GND
= 25°C
= GND
= 25°C
IL
A
IL
A
T
T
V
= 5V
DD
6
V
= 3V
DD
4
2
0
–40
–20
0
20
40
60
80
100
120
140
I
(µA)
TEMPERATURE (°C)
DD
Figure 22. Supply Current vs. Temperature (3 V/5 V Supply)
Figure 25. IDD Histogram (3 V/5 V Supply)
70
60
50
40
30
20
10
0
0.8
0.6
V
= 5V
= 25°C
T
= 25°C
DD
A
V
= 5V
= 3V
DD
T
A
DAC LOADED WITH ZERO-SCALE CODE
0.4
V
DD
0.2
0.0
–0.2
–0.4
–0.6
DAC LOADED WITH FULL-SCALE CODE
0
2000 4000 6000 8000 10000 12000 14000 16000
DAC CODE
–15
–10
–5
0
5
10
15
I (mA)
Figure 23. Supply Current vs. Digital Input Code
Figure 26. Sink and Source Capability
900
800
700
600
500
400
300
200
SCL/SDA INCREASING
V
DD
V
= 5V
DD
= 25°C
V
= 5V
DD
T
A
SCL/SDA DECREASING
= 5V
V
DD
CH1
SCL/SDA
INCREASING
V
= 3V
SCL/SDA DECREASING
= 3V
DD
V
= 70mV
OUT
V
DD
100
0
CH2
0
0.5
1.0
1.5
2.0
V
2.5
LOGIC
3.0
(V)
3.5
4.0
4.5
5.0
CH1 = 1V/DIV, CH2 = 20mV/DIV, TIME BASE = 20µs/DIV
Figure 24. Supply Current vs. SCL/SDA Logic Voltage
Figure 27. Power-On Reset to 0 V
Rev. B | Page 11 of 24
AD5602/AD5612/AD5622
CH1
V
DD
V
= 5V
DD
T
= 25°C
A
V
= 5V
DD
= 25°C
T
A
CH1
CH2
CH2
V
OUT
CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2µs/DIV
CH1 = 1V/DIV, CH2 = 3V/DIV, TIME BASE = 50µs/DIV
Figure 28. Exiting Power-Down Mode
Figure 31. VOUT vs. VDD
2.458
2.456
2.454
2.452
2.450
2.448
2.446
2.444
2.442
2.440
2.438
2.436
V
= 5V
DD
= 25°C
T
A
CH1
V
T
= 5V
DD
= 25°C
A
LOAD = 2kΩ AND 220pF
CODE 0x800 TO 0x7FF
10ns/SAMPLE NUMBER
CH2
CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2µs/DIV
0
100
200
300
400
500
SAMPLE NUMBER
Figure 32. Digital-to-Analog Glitch Impulse
Figure 29. Full-Scale Settling Time
2.4278
2.4276
2.4274
2.4272
2.4270
2.4268
2.4266
2.4264
V
= 5V
DD
= 25°C
T
A
LOAD = 2kΩ AND 220pF
10ns/SAMPLE NUMBER
V
= 5V
DD
= 25°C
T
A
CH1
CH2
2.4262
2.4260
0
100
200
300
400
500
CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2µs/DIV
SAMPLE NUMBER
Figure 33. Digital Feedthrough
Figure 30. Half-Scale Settling Time
Rev. B | Page 12 of 24
AD5602/AD5612/AD5622
700
600
500
400
300
200
100
0
V
= 5V
DD
= 25°C
V
= 5V
DD
T = 25°C
A
T
A
UNLOADED OUTPUT
MIDSCALE LOADED
CH1
ZERO SCALE
MIDSCALE
FULL SCALE
CH1 = 5µV/DIV
100
1000
10000
100000
FREQUENCY (Hz)
Figure 34. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth
Figure 35. Output Noise Spectral Density
Rev. B | Page 13 of 24
AD5602/AD5612/AD5622
TERMINOLOGY
Relative Accuracy
Gain Error
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 4.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
Total unadjusted error is a measure of the output error taking
all the various errors into account. A typical TUE vs. code plot
can be seen in Figure 10.
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 5.
Zero Code Error Drift
Zero code error drift is a measure of the change in zero code
error with a change in temperature. It is expressed in μV/°C.
Zero Code Error
Gain Error Drift
Zero-code error is due to a combination of the offset errors in
the DAC and output amplifier; it is a measure of the output
error when zero code (0x0000) is loaded to the DAC register.
Ideally, the output should be 0 V. The zero-code error is always
positive in the AD5602/AD5612/AD5622 because the output of
the DAC cannot go below 0 V. Zero-code error is expressed in
mV. A plot of zero-code error vs. temperature can be seen in
Figure 17.
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s and
is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FFF to 0x8000) (see Figure 32).
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register; it is expressed in
Digital Feedthrough
percent of full-scale range. Ideally, the output should be VDD
–
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-s and measured with a full-scale code change on
the data bus, that is, from all 0s to all 1s, and vice versa
(see Figure 33).
1 LSB. A plot of full-scale error vs. temperature can be seen in
Figure 17.
Rev. B | Page 14 of 24
AD5602/AD5612/AD5622
THEORY OF OPERATION
D/A SECTION
R
The AD5602/AD5612/AD5622 DACs are fabricated on a
CMOS process. The architecture consists of a string DACs
followed by an output buffer amplifier. Figure 36 shows a block
diagram of the DAC architecture.
R
R
V
TO OUTPUT
AMPLIFIER
DD
REF (+)
RESISTOR
NETWORK
V
DAC REGISTER
OUT
REF (–)
OUTPUT
AMPLIFIER
GND
R
R
Figure 36. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
D
2n
⎛
⎜
⎞
⎟
VOUT = VDD
×
Figure 37. Resistor String Structure
⎝
⎠
OUTPUT AMPLIFIER
where:
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to VDD. It is
capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 26. The slew rate is 0.5 V/μs with a half-
scale settling time of 5 μs with the output unloaded.
D is the decimal equivalent of the binary code that is loaded
to the DAC register; it can range from 0 to 255 (AD5602),
0 to 1023 (AD5612), or 0 to 4095 (AD5622).
n is the bit resolution of the DAC.
RESISTOR STRING
The resistor string structure is shown in Figure 37. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
Rev. B | Page 15 of 24
AD5602/AD5612/AD5622
SERIAL INTERFACE
The AD5602/AD5612/AD5622 have 2-wire I2C-compatible
serial interfaces (refer to I2C-Bus Specification, Version 2.1,
January 2000, available from Philips Semiconductor). The
AD5602/AD5612/AD5622 can be connected to an I2C bus as a
slave device, under the control of a master device. See Figure 2
for a timing diagram of a typical write sequence.
3. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master then brings the SDA line low
before the 10th clock pulse, and then high during the 10th
clock pulse to establish a stop condition.
The AD5602/AD5612/AD5622 support standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) data transfer modes.
Support is not provided for 10-bit addressing and general call
addressing.
Table 6. Device Address Selection
ADDR
A1
A0
1
GND
1
VDD
0
1
0
0
The AD5602/AD5612/AD5622 each have a 7-bit slave address.
The five MSBs are 00011 and the two LSBs are determined by
the state of the ADDR pin. The facility to make hardwired
changes to ADDR allows the user to incorporate up to three of
these devices on one bus as outlined in Table 6.
NC (No Connection)
INPUT REGISTER
The input register is 16 bits wide. Figure 38, Figure 39, and
Figure 40 illustrate the contents of the input register for each
part. Data is loaded into the device as a 16-bit word under the
control of a serial clock input, SCL. The timing diagram for this
operation is shown in Figure 2. The 16-bit word consists of four
control bits followed by 8, 10, or 12 bits of data, depending on
the device type. MSB (DB15) is loaded first. The first two bits
are reserved bits that must be set to zero, the next two bits are
control bits that select the mode of operation of the device
(normal mode or any one of three power-down modes). See the
Power-Down Modes section for a complete description. The
remaining bits are left-justified DAC data bits, starting with the
MSB and ending with the LSB.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address.
The slave address corresponding to the transmitted address
responds by pulling SDA low during the ninth clock pulse
(this is termed the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device
waits for data to be written to, or read from, its shift register.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
DB15 (MSB)
DB0 (LSB)
0
0
PD1
PD1
PD1
PD0
PD0
PD0
D7
D6
D5
D4
D3
D2
D1
D0
D2
D4
X
X
X
X
DATA BITS
Figure 38. AD5602 Input Register Contents
DB15 (MSB)
DB0 (LSB)
0
0
D9
D8
D7
D6
D5
D4
D3
D1
D0
X
X
DATA BITS
Figure 39. AD5612 Input Register Contents
DB15 (MSB)
DB0 (LSB)
0
0
D11
D10
D9
D8
D7
D6
D5
D3
D2
D1
D0
DATA BITS
Figure 40. AD5622 Input Register Contents
Rev. B | Page 16 of 24
AD5602/AD5612/AD5622
POWER-ON RESET
When both bits are set to 0, the part works normally with its
usual power consumption of 100 μA maximum at 5 V. However,
for the three power-down modes, the supply current falls to
<150 nA (at 3 V). Not only does the supply current fall, but the
output stage is internally switched from the output of the
amplifier to a resistor network of known values. This gives the
advantage of knowing the output impedance of the part while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through a
1 kΩ resistor, a 100 kΩ resistor, or it is left open-circuited
(three-state). Figure 41 shows the output stage.
The AD5602/AD5612/AD5622 each contain a power-on reset
circuit that controls the output voltage during power-up. The
DAC register is filled with zeros and the output voltage is 0 V
where it remains until a valid write sequence is made to the
DAC. This is useful in applications where it is important to
know the state of the DAC output while it is in the process of
powering up.
POWER-DOWN MODES
The AD5602/AD5612/AD5622 each contain four separate
modes of operation. These modes are software-programmable
by setting Bit PD1 and Bit PD0 in the control register. Table 7
shows how the state of the bits corresponds to the mode of
operation of the device.
RESISTOR
AMPLIFIER
V
OUT
STRING DAC
Table 7. Modes of Operation
PD1
PD0
Operating Mode
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
0
0
1
1
0
1
0
1
Normal operation
Power-down (1 kΩ load to GND)
Power-down (100 kΩ load to GND)
Power-down (Three-state output)
Figure 41. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are all shut down when the power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 14 μs for VDD = 5 V and 17 μs for VDD
3 V (see Figure 28).
=
Rev. B | Page 17 of 24
AD5602/AD5612/AD5622
Two bytes of data are then written to the DAC, the most
significant byte followed by the least significant byte as shown in
Figure 39; both of these data bytes are acknowledged by the
AD5602/AD5612/AD5622. A stop condition follows. The write
operations for the three DACs are shown in Figure 42, Figure 43,
and Figure 44.
WRITE OPERATION
When writing to the AD5602/AD5612/AD5622, the user must
begin with a start command followed by an address byte (R/
0), after which the DAC acknowledges that it is prepared to
receive data by pulling SDA low.
W
=
1
9
1
9
SCL
0
0
0
0
0
1
1
A1
A0
R/W
0
0
PD1
PD0
D7
D6
D5
D4
SDA
START BY
ACK. BY
AD5602
ACK. BY
AD5602
MASTER
FRAME 1
FRAME 2
SERIAL BUS ADDRESS BYTE
MOST SIGNIFICANT DATA BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D3
D2
D1
D0
X
X
X
X
ACK. BY STOP BY
AD5602 MASTER
FRAME 3
LEAST SIGNIFICANT DATA BYTE
Figure 42. AD5602 Write Sequence
1
9
1
9
SCL
0
0
1
1
A1
A0
R/W
0
0
PD1
PD0
D9
D8
D7
D6
SDA
START BY
ACK. BY
AD5612
ACK. BY
AD5612
MASTER
FRAME 1
FRAME 2
SERIAL BUS ADDRESS BYTE
MOST SIGNIFICANT DATA BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D5
D4
D3
D2
D1
D0
X
X
ACK. BY STOP BY
AD5612 MASTER
FRAME 3
LEAST SIGNIFICANT DATA BYTE
Figure 43. AD5612 Write Sequence
1
9
1
9
SCL
0
0
1
1
A1
A0
R/W
0
0
PD1
PD0
D11
D10
D9
D8
SDA
START BY
ACK. BY
AD5622
ACK. BY
AD5622
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY STOP BY
AD5622 MASTER
FRAME 3
LEAST SIGNIFICANT DATA BYTE
Figure 44. AD5622 Write Sequence
Rev. B | Page 18 of 24
AD5602/AD5612/AD5622
READ OPERATION
prepared to transmit data by pulling SDA low. Two bytes of data
are then read from the DAC, which are both acknowledged by
the master as shown in Figure 45, Figure 46, and Figure 47. A
stop condition follows.
When reading data back from the AD5602/AD5612/AD5622,
the user begins with a start command followed by an address
byte (R/ = 1), after which the DAC acknowledges that it is
W
1
9
1
9
SCL
0
0
0
0
0
1
1
A1
A0
R/W
PD1
PD0
D7
D6
D5
D4
D3
D2
SDA
START BY
ACK. BY
AD5602
ACK. BY
MASTER
MASTER
FRAME 1
FRAME 2
SERIAL BUS ADDRESS BYTE
MOST SIGNIFICANT DATA BYTE FROM AD5602
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D1
D0
0
0
0
0
0
0
NO ACK. BY STOP BY
MASTER MASTER
FRAME 3
LEAST SIGNIFICANT DATA BYTE FROM AD5602
Figure 45. AD5602 Read Sequence
1
9
1
9
SCL
0
0
1
1
A1
A0
R/W
PD1
PD0
D9
D8
D7
D6
D5
D4
SDA
START BY
ACK. BY
AD5612
ACK. BY
MASTER
MASTER
FRAME 1
FRAME 2
SERIAL BUS ADDRESS BYTE
MOST SIGNIFICANT DATA BYTE FROM AD5612
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D3
D2
D1
D0
0
0
0
0
NO ACK. BY STOP BY
MASTER MASTER
FRAME 3
LEAST SIGNIFICANT DATA BYTE FROM AD5612
Figure 46. AD5612 Read Sequence
1
9
1
9
SCL
0
0
1
1
A1
A0
R/W
PD1
PD0
D11
D10
D9
D8
D7
D6
SDA
START BY
ACK. BY
AD5622
ACK. BY
MASTER
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM AD5622
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D5
D4
D3
D2
D1
D0
0
0
NO ACK. BY STOP BY
MASTER MASTER
FRAME 3
LEAST SIGNIFICANT DATA BYTE FROM AD5622
Figure 47. AD5622 Read Sequence
Rev. B | Page 19 of 24
AD5602/AD5612/AD5622
followed by a no acknowledge. The master must then issue a
repeated start followed by the device address. The selected
device then acknowledges its address. All devices continue to
operate in high speed mode until the master issues a stop
condition. When the stop condition is issued, the devices return
to standard/fast mode.
HIGH SPEED MODE
High speed mode communication commences after the master
addresses all devices connected to the bus with the Master
Code 00001XXX to indicate that a high speed mode transfer is
to begin. No device connected to the bus is permitted to
acknowledge the high speed master code, therefore, the code is
FAST MODE
1
HIGH-SPEED MODE
9
1
9
SCL
SDA
START BY
0
0
0
0
1
X
X
X
0
0
0
1
1
A1
A0
R/W
NACK. SR
ACK. BY
AD56x2
MASTER
HS-MODE MASTER CODE
SERIAL BUS ADDRESS BYTE
Figure 48. Placing the AD5602/AD5612/AD5622 into High Speed Mode
Rev. B | Page 20 of 24
AD5602/AD5612/AD5622
APPLICATIONS
CHOOSING A REFERENCE AS POWER SUPPLY
With VDD = 5 V, R1 = R2 = 10 kΩ
The AD5602/AD5612/AD5622 come in tiny SC70 packages
with less than 100 μA supply current, thereby making the
choice of reference dependent upon the application
requirement. For space-saving applications, the ADR425 is
available in an SC70 package with excellent drift at 3ppm/°C. It
also provides very good noise performance at 3.4 μV p-p in the
0.1 Hz to 10 Hz range.
10× D
⎛
⎜
⎞
⎟
VO
=
− 5 V
2n
⎝
⎠
This is an output voltage range of 5 V with 0x000 corresponding
to a −5 V output, and 0xFFF corresponding to a +5 V output.
R2
10kΩ
+5V
R1
10kΩ
+5V
Because the supply current required by the AD5602/AD5612/
AD5622 DACs is extremely low, they are ideal for low supply
applications. The ADR293 voltage reference is recommended in
this case. This requires 15 μA of quiescent current and can
therefore drive multiple DACs in the one system, if required.
AD820/
OP295
±5V OUT
AD5602/
AD5612/
AD5622
V
V
OUT
DD
10µF
0.1µF
–5V
SDA SCL
7V
Figure 50. Bipolar Operation with the AD5602/AD5612/AD5622
5V
ADR425
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5602/
AD5612/AD5622 should have separate analog and digital
sections, each having its own area of the board. If the AD5602,
AD5612, or AD5622 is in a system where other devices require
an AGND to DGND connection, the connection should be
made at one point only. This ground point should be as close as
possible to the AD5602/AD5612/AD5622.
AD5602/
V
= 0V TO 5V
OUT
SCL
SDA
AD5612/
AD5622
Figure 49. ADR425 as Power Supply
Examples of some recommended precision references for use as
supplies to the AD5602/AD5612/AD5622 are shown in Table 8.
Table 8. Recommended Precision References
Initial
Accuracy
Temperature
Drift
The power supply to the AD5602/AD5612/AD5622 should be
bypassed with 10 μF and 0.1 μF capacitors. The capacitors
should be physically as close as possible to the device with the
0.1 μF capacitor ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. It is important that the
0.1 μF capacitor has low effective series resistance (ESR) and
effective series inductance (ESI), such as common ceramic
types. This 0.1 μF capacitor provides a low impedance path to
ground for high frequencies caused by transient currents due to
internal logic switching.
Part
No.
0.1 Hz to 10 Hz Noise
(mV max) (ppm/°C max) (μV p-p typ)
ADR435
ADR425
ADR02
6
6
5
6
3
3
3
25
3.4
3.4
15
5
ADR395
BIPOLAR OPERATION
The AD5602/AD5612/AD5622 have been designed for single-
supply operation, but a bipolar output range is also possible
using the circuit in Figure 50. The circuit in Figure 50 gives an
output voltage range of 5 V. Rail-to-rail operation at the
amplifier output is achievable using an AD820 or an OP295 as
the output amplifier.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique where the component side of the
board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, the microstrip
technique is not always possible with a 2-layer board.
The output voltage for any input code can be calculated as
⎡
⎤
D
2n
R1+ R2
R2
R1
⎛
⎜
⎞ ⎛
⎞
⎟
⎛
⎜
⎞
⎟
VO = VDD
×
×
−V
×
⎟ ⎜
DD
⎢
⎥
⎦
R1
⎝
⎠ ⎝
⎠
⎝
⎠
⎣
where:
D represents the input code in decimal.
n represents the bit resolution of the DAC.
Rev. B | Page 21 of 24
AD5602/AD5612/AD5622
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.46
0.36
0.26
0.30
0.15
0.22
0.08
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 51. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
Rev. B | Page 22 of 24
AD5602/AD5612/AD5622
ORDERING GUIDE
I2C Interface
Modes
Temperature
Range
Power Supply Package Package
Model
AD5602YKSZ-1500RL71
INL (max) Supported
Range
Option
Description
Branding
0.5 LSB
Standard, fast and
−40°C to +125°C
2.7 V to 5.5 V
KS-6
6-Lead SC70
D5W
high speed
Standard, fast and
high speed
AD5602YKSZ-1REEL71
0.5 LSB
−40°C to +125°C
2.7 V to 5.5 V
KS-6
6-Lead SC70
D5W
AD5602BKSZ-2500RL71
AD5602BKSZ-2REEL71
AD5602YKSZ-2500RL71
AD5602YKSZ-2REEL71
AD5612YKSZ-1500RL71
0.5 LSB
0.5 LSB
0.5 LSB
0.5 LSB
0.5 LSB
Standard, fast
Standard, fast
Standard, fast
Standard, fast
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
KS-6
KS-6
KS-6
KS-6
KS-6
6-Lead SC70
6-Lead SC70
6-Lead SC70
6-Lead SC70
6-Lead SC70
D5X
D5X
D5Y
D5Y
D5T
Standard, fast, and −40°C to +125°C
high speed
Standard, fast, and −40°C to +125°C
high speed
AD5612YKSZ-1REEL71
0.5 LSB
2.7 V to 5.5 V
KS-6
6-Lead SC70
D5T
AD5612BKSZ-2500RL71
AD5612BKSZ-2REEL71
AD5612AKSZ-2500RL71
AD5612AKSZ-2REEL71
AD5612YKSZ-2500RL71
AD5612YKSZ-2REEL71
AD5622YKSZ-1500RL71
0.5 LSB
0.5 LSB
4 LSB
Standard, fast
Standard, fast
Standard, fast
Standard, fast
Standard, fast
Standard, fast
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
KS-6
6-Lead SC70
6-Lead SC70
6-Lead SC70
6-Lead SC70
6-Lead SC70
6-Lead SC70
6-Lead SC70
D5U
D5U
D60
D60
D5S
D5S
D5M
4 LSB
0.5 LSB
0.5 LSB
2 LSB
Standard, fast, and −40°C to +125°C
high speed
Standard, fast, and −40°C to +125°C
high speed
AD5622YKSZ-1REEL71
2 LSB
2.7 V to 5.5 V
KS-6
6-Lead SC70
D5M
AD5622BKSZ-2500RL71
AD5622BKSZ-2REEL71
AD5622YKSZ-2500RL71
AD5622YKSZ-2REEL71
AD5622WKSZ-1500RL71
2 LSB
2 LSB
2 LSB
2 LSB
6 LSB
Standard, fast
Standard, fast
Standard, fast
Standard, fast
Standard, fast, and −40°C to +125°C
high speed
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
2.7 V to 5.5 V
KS-6
KS-6
KS-6
KS-6
KS-6
6-Lead SC70
6-Lead SC70
6-Lead SC70
6-Lead SC70
6-Lead SC70
D5N
D5N
D5P
D5P
D5Q
AD5622WKSZ-1REEL71
6 LSB
Standard, fast, and −40°C to +125°C
high speed
2.7 V to 5.5 V
KS-6
6-Lead SC70
D5Q
AD5622AKSZ-2500RL71
AD5622AKSZ-2REEL71
6 LSB
6 LSB
Standard, fast
Standard, fast
−40°C to +85°C
−40°C to +85°C
2.7 V to 5.5 V
2.7 V to 5.5 V
KS-6
KS-6
6-Lead SC70
6-Lead SC70
D5R
D5R
1 Z = Pb-free part.
Rev. B | Page 23 of 24
AD5602/AD5612/AD5622
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05446-0-3/06(B)
Rev. B | Page 24 of 24
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