AD5640CRJ-2 [ADI]
IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PDSO8, MO-178-BA, SOT-23, 8 PIN, Digital to Analog Converter;
| 型号： | AD5640CRJ-2 |
| 厂家： | 
ADI |
| 描述： | IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PDSO8, MO-178-BA, SOT-23, 8 PIN, Digital to Analog Converter 输入元件 光电二极管 |
| 文件： | 总20页 (文件大小：507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 V/5 V, 12/14-Bit nanoDACTM D/A with
10 ppm/°C Max On-Chip Reference in SOT-23
AD5620/AD5640
Preliminary Technical Data
FEATURES
AD5620: low power single 12-bit nanoDAC
FUNCTIONAL BLOCK DIAGRAM
V
V
REFOUT
DD
GND
AD5640: low power single 16-bit nanoDAC
12-bit accuracy guaranteed
1.25/2.5V
REF
POWER-ON
RESET
AD5620/AD5640
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Tiny 8-lead SOT-23/MSOP package
Power-down to 200 nA @ 5 V, 50 nA @ 3 V
3 V/5 V single power supply
V
FB
REF(+)
DAC
DAC
REGISTER
OUTPUT
BUFFER
V
OUT
Guaranteed 16-bit monotonic by design
Power-on reset to zero/midscale
3 power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SYNC interrupt facility
SYNC SCLK DIN
APPLICATIONS
Process control
Data acquisition systems
Figure 1.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 0.7 mW at 5 V, reducing to 1 µW in
power-down mode.
The AD5620/40 parts are a member of the nanoDAC family of
devices. They are low power, single, 12-/14-bit buffered voltage-
out DACs, guaranteed monotonic by design. The AD5620/40x-1
operate from a 3 V single supply featuring an internal reference
of 1.25 V and an internal gain of 2. The AD5620/40x-2/3 operate
from a 5 V single supply featuring an internal reference of 2.5 V
and an internal gain of 2. Each reference has a 10 ppm/°C max
temperature coefficient. The reference associated with each part
is available at the REFOUT pin.
The AD5620/40 is designed with new technology and is the
next generation to the AD53xx family.
RELATED DEVICES
Part No. Description
AD5660 3 V/5 V 16-bit DAC in SOT-23, internal reference
AD5662 2.7 V to 5.5 V 16-bit DAC in SOT-23, external reference
The part incorporates a power-on reset circuit, which ensures
that the DAC output powers up to 0 V (AD5620/40x-1/2) or to
midscale (AD5620/40x-3) and remains there until a valid write
takes place. The part contains a power-down feature that reduces
the current consumption of the device to 200 nA at 5 V and
provides software selectable output loads while in power-down
mode.
PRODUCT HIGHLIGHTS
1. 16-bit DAC; 12-bit accuracy guaranteed.
2. On-chip 1.25 V/2.5 V, 10 ppm/°C max reference.
3. Available in 8-lead SOT-23 and 8-lead MSOP packages.
4. Power-on reset to 0 V or midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 50 nA at 3 V and 200 nA at 5 V.
6. 10 µS settling time.
The AD5620/40 uses a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™, and DSP interface
standards. Its on-chip precision output amplifier allows rail-to-
rail output swing to be achieved.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD5620/AD5640
Preliminary Technical Data
TABLE OF CONTENTS
AD5620/40x-2/3–Specifications..................................................... 3
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 14
Serial Interface............................................................................ 14
Microprocessor Interfacing....................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
AD5620/40x-1–Specifications ........................................................ 5
Timing Characteristics..................................................................... 7
Pin Configuration and Function Descriptions............................. 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Terminology .................................................................................... 10
REVISION HISTORY
10/04—Revision 0: PrA
Rev. PrA | Page 2 of 20
Preliminary Technical Data
AD5620/AD5640
AD5620/40X-2/3–SPECIFICATIONS
VDD = +4.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
B Version 1
Parameter
STATIC PERFORMANCE2
A Grade B Grade C Grade Unit
Conditions/Comments
AD5620
Resolution
12
±6
±1
12
±1
±1
12
±1
±1
Bits min
LSB max
LSB max
Relative Accuracy
Differential Nonlinearity
AD5640
See Figure 4.
Guaranteed monotonic by design. See Figure 5.
Resolution
14
14
14
Bits min
Relative Accuracy
Differential Nonlinearity
Zero Code Error
±±
±1
+5
±4
±1
+5
±4
±1
+5
LSB max
LSB max
mV typ
See Figure 4.
Guaranteed monotonic by design. See Figure 5.
All 0s loaded to DAC register.
+20
±10
−0.15
−1.25
±1.25
±2
+20
±10
−0.15
−1.25
±1.25
±2
+20
±10
−0.15
−1.25
±1.25
±2
mV max
mV typ
Offset Error
Full-Scale Error
% of FSR typ
% of FSR max
% of FSR max
µV/°C typ
ppm typ
dB typ
All 1s loaded to DAC register.
Gain Error
Zero Code Error Drift3
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
OUTPUT CHARACTERISTICS3
Output Voltage Range
±2.5
−100
±2.5
−100
±2.5
−100
Of FSR/°C
DAC code = midscale; VDD = 5 V ±10%
0
0
V min
VDD
±
10
12
1
VDD
±
10
12
1
VDD
±
10
12
1
V max
µs typ
µs max
µs typ
V/µs typ
nF typ
Output Voltage Settling Time
To ±0.003% FSR 0x0200 to 0xFD00
RL = 2 kΩ; 0 pF < CL < 200 pF
RL = 2 kΩ; CL = 500 pF
Slew Rate
Capacitive Load Stability
2
2
2
RL = ∞
10
±0
10
−±0
10
±0
10
−±0
10
±0
10
−±0
nF typ
RL = 2 kΩ
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)
THD, Total Harmonic Distortion
Output Drift
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short Circuit Current
Power-Up Time
nV/√Hz typ
µVp-p typ
dB typ
ppm/°C typ
nV-s typ
nV-s typ
Ω typ
DAC code = midscale, 10kHz
DAC code = midscale
VREF = 2 V ± 300 mV p-p, f = 5 kHz
5
5
5
1 LSB change around major carry.
0.1
0.5
30
4
0.1
0.5
30
4
0.1
0.5
30
4
mA typ
µs typ
VDD = 5 V
Coming out of power-down mode. VDD = 5 V
REFERENCE OUTPUT
Output Voltage
AD5620/40x-2/3
2.495
2.505
±25
2.495
2.505
±25
2.495
2.505
±10
V min
V max
ppm/°C max
Reference TC
LOGIC INPUTS3
Input Current
±1
±1
±1
µA max
1 Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.
2 Linearity calculated using a reduced code range of 512 to 65024. Output unloaded.
3 Guaranteed by design and characterization, not production tested.
Rev. PrA | Page 3 of 20
AD5620/AD5640
Preliminary Technical Data
B Version 1
Conditions/Comments
Parameter
A Grade B Grade C Grade Unit
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
0.±
2
3
0.±
2
3
0.±
2
3
V max
V min
pF max
VDD = 5 V
VDD = 5 V
POWER REQUIREMENTS
VDD
4.5
5.5
0.5
1
4.5
5.5
0.5
1
4.5
5.5
0.5
1
V min
V max
mA typ
mA max
All digital inputs at 0 V or VDD
DAC active and excluding load current
VIH = VDD and VIL = GND
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
POWER EFFICIENCY
IOUT/IDD
VIH = VDD and VIL = GND
0.2
1
0.2
1
0.2
1
µA typ
µA max
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
±9
±9
±9
%
ILOAD = 2 mA, VDD = 5 V
Rev. PrA | Page 4 of 20
Preliminary Technical Data
AD5620/AD5640
AD5620/40X-1–SPECIFICATIONS
VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Version 4
Parameter
STATIC PERFORMANCE5
A Grade B Grade C Grade Unit
Conditions/Comments
AD5620
Resolution
12
±6
±1
12
±1
±1
12
±1
±1
Bits min
LSB max
LSB max
Relative Accuracy
Differential Nonlinearity
AD5640
See Figure 4.
Guaranteed monotonic by design. See Figure 5.
Resolution
14
14
14
Bits min
Relative Accuracy
Differential Nonlinearity
Zero Code Error
±±
±1
+5
±4
±1
+5
±4
±1
+5
LSB max
LSB max
mV typ
See Figure 4.
Guaranteed monotonic by design. See Figure 5.
All 0s loaded to DAC register
+20
±10
−0.15
−1.25
±1.25
±20
±5
+20
±10
−0.15
−1.25
±1.25
±20
±5
+20
±10
−0.15
−1.25
±1.25
±20
±5
mV max
mV typ
Offset Error
Full-Scale Error
% of FSR typ
% of FSR max
% of FSR max
µV/°C typ
ppm typ
dB typ
All 1s loaded to DAC register.
Gain Error
Zero Code Error Drift6
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
OUTPUT CHARACTERISTICS3
Output Voltage Range
Of FSR/°C
DAC code = midscale; VDD = 3 V ±10%
−100
−100
−100
0
0
V min
VDD
±
10
12
1
VDD
±
10
12
1
VDD
±
10
12
1
V max
µs typ
µs max
µs typ
V/µs typ
nF typ
Output Voltage Settling Time
To ±0.003% FSR 0200H to FD00H
RL = 2 kΩ; 0 pF < CL < 200 pF.
RL = 2 kΩ; CL = 500 pF
Slew Rate
Capacitive Load Stability
2
2
2
RL = ∞
10
±0
10
−±0
10
±0
10
−±0
tbd
5
0.1
0.5
30
10
10
±0
10
−±0
nF typ
RL = 2 kΩ
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)
THD, Total Harmonic Distortion
Output Drift
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short Circuit Current
Power-Up Time
nV/√Hz typ
µVp-p typ
dB typ
ppm/°C typ
nV-s typ
nV-s typ
Ω typ
DAC code = midscale, 10 kHz
DAC code = midscale
VREF = 2 V ± 300 mV p-p, f = 5 kHz
5
5
1 LSB change around major carry.
0.1
0.5
30
10
0.1
0.5
30
10
mA typ
µs typ
VDD = 3 V
Coming out of power-down mode. VDD = 3 V
REFERENCE OUTPUT
Output Voltage
AD5620/40x-1
1.24±
1.252
±25
1.24±
1.252
±25
1.24±
1.252
±10
V min
V max
ppm/°C max
Reference TC
4 Temperature ranges are as follows: B Version: -40°C to +105°C, typical at 25°C.
5 Linearity calculated using a reduced code range of 4±5 to 64714. Output unloaded.
6 Guaranteed by design and characterization, not production tested.
Rev. PrA | Page 5 of 20
AD5620/AD5640
Preliminary Technical Data
B Version 4
Conditions/Comments
Parameter
LOGIC INPUTS3
A Grade B Grade C Grade Unit
Input Current
±1
0.±
2
±1
0.±
2
±1
0.±
2
µA max
V max
V min
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
VDD = 3 V
VDD = 3 V
3
3
3
pF max
2.7
3.6
0.5
1
2.7
3.6
0.5
1
2.7
3.6
0.5
1
V min
V max
mA typ
mA max
All digital inputs at 0 V or VDD
DAC active and excluding load current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
0.2
1
0.2
1
0.2
1
µA typ
µA max
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
ILOAD = 2 mA, VDD = 3 V
Rev. PrA | Page 6 of 20
Preliminary Technical Data
TIMING CHARACTERISTICS
AD5620/AD5640
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 2.
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
VDD = 3.6 V to 5.5 V
Parameter
VDD = 2.7 V to 3.6 V
Unit
Conditions/Comments
7
t1
50
33
ns min
SCLK cycle time
t2
t3
t4
t5
t6
t7
t±
t9
t10
13
13
0
13
13
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK high time
SCLK low time
SYNC
to SCLK falling edge setup time
5
4.5
0
5
4.5
0
Data setup time
Data hold time
SYNC
SCLK falling edge to
SYNC
rising edge
50
13
0
33
13
0
Minimum
SYNC
high time
rising edge to SCLK fall ignore
SYNC
SCLK falling edge to
fall ignore
7 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.
t10
t1
t9
SCLK
t2
t8
t3
t7
t4
SYNC
DIN
t6
t5
DB15
DB0
Figure 2. Serial Write Operation
Rev. PrA | Page 7 of 20
AD5620/AD5640
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
6
5
GND
DIN
DD
AD5620/
AD5640
V
REFOUT
TOP VIEW
V
SCLK
SYNC
FB
(Not to Scale)
V
OUT
Figure 3. 8-Lead S0T-23/MSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1
2
3
4
5
VDD
VREFOUT
VFB
VOUT
SYNC
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and VDD should be de-coupled to GND.
Reference Voltage Output.
Feedback Connection for the Output Amplifier.
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following
SYNC
clocks. The DAC is updated following the 16th clock cycle, unless
is taken high before this edge; in which
SYNC
case, the rising edge of
acts as an interrupt, and the write sequence is ignored by the DAC.
6
7
±
SCLK
DIN
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
GND
Ground Reference Point for All Circuitry on the Part.
Rev. PrA | Page ± of 20
Preliminary Technical Data
AD5620/AD5640
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
Rating
VDD to GND
Digital Input Voltage to GND
VOUT to GND
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
SOT-23 Package
−40°C to +105°C
−65°C to +150°C
150°C
Power Dissipation
(TJ max − TA)/θJA
240°C/W
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 s)
215°C
220°C
Infrared (15 s)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 9 of 20
AD5620/AD5640
TERMINOLOGY
Preliminary Technical Data
Relative Accuracy
Gain Error
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 4.
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Total Unadjusted Error (TUE)
Differential Nonlinearity
TUE is a measure of the output error taking all the various
errors into account. A typical TUE vs. code plot can be seen in
Figure 6.
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 5.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Error Drift
Zero-Code Error
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
It is a measure of the output error when zero code (0x000) is
loaded to the DAC register. Ideally, the output should be 0 V.
The zero-code error is always positive in the AD5620/AD5640
because the output of the DAC cannot go below 0 V. It is due to
a combination of the offset errors in the DAC and output
amplifier. Zero-code error is expressed in mV. A plot of the
zero-code error vs. temperature can be seen in Figure 8.
Digital-to-Analog Glitch Impulse
It is the impulse injected into the analog output when the input
code in the DAC register changes state. It is normally specified
as the area of the glitch in nV-secs and is measured when the
digital input code is changed by 1 LSB at the major carry
transition (0x7FF to 0x800). See Figure 21.
Full-Scale Error
It is a measure of the output error when full-scale code (0xFFF)
is loaded to the DAC register. Ideally, the output should be
VDD − 1 LSB. Full-scale error is expressed in percent of full-scale
range. A plot of the full-scale error vs. temperature can be seen
in Figure 8.
Digital Feedthrough
It is a measure of the impulse injected into the analog output of
the DAC from the digital inputs of the DAC but is measured
when the DAC output is not updated. It is specified in nV-secs
and measured with a full-scale code change on the data bus, i.e.,
from all 0s to all 1s and vice versa.
Rev. PrA | Page 10 of 20
Preliminary Technical Data
AD5620/AD5640
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. AD5620 Typical INL Plot
Figure 7. INL Error and DNL Error vs. Temperature
Figure 5. AD5620 Typical DNL Plot
Figure 8. Zero-Scale Error and Full-Scale Error vs. Temperature
Figure 6. AD5620 Typical Total Unadjusted Error (TUE) Plot
Figure 9. IDD Histogram with VDD = 3 V and VDD = 5 V
Rev. PrA | Page 11 of 20
AD5620/AD5640
Preliminary Technical Data
Figure 10. Source and Sink Current Capability with VDD = 3 V
Figure 13. Supply Current vs. Temperature
Figure 11. Source and Sink Current Capability with VDD = 5 V
Figure 14. Supply Current vs. Supply Voltage
Figure 12. Supply Current vs. Code
Figure 15. Power-Down Current vs. Supply Voltage
Rev. PrA | Page 12 of 20
Preliminary Technical Data
Figure 16. Supply Current vs. Logic Input Voltage
Figure 17. Full-Scale Settling Time
AD5620/AD5640
Figure 19. Power-On Reset to 0 V
Figure 20. Exiting Power-Down (0x800 Loaded)
Figure 18. Half-Scale Settling Time
Figure 21. Digital-to-Analog Glitch Impulse
Rev. PrA | Page 13 of 20
AD5620/AD5640
Preliminary Technical Data
THEORY OF OPERATION
D/A Section
Resistor String
The AD5620/AD5640 DAC is fabricated on a CMOS process.
The architecture consists of a string DAC followed by an output
buffer amplifier. The parts include an internal 1.25 V/2.5 V,
10 ppm/°C reference with an internal gain of 2. Figure 22 shows
a block diagram of the DAC architecture.
The resistor string section is shown in Figure 23. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
V
DD
V
FB
REF (+)
Output Amplifier
RESISTOR
STRING
V
DAC REGISTER
OUT
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, which gives an output range of 0 V to
VDD. It is capable of driving a load of 2 kΩ in parallel with
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 10 and Figure 11. The slew rate
is 1 V/µs with a half-scale settling time of 8 µs with the output
unloaded.
REF (–ٛ)
OUTPUT
AMPLIFIER
GND
Figure 22. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by
SERIAL INTERFACE
D
65536
⎛
⎜
⎝
⎞
⎟
⎠
SYNC
The AD5620/AD5640 has a 3-wire serial interface (
,
VOUT = 2×VREF×
SCLK, and DIN), which is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
where:
D equals the decimal equivalent of the binary code that is
loaded to the DAC register; 0 − 4095 for AD5620 (12 bit)
and 0 − 16383 for AD5640 (14 bit).
SYNC
The write sequence begins by bringing the
line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5620/AD5640 compatible with high
speed DSPs. On the 24th falling clock edge, the last data bit is
clocked in and the programmed function is executed, i.e., a
change in DAC register contents and/or a change in the mode
N equals the DAC resolution.
R
R
SYNC
of operation. At this stage, the
line can be kept low or can
be brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a
TO OUTPUT
R
AMPLIFIER
SYNC
falling edge of
can initiate the next write sequence. Since
buffer draws more current when VIN = 2.4 V than it
SYNC
SYNC
the
does when VIN = 0.8 V,
should be idled low between
write sequences for even lower power operation of the part. As
is mentioned previously, however, it must be brought high again
just before the next write sequence.
R
R
Input Shift Register
The input shift register is 16 bits wide (see Figure 24 and
Figure 25). The first two bits are control bits, which control the
mode of operation that the part is in (normal mode or any one
of the three power-down modes). For a more complete
description of the various modes, see the Power-Down Modes
section. The next 14/12 bits are the data bits. These are
transferred to the DAC register on the 16th falling edge of
SCLK.
Figure 23. Resistor String
Rev. PrA | Page 14 of 20
Preliminary Technical Data
AD5620/AD5640
DB15 (MSB)
DBO (LSB)
PD1
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DATA BITS
Figure 24. AD5620 Input Register Contents
DB15 (MSB)
DBO (LSB)
PD1
PD0 D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
Figure 25. AD5640 Input Register Contents
SCLK
SYNC
DIN
DB15
DB0
DB15
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16TH FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16TH FALLING EDGE
SYNC
Figure 26.
Interrupt Facility
Table 6. Modes of Operation for the AD5620/AD5640
SYNC
Interrupt
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
DB15
0
DB14
0
SYNC
In a normal write sequence, the
least 16 falling edges of SCLK, and the DAC is updated on the
SYNC
line is kept low for at
16th falling edge. However, if
is brought high before the
0
1
1
1
0
1
16th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents or a
change in the operating mode occurs (see Figure 26).
When both bits are set to 0, the part works normally with its
normal power consumption of 250 µA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V and to 0 nA at 3 V. Not only does the supply current fall, but
the output stage is internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through a
1 kΩ resistor, a 100 kΩ resistor, or left open-circuited (three-
state). The output stage is illustrated in Figure 27.
Power-On Reset
The AD5620/AD5640 family contains a power-on-reset circuit,
which controls the output voltage during power-up. The
AD5620/AD5640x-1/AD5620/AD5640x-2 DAC output powers
up to 0 V, and the AD5620/AD5640x-3 DAC output powers up
to midscale. The output remains there until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up.
Power-Down Modes
V
FB
The AD5620/AD5640 family contains four separate modes of
operation. These modes are software-programmable by setting
two bits, DB15 and DB14, in the control register. Table 6 shows
how the state of the bits corresponds to the mode of operation
of the device.
AMPLIFIER
V
OUT
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 27. Output Stage During Power-Down
Rev. PrA | Page 15 of 20
AD5620/AD5640
Preliminary Technical Data
The bias generator, the output amplifier, the resistor string, and
the other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
68HC11/68L11*
AD5620/
AD5640*
PC7
SCK
SYNC
SCLK
DIN
power-down is typically 2.5 µs for VDD = 5 V and 5 µs for VDD
3 V. See Figure 20.
=
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
MICROPROCESSOR INTERFACING
AD5620/AD5640 to ADSP-2101/ADSP-2103 Interface
Figure 29. AD5620/AD5640 to 68HC11/68L11 Interface
Figure 28 shows a serial interface between the AD5620/AD5640
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP-2101/ADSP-2103 SPORT is
programmed through the SPORT control register and should be
configured as follows: internal clock operation, active low
framing, and 16-bit word length. Transmission is initiated by
writing a word to the Tx register after SPORT is enabled.
AD5620/AD5640 to 80C51/80L51 Interface
Figure 30 shows a serial interface between the AD5620/AD5640
and the 80C51/80L51 microcontroller. The setup for the
interface is as follows: TXD of the 80C51/80L51 drives SCLK of
the AD5620/AD5640, while RXD drives the serial data line of
SYNC
the part. The
signal is again derived from a bit-
programmable pin on the port. In this case, Port Line P3.3 is
used. When data transmits to the AD5620/AD5640, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus only eight falling clock edges occur in the transmit cycle.
To load data to the DAC, P3.3 is left low after the first eight bits
are transmitted, and a second write cycle is initiated to transmit
the second byte of data. P3.3 is taken high following the
completion of this cycle. The 80C51/80L51 outputs the serial
data in a format that has the LSB first. The AD5620/AD5640
requires its data with MSBfirst. The 80C51/80L51 transmit
routine should take this into account.
ADSP-2101/
AD5620/
ADSP-2103*
AD5640*
TFS
DT
SYNC
DIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 28. AD5620/AD5640 to ADSP-2101/ADSP-2103 Interface
AD5620/AD5640 to 68HC11/68L11 Interface
AD5620/
AD5640*
80C51/80L51*
Figure 29 shows a serial interface between the AD5620/AD5640
and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5620/AD5640, while
P3.3
TXD
RXD
SYNC
SCLK
DIN
the MOSI output drives the serial data line of the DAC. The
SYNC
signal is derived from a port line (PC7). The set-up
conditions for correct operation of this interface are as follows:
the 68HC11/68L11 should be configured so that its CPOL bit is
0 and its CPHA bit is 1. When data transmits to the DAC, the
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 30. AD5620/AD5640 to 80C51/80L51 Interface
SYNC
line is taken low (PC7). When the 68HC11/68L11 is
AD5620/AD5640 to MICROWIRE Interface
configured as above, data appearing on the MOSI output is
valid on the falling edge of SCK. Serial data from the
68HC11/68L11 transmits in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Data transmits MSB
first. In order to load data to the AD5620/AD5640, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC and PC7 is taken high
at the end of this procedure.
Figure 31 shows an interface between the AD5320 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5320 on the rising edge of the SK.
AD5620/
AD5640*
MICROWIRE*
CS
SK
SO
SYNC
SCLK
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 31. AD5620/AD5640 to MICROWIRE Interface
Rev. PrA | Page 16 of 20
Preliminary Technical Data
AD5620/AD5640
OUTLINE DIMENSIONS
3.00
BSC
2.90 BSC
8
1
7
2
6
3
5
4
8
5
4
4.90
BSC
3.00
BSC
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
PIN 1
0.65 BSC
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.10 MAX
0.15
0.00
0.80
0.60
0.40
1.45 MAX
0.22
0.08
8°
0°
0.38
0.22
COPLANARITY
0.10
0.23
0.08
0.60
0.45
0.30
8°
4°
0°
SEATING
PLANE
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 33. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Figure 32. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
Dimension shown in millimeters
ORDERING GUIDE
Power-On
Internal
Package
Package
Model
Grade
Reset to
Reference
Description
Options
Branding
D2K
D2L
D2H
D2J
D2M
D2N
D2P
Description
AD5620ARJ-1
AD5620ARJ-2
AD5620BRJ-1
AD5620BRJ-2
AD5620CRJ-1
AD5620CRJ-2
AD5620CRJ-3
AD5620CRM-1
AD5620CRM-2
AD5620CRM-3
AD5640ARJ-1
AD5640ARJ-2
AD5640BRJ-1
AD5640BRJ-2
AD5640CRJ-1
AD5640CRJ-2
AD5640CRJ-3
AD5640CRM-1
AD5640CRM-2
AD5640CRM-3
A
A
B
B
C
C
C
C
C
C
A
A
B
B
C
C
C
C
C
C
Zero
Zero
Zero
Zero
Zero
Zero
Midscale
Zero
Zero
Midscale
Zero
Zero
Zero
Zero
Zero
Zero
Midscale
Zero
Zero
1.25 V
2.5 V
1.25 V
2.5 V
1.25 V
2.5 V
2.5 V
1.25 V
2.5 V
2.5 V
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
MSOP
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RM-±
RM-±
RM-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
RJ-±
±2 LSB INL, 25 ppm/°C Ref
±2 LSB INL, 25 ppm/°C Ref
±1 LSB INL, 25 ppm/°C Ref
±1 LSB INL, 25 ppm/°C Ref
±1 LSB INL, 25 ppm/°C Ref
±1 LSB INL, 10 ppm/°C Ref
±1 LSB INL, 10 ppm/°C Ref
±1 LSB INL, 10 ppm/°C Ref
±1 LSB INL, 10 ppm/°C Ref
±1 LSB INL, 10 ppm/°C Ref
±± LSB INL, 25 ppm/°C Ref
±± LSB INL, 25 ppm/°C Ref
±4 LSB INL, 25 ppm/°C Ref
±4 LSB INL, 25 ppm/°C Ref
±4 LSB INL, 25 ppm/°C Ref
±4 LSB INL, 10 ppm/°C Ref
±4 LSB INL, 10 ppm/°C Ref
±4 LSB INL, 10 ppm/°C Ref
±4 LSB INL, 10 ppm/°C Ref
±4 LSB INL, 10 ppm/°C Ref
D2M
D2N
D2P
MSOP
MSOP
1.25 V
2.5 V
1.25 V
2.5 V
1.25 V
2.5 V
2.5 V
1.25 V
2.5 V
2.5 V
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
MSOP
D2S
D2T
D2Q
D2R
D2U
D2V
D2W
D2U
D2V
D2W
RM-±
RM-±
RM-±
MSOP
MSOP
Midscale
Rev. PrA | Page 17 of 20
AD5620/AD5640
NOTES
Preliminary Technical Data
Rev. PrA | Page 1± of 20
Preliminary Technical Data
NOTES
AD5620/AD5640
Rev. PrA | Page 19 of 20
AD5620/AD5640
NOTES
Preliminary Technical Data
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04781–0–10/04(PrA)
Rev. PrA | Page 20 of 20
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