AD5644RBRMZ-5 [ADI]
Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference; 四， 12位/ 14位/ 16位nanoDACs 5 PPM / C片参考
| 型号： | AD5644RBRMZ-5 |
| 厂家： | 
ADI |
| 描述： | Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference |
| 文件： | 总28页 (文件大小：1067K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, 12-/14-/16-Bit nanoDACs® with
5 ppm/°C On-Chip Reference
AD5624R/AD5644R/AD5664R
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
/V
DD
GND
REFIN REFOUT
Low power, smallest pin-compatible, quad nanoDACs
AD5664R: 16 bits
1.25V/2.5V REF
AD5624R/AD5644R/AD5664R
AD5644R: 14 bits
AD5624R: 12 bits
INPUT
DAC
STRING
DAC A
V
V
V
V
A
B
C
D
BUFFER
BUFFER
BUFFER
BUFFER
OUT
OUT
OUT
OUT
REGISTER
REGISTER
SCLK
SYNC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
User selectable external or internal reference
External reference default
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
10-lead MSOP and 3 mm × 3 mm LFCSP_WD
2.7 V to 5.5 V power supply
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
DIN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
POWER-ON
RESET
POWER-DOWN
LOGIC
Figure 1.
Serial interface, up to 50 MHz
Table 1. Related Devices
Part No.
Description
APPLICATIONS
Process control
AD5624/AD5664
2.7 V to 5.5 V quad, 12-/16-bit
DACs, external reference
AD5666
2.7 V to 5.5 V quad 16-bit DAC,
internal reference, LDAC, CLR pins
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5624R/AD5644R/AD5664R, members of the nanoDAC
family, are low power, quad, 12-/14-/16-bit buffered voltage-out
DACs. All devices operate from a single 2.7 V to 5.5 V supply
and are guaranteed monotonic by design.
while in power-down mode. The low power consumption of
this part in normal operation makes it ideally suited to portable
battery-operated equipment.
The AD5624R/AD5644R/AD5664R use a versatile 3-wire serial
interface that operates at clock rates up to 50 MHz, and is
compatible with standard SPI®, QSPI™, MICROWIRE™, and
DSP interface standards. The on-chip precision output amplifier
enables rail-to-rail output swing.
The AD5624R/AD5644R/AD5664R have an on-chip reference.
The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference, giving a full-
scale output range of 2.5 V; the AD56x4R-5 has a 2.5 V,
5 ppm/°C reference giving a full-scale output range of 5 V. The
on-chip reference is off at power-up allowing the use of an
external reference and all devices can be operated from a single
2.7 V to 5.5 V supply. The internal reference is enabled via a
software write.
PRODUCT HIGHLIGHTS
1. Quad 12-/14-/16-bit DACs.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
The part incorporates a power-on reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place. The part contains a per-channel power-down
feature that reduces the current consumption of the device to
480 nA at 5 V and provides software-selectable output loads
3. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm,
LFCSP_WD.
4. Low power, typically consumes 1.32 mW at 3 V and
2.25 mW at 5 V.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD5624R/AD5644R/AD5664R
TABLE OF CONTENTS
Features .............................................................................................. 1
Internal Reference ...................................................................... 20
External Reference ..................................................................... 20
Serial Interface............................................................................ 20
Input Shift Register .................................................................... 21
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5624R-5/AD5644R-5/AD5664R-5....................................... 3
AD5624R-3/AD5644R-3/AD5664R-3....................................... 5
AC Characteristics........................................................................ 6
Timing Characteristics ................................................................ 7
Timing Diagram ........................................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 20
D/A Section................................................................................. 20
Resistor String............................................................................. 20
Output Amplifier........................................................................ 20
SYNC
Interrupt .......................................................................... 21
Power-On Reset.......................................................................... 22
Software Reset............................................................................. 22
Power-Down Modes .................................................................. 22
LDAC Function........................................................................... 23
Internal Reference Setup ........................................................... 23
Microprocessor Interfacing....................................................... 24
Applications..................................................................................... 25
Using a Reference as a Power Supply for the
AD5624R/AD5644R/AD5664R ............................................... 25
Bipolar Operation
Using the AD5624R/AD5644R/AD5664R ............................. 25
Using AD5624R/AD5644R/AD5664R
with a Galvanically Isolated Interface...................................... 25
Power Supply Bypassing and Grounding................................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 28
REVISION HISTORY
11/06—Rev. 0 to Rev A
Changes to Reference Output Parameter in Table 2.................... 3
Changes to Reference Output Parameter in Table 3.................... 5
Added Note to Figure 3.................................................................... 9
4/06—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD5624R/AD5644R/AD5664R
SPECIFICATIONS
AD5624R-5/AD5644R-5/AD5664R-5
VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Grade1
Parameter
STATIC PERFORMANCE2
Min
Typ
Max
Unit
Conditions/Comments
AD5664R
Resolution
16
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5644R
±8
±16
±1
Guaranteed monotonic by design
Guaranteed monotonic by design
Resolution
14
12
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5624R
±2
±4
±±.5
Resolution
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection
Ratio
±±.5
±1
±±.25
1±
±1±
±1
±1.5
LSB
LSB
mV
mV
% of FSR
% of FSR
μV/°C
ppm
dB
Guaranteed monotonic by design
All zeroes loaded to DAC register
2
±1
−±.1
All ones loaded to DAC register
±2
±2.5
−1±±
Of FSR/°C
DAC code = midscale ; VDD = 5 V ± 1±%
DC Crosstalk
(External Reference)
1±
μV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
1±
5
μV/mA
μV
Due to load current change
Due to powering down (per channel)
DC Crosstalk
(Internal Reference)
25
μV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
2±
1±
μV/mA
μV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
±
VDD
V
Capacitive Load Stability
2
nF
nF
Ω
mA
μs
RL = ∞
RL = 2 kΩ
1±
±.5
3±
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode; VDD = 5 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
17±
26
2±±
VDD
μA
V
kΩ
VREF = VDD = 5.5 V
±.75
2.495
2.5±5
±1±
V
At ambient
MSOP package models
LFCSP package models
Reference TC3
±5
±1±
7.5
ppm/°C
ppm/°C
kΩ
Output Impedance
Rev. A | Page 3 of 28
AD5624R/AD5644R/AD5664R
B Grade1
Typ
Parameter
LOGIC INPUTS3
Min
Max
Unit
Conditions/Comments
Input Current
±2
±.8
μA
V
V
All digital inputs
VDD = 5 V
VDD = 5 V
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
2
3
pF
POWER REQUIREMENTS
VDD
4.5
5.5
V
IDD (Normal Mode)4
VDD = 4.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
IDD (All Power-Down Modes)5
VDD = 4.5 V to 5.5 V
VIH = VDD, VIL = GND
Internal reference off
Internal reference on
VIH = VDD, VIL = GND
±.45
±.95
±.9
1.2
mA
mA
±.48
1
μA
1 Temperature range: B grade: −4±°C to +1±5°C.
2 Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,±24); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4±64). Output
unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down.
Rev. A | Page 4 of 28
AD5624R/AD5644R/AD5664R
AD5624R-3/AD5644R-3/AD5664R-3
VDD = 2.7 V to 3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Grade1
Parameter
STATIC PERFORMANCE2
Min
Typ
Max
Unit
Conditions/Comments
AD5664R
Resolution
16
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5644R
±8
±16
±1
Guaranteed monotonic by design
Guaranteed monotonic by design
Resolution
14
12
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5624R
±2
±4
±±.5
Resolution
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection
Ratio
±±.5
±1
±±.25
1±
±1±
±1
±1.5
LSB
LSB
mV
mV
% of FSR
% of FSR
μV/°C
ppm
dB
Guaranteed monotonic by design
All zeroes loaded to DAC register
2
±1
−±.1
All ones loaded to DAC register
±2
±2.5
−1±±
Of FSR/°C
DAC code = midscale; VDD = 3 V ± 1±%
DC Crosstalk
(External Reference)
1±
μV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
1±
5
μV/mA
μV
Due to load current change
Due to powering down (per channel)
DC Crosstalk
(Internal Reference)
25
μV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
2±
1±
μV/mA
μV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
±
VDD
V
Capacitive Load Stability
2
nF
nF
Ω
mA
μs
RL = ∞
RL = 2 kΩ
1±
±.5
3±
4
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 3 V
Coming out of power-down mode; VDD = 3 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
17±
26
2±±
VDD
μA
V
kΩ
VREF = VDD = 3.6 V
±
1.247
1.253
±15
V
At ambient
MSOP package models
LFCSP package models
Reference TC3
±5
±1±
7.5
ppm/°C
ppm/°C
kΩ
Output Impedance
Rev. A | Page 5 of 28
AD5624R/AD5644R/AD5664R
B Grade1
Typ
Parameter
LOGIC INPUTS3
Min
Max
Unit
Conditions/Comments
Input Current
±2
±.8
μA
V
V
All digital inputs
VDD = 3 V
VDD = 3 V
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
2
3
pF
POWER REQUIREMENTS
VDD
2.7
3.6
V
IDD (Normal Mode)4
VDD = 2.7 V to 3.6 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)5
VDD = 2.7 V to 3.6 V
VIH = VDD, VIL = GND
Internal reference off
Internal reference on
VIH = VDD, VIL = GND
±.44
±.95
±.85
1.15
mA
mA
±.2
1
μA
1 Temperature range: B grade: −4±°C to +1±5°C.
2 Linearity calculated using a reduced code range: AD5664R (Code 512 to Code 65,±24); AD5644R (Code 128 to Code 16,256); AD5624R (Code 32 to Code 4±64). Output
unloaded.
3 Guaranteed by design and characterization, not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.1
Table 4.
Parameter2
Min
Typ
Max
Unit
Conditions/Comments3
Output Voltage Settling Time
AD5624R
AD5644R
3
3.5
4
4.5
5
7
μs
μs
μs
¼ to ¾ scale settling to ±±.5 LSB
¼ to ¾ scale settling to ±±.5 LSB
¼ to ¾ scale settling to ±2 LSB
AD5664R
Slew Rate
1.8
1±
±.1
−9±
±.1
1
4
1
4
34±
−8±
12±
1±±
15
V/μs
nV-s
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
Analog Crosstalk
1 LSB change around major carry
VREF = 2 V ± ±.1 V p-p, frequency 1± Hz to 2± MHz
External reference
Internal reference
External reference
Internal reference
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
VREF = 2 V ± ±.1 V p-p
dB
VREF = 2 V ± ±.1 V p-p, frequency = 1± kHz
DAC code = midscale, 1 kHz
DAC code = midscale, 1± kHz
±.1 Hz to 1± Hz
nV/√Hz
nV/√Hz
μV p-p
Output Noise
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range is −4±°C to +1±5°C, typical at 25°C.
Rev. A | Page 6 of 28
AD5624R/AD5644R/AD5664R
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
DD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1
V
Table 5.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
2
t1
2±
9
9
13
5
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t2
t3
t4
t5
t6
t7
t8
t9
t1±
Data hold time
±
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
15
13
±
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 5± MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
t10
t1
t9
SCLK
t2
t8
t3
t7
t4
SYNC
DIN
t6
t5
DB23
DB0
Figure 2. Serial Write Operation
Rev. A | Page 7 of 28
AD5624R/AD5644R/AD5664R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−±.3 V to +7 V
VOUT to GND
VREFIN/VREFOUT to GND
−±.3 V to VDD + ±.3 V
−±.3 V to VDD + ±.3 V
−±.3 V to VDD + ±.3 V
Digital Input Voltage to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
−4±°C to +1±5°C
−65°C to +15±°C
15±°C
ESD CAUTION
(TJ max − TA)/θJA
LFCSP_WD Package (4-Layer Board)
θJA Thermal Impedance
MSOP Package (4-Layer Board)
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
61°C/W
142°C/W
43.7°C/W
26±°C ± 5°C
Rev. A | Page 8 of 28
AD5624R/AD5644R/AD5664R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
10
9
V
V
A
B
V
V
/V
OUT
REFIN REFOUT
AD5624R/
AD5644R/
AD5664R
TOP VIEW
(Not to Scale)
OUT
DD
8
GND
DIN
7
V
V
C
SCLK
SYNC
OUT
6
D
OUT
EXPOSED PAD TIED TO
GND ON LFCSP PACKAGE
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
VOUT
VOUT
GND
A
B
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for all Circuitry on the Part.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an
interrupt and the write sequence is ignored by the device.
VOUTC
VOUTD
SYNC
7
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 5± MHz.
8
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
9
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
1± μF capacitor in parallel with a ±.1 μF capacitor to GND.
1±
VREFIN/VREFOUT
The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.
Rev. A | Page 9 of 28
AD5624R/AD5644R/AD5664R
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
10
V
T
= V
= 25°C
= 5V
V
T
= V
= 25°C
= 5V
DD
REF
DD
REF
0.8
0.6
0.4
0.2
8
A
A
6
4
2
0
0
–2
–4
–0.2
–0.4
–0.6
–6
–8
–0.8
–1.0
–10
0
10k
20k
30k
CODE
40k
50k
60k
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
Figure 7. DNL AD5664R, External Reference
Figure 4. INL AD5664R, External Reference
0.5
4
3
V
= V
= 25°C
= 5V
V
T
= V
= 25°C
= 5V
DD
REF
DD
REF
T
0.4
0.3
0.2
0.1
A
A
2
1
0
0
–0.1
–1
–2
–3
–4
–0.2
–0.3
–0.4
–0.5
0
2500
5000
7500
CODE
10000
12500
15000
0
2500
5000
7500
CODE
10000
12500
15000
Figure 8. DNL AD5644R, External Reference
Figure 5. INL AD5644R, External Reference
0.20
0.15
0.10
0.05
0
1.0
0.8
V
T
= V
= 25°C
= 5V
V
T
= V
= 25°C
= 5V
DD
REF
DD
REF
A
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.05
–0.10
–0.15
–0.20
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
500
1000
1500 2000
CODE
2500 3000 3500 4000
Figure 9. DNL AD5624R, External Reference
Figure 6. INL AD5624R, External Reference
Rev. A | Page 1± of 28
AD5624R/AD5644R/AD5664R
1.0
0.8
0.6
0.4
0.2
10
8
V
V
T
= 5V
V
V
= 5V
DD
DD
= 2.5V
= 2.5V
REFOUT
= 25°C
REFOUT
TA = 25°C
A
6
4
2
0
0
–0.2
–2
–4
–6
–0.4
–0.6
–8
–0.8
–1.0
–10
CODE
CODE
Figure 10. INL AD5664R-5, Internal Reference
Figure 13. DNL AD5664R-5, Internal Reference
4
0.5
0.4
0.3
0.2
0.1
V
V
= 5V
= 2.5V
= 25°C
DD
REFOUT
V
V
= 5V
= 2.5V
= 25°C
DD
REFOUT
3
2
T
A
T
A
1
0
0
–0.1
–1
–2
–0.2
–0.3
–3
–4
–0.4
–0.5
CODE
CODE
Figure 11. INL AD5644R-5, Internal Reference
Figure 14. DNL AD5644R-5, Internal Reference
1.0
0.20
0.15
0.10
0.05
V
V
= 5V
V
V
T
= 5V
= 2.5V
= 25°C
DD
DD
REFOUT
= 2.5V
0.8
0.6
0.4
0.2
REFOUT
= 25°C
T
A
A
0
–0.2
–0.4
–0.6
0
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
500
1000
1500 2000 2500 3000
CODE
3500 4000
0
500
1000
1500 2000 2500 3000
CODE
3500 4000
Figure 12. INL AD5624R-5, Internal Reference
Figure 15. DNL AD5624R-5, Internal Reference
Rev. A | Page 11 of 28
AD5624R/AD5644R/AD5664R
10
1.0
V
V
= 3V
= 1.25V
= 25°C
V
V
= 3V
DD
REFOUT
DD
REFOUT
= 25°C
8
6
0.8
0.6
= 1.25V
T
T
A
A
4
0.4
2
0.2
0
0
–2
–4
–6
–0.2
–0.4
–0.6
–8
–0.8
–1.0
–10
CODE
CODE
Figure 16. INL AD5664R-3, Internal Reference
Figure 19. DNL AD5664R-3, Internal Reference
4
3
0.5
0.4
V
V
= 3V
= 1.25V
= 25°C
V
V
T
= 3V
= 1.25V
= 25°C
A
DD
REFOUT
DD
REFOUT
T
A
0.3
2
0.2
1
0.1
0
0
–0.1
–0.2
–0.3
–1
–2
–3
–4
–0.4
–0.5
CODE
CODE
Figure 17. INL AD5644R-3, Internal Reference
Figure 20. DNL AD5644R-3, Internal Reference
1.0
0.8
0.20
0.15
0.10
0.05
0
V
V
= 3V
V
V
= 3V
DD
DD
REFOUT
= 25°C
= 1.25V
= 1.25V
REFOUT
= 25°C
T
T
A
A
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.05
–0.10
–0.15
–0.20
–0.8
–1.0
0
500
1000 1500
2000 2500
CODE
3000 3500 4000
0
500
1000 1500
2000 2500
CODE
3000 3500 4000
Figure 18. INL AD5624R-3, Internal Reference
Figure 21. DNL AD5624R-3, Internal Reference
Rev. A | Page 12 of 28
AD5624R/AD5644R/AD5664R
8
6
0
–0.02
–0.04
–0.06
–0.08
V
= 5V
DD
MAX INL
V
= V = 5V
REF
DD
GAIN ERROR
4
2
MAX DNL
MIN DNL
0
–0.10
–0.12
–2
–4
–6
–8
–0.14
–0.16
FULL-SCALE ERROR
MIN INL
80
–0.18
–0.20
–40
–20
0
20
40
60
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. INL Error and DNL Error vs. Temperature
Figure 25. Gain Error and Full-Scale Error vs. Temperature
10
1.5
8
6
MAX INL
1.0
ZERO-SCALE ERROR
0.5
0
V
= 5V
= 25°C
DD
4
T
A
2
MAX DNL
MIN DNL
–0.5
–1.0
–1.5
–2.0
–2.5
0
–2
–4
–6
OFFSET ERROR
MIN INL
4.25
–8
–10
0.75
1.25
1.75
2.25
2.75
3.25
(V)
3.75
4.75
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
REF
Figure 26. Zero-Scale Error and Offset Error vs. Temperature
Figure 23. INL Error and DNL Error vs. VREF
1.0
0.5
8
6
MAX INL
T
= 25°C
A
4
2
GAIN ERROR
0
MAX DNL
MIN DNL
FULL-SCALE ERROR
–0.5
0
–2
–4
–6
–8
–1.0
MIN INL
–1.5
–2.0
2.7
3.2
3.7
4.2
(V)
4.7
5.2
2.7
3.2
3.7
4.2
(V)
4.7
5.2
V
V
DD
DD
Figure 27. Gain Error and Full-Scale Error vs. Supply
Figure 24. INL Error and DNL Error vs. Supply
Rev. A | Page 13 of 28
AD5624R/AD5644R/AD5664R
1.0
8
7
6
5
4
3
2
1
0
V
= 3.6V
= 25°C
DD
T
= 25°C
A
T
A
0.5
0
ZERO-SCALE ERROR
–0.5
–1.0
–1.5
–2.0
–2.5
OFFSET ERROR
0.39
0.40
0.41
0.42
0.43
2.7
3.2
3.7
4.2
(V)
4.7
5.2
I
(mA)
DD
V
DD
Figure 31. IDD Histogram with External Reference, 3.6 V
Figure 28. Zero-Scale Error and Offset Error vs. Supply
8
V
T
= 5.5V
= 25°C
V
T
= 3.6V
= 25°C
DD
DD
6
A
A
7
6
5
4
3
2
1
0
5
4
3
2
1
0
0.92
0.94
(mA)
0.96
0.41
0.42
0.43
(mA)
0.44
0.45
0.90
I
I
DD
DD
Figure 29. IDD Histogram with External Reference, 5.5 V
Figure 32. IDD Histogram with Internal Reference, VREFOUT = 1.25 V
0.5
6
5
4
3
2
1
0
V
= 5.5V
= 25°C
DD
DAC LOADED WITH
FULL-SCALE
DAC LOADED WITH
ZERO-SCALE
T
A
0.4
0.3
SOURCING CURRENT
SINKING CURRENT
0.2
V
V
= 3V
0.1
DD
REFOUT
= 1.25V
0
–0.1
–0.2
–0.3
V
V
= 5V
DD
= 2.5V
–2
REFOUT
–0.4
–0.5
0.92
0.94
0.96
(mA)
0.98
–10
–8
–6
–4
0
2
4
6
8
10
I
DD
CURRENT (mA)
Figure 33. Headroom at Rails vs. Source and Sink
Figure 30. IDD Histogram with Internal Reference, VREFOUT = 2.5 V
Rev. A | Page 14 of 28
AD5624R/AD5644R/AD5664R
6
5
4
3
V
V
= 5V
DD
REFOUT
= 25°C
FULL SCALE
= 2.5V
T
A
3/4 SCALE
V
= V = 5V
REF
DD
= 25°C
T
A
MIDSCALE
1/4 SCALE
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
2
1
V
= 909mV/DIV
OUT
0
ZERO SCALE
1
–1
–30
–20
–10
0
10
20
30
CURRENT (mA)
TIME BASE = 4µs/DIV
Figure 34. AD56x4R-5 Source and Sink Capability
Figure 37. Full-Scale Settling Time, 5 V
4
3
2
1
V
V
= 3V
V
T
= V = 5V
REF
DD
REFOUT
= 25°C
DD
= 25°C
= 1.25V
A
T
A
FULL SCALE
3/4 SCALE
MIDSCALE
1/4 SCALE
V
DD
1
2
MAX(C2)
420.0mV
0
ZERO SCALE
V
OUT
CH2 500mV
–1
–30
CH1 2.0V
M100µs 125MS/s
A CH1 1.28V
8.0ns/pt
–20
–10
0
10
20
30
CURRENT (mA)
Figure 35. AD56x4R-3 Source and Sink Capability
Figure 38. Power-On Reset to 0 V
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
SYNC
SLCK
V
= V
= 5V
= 3V
DD
REFIN
1
3
V
= V
REFIN
DD
V
OUT
V
= 5V
DD
2
T
= 25°C
–20
A
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
1.4V
–40
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 39. Exiting Power-Down to Midscale
Figure 36. Supply Current vs. Temperature
Rev. A | Page 15 of 28
AD5624R/AD5644R/AD5664R
2.538
V
T
= V = 5V
REF
V
T
= V
= 25°C
= 5V
DD
= 25°C
DD
REF
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
A
A
DAC LOADED WITH MIDSCALE
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
1
Y AXIS = 2µV/DIV
X AXIS = 4s/DIV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
Figure 40. Digital-to-Analog Glitch Impulse (Negative)
Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
V
V
= 5V
= 2.5V
= 25°C
V
= V
= 25°C
= 5V
DD
REFOUT
DD
REF
T
A
T
A
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
DAC LOADED WITH MIDSCALE
1
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
5s/DIV
Figure 41. Analog Crosstalk, External Reference
Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
2.496
2.494
2.492
2.490
2.488
2.486
2.484
2.482
2.480
2.478
2.476
2.474
2.472
2.470
2.468
2.466
2.464
2.462
2.460
2.458
2.456
V
V
= 3V
= 1.25V
= 25°C
DD
REFOUT
T
A
DAC LOADED WITH MIDSCALE
1
V
V
= 5V
= 2.5V
= 25°C
DD
REFOUT
T
A
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 4.462nV
0
50
100 150 200 250 300 350 400 450
SAMPLE NUMBER
512
4s/DIV
Figure 42. Analog Crosstalk, Internal Reference
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, 1.25 V Internal Reference
Rev. A | Page 16 of 28
AD5624R/AD5644R/AD5664R
800
700
600
500
400
300
200
16
14
12
10
8
T
= 25°C
V
= V
DD
A
REF
= 25°C
MIDSCALE LOADED
T
A
V
= 3V
DD
V
= 5V
DD
V
V
= 5V
DD
REFOUT
= 2.5V
6
4
100
0
V
V
= 3V
DD
REFOUT
= 1.25V
1k
100
10k
FREQUENCY (Hz)
100k
1M
0
1
2
3
4
5
6
7
8
9
10
CAPACITANCE (nF)
Figure 48. Settling Time vs. Capacitive Load
Figure 46. Noise Spectral Density, Internal Reference
5
0
–20
–30
–40
V
A
= 5V
DD
V
= 5V
= 25°C
DD
T
= 25°C
T
A
DAC LOADED WITH FULL SCALE
= 2V ± 0.3V p-p
V
–5
REF
–10
–15
–20
–25
–30
–35
–40
–50
–60
–70
–80
–90
–100
10k
100k
FREQUENCY (Hz)
1M
10M
2k
4k
6k
8k
10k
FREQUENCY (Hz)
Figure 47. Total Harmonic Distortion
Figure 49. Multiplying Bandwidth
Rev. A | Page 17 of 28
AD5624R/AD5644R/AD5664R
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
Output Voltage Settling Time
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 4.
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the 24th falling edge of SCLK.
Digital-to-Analog Glitch Impulse
Differential Nonlinearity (DNL)
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 40).
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 7.
Zero-Code Error
Digital Feedthrough
Zero-scale error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5664R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV. A plot
of zero-code error vs. temperature can be seen in Figure 26.
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range. A plot of full-scale error vs.
temperature can be seen in Figure 25.
Noise Spectral Density
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. A plot
of noise spectral density can be seen in Figure 46.
Gain Error
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from the ideal
expressed as % of FSR.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC kept
at midscale. It is expressed in ꢀV.
Zero-Code Error Drift
This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in ppm of FSR/°C.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in ꢀV/mA.
Offset Error
Digital Crosstalk
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5664R
with code 512 loaded in the DAC register. It can be negative or
positive.
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in dB. VREF is held at 2 V, and VDD is varied by 10%.
Rev. A | Page 18 of 28
AD5624R/AD5644R/AD5664R
Analog Crosstalk
Multiplying Bandwidth
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa). Then execute a software LDAC
and monitor the output of the DAC whose digital code was not
changed. The area of the glitch is expressed in nV-s.
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
DAC-to-DAC Crosstalk
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent analog output
change of another DAC. It is measured by loading the attack
channel with a full-scale code change (all 0s to all 1s and vice
versa) using the command write to and update while
monitoring the output of the victim channel that is at midscale.
The energy of the glitch is expressed in nV-s.
Rev. A | Page 19 of 28
AD5624R/AD5644R/AD5664R
THEORY OF OPERATION
D/A SECTION
R
The AD5624R/AD5644R/AD5664R DACs are fabricated on a
CMOS process. The architecture consists of a string DAC
followed by an output buffer amplifier. Figure 50 shows a block
diagram of the DAC architecture.
R
R
TO OUTPUT
AMPLIFIER
V
DD
OUTPUT
AMPLIFIER
(GAIN = +2)
REF (+)
DAC
REGISTER
RESISTOR
STRING
V
OUT
REF (–)
R
R
GND
Figure 50. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
Figure 51. Resistor String
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = VREFIN
×
INTERNAL REFERENCE
2N
The AD5624R/AD5644R/AD5664R on-chip reference is off at
power-up and is enabled via a write to a control register. See the
Internal Reference Setup section for details.
The ideal output voltage when using the internal reference is
given by
D
⎛
⎜
⎝
⎞
⎟
⎠
The AD56x4R-3 has a 1.25 V, 5 ppm/°C reference giving a full-
scale output of 2.5 V. The AD56x4R-5 has a 2.5 V, 5 ppm/°C
reference giving a full-scale output of 5 V. The internal reference
associated with each part is available at the VREFOUT pin.
A buffer is required if the reference output is used to drive
external loads. When using the internal reference, it is
recommended that a 100 nF capacitor is placed between
reference output and GND for reference stability.
VOUT = 2×VREFOUT
where:
×
2N
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 4095 for AD5624R (12 bit).
0 to 16,383 for AD5644R (14 bit).
0 to 65,535 for AD5664R (16 bit).
EXTERNAL REFERENCE
The VREFIN pin on the AD56x4R-3 and AD56x4R-5 allows the
use of an external reference if the application requires it. The
default condition of the on-chip reference is off at power-up. All
devices (AD56x4R-3 and the AD56x4R-5) can be operated from
a single 2.7 V to 5.5 V supply.
N is the DAC resolution.
RESISTOR STRING
The resistor string is shown in Figure 51. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the
amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
SERIAL INTERFACE
The AD5624R/AD5644R/AD5664R have a 3-wire serial interface
SYNC
(
, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as with most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
OUTPUT AMPLIFIER
The write sequence begins by bringing the
line low. Data
SYNC
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. It can drive
a load of 2 kꢁ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in Figure 33
and Figure 34. The slew rate is 1.8 V/μs with a ¼ to ¾ full-scale
settling time of 7 μs.
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high as
50 MHz, making the AD5624R/AD5644R/AD5664R compatible
with high speed DSPs. On the 24th falling clock edge, the last data
bit is clocked in and the programmed function is executed, that is, a
change in DAC register contents and/or a change in the mode of
operation.
Rev. A | Page 2± of 28
AD5624R/AD5644R/AD5664R
At this stage, the
line can be kept low or be brought high. In
Table 8. Command Definition
SYNC
C2
C1
C0
Command
either case, it must be brought high for a minimum of 15 ns before
the next write sequence so that a falling edge of
the next write sequence.
can initiate
±
±
±
Write to input register n
Update DAC register n
Write to input register n, update all
SYNC
±
±
±
1
1
±
Since the
buffer draws more current when VIN = 2 V than
SYNC
(software LDAC)
it does when VIN = 0.8 V,
should be idled low between
±
1
1
1
1
1
±
±
1
1
1
±
1
±
1
Write to and update DAC channel n
Power down DAC (power-up)
Reset
LDAC register setup
Internal reference setup (on/off)
SYNC
write sequences for even lower power operation. As mentioned
previously, it must, however, be brought high again just before
the next write sequence.
INPUT SHIFT REGISTER
Table 9. Address Command
A2
The input shift register is 24 bits wide (see Figure 52). The first
two bits are don’t care bits. The next three are the command
bits, C2 to C0 (see Table 8), followed by the 3-bit DAC address,
A2 to A0 (see Table 9), and then the 16-, 14-, 12-bit data-word.
The data-word comprises the 16-, 14-, 12-bit input code
followed by 0, 2, or 4 don’t care bits, for the AD5664R,
AD5644R, and AD5624R, respectively (see Figure 52, Figure 53,
and Figure 54). These data bits are transferred to the DAC
register on the 24th falling edge of SCLK.
A1
A0
Address (n)
±
±
±
±
±
1
DAC A
DAC B
±
1
±
DAC C
±
1
1
DAC D
1
1
1
All DACs
SYNC INTERRUPT
SYNC
In a normal write sequence, the
line is kept low for at least
24 falling edges of SCLK, and the DAC is updated on the 24th
th
SYNC
falling edge. However, if
is brought high before the 24
falling edge, then this acts as an interrupt to the write sequence.
The input shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 55).
DB23 (MSB)
DB0 (LSB)
X
X
C2
C1
C0
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D3
D1
D4
D2
D0
D3
D1
X
D2
D0
X
D1
D0
DATA BITS
COMMAND BITS ADDRESS BITS
Figure 52. AD5664R Input Shift Register Contents
DB23 (MSB)
DB0 (LSB)
X
X
C2
C1
C0
A2
A1
A0 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
X
X
DATA BITS
COMMAND BITS ADDRESS BITS
Figure 53. AD5644R Input Shift Register Contents
DB23 (MSB)
DB0 (LSB)
X
X
C2
C1
C0
A2
A1
A0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
X
X
DATA BITS
COMMAND BITS ADDRESS BITS
Figure 54. AD5624R Input Shift Register Contents
SCLK
SYNC
DIN
DB23
DB0
DB23
DB0
INVALID WRITE SEQUENCE:
TH
VALID WRITE SEQUENCE, OUTPUT UPDATES
TH
SYNC HIGH BEFORE 24 FALLING EDGE
ON THE 24 FALLING EDGE
SYNC
Figure 55.
Interrupt Facility
Rev. A | Page 21 of 28
AD5624R/AD5644R/AD5664R
POWER-ON RESET
By executing the same Command 100, any combination of DACs
can be powered up by setting the bits (DB5 and DB4) to normal
operation mode. To select which combination of DAC channels
to power-up, set the corresponding four bits (DB3, DB2, DB1,
and DB0) to 1. See Table 13 for contents of the input shift register
during power-down/power-up operation.
The AD5624R/AD5644R/AD5664R family contains a power-on
reset circuit that controls the output voltage during power-up.
The AD5624R/AD5644R/AD5664R DACs output power up to
0 V and the output remains there until a valid write sequence is
made to the DACs. This is useful in applications where it is
important to know the state of the output of the DACs while
they are in the process of powering up.
Table 11. Modes of Operation for the AD5624R/AD5644R/
AD5664R
DB5
DB4
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
1±± kΩ to GND
Three-state
SOFTWARE RESET
±
±
The AD5624R/AD5644R/AD5664R contain a software reset
function. Command 101 is reserved for the software reset
function (see Table 8). The software reset command contains
two reset modes that are software programmable by setting bit
DB0 in the control register.
±
1
1
1
±
1
When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 450 μA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V (200 nA at 3 V). Not only does the supply current
fall, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This allows the output impedance of the part to be known while
the part is in power-down mode. The outputs can either be
connected internally to GND through a 1 kꢁ resistor, or left
open-circuited (three-state) as shown in Figure 54.
Table 10 shows how the state of the bit corresponds to the
software reset modes of operation of the devices. Table 12 shows
the contents of the input shift register during the software reset
mode of operation.
Table 10. Software Reset Modes for the
AD5624R/AD5644R/AD5664R
DB0
Registers Reset to Zero
±
DAC register
Input shift register
DAC register
1 (Power-On Reset)
Input shift register
LDAC register
RESISTOR
STRING DAC
AMPLIFIER
V
OUT
Power-down register
Internal reference setup register
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
POWER-DOWN MODES
The AD5624R/AD5644R/AD5664R contain four separate modes
of operation. Command 100 is reserved for the power-down
function (see Table 8). These modes are software programmable
by setting two bits (DB5 and DB4) in the control register. Table
11 shows how the state of the bits corresponds to the mode of
operation of the device. All DACs, (DAC D to DAC A) can be
powered down to the selected mode by setting the corresponding
four bits (DB3, DB2, DB1, and DB0) to 1.
Figure 56. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shutdown when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 μs for VDD = 5 V and for VDD = 3 V
(see Figure 39).
Table 12. 24-Bit Input Shift Register Contents for Software Reset Command
DB23 to DB22 (MSB)
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
x
DB0 (LSB)
x
1
±
1
x
x
x
1/±
Don’t care
Command bits (C2 to C±)
Address bits (A2 to A±)
Don’t care
Determines software
reset mode
Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for the AD5624R/AD5644R/AD5664R
DB23 to
DB22
(MSB)
DB15
to DB6 DB5
DB0
(LSB)
DB21
DB20
DB19
DB18
DB17
DB16
DB4
DB3
DB2
DB1
x
1
±
±
x
x
x
x
PD1
PD±
DAC D DAC C DAC B DAC A
Don’t
care
Command bits (C2 to C±)
Address bits (A2 to A±)
Don’t care
Don’t
care
Power-down
mode
Power-down/power-up channel
selection, set bit to 1 to select channel
Rev. A | Page 22 of 28
AD5624R/AD5644R/AD5664R
This flexibility is useful in applications where the user wants to
update select channels simultaneously, while the rest of the
channels update synchronously.
LDAC FUNCTION
The AD5624R/AD5644R/AD5664R DACs have double-
buffered interfaces consisting of two banks of registers: input
registers and DAC registers. The input registers are connected
directly to the input shift register and the digital code is
transferred to the relevant input register on completion of a
valid write sequence. The DAC registers contain the digital
code used by the resistor strings.
Table 14. LDAC Register Mode of Operation
Load DAC Register
LDAC Bits
(DB3 to DB0)
LDAC Mode of Operation
±
Normal operation (default), DAC register
update is controlled by write command.
The double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually and then write to the
remaining input register, updating all DAC registers simulta-
neously. Command 010 is reserved for this software LDAC.
1
The DAC registers are updated after new
data is read in on the falling edge of the
24th SCLK pulse.
INTERNAL REFERENCE SETUP
The on-chip reference is off at power-up by default. This
reference can be turned on or off by setting a software
programmable bit, DB0 in the control register. Table 15 shows
how the state of the bit corresponds to the mode of operation.
Command 111 is reserved for setting up the internal reference
(see Table 8). Table 16 shows how the state of the bits in the
input shift register corresponds to the mode of operation of the
device during internal reference setup.
Access to the DAC registers is controlled by the LDAC
function. The LDAC register contains two modes of operation
for each DAC channel. The DAC channels are selected by
setting the bits of the 4-bit LDAC register (DB3, DB2, DB1, and
DB0). Command 110 is reserved for setting up the LDAC
register. When the LDAC bit register is set low, the
corresponding DAC registers are latched and the input
registers can change state without affecting the contents of the
DAC registers. When the LDAC bit register is set high,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them on the
falling edge of the 24th SCLK pulse. This is equivalent to having
Table 15. Reference Set-up Register
Internal Reference
Setup Register (DB0) Action
±
1
Reference off (default)
Reference on
LDAC
an
hardware pin tied permanently low for the selected
DAC channel, that is, synchronous update mode. See Table 14
for the LDAC register mode of operation. See Table 16 for
contents of the input shift register during the LDAC register
setup command.
Table 16. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624R/AD5644R/AD5664R
DB23 to DB22
(MSB)
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB4
x
DB3
DB2
DB1
DB0 (LSB)
x
1
1
±
x
x
x
DAC D
DAC C
DAC B
DAC A
Don’t care
Command bits
(C2 to C±)
Address bits
(A2 to A±); don’t care
Don’t care
Set bit to ± or 1 for required mode of
operation on respective channel
Table 17. 24-Bit Input Shift Register Contents for Internal Reference Setup Command
DB23 to DB22
(MSB)
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
DB0 (LSB)
x
1
1
1
x
x
x
x
1/±
Don’t care
Command bits (C2 to C±)
Address bits (A2 to A±)
Don’t care
Reference setup register
Rev. A | Page 23 of 28
AD5624R/AD5644R/AD5664R
AD5624R/AD5644R/AD5664R to 80C51/80L51 Interface
MICROPROCESSOR INTERFACING
Figure 59 shows a serial interface between the AD5624R/
AD5644R/AD5664R and the 80C51/80L51 microcontroller. The
setup for the interface is that the TxD of the 80C51/80L51 drives
SCLK of the AD5624R/AD5644R/AD5664R, while RxD drives the
AD5624R/AD5644R/AD5664R to Blackfin® ADSP-BF53x
Interface
Figure 57 shows a serial interface between the AD5624R/
AD5644R/AD5664R and the Blackfin ADSP-BF53x micro-
processor. The ADSP-BF53x processor family incorporates two
dual-channel synchronous serial ports, SPORT1 and SPORT0, for
serial and multiprocessor communications. Using SPORT0 to
connect to the AD5624R/AD5644R/AD5664R, the setup for the
interface is that the DT0PRI drives the DIN pin of the AD5624R/
AD5644R/AD5664R, while TSCLK0 drives the SCLK of the part.
serial data line of the part. The
signal is derived from a bit-
SYNC
programmable pin on the port. In this case, port line P3.3 is used.
When data is transmitted to the AD5624R/AD5644R/AD5664R,
P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes
only; thus, only eight falling clock edges occur in the transmit cycle.
To load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion of
this cycle. The 80C51/80L51 outputs the serial data in LSB first
format. The AD5624R/ AD5644R/AD5664R must receive data
with the MSB first. The 80C51/80L51 transmit routine should take
this into account.
The
is driven from TFS0.
SYNC
1
AD5624R/
AD5644R/
AD5664R1
ADSP-BF53x
TFS0
DTOPRI
TSCLK0
SYNC
DIN
SCLK
1
AD5624R/
AD5644R/
AD5664R1
80C51/80L51
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 57. Blackfin ADSP-BF53x Interface to AD5624R/AD5644R/AD5664R
P3.3
TxD
RxD
SYNC
SCLK
DIN
AD5624R/AD5644R/AD5664R to 68HC11/68L11
Interface
1
Figure 58 shows a serial interface between the AD5624R/
AD5644R/AD5664R and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5624R/
AD5644R/AD5664R, while the MOSI output drives the serial
data line of the DAC.
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 59. 80C51/80L51 Interface to AD5624R/AD5644R/AD5664R
AD5624R/AD5644R/AD5664R to MICROWIRE Interface
Figure 60 shows an interface between the AD5624R/AD5644R/
AD5664R and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock and is
clocked into the AD5624R/AD5644R/AD5664R on the rising
edge of the SK.
The
signal is derived from a port line (PC7). The setup
SYNC
conditions for correct operation of this interface are that the
68HC11/68L11 is configured with its CPOL bit as 0 and its
CPHA bit as 1. When data is transmitted to the DAC, the
SYNC
1
AD5624R/
AD5644R/
AD5664R1
MICROWIRE
line is taken low (PC7). When the 68HC11/68L11 is configured
as described above, data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11/68L11
is transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
In order to load data to the AD5624R/AD5644R/AD5664R,
PC7 is left low after the first eight bits are transferred, and a
second serial write operation is performed to the DAC; PC7 is
taken high at the end of this procedure.
CS
SYNC
SCLK
DIN
SK
SO
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 60. MICROWIRE Interface to AD5624R/AD5644R/AD5664R
1
AD5624R/
AD5644R/
AD5664R1
68HC11/68L11
PC7
SCK
SYNC
SCLK
DIN
MOSI
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 58. 68HC11/68L11 Interface to AD5624R/AD5644R/AD5664R
Rev. A | Page 24 of 28
AD5624R/AD5644R/AD5664R
APPLICATIONS
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5624R/AD5644R/AD5664R
Because the supply current required by the AD5624R/AD5644R/
AD5664R is extremely low, an alternative option is to use a
voltage reference to supply the required voltage to the part (see
Figure 61). This is especially useful if the power supply is quite
noisy, or if the system supply voltages are at some value other
than 5 V or 3 V, for example, 15 V. The voltage reference
outputs a steady supply voltage for the AD5624R/AD5644R/
AD5664R (see Figure 59). If the low dropout REF195 is used, it
must supply 450 μA of current to the AD5624R/AD5644R/
AD5664R with no load on the output of the DAC. When the
DAC output is loaded, the REF195 also needs to supply the
current to the load. The total current required (with a 5 kΩ load
on the DAC output) is
R2 = 10kΩ
+5V
+5V
R1 = 10kΩ
AD820/
OP295
±5V
V
V
OUT
DD
10µF
0.1µF
AD5624R/
AD5644R/
AD5664R
–5V
3-WIRE
SERIAL
INTERFACE
Figure 62. Bipolar Operation with the AD5624R/AD5644R/AD5664R
USING AD5624R/AD5644R/AD5664R WITH A
GALVANICALLY ISOLATED INTERFACE
450 μA + (5 V/5 kΩ) = 1.45 mA
The load regulation of the REF195 is typically 2 ppm/mA,
resulting in a 2.9 ppm (14.5 μV) error for the 1.45 mA current
drawn from it. This corresponds to a 0.191 LSB error.
In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that might occur in the area where the
DAC is functioning. Isocouplers provide isolation in excess of
3 kV. The AD5624R/AD5644R/AD5664R use a 3-wire serial
logic interface, so the ADuM130x 3-channel digital isolator
provides the required isolation (see Figure 63). The power
supply to the part also needs to be isolated, which is done by
using a transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the AD5624R/
AD5644R/AD5664R.
15V
5V
REF195
V
DD
SYNC
SCLK
DIN
3-WIRE
SERIAL
INTERFACE
AD5624R/
AD5644R/
AD5664R
V
= 0V TO 5V
OUT
Figure 61. REF195 as Power Supply to the AD5624R/AD5644R/AD5664R
5V
REGULATOR
BIPOLAR OPERATION USING THE
AD5624R/AD5644R/AD5664R
10µF
0.1µF
POWER
The AD5624R/AD5644R/AD5664R has been designed for
single-supply operation, but a bipolar output range is also
possible using the circuit in Figure 62. The circuit gives an
output voltage range of 5 V. Rail-to-rail operation at the
amplifier output is achievable using an AD820 or an OP295 as
the output amplifier.
V
DD
SCLK
V
V
V
V
SCLK
SYNC
1A
OA
ADuM1300
V
SDI
OUT
V
1B
OB
OC
AD5624R/
AD5644R/
AD5664R
The output voltage for any input code can be calculated as
follows:
V
DATA
DIN
1C
GND
⎡
⎤
⎥
⎦
D
65,536
R1+ R2
R1
R2
R1
⎛
⎜
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
V = V
×
×
−V
×
⎢
⎣
Figure 63. AD5624R/AD5644R/AD5664R with a Galvanica ly Isolated Interface
O
DD
DD
⎝
⎠
where D represents the input code in decimal (0 to 65536).
With VDD = 5 V, R1 = R2 = 10 kΩ,
10×D
65,536
⎛
⎜
⎞
⎟
V =
−5 V
O
⎝
⎠
Rev. A | Page 25 of 28
AD5624R/AD5644R/AD5664R
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5624R/
AD5644R/AD5664R should have separate analog and digital
sections, each having its own area of the board. If the AD5624R/
AD5644R/AD5664R are in a system where other devices require
an AGND-to-DGND connection, the connection should be
made at one point only. This ground point should be as close as
possible to the AD5624R/AD5644R/AD5664R.
The power supply to the AD5624R/AD5644R/AD5664R should
be bypassed with 10 μF and 0.1 μF capacitors. The capacitors
should be located as close as possible to the device, with the
0.1 μF capacitor ideally right up against the device. The 10 μF
capacitor is the tantalum bead type. It is important that the
0.1 μF capacitor have low effective series resistance (ESR) and
effective series inductance (ESI), for example, common ceramic
types of capacitors. This 0.1 μF capacitor provides a low
impedance path to ground for high frequencies caused by
transient currents due to internal logic switching.
Rev. A | Page 26 of 28
AD5624R/AD5644R/AD5664R
OUTLINE DIMENSIONS
INDEX
AREA
PIN 1
INDICATOR
3.00
BSC SQ
10
1
1.50
BCS SQ
0.50
BSC
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOTTOM VIEW)
6
5
0.50
0.40
0.30
1.74
1.64
1.49
0.80 MAX
0.55 TYP
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SIDE VIEW
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 64. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
3.10
3.00
2.90
10
6
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 65. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. A | Page 27 of 28
AD5624R/AD5644R/AD5664R
ORDERING GUIDE
Package
Description
Package
Option
Model
Temperature Range
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
−4±°C to +1±5°C
Accuracy
Internal Reference
1.25 V
1.25 V
1.25 V
1.25 V
2.5 V
Branding
D7L
D7L
D7L
D7L
D7V
D7V
D7E
AD5624RBCPZ-3R21
AD5624RBCPZ-3REEL71
AD5624RBRMZ-31
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
±16 LSB INL
1±-Lead LFCSP_WD
1±-Lead LFCSP_WD
1±-Lead MSOP
1±-Lead MSOP
1±-Lead MSOP
1±-Lead MSOP
1±-Lead MSOP
1±-Lead MSOP
1±-Lead MSOP
1±-Lead MSOP
1±-Lead LFCSP_WD
1±-Lead LFCSP_WD
1±-Lead MSOP
1±-Lead MSOP
1±-Lead MSOP
1±-Lead MSOP
Evaluation Board
CP-1±-9
CP-1±-9
RM-1±
RM-1±
RM-1±
RM-1±
RM-1±
RM-1±
RM-1±
RM-1±
CP-1±-9
CP-1±-9
RM-1±
RM-1±
RM-1±
RM-1±
AD5624RBRMZ-3REEL71
AD5624RBRMZ-51
AD5624RBRMZ-5REEL71
AD5644RBRMZ-31
AD5644RBRMZ-3REEL71
AD5644RBRMZ-51
AD5644RBRMZ-5REEL71
AD5664RBCPZ-3R21
AD5664RBCPZ-3REEL71
AD5664RBRMZ-31
2.5 V
1.25 V
1.25 V
2.5 V
D7E
D7D
D7D
D73
D73
D73
D73
D75
D75
2.5 V
1.25 V
1.25 V
1.25 V
1.25 V
2.5 V
AD5664RBRMZ-3REEL71
AD5664RBRMZ-51
AD5664RBRMZ-5REEL71
2.5 V
EVAL-AD5664REB
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05856-0-11/06(A)
Rev. A | Page 28 of 28
相关型号：
AD5647RBCPZ-R2
SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 14-BIT DAC, DSO10, 3 X 3 MM, LEAD FREE, LFCSP-10
ROCHESTER
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