AD565AKN/BIN [ADI]
AD565AKN/BIN;
| 型号： | AD565AKN/BIN |
| 厂家： | 
ADI |
| 描述： | AD565AKN/BIN 转换器 |
| 文件： | 总11页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed 12-Bit
Monolithic D/A Converters
a
AD565A*/AD566A*
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Single Chip Construction
V
REF OUT
CC
BIPOLAR OFF
Very High-Speed Settling to 1/2 LSB
AD565A: 250 ns max
AD566A: 350 ns max
Full-Scale Switching Time: 30 ns
Guaranteed for Operation with ؎12 V Supplies:
AD565A with –12 V Supply: AD566A
Linearity Guaranteed Over Temperature:
1/2 LSB max (K, T Grades)
20V SPAN
10V
AD565A
5k⍀
9.95k⍀
10V SPAN
DAC OUT
19.95k⍀
0.5mA
REF
IN
5k⍀
I
REF
DAC
I
=
20k⍀
OUT
4
؋
I I
REF
GND
8k⍀
O
؋
CODE REF
CODE INPUT
Monotonicity Guaranteed Over Temperature
Low Power: AD566A = 180 mW max;
AD565A = 225 mW max
–V
EE
POWER
GND
MSB
LSB
BIPOLAR OFF
Use with On-Board High-Stability Reference (AD565A)
or with External Reference (AD566A)
Low Cost
20V SPAN
AD566A
5k⍀
9.95k⍀
10V SPAN
DAC OUT
19.95k⍀
0.5mA
MlL-STD-883-Compliant Versions Available
REF
IN
5k⍀
I
REF
DAC
PRODUCT DESCRIPTION
I
=
20k⍀
OUT
4
؋
I I
REF
GND
8k⍀
O
The AD565A and AD566A are fast 12-bit digital-to-analog
converters that incorporate the latest advances in analog circuit
design to achieve high speeds at low cost.
؋
CODE REF
CODE INPUT
The AD565A and AD566A use 12 precision, high-speed bipolar
current-steering switches, control amplifier and a laser-trimmed
thin-film resistor network to produce a very fast, high accuracy
analog output current. The AD565A also includes a buried
Zener reference that features low-noise, long-term stability and
temperature drift characteristics comparable to the best discrete
reference diodes.
–V
EE
POWER
GND
LSB
MSB
AD565A and AD566A are available in four performance
grades. The J and K are specified for use over the 0°C to +70°C
temperature range while the S and T grades are specified for the
–55°C to +125°C range. The D grades are all packaged in a
24-lead, hermetically sealed, ceramic, dual-in-line package. The
JR grade is packaged in a 28-lead plastic SOIC.
The combination of performance and flexibility in the AD565A
and AD566A has resulted from major innovations in circuit
design, an important new high-speed bipolar process, and con-
tinuing advances in laser-wafer-trimming techniques (LWT).
The AD565A and AD566A have a 10–90% full-scale transition
time less than 35 ns and settle to within 1/2 LSB in 250 ns
max (350 ns for AD566A). Both are laser-trimmed at the wafer
level to 1/8 LSB typical linearity and are specified to 1/4 LSB
max error (K and T grades) at +25°C. High speed and accuracy
make the AD565A and AD566A the ideal choice for high-speed
display drivers as well as fast analog-to-digital converters.
PRODUCT HIGHLIGHTS
1. The wide output compliance range of the AD565A and
AD566A are ideally suited for fast, low noise, accurate volt-
age output configurations without an output amplifier.
2. The devices incorporate a newly developed, fully differential,
nonsaturating precision current switching cell structure
which combines the dc accuracy and stability first developed
in the AD562/3 with very fast switching times and an
optimally-damped settling characteristic.
3. The devices also contain SiCr thin film application resistors
which can be used with an external op amp to provide a
precision voltage output or as input resistors for a successive
approximation A/D converter. The resistors are matched to
the internal ladder network to guarantee a low gain tempera-
ture coefficient and are laser-trimmed for minimum
full-scale and bipolar offset errors.
The laser trimming process which provides the excellent linear-
ity is also used to trim both the absolute value and the tempera-
ture coefficient of the reference of the AD565A resulting in a
typical full-scale gain TC of 10 ppm/°C. When tighter TC per-
formance is required or when a system reference is available, the
AD566A may be used with an external reference.
*Covered by Patent Nos.: 3,803,590; RE 28,633; 4,213,806; 4,136,349;
4,020,486; 3,747,088.
4. The AD565A and AD566A are available in versions compli-
ant with MIL-STD-883. Refer to the Analog Devices Mili-
tary Products Databook or current /883B data sheet for
detailed specifications.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD565A–SPECIFICATIONS (TA = +25؇C, VCC = +15 V, VEE = +15 V, unless otherwise noted.)
AD565AJ
Typ
AD565AK
Typ
Model
Min
Max
Min
Max
Units
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic “1”
+2.0
+5.5
+0.8
+2.0
+5.5
+0.8
V
V
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
+120
+35
+300
+100
+120
+35
+300
+100
µA
µA
Bit OFF Logic “0”
RESOLUTION
12
12
Bits
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
–1.6
؎0.8
6
–2.0
1.0
8
–2.4
؎1.2
10
–1.6
؎0.8
6
–2.0
1.0
8
–2.4
؎1.2
10
mA
mA
kΩ
Unipolar
0.01
0.05
25
0.05
0.15
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
Bipolar (Figure 3, R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
–1.5
+10
–1.5
+10
V
ACCURACY (Error Relative to
Full Scale) +25°C
1/4
؎1/2
1/8
؎1/4
LSB
(0.006)
1/2
(0.012)
؎3/4
(0.003)
1/4
(0.006)
؎1/2
% of F.S. Range
LSB
T
MIN to TMAX
(0.012)
(0.018)
(0.006)
(0.012)
% of F.S. Range
DIFFERENTIAL NONLINEARITY
+25°C
1/2
؎3/4
1/4
؎1/2
LSB
TMIN to TMAX
MONOTONICITY GUARANTEED
MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
1
2
10
50
1
2
10
20
ppm/°C
ppm/°C
ppm/°C
ppm/°C
Bipolar Zero
5
5
Gain (Full Scale)
Differential Nonlinearity
15
2
10
2
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
250
400
250
400
ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
15
30
30
50
15
30
30
50
ns
ns
TEMPERATURE RANGE
Operating
Storage
0
–65
+70
+150
0
–65
+70
+150
°C
°C
POWER REQUIREMENTS
VCC, +11.4 to +16.5 V de
VEE, –11.4 to –16.5 V dc
3
5
3
5
mA
mA
–12
–18
–12
–18
POWER SUPPLY GAIN SENSITIVITY2
VCC = +11.4 to +16.5 V dc
3
15
10
25
3
15
10
25
ppm of F.S./%
ppm of F.S./%
VEE = –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4)
0 to +5
0 to +5
V
V
V
V
V
–2.5 to +2.5
0 to +10
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
–5 to +5
–10 to +10
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 2)
0.1
؎0.25
؎0.15
0.1
؎0.25
% of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 3)
Gain Adjustment Range (Figure 2)
Bipolar Zero Adjustment Range
0.05
0.05
0.1
% of F.S. Range
% of F.S. Range
% of F.S. Range
0.25
0.15
0.25
0.15
REFERENCE INPUT
Input Impedance
15
20
25
15
20
25
kΩ
REFERENCE OUTPUT
Voltage
9.90
1.5
10.00
2.5
10.10
345
9.90
1.5
10.00
2.5
10.10
345
V
Current (Available for External Loads)3
mA
POWER DISSIPATION
225
225
mW
NOTES
1The digital inputs are guaranteed but not tested over the operating temperature range.
2The power supply gain sensitivity is tested in reference to a VCC, VEE of 15 V dc.
3For operation at elevated temperatures the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.
Specifications subject to change without notice.
–2–
REV. D
AD565A/AD566A
AD565AS
Typ
AD565AT
Typ
Model
Min
+2.0
Max
Min
+2.0
Max
Units
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
+5.5
+0.8
+5.5
+0.8
V
V
Logic Current (Each Bit)
Bit ON Logic “1”
+120
+35
+300
+100
+120
+35
+300
+100
µA
µA
Bit OFF Logic “0”
RESOLUTION
12
12
Bits
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
–1.6
؎0.8
6
–2.0
1.0
8
–2.4
؎1.2
10
–1.6
؎0.8
6
–2.0
1.0
8
–2.4
؎1.2
10
mA
mA
kΩ
Unipolar
0.01
0.05
25
0.05
0.15
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
Bipolar (Figure 3, R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
–1.5
+10
–1.5
+10
V
ACCURACY (Error Relative to
Full Scale) +25°C
1/4
؎1/2
1/8
؎1/4
LSB
(0.006)
1/2
(0.012)
؎3/4
(0.003)
1/4
(0.006)
؎1/2
% of F.S. Range
LSB
TMIN to TMAX
(0.012)
(0.018)
(0.006)
(0.012)
% of F.S. Range
DIFFERENTIAL NONLINEARITY
+25°C
1/2
؎3/4
1/4
؎1/2
LSB
TMIN to TMAX
MONOTONICITY GUARANTEED
MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
1
2
10
30
1
2
10
15
ppm/°C
ppm/°C
ppm/°C
ppm/°C
Bipolar Zero
5
5
Gain (Full Scale)
Differential Nonlinearity
15
2
10
2
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
250
400
250
400
ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
15
30
30
50
15
30
30
50
ns
ns
TEMPERATURE RANGE
Operating
Storage
–55
–65
+125
+150
–55
–65
+125
+150
°C
°C
POWER REQUIREMENTS
VCC, +11.4 to +16.5 V dc
VEE, –11.4 to –16.5 V dc
3
5
3
5
mA
mA
–12
–18
–12
–18
POWER SUPPLY GAIN SENSITIVITY2
VCC = +11.4 to +16.5 V dc
3
15
10
25
3
15
10
25
ppm of F.S./%
ppm of F.S./%
VEE = –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4)
0 to +5
0 to +5
V
V
V
V
V
–2.5 to +2.5
0 to +10
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
–5 to +5
–10 to +10
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 2)
0.1
؎0.25
؎0.15
0.1
؎0.25
؎0.1
% of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 3)
Gain Adjustment Range (Figure 2)
Bipolar Zero Adjustment Range
0.05
0.05
% of F.S. Range
% of F.S. Range
% of F.S. Range
0.25
0.15
0.25
0.15
REFERENCE INPUT
Input Impedance
15
20
25
15
20
25
kΩ
REFERENCE OUTPUT
Voltage
9.90
1.5
10.00
2.5
10.10
9.90
1.5
10.00
2.5
10.10
345
V
Current (Available for External Loads)3
mA
POWER DISSIPATION
225
345
225
mW
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specification subject to change without notice.
REV. D
–3–
(T = +25؇C, V = –15 V, unless otherwise noted)
AD566A–SPECIFICATIONS
A
EE
AD566AJ
Typ
AD566AK
Typ
Model
Min
Max
Min
Max
Units
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic “1”
+2.0
0
+5.5
+0.8
+2.0
0
+5.5
+0.8
V
V
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
+120
+35
+300
+100
+120
+35
+300
+100
µA
µA
Bit OFF Logic “0”
RESOLUTION
12
12
Bits
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
–1.6
؎0.8
6
–2.0
1.0
8
–2.4
؎1.2
10
–1.6
؎0.8
6
–2.0
1.0
8
–2.4
؎1.2
10
mA
mA
kΩ
Unipolar (Adjustable to Zero per Figure 3)
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
0.01
0.05
25
0.05
0.15
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
–1.5
+10
–1.5
+10
V
ACCURACY (Error Relative to
Full Scale) +25°C
1/4
؎1/2
1/8
؎1/4
LSB
(0.006)
1/2
(0.012)
؎3/4
(0.003)
1/4
(0.006)
؎1/2
% of F.S. Range
LSB
T
MIN to TMAX
(0.012)
(0.018)
(0.006)
(0.012)
% of F.S. Range
DIFFERENTIAL NONLINEARITY
+25°C
1/2
؎3/4
1/4
؎1/2
LSB
TMIN to TMAX
MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
Unipolar Zero
1
5
7
2
2
10
10
1
5
3
2
2
10
5
ppm/°C
ppm/°C
ppm/°C
ppm/°C
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON (Figure 8)
250
350
250
350
ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
15
30
30
50
15
30
30
50
ns
ns
POWER REQUIREMENTS
VEE, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY2
VEE = –11.4 to –16.5 V dc
–12
15
–18
25
–12
15
–18
25
mA
ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5)
0 to +5
0 to +5
V
V
V
V
V
–2.5 to +2.5
0 to +10
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
–5 to +5
–10 to +10
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3)
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4)
Gain Adjustment Range (Figure 3)
Bipolar Zero Adjustment Range
0.1
؎0.25
؎0.15
0.1
؎0.25
؎0.1
% of F.S. Range
0.05
0.05
% of F.S. Range
% of F.S. Range
% of F.S. Range
0.25
0.15
0.25
0.15
REFERENCE INPUT
Input Impedance
15
20
25
15
20
25
kΩ
POWER DISSIPATION
180
300
180
300
mW
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Two (2): Bipolar Operation at Digital Input Only
+1 V to +10 V, Unipolar
10 Bits ( 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
Reference Voltage
Accuracy
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to +10 V [p-p], Sine Wave
Frequency for 1/2 LSB [p-p] Feedthrough)
Output Slew Rate 10%–90%
40 kHz typ
5 mA/µs
90%–10%
1 mA/µs
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage)
1.5 µs to 0.01% F.S.
CONTROL AMPLIFIER
Full Power Bandwidth
300 kHz
1.8 MHz
Small-Signal Closed-Loop Bandwidth
NOTES
1The digital input levels are guaranteed but not tested over the temperature range.
2The power supply gain sensitivity is tested in reference to a VEE of –1.5 V dc.
Specifications subject to change without notice.
–4–
REV. D
AD565A/AD566A
AD566AS
Typ
AD566AT
Typ
Model
Min
Max
Min
Max
Units
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 Volt CMOS
Input Voltage
Bit ON Logic “1”
+2.0
0
+5.5
+0.8
+2.0
0
+5.5
+0.8
V
V
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
+120
+35
+300
+100
+120
+35
+300
+100
µA
µA
Bit OFF Logic “0”
RESOLUTION
12
12
Bits
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
–1.6
؎0.8
6
–2.0
1.0
8
–2.4
؎1.2
10
–1.6
؎0.8
6
–2.0
1.0
8
–2.4
؎1.2
10
mA
mA
kΩ
Unipolar (Adjustable to Zero per Figure 3)
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
0.01
0.05
25
0.05
0.15
0.01
0.05
25
0.05
0.1
% of F.S. Range
% of F.S. Range
pF
–1.5
+10
–1.5
+10
V
ACCURACY (Error Relative to
Full Scale) +25°C
1/4
؎1/2
1/8
؎1/4
LSB
(0.006)
1/2
(0.012)
؎3/4
(0.003)
1/4
(0.006)
؎1/2
% of F.S. Range
LSB
T
MIN to TMAX
(0.012)
(0.018)
(0.006)
(0.012)
% of F.S. Range
DIFFERENTIAL NONLINEARITY
+25°C
1/2
؎3/4
1/4
؎1/2
LSB
TMIN to TMAX
MONOTONICITY GUARANTEED
MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
Unipolar Zero
1
5
7
2
2
10
10
1
5
3
2
2
10
5
ppm/°C
ppm/°C
ppm/°C
ppm/°C
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON (Figure 8)
250
350
250
350
ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
15
30
30
50
15
30
30
50
ns
ns
POWER REQUIREMENTS
VEE, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY2
VEE = –11.4 to –16.5 V dc
–12
15
–18
25
–12
15
–18
25
mA
ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5)
0 to +5
0 to +5
V
V
V
V
V
–2.5 to +2.5
0 to +10
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
–5 to +5
–10 to +10
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3)
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4)
Gain Adjustment Range (Figure 3)
Bipolar Zero Adjustment Range
0.1
؎0.25
؎0.15
0.1
؎0.25
؎0.1
% of F.S. Range
0.05
0.05
% of F.S. Range
% of F.S. Range
% of F.S. Range
0.25
0.15
0.25
0.15
REFERENCE INPUT
Input Impedance
15
20
25
15
20
25
kΩ
POWER DISSIPATION
180
300
180
300
mW
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Two (2): Bipolar Operation at Digital Input Only
+1 V to +10 V, Unipolar
10 Bits ( 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
Reference Voltage
Accuracy
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to +10 V [p-p], Sine Wave
Frequency for l/2 LSB [p-p] Feedthrough)
Output Slew Rate 10%–90%
40 kHz typ
5 mA/µs
90%–10%
1 mA/µs
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage)
1.5 µs to 0.01% F.S.
CONTROL AMPLIFIER
Full Power Bandwidth
300 kHz
1.8 MHz
Small-Signal Closed-Loop Bandwidth
NOTES
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specification subject to change without notice.
REV. D
–5–
AD565A/AD566A
GROUNDING RULES
ABSOLUTE MAXIMUM RATINGS
The AD565A and AD566A bring out separate reference and
power grounds to allow optimum connections for low noise and
high-speed performance. These grounds should be tied together
at one point, usually the device power ground. The separate
ground returns are provided to minimize current flow in
low-level signal paths. In this way, logic return currents are not
summed into the same return path with analog signals.
VCC to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
VEE to Power Ground (AD565A) . . . . . . . . . . . . 0 V to –18 V
Voltage on DAC Output (Pin 9) . . . . . . . . . . . . –3 V to +12 V
Digital Inputs (Pins 13 to 24) to
Power Ground . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V
REF IN to Reference Ground . . . . . . . . . . . . . . . . . . . . 12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . 12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . . . 12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . . 24 V
REF OUT (AD565A) . . . . . Indefinite Short to Power Ground
Momentary Short to VCC
CONNECTING THE AD565A FOR BUFFERED VOLTAGE
OUTPUT
The standard current-to-voltage conversion connections using
an operational amplifier are shown here with the preferred
trimming techniques. If a low offset operational amplifier
(AD510L, AD517L, AD741L, AD301AL, AD OP07) is used,
excellent performance can be obtained in many situations with-
out trimming (an op amp with less than 0.5 mV max offset
voltage should be used to keep offset errors below 1/2 LSB). If
a 50 Ω fixed resistor is substituted for the 100 Ω trimmer, uni-
polar zero will typically be within 1/2 LSB (plus op amp off-
set), and full-scale accuracy will be within 0.1% (0.25% max).
Substituting a 50 Ω resistor for the 100 Ω bipolar offset trimmer
will give a bipolar zero error typically within 2 LSB (0.05%).
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
AD565A ORDERING GUIDE
Max Gain
Linearity
T.C. (ppm Temperature
of F.S./؇C) Range
Error Max Package
@ +25؇C
Model1
Options2
AD565AJD 50
AD565AJR 50
AD565AKD 20
AD565ASD 30
AD565ATD 15
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
1/2 LSB
1/2 LSB
1/4 LSB
1/2 LSB
1/4 LSB
Ceramic (D-24)
SOIC (R-28)
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
NOTES
1For details on grade and package offerings screened in accordance with MIL-
STD-883, refer to the Analog Devices Military Products Databook or current/
883B data sheet.
The AD509 is recommended for buffered voltage-output appli-
cations which require a settling time to 1/2 LSB of one micro-
second. The feedback capacitor is shown with the optimum
value for each application; this capacitor is required to compen-
sate for the 25 picofarad DAC output capacitance.
2D = Ceramic DIP, R = SOIC.
AD566A ORDERING GUIDE
Max Gain
Linearity
T.C. (ppm Temperature
of F.S./؇C) Range
Error Max Package
@ +25؇C
Model1
Option2
AD566AJD 10
AD566AKD
AD566ASD 10
0°C to +70°C
1/2 LSB
1/4 LSB
1/2 LSB
1/4 LSB
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
Ceramic (D-24)
3
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
AD566ATD
3
NOTES
1For details on grade and package offerings screened in accordance with MIL-
STD-883, refer to the Analog Devices Military Products Databook or current/
883B data sheet.
2D = Ceramic DIP.
–6–
REV. D
AD565A/AD566A
PIN DESIGNATIONS
24-Lead DIP
1
2
24
23
22
21
20
19
18
NC
NC
BIT 1 IN (MSB)
BIT 2 IN
1
2
24
23
22
21
20
19
18
NC
NC
BIT 1 IN (MSB)
BIT 2 IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
3
3
REF GND
BIT 3 IN
V
CC
4
4
AMP SUMMING JUNCTION
REF V HI IN
BIT 4 IN
REF OUT (+10V 1ꢀ)
5
5
BIT 5 IN
REF GND
REF IN
AD566A
AD565A
TOP VIEW
(Not to Scale)
6
–V –15V IN (20mA)
BIT 6 IN
6
EE
TOP VIEW
(Not to Scale)
7
7
BIPOLAR OFFSET IN
NC
BIT 7 IN
–V
BIT 7 IN
EE
8
17 BIT 8 IN
8
BIPOLAR OFFSET IN
DAC OUT (–2mA F.S.)
10V SPAN R
17 BIT 8 IN
DAC OUT (–2mA F.S.)
10V SPAN R
9
BIT 9 IN
16
15
9
BIT 9 IN
16
15
10
11
BIT 10 IN
10
11
BIT 10 IN
20V SPAN R
14 BIT 11 IN
BIT 12 IN (LSB)
13
20V SPAN R
14 BIT 11 IN
BIT 12 IN (LSB)
PWR GND 12
NC = NO CONNECT
PWR GND 12
13
NC = NO CONNECT
28-Lead SOIC
NC
NC
NC
1
2
28 NC
27
BIT 1 (MSB)
3
26
25
24
BIT 2
BIT 3
BIT 4
4
V
CC
5
REF OUT (10V)
6
REF GND
REF IN
NC
23 BIT 5
22
AD565A
TOP VIEW
(Not to Scale)
7
BIT 6
8
21 BIT 7
BIT 8
20
9
–V
EE
BIT 9
19
10
11
12
13
14
BIPOLAR OFFSET IN
DAC OUT
BIT 10
18
NC
10V SPAN R
20V SPAN R
BIT 11
17
BIT 12 (LSB)
16
15
PWR GND
NC = NO CONNECT
–7–
REV. D
AD565A/AD566A
STEP I . . . OFFSET ADJUST
Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000
volts output.
FIGURE 1. UNIPOLAR CONFIGURATION
This configuration will provide a unipolar 0 volt to +10 volt
output range. In this mode, the bipolar terminal, Pin 8, should
be grounded if not used for trimming.
STEP II . . . GAIN ADJUST
Turn ON All bits. Adjust 100 Ω gain trimmer R2 to give a read-
ing of +4.9976 volts.
+15V
100k⍀
R1
50k⍀
100⍀
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.
–15V
REF
OUT
V
BIPOLAR OFF
CC
20V SPAN
5k⍀
5k⍀
9.95k⍀
10V SPAN
FIGURE 3. OTHER VOLTAGE RANGES
R2
10V
100⍀
AD565A
The AD565A can also be easily configured for a unipolar 0 volt
to +5 volt range or 2.5 volt and 10 volt bipolar ranges by
using the additional 5k application resistor provided at the 20
volt span R terminal, Pin 11. For a 5 volt span (0 to +5 or
2.5), the two 5k resistors are used in parallel by shorting Pin
11 to Pin 9 and connecting Pin 10 to the op amp output and the
bipolar offset either to ground for unipolar or to REF OUT for
the bipolar offset either to ground for unipolar or to REF OUT
for the bipolar range. For the 10 volt range (20 volt span) use
the 5k resistors in series by connecting only Pin 11 to the op
amp output and the bipolar offset connected as shown. The 10
volt option is shown in Figure 3.
10pF
OUTPUT
0V TO
+10V
19.95k⍀
0.5mA
DAC
OUT
I
O
8k⍀
REF
IN
I
AD509
2.4k⍀
REF
DAC
I
=
OUT
20k⍀
REF
GND
4
؋
I REF
؋
CODE CODE
INPUT
POWER
GND
–V
EE
MSB
LSB
Figure 1. 0 V to +10 V Unipolar Voltage Output
STEP I . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer R1, until the output
reads 0.000 volts (1 LSB = 2.44 mV). In most cases this trim is
not needed, but Pin 8 should then be connected to Pin 12.
R1
REF
V
100⍀
BIPOLAR OFF
CC
OUT
20V SPAN
10V SPAN
5k⍀
5k⍀
9.95k⍀
STEP II . . . GAIN ADJUST
R2
100⍀
10V
Turn all bits ON and adjust 100 Ω gain trimmer R2, until the
output is 9.9976 volts. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 volts.) If a 10.2375 V full scale is
desired (exactly 2.5 mV/bit), insert a 120 Ω resistor in series
with the gain resistor at Pin 10 to the op amp output.
AD565A
10pF
OUTPUT
–10V TO
+10V
19.95k⍀
0.5mA
DAC
OUT
I
O
8k⍀
REF
IN
I
AD509
REF
DAC
I
=
OUT
4
؋
I 3.0k⍀
20k⍀
REF
GND
REF
؋
CODE FIGURE 2. BIPOLAR CONFIGURATION
This configuration will provide a bipolar output voltage from
–5.000 to +4.9976 volts, with positive full scale occurring with
all bits ON (all 1s).
CODE
INPUT
POWER
GND
–V
EE
MSB
LSB
Figure 3. 10 V Voltage Output
R1
100⍀
REF
OUT
V
BIPOLAR OFF
CC
20V SPAN
10V SPAN
5k⍀
5k⍀
9.95k⍀
R2
100⍀
10V
AD565A
10pF
OUTPUT
–5V TO
+5V
19.95k⍀
0.5mA
DAC
OUT
I
O
8k⍀
REF
IN
I
AD509
2.4k⍀
REF
DAC
I
=
OUT
4
؋
I 20k⍀
REF
GND
REF
؋
CODE CODE
INPUT
POWER
GND
–V
EE
MSB
LSB
Figure 2. 5 V Bipolar Voltage Output
–8–
REV. D
AD565A/AD566A
CONNECTING THE AD566A FOR BUFFERED VOLTAGE
OUTPUT
FIGURE 5. BIPOLAR CONFIGURATION
This configuration will provide a bipolar output voltage from
–5.000 volts to +4.9976 volts, with positive full scale occurring
with all bits ON (all 1s).
The standard current-to-voltage conversion connections using
an operational amplifier are shown here with the preferred trim-
ming techniques. If a low offset operational amplifier (AD510L,
AD517L, AD741L, AD301AL, AD OP07) is used, excellent
performance can be obtained in many situations without trim-
ming (an op amp with less than 0.5 mV max offset voltage
should be used to keep offset errors below 1/2 LSB). If a 50 Ω
fixed resistor is substituted for the 100 Ω trimmer, unipolar zero
will typically be within 1/2 LSB (plus op amp offset), and full
scale accuracy will be within 0.1% (0.25% max). Substituting a
50 Ω resistor for the 100 Ω bipolar offset trimmer will give a
bipolar zero error typically within 2 LSB (0.05%).
R1
100⍀
BIPOLAR OFF
20V SPAN
10V SPAN
AD566A
9.95k⍀
5k⍀
R2
100⍀
5k⍀
10pF
REF
IN
19.95k⍀
0.5mA
DAC
OUT
I
O
8k⍀
I
REF
DAC
E
The AD509 is recommended for buffered voltage-output appli-
cations which require a settling time to 1/2 LSB of one micro-
second. The feedback capacitor is shown with the optimum
value for each application; this capacitor is required to compen-
sate for the 25 picofarad DAC output capacitance.
REF
AD509
10V
+V
I
=
AD561
OUT
20k⍀
2.4k⍀
4
؋
I REF
؋
CODE REF
GND
CODE
INPUT
POWER
GND
–V
MSB
LSB
EE
FIGURE 4. UNIPOLAR CONFIGURATION
This configuration will provide a unipolar 0 volt to +10 volt
output range. In this mode, the bipolar terminal, Pin 7, should
be grounded if not used for trimming.
Figure 5. 5 V Bipolar Voltage Output
STEP I . . . OFFSET ADJUST
+15V
Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000
output volts.
100⍀
100k⍀
R1
50k⍀
BIPOLAR OFF
–15V
STEP II . . . GAIN ADJUST
Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a read-
ing of +4.9976 volts.
20V SPAN
AD566A
9.95k⍀
5k⍀
5k⍀
10V SPAN
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.
10pF
REF
IN
R2
100⍀
19.95k⍀
0.5mA
DAC
OUT
I
O
8k⍀
I
REF
DAC
E
REF
AD509
10V
+V
I
=
AD561
OUT
20k⍀
2.4k⍀
4
؋
I REF
؋
CODE REF
GND
CODE
INPUT
POWER
GND
–V
EE
MSB
LSB
Figure 4. 0 V to +10 V Unipolar Voltage Output
STEP I . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R1, until the output
reads 0.000 volts (1 LSB = 2.44 mV). In most cases this trim is
not needed, but Pin 7 should then be connected to Pin 12.
STEP II . . . GAIN ADJUST
Turn all bits ON and adjust 100 Ω gain trimmer, R2, until the
output is 9.9976 volts. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 volts.) If a 10.2375 V full scale is
desired (exactly 2.5 mV/bit), insert a 120 Ω resistor in series
with the gain resistor at Pin 10 to the op amp output.
–9–
REV. D
AD565A/AD566A
FIGURE 6. OTHER VOLTAGE RANGES
Table I. Digital Input Codes
The AD566A can also be easily configured for a unipolar 0 volt
to +5 volt range or 2.5 volt and 10 volt bipolar ranges by
using the additional 5k application resistor provided at the 20
volt span R terminal, Pin 11. For a 5 volt span (0 V to +5 V or
2.5 V), the two 5k resistors are used in parallel by shorting Pin
11 to Pin 9 and connecting Pin 10 to the op amp output and the
bipolar offset resistor either to ground for unipolar or to VREF
for the bipolar range. For the 10 volt range (20 volt span) use
the 5k resistors in series by connecting only Pin 11 to the op
amp output and the bipolar offset connected as shown. The
10 volt option is shown in Figure 6.
DIGITAL INPUT
ANALOG OUTPUT
MSB
LSB
Straight Binary
Offset Binary
Twos Compl.*
0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1
Zero
–FS
Zero
Mid Scale – 1 LSB Zero – 1 LSB
+FS – 1 LSB
–FS
+1/2 FS
Zero
+FS – l LSB
+ FS – 1 LSB
Zero – 1 LSB
*Inverts the MSB of the offset binary code with an external inverter to obtain
twos complement.
R1
5k⍀
BIPOLAR OFF
20V SPAN
10V SPAN
AD566A
9.95k⍀
5k⍀
5k⍀
14k⍀
10pF
R2
5k⍀
REF
IN
19.95k⍀
DAC
OUT
0.5mA
I
O
8k⍀
I
REF
DAC
E
REF
AD509
7.5V
–V
I
=
AD561
OUT
20k⍀
2.4k⍀
4
؋
I REF
؋
CODE REF
GND
CODE
INPUT
POWER
GND
R3
26k⍀*
–V
LSB
EE
MSB
*
THE PARALLEL COMBINATION OF THE BIPOLAR OFFSET RESISTOR
AND R3 ESTABLISHES A CURRENT TO BALANCE THE MSB CURRENT.
THE EFFECT OF TEMPERATURE COEFFICIENT MISMATCH BETWEEN
THE BIPOLAR RESISTOR COMBINATION AND DAC RESISTORS IS
EXPANDED ON PREVIOUS PAGE.
Fgure 6. 10 V Voltage Output
–10–
REV. D
AD565A/AD566A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Ceramic DIP (D-24)
0.098 (2.49) MAX
0.005 (0.13) MIN
24
13
0.610 (15.49)
0.500 (12.70)
1
12
0.620 (15.75)
0.590 (14.99)
PIN 1
0.075 (1.91)
0.015 (0.38)
1.290 (32.77) MAX
0.225 (5.72)
MAX
0.150
(3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.120 (3.05)
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
0.100 (2.54)
BSC
SOIC (R-28) Package
0.7125 (18.10)
0.6969 (17.70)
28
15
14
1
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
–11–
REV. D
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