AD5675ACPZ-RL [ADI]
Octal, 16-Bit nanoDAC;
| 型号： | AD5675ACPZ-RL |
| 厂家： | 
ADI |
| 描述： | Octal, 16-Bit nanoDAC |
| 文件： | 总27页 (文件大小：712K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Octal, 16-Bit nanoDAC+
with I2C Interface
AD5675
Data Sheet
FEATURES
GENERAL DESCRIPTION
High performance
The AD5675 is a low power, octal, 16-bit buffered voltage output
digital-to-analog converter (DAC). The device includes a gain
select pin, giving a full-scale output of VREF (gain = 1) or 2 ×
High relative accuracy (INL): 3 LSB maximum at 16 bits
Total unadjusted error (TUE): 0.14% of FSR maximum
Offset error: 1.5 mV maximum
V
REF (gain = 2). The device operates from a single 2.7 V to 5.5 V
Gain error: 0.06% of FSR maximum
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
supply and is guaranteed monotonic by design. The AD5675 is
available in 20-lead TSSOP and LFCSP packages. The power-on
reset circuit and a RSTSEL pin ensure that the output DACs power
up to zero scale or midscale and remain there until a valid write
takes place. The AD5675 contains a power-down mode, reducing
the current consumption to 1 µA typical while in power-down
mode. The AD5675 uses a versatile 2-wire serial interface that
operates at clock rates up to 400 kHz, and includes a VLOGIC pin
intended for 1.62 V to 5.5 V logic.
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/bit)
1.8 V logic compatibility
I2C-compatible serial interface
20-lead TSSOP and LFCSP RoHS-compliant packages
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Table 1. Octal nanoDAC+® Devices
Interface
Reference
16-Bit
12-Bit
SPI
Internal
External
Internal
AD5676R
AD5676
AD5675R
AD5672R
Not applicable
AD5671R
I2C
Data acquisition systems
FUNCTIONAL BLOCK DIAGRAM
V
V
V
REF
LOGIC
DD
AD5675
BUFFER
DAC
INPUT
STRING
DAC 0
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
OUT
OUT
OUT
OUT
OUT
OUT
OUT
REGISTER
REGISTER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
DAC
REGISTER
STRING
DAC 1
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
INPUT
REGISTER
SCL
DAC
REGISTER
INPUT
REGISTER
STRING
DAC 3
SDA
A1
DAC
REGISTER
INPUT
REGISTER
STRING
DAC 4
DAC
REGISTER
INPUT
REGISTER
STRING
DAC 5
A0
DAC
REGISTER
STRING
DAC 6
INPUT
REGISTER
LDAC
DAC
REGISTER
STRING
DAC 7
INPUT
REGISTER
RESET
OUT
GAIN POWER-DOWN
POWER-ON
RESET
×1/×2
LOGIC
RSTSEL
GAIN
GND
Figure 1.
Rev. C
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Technical Support
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AD5675
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
I2C Slave Address........................................................................ 20
Serial Operation ......................................................................... 20
Write Operation.......................................................................... 20
Read Operation........................................................................... 21
Multiple DAC Readback Sequence.......................................... 21
Power-Down Operation ............................................................ 22
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 18
Digital-to-Analog Converter .................................................... 18
Transfer Function ....................................................................... 18
DAC Architecture....................................................................... 18
Serial Interface ............................................................................ 19
Write and Update Commands.................................................. 20
LDAC
Load DAC (Hardware
Pin)........................................... 22
LDAC
Mask Register ................................................................. 23
RESET
Hardware Reset (
) .......................................................... 24
Reset Select Pin (RSTSEL) ........................................................ 24
Software Reset............................................................................. 24
Amplifier Gain Selection on LFCSP Package......................... 24
Applications Information .............................................................. 25
Power Supply Recommendations............................................. 25
Microprocessor Interfacing....................................................... 25
AD5675 to ADSP-BF531 Interface........................................... 25
Layout Guidelines....................................................................... 25
Galvanically Isolated Interface ................................................. 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
REVISION HISTORY
4/2018—Rev. B to Rev. C
8/2016—Rev. A to Rev. B
Change to Output Noise Spectral Density Parameter; Table 3 ...5
Changes to Features Section, General Description Section, and
Figure 1 .............................................................................................. 1
Changes to Specifications Section.................................................. 3
Changes to VLOGIC Parameter, Table 2 ............................................ 4
Deleted Endnote 3, Table 2; Renumbered Sequentially .............. 4
Changes to AC Characteristics Section, Timing Characteristics
Section, and Table 3.......................................................................... 5
Changes to Figure 2 and Figure 3................................................... 6
Changes to Table 5 and Thermal Resistance Section................... 7
Change to VLOGIC Pin Description, Table 7.................................... 8
Change to VLOGIC Pin Description, Table 8.................................... 9
Changes to Figure 19...................................................................... 12
Changes to Table 9.......................................................................... 19
Changes to Update DAC Register n with Contents of Input
Register n Section and Write to and Update DAC Channel n
(Independent of LDAC) Section................................................... 20
Changes to Power-Down Operation Section.............................. 22
10/2015—Rev. 0 to Rev. A
Added 20-Lead LFCSP ......................................................Universal
Changes to Features Section and General Description Section....1
Changes to Table 2.............................................................................3
Change to Table 5 ..............................................................................7
Added Table 6; Renumbered Sequentially .....................................9
Change to Figure 4 Caption and Table 6 Title...............................8
Added Figure 5; Renumbered Sequentially and Table 7 ..............9
Change to Figure 19 Caption........................................................ 12
Change to Figure 33 ....................................................................... 14
Change to Table 8 ........................................................................... 19
Change to Read Operation Section.............................................. 21
LDAC
Changes to
Mask Register Section and Table 13 ............... 23
Added Amplifier Gain Selection on LFCSP Package Section,
Table 15, and Table 16.................................................................... 24
Added Figure 52, Outline Dimensions........................................ 26
Changes to Ordering Guide.......................................................... 26
RESET
Changes to Hardware Reset (
) Section............................ 24
Added Software Reset Section ...................................................... 24
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 27
1/2015—Revision 0: Initial Version
Rev. C | Page 2 of 27
Data Sheet
AD5675
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, resistive load (RL) = 2 kΩ, capacitive load (CL) = 200 pF, all specifications TA = −40°C to
+125°C, unless otherwise noted.
Table 2.
A Grade
Typ
B Grade
Typ
Parameter
STATIC PERFORMANCE1
Min
Max
Min
Max
Unit
Test Conditions/Comments
Resolution
Relative Accuracy/Integral
Nonlinearity (INL)2
16
16
Bits
LSB
1.8
8
1.8
3
Gain = 1
1.7
0.7
8
1
1.7
0.7
3
1
LSB
LSB
Gain = 2
Gain = 1
Differential Nonlinearity
(DNL)2
0.5
0.8
−0.75
−0.1
−0.018
1
4
6
4
0.28
0.5
0.8
−0.75
−0.1
−0.018
1
1.6
2
1.5
0.14
LSB
mV
mV
mV
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Zero Code Error2
Offset Error2
Gain = 2
Full-Scale Error2
% of full- Gain = 1
scale
range
(FSR)
−0.013
+0.04
−0.02
0.03
0.006
1
0.14
0.24
0.12
0.3
−0.013
+0.04
−0.02
0.03
0.006
1
0.07
0.12
0.06
0.18
0.14
% of FSR Gain = 2
% of FSR Gain = 1
% of FSR Gain = 2
% of FSR Gain = 1
% of FSR Gain = 2
µV/°C
Gain Error2
TUE
0.25
Offset Error Drift2
DC Power Supply Rejection
0.25
0.25
mV/V
DAC code = midscale, VDD = 5 V 10%
Ratio (PSRR)2
DC Crosstalk2
2
2
µV
Due to single channel, full-scale
output change
3
2
3
2
µV/mA
µV
Due to load current change
Due to powering down (per channel)
OUTPUT CHARACTERISTICS
Output Voltage Range
0
0
VREF
2 × VREF
15
0
0
VREF
2 × VREF
15
V
V
mA
nF
Gain = 1
Gain = 2
Output Current Drive (IOUT
Capacitive Load Stability
)
2
2
RL = ∞
10
10
nF
kΩ
µV/mA
RL = 1 kΩ
Resistive Load3
Load Regulation
1
1
183
177
183
177
VDD = 5 V 10%, DAC code =
midscale, −30 mA ≤ IOUT ≤ +30 mA
VDD = 3 V 10%, DAC code =
µV/mA
midscale, −20 mA ≤ IOUT ≤ +20 mA
Short-Circuit Current4
Load Impedance at Rails5
Power-Up Time
40
25
2.5
40
25
2.5
mA
Ω
µs
Exiting power-down mode, VDD = 5 V
REFERENCE INPUT
Reference Input Current
398
789
398
789
µA
µA
V
V
kΩ
kΩ
VREF = VDD = VLOGIC = 5.5 V, gain = 1
VREF = VDD = VLOGIC = 5.5 V, gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Reference Input Range
1
1
VDD
VDD/2
1
1
VDD
VDD/2
Reference Input Impedance
14
7
14
7
Rev. C | Page 3 of 27
AD5675
Data Sheet
A Grade
Typ
B Grade
Typ
Parameter
LOGIC INPUTS
Input Current
Input Voltage
Low, VIL
Min
Max
Min
Max
Unit
Test Conditions/Comments
1
1
µA
Per pin
0.3 ×
VLOGIC
0.3 ×
VLOGIC
V
High, VIH
0.7 ×
VLOGIC
0.7 ×
VLOGIC
V
Pin Capacitance
LOGIC OUTPUTS (SDA)
Output Voltage
Low, VOL
3
4
3
4
pF
0.4
0.4
V
V
ISINK = 200 μA
ISOURCE = 200 μA
High, VOH
VLOGIC
0.4
−
VLOGIC
0.4
−
Floating State Output
Capacitance
pF
POWER REQUIREMENTS
VLOGIC
VLOGIC Supply Current (ILOGIC
1.62
5.5
3
3
3
3
1.62
5.5
3
3
3
3
V
)
µA
µA
µA
µA
V
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
VDD
2.7
5.5
5.5
2.7
5.5
5.5
VREF
1.5
+
VREF
1.5
+
V
Gain = 2
VDD Supply Current, IDD
Normal Mode6
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
−40°C to +85°C
−40°C to +125°C
Tristate to 1 kΩ, −40°C to +85°C
Power-down to 1 kΩ, −40°C to +85°C
Tristate to 1 kΩ, −40°C to +105°C
Power-down to 1 kΩ, −40°C to +105°C
Tristate to 1 kΩ, −40°C to +125°C
Power-down to 1 kΩ, −40°C to +125°C
1.1
1.1
1
1
1
1
1
1
1.26
1.3
1.7
1.7
2.5
2.5
5.5
5.5
1.1
1.1
1
1
1
1
1
1
1.26
1.3
1.7
1.7
2.5
2.5
5.5
5.5
mA
mA
µA
µA
µA
µA
µA
µA
All Power-Down Modes7
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =
V
DD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2 See the Terminology section.
3 Together, Channel 0, Channel 1, Channel 2, and Channel 3 can source or sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source or
sink 40 mA up to a junction temperature of 125°C.
4 VDD = 5 V. The AD5675 includes current limiting to protect the device during temporary overload conditions. Junction temperature can be exceeded during current
limit. Operation above the specified maximum operation junction temperature can impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
6 Interface inactive. All DACs active. DAC outputs unloaded.
7 All DACs powered down.
Rev. C | Page 4 of 27
Data Sheet
AD5675
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 1.62 V ≤ VLOGIC ≤ 5.5 V, all specifications TA = −40°C to +125°C, unless
otherwise noted.
Table 3.
Parameter
Min Typ
Max
Unit
Test Conditions/Comments
Output Voltage Settling Time1
5
8
µs
¼ to ¾ scale settling to 2 LSB
Slew Rate
0.8
1.4
0.13
0.1
V/µs
Digital-to-Analog Glitch Impulse1
Digital Feedthrough1
Digital Crosstalk1
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
dB
1 LSB change around major carry (gain = 1)
Analog Crosstalk1
−0.25
Gain = 1
Gain = 2
Gain = 2
−1.3
−2.0
−80
80
6
90
DAC-to-DAC Crosstalk1
Total Harmonic Distortion (THD)1, 2
Output Noise Spectral Density (NSD)1
Output Noise
TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
nV/√Hz DAC code = midscale, bandwidth = 10 kHz, gain = 1 and 2
µV p-p
dB
dB
dB
0.1 Hz to 10 Hz, gain = 1
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Signal-to-Noise-and-Distortion Ratio
(SINAD)
TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
83
80
1 See the Terminology section.
2 Digitally generated sine wave (fOUT) at 1 kHz.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless otherwise noted.
Table 4.
Parameter1
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
Max
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Description
t1
t2
t3
t4
t5
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start hold time
tSU,DAT, data setup time
2
t6
0.9
tHD,DAT, data hold time
t7
t8
t9
t10
t11
tSU,STA, repeated start setup time
tSU,STO, stop condition setup time
tBUF, bus free time between a stop condition and a start condition
tR, rise time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting/receiving
LDAC pulse width
3
0
300
3
20 + 0.1CB
20
t12
t13
t14
400
8
SCL rising edge to LDAC rising edge
RESET minimum pulse width low, 1.62 V ≤ VLOGIC ≤ 2.7 V
RESET minimum pulse width low, 2.7 V ≤ VLOGIC ≤ 5.5 V
RESET activation time, 1.62 V ≤ VLOGIC ≤ 2.7 V
RESET activation time, 2.7 V ≤ VLOGIC ≤ 5.5 V
Pulse width of suppressed spike
Capacitive load for each bus line
10
90
90
0
t15
4
tSP
CB
50
400
4
1 See Figure 2 and Figure 3.
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the minimum VIH of the SCL signal) to bridge the undefined region of the
SCL falling edge.
3 tR and tF are measured from 0.3 × VDD to 0.7 × VDD
.
4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
Rev. C | Page 5 of 27
AD5675
Data Sheet
Timing Diagrams
START
REPEATED START
CONDITION
STOP
CONDITION
CONDITION
SDA
t9
t10
t11
t4
t3
SCL
t4
t2
t1
t6
t5
t7
t8
t12
1
2
t13
LDAC
LDAC
t12
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
2
Figure 2. Two-Wire Serial Interface Timing Diagram
t14
RESET
t15
V
x
OUT
RESET
Figure 3.
Timing Diagram
Rev. C | Page 6 of 27
Data Sheet
AD5675
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 5.
Parameter
Rating
VDD to GND
VLOGIC to GND
VOUTx to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak Temperature,
Pb-Free (J-STD-020)
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +125°C
−65°C to +150°C
125°C
Table 6. Thermal Resistance
Package Type
θJA
θJB
θJC
ΨJT
ΨJB
Unit
20-Lead TSSOP
(RU-20)1
98.65 44.39 17.58 1.77 43.9 °C/W
20-Lead LFCSP
(CP-20-8)2
82
16.67 32.5
0.43 22
°C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51
260°C
2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 7 of 27
AD5675
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
20
19
18
17
16
15
14
13
12
11
V
1
V
2
OUT
OUT
2
V
0
V
3
OUT
OUT
REF
3
V
V
DD
4
V
RESET
SDA
LOGIC
SCL
A0
AD5675
TOP VIEW
(Not to Scale)
5
6
LDAC
RSTSEL
GND
7
A1
8
GAIN
9
V
7
6
V
V
4
5
OUT
OUT
OUT
OUT
10
V
Figure 4. TSSOP Pin Configuration
Table 7. TSSOP Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
VOUT
VOUT
VDD
1
0
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
Power Supply Input. The AD5675 operates from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF capacitor in
parallel with a 0.1 µF capacitor to GND.
4
5
VLOGIC
SCL
Digital Power Supply. The voltage on this pin ranges from 1.62 V to 5.5 V.
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 24-bit input shift
register.
6
7
8
A0
A1
GAIN
Address Input. This pin sets the first LSB of the 7-bit slave address.
Address Input. This pin sets the second LSB of the 7-bit slave address.
Span Set. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC
all eight DACs output a span of 0 V to 2 × VREF
,
.
9
VOUT
VOUT
VOUT
VOUT
GND
RSTSEL
7
6
5
4
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Device.
10
11
12
13
14
Power-On Reset. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to power up all
eight DACs to midscale.
15
LDAC
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all
DAC registers to be updated if the input registers have new data, which allows all DAC outputs to update
simultaneously. This pin can also be tied permanently low.
16
17
SDA
Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift
register. SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external pull-up resistor.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored.
When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending
on the state of the RSTSEL pin.
RESET
18
19
20
VREF
VOUT
VOUT
Reference Input Voltage.
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
3
2
Rev. C | Page 8 of 27
Data Sheet
AD5675
15
V
REF
V
1
2
3
4
5
DD
14 RESET
13 SDA
V
AD5675
LOGIC
SCL
TOP VIEW
(Not to Scale)
12 LDAC
11 GND
A0
A1
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. THE EXPOSED PAD
MUST BE TIED TO GND.
Figure 5. LFCSP Pin Configuration
Table 8. LFCSP Function Descriptions
Pin No. Mnemonic
Description
1
VDD
Power Supply Input. The AD5675 operates from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF capacitor in
parallel with a 0.1 µF capacitor to GND.
2
3
VLOGIC
SCL
Digital Power Supply. The voltage on this pin ranges from 1.62 V to 5.5 V.
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 24-bit input shift
register.
4
5
6
7
8
9
A0
A1
Address Input. Sets the first LSB of the 7-bit slave address.
Address Input. Sets the second LSB of the 7-bit slave address.
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
No Internal Connection.
VOUT
VOUT
VOUT
VOUT
NIC
7
6
5
4
10, 16
11
12
GND
LDAC
Ground Reference Point for All Circuitry on the Device.
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all
DAC registers to be updated if the input registers have new data, which allows all DAC outputs to update
simultaneously. This pin can also be tied permanently low.
13
14
SDA
Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift
register. SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external pull-up resistor.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored.
When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending
on the state of the RSTSEL pin.
RESET
15
17
18
19
20
VREF
Reference Input Voltage.
VOUT
VOUT
VOUT
VOUT
3
2
1
0
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
EPAD
Rev. C | Page 9 of 27
AD5675
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
10
8
1.5
6
1.0
4
0.5
2
0
0
–2
–4
–6
–8
–10
–0.5
–1.0
–1.5
–2.0
V
= 5V
= 25°C
DD
T
A
–40
–20
0
20
40
60
80
100
100
100
120
120
120
0
10000
20000
30000
40000
50000
60000
70000
TEMPERATURE (°C)
CODE
Figure 9. INL Error vs. Temperature
Figure 6. INL Error vs. Code
10
8
1.0
0.8
6
0.6
4
0.4
2
0.2
0
0
–2
–4
–6
–8
–10
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 5V
DD
T
= 25°C
A
–40
–20
0
20
40
60
80
0
10000
20000
30000
40000
50000
60000
70000
TEMPERATURE (°C)
CODE
Figure 10. DNL Error vs. Temperature
Figure 7. DNL Error vs. Code
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.04
0.03
0.02
0.01
0
V
T
= 5V
DD
= 25°C
A
–0.01
–0.02
–40
–20
0
20
40
60
80
0
10000
20000
30000
40000
50000
60000
70000
TEMPERATURE (°C)
CODE
Figure 11. TUE vs. Temperature
Figure 8. TUE vs. Code
Rev. C | Page 10 of 27
Data Sheet
AD5675
10
8
0.10
0.08
0.06
0.04
0.02
0
6
4
2
FULL-SCALE ERROR
GAIN ERROR
0
–2
–4
–6
–0.02
–0.04
–0.06
–0.08
–0.10
V
= 5V
DD
T = 25°C
A
V
= 5V
= 25°C
DD
–8
T
A
–10
–40
–20
0
20
40
60
80
100
120
2.7
3.2
3.7
4.2
4.7
5.2
5.2
5.2
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 12. INL Error vs. Supply Voltage
Figure 15. Gain Error and Full-Scale Error vs. Temperature
10
8
0.10
0.08
0.06
0.04
0.02
0
6
4
2
GAIN ERROR
0
–2
–4
–6
–8
–10
–0.02
–0.04
–0.06
–0.08
–0.10
FULL-SCALE ERROR
V
= 5V
= 25°C
DD
T
A
V
T
= 5V
DD
= 25°C
A
2.7
3.2
3.7
4.2
4.7
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 13. DNL Error vs. Supply Voltage
Figure 16. Gain Error and Full-Scale Error vs. Supply Voltage
0.10
0.08
0.06
0.04
0.02
0
1.8
1.5
1.2
0.9
0.6
0.3
0
V
T
= 5V
= 25°C
DD
A
ZERO CODE ERROR
OFFSET ERROR
–0.02
–0.04
–0.06
–0.08
–0.10
V
T
= 5V
= 25°C
DD
A
–0.3
–0.6
2.7
3.2
3.7
4.2
4.7
–40
–20
0
20
40
60
80
100
120
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 14. TUE vs. Supply Voltage
Figure 17. Zero Code Error and Offset Error vs. Temperature
Rev. C | Page 11 of 27
AD5675
Data Sheet
1.5
1.0
0.5
0
6
5
0xFFFF
0xC000
0x8000
ZERO CODE ERROR
OFFSET ERROR
4
3
2
0x4000
0x0000
1
–0.5
0
–1.0
–1.5
V
= 5V
DD
= 25°C
–1
–2
T
A
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
LOAD CURRENT (A)
Figure 18. Zero Code Error and Offset Error vs. Supply Voltage
Figure 21. Source and Sink Capability at 5 V
120
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
DD
= 25°C
T
A
REFERENCE = 2.5V
100
80
60
40
20
0
0xFFFF
0xC000
0x8000
0x4000
0x0000
–0.5
–1.0
–0.06
0.83 0.85 0.87 0.89 0.91 0.93 0.95 0.97 0.99 1.01
–0.04
–0.02
0
0.02
0.04
0.06
LOAD CURRENT (A)
I
FULL SCALE (mA)
DD
Figure 19. Supply Current (IDD) Histogram
Figure 22. Source and Sink Capability at 3 V
1.4
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.0
0.6
DEVICE 1
DEVICE 2
DEVICE 3
SINKING, V = –2.7V
DD
SINKING, V = –3.0V
DD
SINKING, V = –5.0V
DD
SOURCING, V = –5.0V
DD
SOURCING, V = –3.0V
DD
SOURCING, V = –2.7V
DD
0.2
–0.2
–0.6
–1.0
–1.4
0
0.005
0.010
0.015
0.020
0.025
0.030
0
10000
20000
30000
40000
50000
60000
70000
LOAD CURRENT (A)
CODE
Figure 20. Headroom/Footroom (ΔVOUT) vs. Load Current
Figure 23. IDD vs. Code
Rev. C | Page 12 of 27
Data Sheet
AD5675
2.0
1.8
1.6
1.4
1.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
FULL SCALE
ZERO CODE
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
EXTERNAL REFERENCE, FULL SCALE
1.0
0.8
0.6
0.4
V
= 5.5V
DD
GAIN = 1
1/4 TO 3/4 SCALE
–40
–20
0
20
40
60
80
100
120
80
100
120
140
160
180
200
TEMPERATURE (°C)
TIME (µs)
Figure 24. IDD vs. Temperature
Figure 27. Full-Scale Settling Time
6
5
0.006
0.005
0.004
0.003
0.002
0.001
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
V
V
(V)
DD
0 (V)
1 (V)
2 (V)
3 (V)
4 (V)
5 (V)
6 (V)
7 (V)
OUT
4
FULL SCALE
ZERO CODE
V
OUT
V
V
OUT
3
OUT
V
OUT
V
OUT
2
V
V
OUT
OUT
EXTERNAL REFERENCE, FULL SCALE
1
0
–1
–0.001
10
0
2
4
6
8
2.7
3.2
3.7
4.2
4.7
5.2
TIME (ms)
SUPPLY VOLTAGE (V)
Figure 25. IDD vs. Supply Voltage
Figure 28. Power-On Reset to 0 V and Midscale
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
3.0
MIDSCALE, GAIN = 2
FULL SCALE
2.5
2.0
1.5
1.0
0.5
0
RESET
ZERO CODE
MIDSCALE, GAIN = 1
EXTERNAL REFERENCE, FULL SCALE
V
= 5V
DD
= 25°C
T
A
2.7
3.2
3.7
4.2
4.7
5.2
–5
0
5
10
INPUT LOGIC VOLTAGE (V)
TIME (µs)
Figure 26. IDD vs. Input Logic Voltage
Figure 29. Exiting Power-Down to Midscale
Rev. C | Page 13 of 27
AD5675
Data Sheet
0.004
0.003
0.002
0.001
0
1
–0.001
–0.002
–0.003
V
= 5V
DD
GAIN = 1
= 25°C
T
A
REFERENCE = 2.5V
CODE = 7FFF TO 8000
ENERGY = 1.209376nV-sec
2
–0.004
15
16
17
18
19
20
21
22
CH1 5µV
M1.00s
A
CH1
401mV
TIME (µs)
Figure 33. 0.1 Hz to 10 Hz Output Noise Plot
Figure 30. Digital-to-Analog Glitch Impulse
1200
1000
800
600
400
200
0
0.003
0.002
0.001
0
V
= 5V
= 25°C
FULL SCALE
MIDSCALE
DD
T
A
ZERO SCALE
GAIN = 1
–0.001
–0.002
–0.003
–0.004
–0.005
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
–0.006
0
2
4
6
8
10
12
14
16
18
20
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
TIME (µs)
Figure 31. Analog Crosstalk
Figure 34. Noise Spectral Density (NSD)
0.012
0.010
0.008
0.006
0.004
0.002
0
0
–20
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
V
= 5V
= 25°C
DD
T
A
–40
–60
–80
–100
–120
–140
–160
–180
–0.002
–0.004
–0.006
–0.008
–0.010
0
0
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
TIME (µs)
FREQUENCY (kHz)
Figure 35. Total Harmonic Distortion (THD) at 1 kHz
Figure 32. DAC-to-DAC Crosstalk
Rev. C | Page 14 of 27
Data Sheet
AD5675
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
3
2
1
0.3
C
C
C
C
C
= 0nF
= 0.1nF
= 1nF
= 4.7nF
= 10nF
L
L
L
L
L
0.2
0.1
RESET
MIDSCALE, GAIN = 1
ZERO SCALE, GAIN = 1
0
0
–20
0
20
40
60
0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20
TIME (ms)
TIME (µs)
Figure 36. Settling Time at Various Capacitive Loads
Figure 38. Hardware Reset
2.0
4.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
0xFFFF
0xC000
0x8000
0x4000
0x0000
–0.5
–1.0
–0.06
80
100
120
140
160
180
200
–0.04
–0.02
0
0.02
0.04
0.06
LOAD CURRENT (A)
TIME (µs)
Figure 37. Settling Time, 5.5 V
Figure 39. Multiplying Bandwidth
Rev. C | Page 15 of 27
AD5675
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For a DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000).
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of 1 LSB maximum ensures monotonicity. This DAC is
guaranteed monotonic by design.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. The ideal output is
0 V. The zero code error is always positive because the output of
the DAC cannot go below 0 V due to a combination of the offset
errors in the DAC and the output amplifier. Zero code error is
expressed in mV.
Noise Spectral Density (NSD)
NSD is a measurement of the internally generated random
noise. Random noise is characterized as spectral density
(nV/√Hz). To measure NSD, load the DAC to midscale and
measure the noise at the output. It is measured in nV/√Hz.
Full-Scale Error
DC Crosstalk
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. The ideal
output is VDD − 1 LSB. Full-scale error is expressed in percent of
full-scale range (% of FSR).
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in μV.
Gain Error
Gain error is a measure of the span error of a DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has on
another DAC kept at midscale. It is expressed in μV/mA.
Offset Error Drift
Digital Crosstalk
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured with Code 256
loaded in the DAC register. It can be negative or positive.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. To
measure analog crosstalk, first load one of the input registers
with a full-scale code change (all 0s to all 1s and vice versa).
DC Power Supply Rejection Ratio (PSRR)
The dc PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
LDAC
Then, execute a software
and monitor the output of the
V
OUT to the change in VDD for the full-scale output of the DAC.
DAC whose digital code was not changed. The area of the glitch
is expressed in nV-sec.
It is measured in mV/V. VREF is held at 2 V, and VDD is varied by
10%.
DAC-to-DAC Crosstalk
Output Voltage Settling Time
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa), using the write to and update commands
while monitoring the output of the victim channel that is at
midscale. The energy of the glitch is expressed in nV-sec.
The output voltage settling time is the amount of time it takes
for the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change.
Rev. C | Page 16 of 27
Data Sheet
AD5675
Multiplying Bandwidth
Total Harmonic Distortion (THD)
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. THD is measured in dB.
Rev. C | Page 17 of 27
AD5675
Data Sheet
THEORY OF OPERATION
V
REF
DIGITAL-TO-ANALOG CONVERTER
R
The AD5675 is an octal, 16-bit, serial input, voltage output DAC.
The AD5675 operates from a supply voltage of 2.7 V to 5.5 V.
Data is written to the AD5675 in a 24-bit word format via a
2-wire serial interface. The AD5675 incorporates a power-on
reset circuit to ensure that the DAC output powers up to a known
output state. The device also has a software power-down mode
that reduces the typical current consumption to 1 µA.
R
R
TO OUTPUT
AMPLIFIER
TRANSFER FUNCTION
The gain of the output amplifier is set to ×1 or ×2 using the gain
select pin (GAIN). When the gain select pin is tied to GND, all
eight DAC outputs have a span from 0 V to VREF. When the gain
select pin is tied to VLOGIC, all eight DACs output a span of 0 V to 2
R
R
× VREF
.
DAC ARCHITECTURE
Figure 41. Resistor String Structure
The AD5675 implements a segmented string DAC architecture
with an internal output buffer. Figure 40 shows the internal
block diagram.
Output Amplifier
The output buffer amplifier generates rail-to-rail voltages on its
output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, the offset
error, and the gain error. The GAIN pin selects the gain of the
output. If the GAIN pin is tied to GND, all eight outputs have a
gain of 1, and the output range is 0 V to VREF. If the GAIN pin is
tied to VLOGIC, all eight outputs have a gain of 2, and the output
V
REF
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
x
OUT
REF (–)
GAIN
(GAIN = 1 OR 2)
GND
range is 0 V to 2 × VREF
.
Figure 40. Single DAC Channel Architecture Block Diagram
This amplifier can drive a load of 1 kΩ in parallel with 10 nF
to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾ scale
settling time of 5 µs.
The simplified segmented resistor string DAC structure is
shown in Figure 41. The code loaded to the DAC register
determines the node on the string where the voltage is tapped
off and fed into the output amplifier. The voltage is tapped off
by closing one of the switches and connecting the string to the
amplifier. Because each resistance in the string has the same
value, R, the string DAC is guaranteed monotonic.
Rev. C | Page 18 of 27
Data Sheet
AD5675
Table 9. Command Definitions
Command
SERIAL INTERFACE
The AD5675 uses a 2-wire, I2C-compatible serial interface. The
device can be connected to an I2C bus as a slave device under
the control of the master devices. The AD5675 supports
standard (100 kHz) and fast (400 kHz) data transfer modes.
Support is not provided for 10-bit addressing and general call
addressing.
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
1
No operation
Write to Input Register n (where n = 0 to 7,
depending on the DAC selected from the
address bits in Table 10, dependent
on LDAC)
Input Shift Register
0
0
1
0
Update DAC Register n with the contents
of Input Register n
The input shift register of the AD5675 is 24 bits wide. Data
is loaded MSB first (DB23), and the first four bits are the
command bits, C3 to C0 (see Table 9), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 10), and finally, the 16-
bit data-word.
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Write to and update DAC Channel n
Power down/power up the DAC
Hardware LDAC mask register
Software reset (power-on reset)
Gain setup register (LFCSP package only)
Reserved
The data-word comprises a 16-bit input code (see Figure 42).
These data bits are transferred to the input register on the
24 falling edges of SCL.
Set up the readback register (readback
enable)
1
1
0
0
1
1
0
1
Update all channels of the input register
simultaneously with the input data
Update all channels of the DAC register
and input register simultaneously with
the input data
Commands execute on individual DAC channels, combined DAC
channels, or on all DACs, depending on the address bits selected.
1
1
0
0
Reserved
…
1
…
1
…
1
…
1
Reserved
Table 10. Address Commands
Channel Address, Bits[3:0]
A3
0
0
0
0
0
0
0
0
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Selected DAC Channel
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 42. Input Shift Register Content
Rev. C | Page 19 of 27
AD5675
Data Sheet
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on
SERIAL OPERATION
The 2-wire I2C serial bus protocol operates as follows:
LDAC
)
Command 0001 allows the user to write to the dedicated input
LDAC
1. The master initiates a data transfer by establishing a start
condition when a high to low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address.
register of each DAC individually. When
register is transparent, if not controlled by the
is low, the input
LDAC
mask register.
Update DAC Register n with Contents of Input Register n
2. The slave device with the transmitted address responds by
pulling SDA low during the ninth clock pulse (this is called
the acknowledge bit, or ACK). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to or read from its input shift register.
3. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
Transitions on the SDA line must occur during the low period
of SCL; SDA must remain stable during the high period of SCL.
4. After all data bits are read or written, a stop condition is
established. In write mode, the master pulls the SDA line high
during the 10th clock pulse to establish a stop condition. In
read mode, the master issues a no acknowledge (NACK)
for the ninth clock pulse (that is, the SDA line remains
high). The master then brings the SDA line low before the
10th clock pulse, and then high again during the 10th clock
pulse to establish a stop condition.
Command 0010 loads the DAC registers and outputs with the
contents of the selected input registers and updates the DAC
outputs directly. Data Bit D7 to Bit D0 determine which DACs
have data from the input register transferred to the DAC
register. Setting a bit to 1 transfers data from the input register
to the appropriate DAC register.
LDAC
Write to and Update DAC Channel n (Independent of
)
Command 0011 allows the user to write to the DAC registers
and updates the DAC outputs directly. The DAC address bits
are used to select the DAC channel.
I2C SLAVE ADDRESS
The AD5675 has a 7-bit I2C slave address. The five MSBs are
00011, and the two LSBs (A1 and A0) are set by the state of the
A1 and A0 address pins. The ability to make hardwired changes to
A1 and A0 allows the user to incorporate up to four AD5675
devices on one bus (see Table 11).
WRITE OPERATION
Table 11. Device Address Selection
When writing to the AD5675, begin with a start command
A1 Pin Connection
A0 Pin Connection
A1
0
0
1
1
A0
0
1
0
1
W
followed by an address byte (R/ = 0), after which the DAC
GND
GND
VLOGIC
VLOGIC
GND
VLOGIC
GND
VLOGIC
acknowledges that it is prepared to receive data by pulling SDA
low. The AD5675 require two bytes of data for the DAC, and a
command byte that controls various DAC functions. Three bytes
of data must, therefore, be written to the DAC with the command
byte followed by the most significant data byte and the least
significant data byte, as shown in Figure 43. All these data bytes
are acknowledged by the AD5675. A stop condition follows.
1
9
1
9
SCL
0
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK BY
SDA
ACK BY
AD5675
START BY
MASTER
AD5675
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB8
ACK BY
AD5675
ACK BY
AD5675
STOP BY
MASTER
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 43. I2C Write Operation
Rev. C | Page 20 of 27
Data Sheet
AD5675
READ OPERATION
MULTIPLE DAC READBACK SEQUENCE
When reading data back from the AD5675, begin with a start
When reading data back from multiple AD5675 DACs, the user
W
W
command followed by an address byte (R/ = 0), after which
begins with an address byte (R/ = 0), after which the DAC
the DAC acknowledges that it is prepared to receive data by
pulling SDA low. The address byte must be followed by the
command byte, which determines both the read command that
is to follow and the pointer address to read from; the command
byte is also acknowledged by the DAC. The user configures the
channel to read back the contents of one or more DAC input
registers and sets the readback command to active using the
command byte.
acknowledges that it is prepared to receive data by pulling SDA
low. The address byte must be followed by the command byte,
which is also acknowledged by the DAC. The user selects the
first channel to read back using the command byte.
Following this sequence, the master establishes a repeated start
W
condition, and the address is resent with R/ = 1. This byte is
acknowledged by the DAC, indicating that it is prepared to
transmit data. The first two bytes of data are then read from
DAC Input Register n (selected using the command byte), MSB
first, as shown in Figure 44. The next two bytes read back are the
contents of DAC Input Register n + 1, and the next bytes read
back are the contents of DAC Input Register n + 2. Data is read
from the DAC input registers in this auto-incremented fashion
until a NACK followed by a stop condition follows. If the
contents of DAC Input Register 7 are read out, the next two
bytes of data read are the contents of DAC Input Register 0.
Then, the master establishes a repeated start condition, and the
W
address is resent with R/ = 1. This byte is acknowledged by the
DAC, indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC, as shown in Figure 44. A
NACK condition from the master, followed by a stop condition,
completes the read sequence. If more than one DAC is selected,
DAC 0 is read back by default.
1
9
1
9
SCL
SDA
0
0
0
1
1
A1
A0
R/W
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK BY
ACK BY
AD5675
START BY
MASTER
AD5675
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
SDA
0
0
0
1
1
A1
A0
R/W
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
REPEATED START BY
MASTER
ACK BY
AD5675
ACK BY
MASTER
FRAME 3
SLAVE ADDRESS
FRAME 4
MOST SIGNIFICANT
DATA BYTE n
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7 DB6
DB5 DB4
DB3 DB2
DB1
DB0
ACK BY
MASTER
NACK BY
MASTER
STOP BY
MASTER
FRAME 5
LEAST SIGNIFICANT
DATA BYTE n
FRAME 6
MOST SIGNIFICANT
DATA BYTE n + 1
Figure 44. I2C Read Operation
Rev. C | Page 21 of 27
AD5675
Data Sheet
The bias generator, output amplifier, resistor string, and other
associated linear circuitry shut down when power-down mode
is activated. However, the contents of the DAC registers are
unaffected when in power-down mode. The DAC registers can
be updated while the device is in power-down mode. The time
required to exit power-down is typically 2.5 µs for VDD = 5 V.
POWER-DOWN OPERATION
The AD5675 contains two separate power-down modes.
Command 0100 is designated for the power-down function (see
Table 9). These power-down modes are software programmable
by setting 16 bits, Bit DB15 to Bit DB0, in the input shift
register. There are two bits associated with each DAC channel.
Table 12 shows how the state of the two bits corresponds to the
mode of operation of the device.
LOAD DAC (HARDWARE LDAC PIN)
The AD5675 DACs have a double buffered interface consisting
of two banks of registers: input registers and DAC registers.
The user can write to any combination of the input registers.
Any or all DACs (DAC 0 to DAC 7) power down to the selected
mode by setting the corresponding bits. See Table 13 for the
contents of the input shift register during the power-down/
power-up operation.
LDAC
Updates to the DAC registers are controlled by the
pin.
LDAC
Instantaneous DAC Updating (
For instantaneous updating of the DACs,
Held Low)
Table 12. Modes of Operation
LDAC
is held low while
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
PD1
PD0
data is clocked into the input register using Command 0001. Both
the addressed input register and the DAC register are updated on
the 24th clock, and the output changes immediately.
0
0
0
1
1
1
LDAC
Deferred DAC Updating (
For deferred updating of the DACs,
is clocked into the input register using Command 0001. All DAC
is Pulsed Low)
Tristate
LDAC
is held high while data
When both Bit PD1 and Bit PD0 in the input shift register are
set to 0, the device works normally with its normal power
consumption of typically 1 mA at 5 V. However, for the two
power-down modes, the supply current falls to typically 1 µA.
In addition to this fall, the output stage switches internally from
the amplifier output to a resistor network of known values.
Therefore, the DAC channel output impedance is defined when
the channel is powered down. There are two different power-
down options. The output is connected internally to GND
through either a 1 kΩ resistor, or it is left open circuited
(tristate). The output stage is shown in Figure 45.
LDAC
outputs are asynchronously updated by pulling
low after the
th
LDAC
24 clock. The update occurs on the falling edge of
.
AMPLIFIER
16-BIT
DAC
V
V
x
REF
OUT
DAC
REGISTER
LDAC
INPUT
REGISTER
AMPLIFIER
V
x
DAC
OUT
SCL
SDA
INTERFACE
LOGIC
Figure 46. Simplified Diagram of Input Loading Circuitry for a Single DAC
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 45. Output Stage During Power-Down
Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation
DAC 7
DAC 6
DAC 5
DAC 4
DAC 3
DAC 2
DAC 1
DAC 0
[DB23:DB20]
DB19 [DB18:DB16]
XXX1
[DB15:DB14] [DB13:DB12] [DB11:DB10] [DB9:DB8] [DB7:DB6] [DB5:DB4] [DB3:DB2] [DB1:DB0]
0100
0
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
[PD1:PD0]
1 X means don’t care.
Rev. C | Page 22 of 27
Data Sheet
AD5675
LDAC
The
over the hardware
(DB0 to DB7) to 0 for a DAC channel means that the update for
LDAC
register gives the user extra flexibility and control
LDAC MASK REGISTER
LDAC LDAC
pin (see Table 15). Setting the
bits
LDAC
Command 0101 is reserved for this hardware
function.
The address bits are ignored. Writing to the DAC using
LDAC
this channel is controlled by the hardware
pin.
Command 0101 loads the 8-bit
The default for each channel is 0, that is, the
normally. Setting the bits to 1 forces this DAC channel to ignore
LDAC
register (DB7 to DB0).
LDAC
pin works
transitions on the
pin, regardless of the state of the
pin. This flexibility is useful in applications
where the user wants to select which channels respond to
LDAC
hardware
LDAC
the
pin.
LDAC
LDAC
Bits (DB7 to DB0)
Table 14.
Overwrite Definition
Load Register
Pin
Operation
LDAC
LDAC
LDAC
Determined by the LDAC pin.
DAC channels update and override the LDAC pin. DAC channels see LDAC as 1.
00000000
11111111
1 or 0
X1
1 X means don’t care.
1
LDAC
Table 15. Write Commands and
Pin Truth Table
Hardware
Pin State
LDAC
Command Description
Input Register Contents
Data update
Data update
DAC Register Contents
No change (no update)
Data update
0001
0010
Write to Input Register n
(dependent on LDAC)
VLOGIC
GND2
VLOGIC
GND
Update DAC Register n
with the contents of
Input Register n
No change
Updated with input register contents
Updated with input register contents
No change
0011
Write to and update DAC VLOGIC
Channel n
Data update
Data update
Data update
Data update
GND
1
LDAC
A high to low hardware
pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
mask register.
is permanently tied low, the
LDAC
(blocked) by the
2
LDAC
LDAC
mask bits are ignored.
When
Rev. C | Page 23 of 27
AD5675
Data Sheet
HARDWARE RESET (RESET)
SOFTWARE RESET
A software executable reset function is also available, which
resets the DAC to the power-on reset code. Command 0110 is
designated for this software reset function. The DAC address
bits must be set to 0x0 and the data bits set to 0x1234 for the
software reset command to execute.
RESET
The
be cleared to either zero scale or midscale. The clear code value
RESET
pin is an active low reset that allows the outputs to
is user selectable via the RSTSEL pin. Keep
minimum of 2 µs to complete the operation (see Table 4). When
RESET
low for a
the
cleared value until a new value is programmed. While
RESET
signal is returned high, the output remains at the
AMPLIFIER GAIN SELECTION ON LFCSP PACKAGE
the
value. Any events on
RESET
pin is low, the outputs cannot be updated with a new
The output amplifier gain setting for the LFCSP package is
determined by the state of Bit DB2 in the gain setup register
(see Table 16 and Table 17).
LDAC RESET
or
during power-on reset
are ignored. If the
pin is pulled low at power-up, the
device does not initialize correctly until the pin is released.
Table 16. Gain Setup Register
RESET SELECT PIN (RSTSEL)
Bit
Description
The AD5675 contains a power-on reset circuit that controls the
output voltage during power-up. By connecting the RSTSEL pin
low, the output powers up to zero scale. Note that this power-up
is outside the linear region of the DAC; by connecting the
RSTSEL pin high, the VOUTx pins power up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC.
DB2
Amplifier gain setting
DB2 = 0; amplifier gain = 1 (default)
DB2 = 1; amplifier gain = 2
Table 17. 24-Bit Input Shift Register Contents for Gain Setup Command
DB23 (MSB)
DB22
DB21
DB20
DB19 to DB3
DB2
DB1
DB0 (LSB)
Reserved; set to 0
0
1
1
1
Don’t care
Gain
Reserved; set to 0
Rev. C | Page 24 of 27
Data Sheet
AD5675
APPLICATIONS INFORMATION
series inductance (ESI), such as the common ceramic types,
POWER SUPPLY RECOMMENDATIONS
which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
The AD5675 is typically powered by the following supplies: VDD
= 3.3 V and VLOGIC = 1.8 V.
The ADP7118 can be used to power the VDD pin. The ADP160
can be used to power the VLOGIC pin. This setup is shown in
Figure 47. The ADP7118 can operate from input voltages up to
20 V. The ADP160 can operate from input voltages up to 5.5 V.
In systems where many devices are on one board, it is often
useful to provide some heat sinking capability to allow the
power to dissipate easily.
The GND plane on the device can be increased (as shown in
Figure 49) to provide a natural heat sinking effect.
5V
INPUT
ADP7118
LDO
3.3V: V
DD
ADP160
LDO
AD5675
1.8V: V
LOGIC
Figure 47. Low Noise Power Solution for the AD5675
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5675 is performed via a
serial bus that uses a standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 2-wire interface consisting of a clock signal
and a data signal.
GND
PLANE
BOARD
AD5675 TO ADSP-BF531 INTERFACE
Figure 49. Pad Connection to Board
The I2C interface of the AD5675 is designed for easy connection
to industry-standard DSPs and microcontrollers. Figure 48
shows the AD5675 connected to the Analog Devices, Inc.,
Blackfin® processor. The Blackfin processor has an integrated
I2C port that can be connected directly to the I2C pins of the
AD5675.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. iCoupler®
products from Analog Devices provide voltage isolation in
excess of 2.5 kV. The serial loading structure of the AD5675
makes the device ideal for isolated interfaces because the
number of interface lines is kept to a minimum. Figure 50
shows a 4-channel isolated interface to the AD5675 using
an ADuM1251. For further information, visit
AD5675
ADSP-BF531
GPIO1
GPIO2
SCL
SDA
www.analog.com/icoupler.
PF9
PF8
LDAC
ADuM12511
CONTROLLER
RESET
DECODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
Figure 48. AD5675 to ADSP-BF531 Interface
SDA
SCL
TO SDA
TO SCL
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. Design the PCB on which the
AD5675 is mounted so that the device lies on the analog plane.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 50. Isolated Interface
The AD5675 must have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply, located as close to the package
as possible, ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
must have low effective series resistance (ESR) and low effective
Rev. C | Page 25 of 27
AD5675
Data Sheet
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 51. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
16
20
0.50
BSC
1
15
2.75
2.60 SQ
2.35
EXPOSED
PAD
5
11
10
6
0.50
0.40
0.30
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11.
Figure 52. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
Rev. C | Page 26 of 27
Data Sheet
AD5675
ORDERING GUIDE
Resolution Temperature
Package
Option
Model1
(Bits)
Range
Accuracy
Package Description
AD5675ARUZ
AD5675ARUZ-REEL7
AD5675BRUZ
AD5675BRUZ-REEL7
AD5675ACPZ-REEL7
AD5675ACPZ-RL
AD5675BCPZ-REEL7
AD5675BCPZ-RL
EVAL-AD5675SDZ
16
16
16
16
16
16
16
16
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8 LSB INL 20-Lead Thin Shrink Small Outline Package [TSSOP]
8 LSB INL 20-Lead Thin Shrink Small Outline Package [TSSOP]
3 LSB INL 20-Lead Thin Shrink Small Outline Package [TSSOP]
3 LSB INL 20-Lead Thin Shrink Small Outline Package [TSSOP]
8 LSB INL 20-Lead Lead Frame Chip Scale Package [LFCSP]
8 LSB INL 20-Lead Lead Frame Chip Scale Package [LFCSP]
3 LSB INL 20-Lead Lead Frame Chip Scale Package [LFCSP]
3 LSB INL 20-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
RU-20
RU-20
RU-20
RU-20
CP-20-8
CP-20-8
CP-20-8
CP-20-8
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12550-0-4/18(C)
Rev. C | Page 27 of 27
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