AD5676BRUZ-REEL7 [ADI]
Easy implementation;
| 型号： | AD5676BRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Easy implementation |
| 文件： | 总28页 (文件大小：1054K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Octal, 16-Bit nanoDAC+ with SPI Interface
Data Sheet
AD5676
FEATURES
GENERAL DESCRIPTION
High performance
The AD5676 is a low power, octal, 16-bit buffered voltage
High relative accuracy (INL): 3 LSB maximum at 16 bits
Total unadjusted error (TUE): 0.14% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.06% of FSR maximum
Wide operating ranges
output digital-to-analog converter (DAC). The device includes
a gain select pin, giving a full-scale output of VREF (gain = 1) or
2 × VREF (gain = 2). The AD5676 DAC operates from a single
2.7 V to 5.5 V supply and is guaranteed monotonic by design.
The AD5676 is available in 20-lead TSSOP and LFCSP packages.
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/gain bit)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
The internal power-on reset circuit and the RSTSEL pin of the
AD5676 ensure that the output DACs power up to zero scale or
midscale and then remain there until a valid write takes place. The
AD5676 contains a per channel power-down mode that typically
reduces the current consumption of the device to 1 µA.
The AD5676 employs a versatile serial peripheral interface (SPI)
that operates at clock rates up to 50 MHz, and contains a VLOGIC pin
intended for 1.8 V to 5.5 V logic.
50 MHz SPI with readback or daisy chain
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead, TSSOP and LFCSP RoHS-compliant packages
Table 1. Octal nanoDAC+® Devices
APPLICATIONS
Interface
Reference
Internal
External
Internal
External
16-Bit
12-Bit
Optical transceivers
SPI
AD5676R
AD5676
AD5675R
AD5675
AD5672R
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Not applicable
AD5671R
I2C
Not applicable
Data acquisition systems
PRODUCT HIGHLIGHTS
1. High relative accuracy (INL) 16-bit: 3 LSB maximum.
2. −40°C to +125°C temperature range.
3. 20-lead, TSSOP and LFCSP RoHS-compliant packages.
FUNCTIONAL BLOCK DIAGRAM
V
V
V
REF
LOGIC
DD
AD5676
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
DAC
STRING
DAC 0
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
REGISTER
REGISTER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 1
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
SCLK
SYNC
SDI
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 3
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 4
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 5
SDO
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 6
LDAC
RESET
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 7
POWER-DOWN
LOGIC
POWER-ON RESET
GAIN x1/x2
GAIN
RSTSEL
GND
Figure 1.
Rev. B
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AD5676* Product Page Quick Links
Last Content Update: 11/01/2016
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frequently modified.
AD5676
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Standalone Operation................................................................ 21
Write and Update Commands.................................................. 21
Daisy-Chain Operation ............................................................. 21
Readback Operation .................................................................. 22
Power-Down Operation............................................................ 22
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Daisy-Chain and Readback Timing Characteristics ............... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
Digital-to-Analog Converter .................................................... 19
Transfer Function ....................................................................... 19
DAC Architecture....................................................................... 19
Serial Interface ............................................................................ 20
LDAC
Load DAC (Hardware
Pin)........................................... 23
Mask Register ................................................................. 23
Hardware Reset ( ) .......................................................... 24
LDAC
RESET
Reset Select Pin (RSTSEL) ........................................................ 24
Amplifier Gain Selection on LFCSP Package......................... 24
Applications Information .............................................................. 25
Power Supply Recommendations............................................. 25
Microprocessor Interfacing....................................................... 25
AD5676 to ADSP-BF531 Interface .......................................... 25
AD5676 to SPORT Interface..................................................... 25
Layout Guidelines....................................................................... 25
Galvanically Isolated Interface ................................................. 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
10/15—Rev. A to Rev. B
Changes to Readback Operation Section.................................... 22
Added 20-Lead LFCSP.......................................................Universal
Changes to Features Section, General Description Section,
Table 1, Product Highlights Section, and Figure 1....................... 1
Changes to Table 2 ............................................................................ 3
Deleted Figure 5; Renumbered Sequentially................................. 8
Change to Table 5 ............................................................................. 8
Added Table 6; Renumbered Sequentially .................................... 8
Change to Table 7 ............................................................................. 9
Added Figure 6 and Table 8........................................................... 10
Change to Figure 10 to Figure 12 ................................................. 11
Change to Figure 13 to Figure 18 ................................................. 12
Changes to Figure 19, Figure 20, and Figure 22 ......................... 13
Change to Figure 25, Figure 28, and Figure 30........................... 14
Change to Figure 31, Figure 34, Figure 35, and Figure 36 ........ 15
Change to Figure 37 and Figure 38 .............................................. 16
Changes to Transfer Function Section and Output Amplifiers
Section.............................................................................................. 19
Change to Table 9 ........................................................................... 20
Changes to Write to and Update DAC Channel n (Independent
Changes to
Mask Register Section and Table 14............ 23
LDAC
Changes to Reset Select Pin (RSTSEL) Section.......................... 24
Added Amplifier Gain Selection on LFCSP Section, Table 16,
and Table 17 .................................................................................... 24
Added Figure 53, Outline Dimensions........................................ 27
Changes to Ordering Guide.......................................................... 27
2/15—Rev. 0 to Rev. A
Changes to Table 2.............................................................................3
RESET
Change to
Pulse Activation Time Parameter, Table 4.....6
Change to Terminology Section................................................... 17
Changes to Transfer Function Section and Output Amplifiers
Section.............................................................................................. 19
RESET
Changes to Hardware Reset (
) Section............................ 24
Changes to Ordering Guide .......................................................... 27
10/14—Revision 0: Initial Version
of
) Section ........................................................................... 21
LDAC
Rev. B | Page 2 of 27
Data Sheet
AD5676
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications −40°C to +125°C, unless otherwise noted.
Table 2.
A Grade
Typ
B Grade
Typ
Parameter
STATIC PERFORMANCE1
Min
Max
Min
Max
Unit
Test Conditions/Comments
Resolution
16
16
Bits
LSB
LSB
LSB
Relative Accuracy (INL)2
1.8
1.7
0.7
8
8
1
1.8
1.7
0.7
3
3
1
Gain = 1
Gain = 2
Gain = 1
Differential Nonlinearity
(DNL)2
0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
+0.03
+0.006
1
1
4
6
4
0.28
0.14
0.24
0.12
0.3
0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
+0.03
+0.006
1
1
1.6
2
1.5
0.14
0.07
0.12
0.06
0.18
0.14
LSB
mV
mV
mV
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Zero Code Error2
Offset Error2
Gain = 2
Full-Scale Error2
% of FSR Gain = 1
% of FSR Gain = 2
% of FSR Gain = 1
% of FSR Gain = 2
% of FSR Gain = 1
% of FSR Gain = 2
µV/°C
Gain Error2
Total Unadjusted Error (TUE)
Offset Error Drift2, 3
0.25
DC Power Supply Rejection
0.25
0.25
mV/V
DAC code = midscale, VDD = 5 V
10%
Due to single channel, full-
scale output change
Ratio (PSRR)2, 3
DC Crosstalk2, 3
2
2
µV
3
2
3
2
µV/mA
µV
Due to load current change
Due to powering down (per
channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
0
VREF
2 × VREF
15
0
0
VREF
2 × VREF
15
V
V
mA
nF
Gain = 1
Gain = 2
Output Current Drive
Capacitive Load Stability
2
2
RL = ∞
10
10
nF
kΩ
µV/mA
RL = 1 kΩ
Resistive Load4
Load Regulation
1
1
183
177
183
177
5 V 10%, DAC code = midscale,
−30 mA ≤ IOUT ≤ +30 mA
3 V 10%, DAC code = midscale,
−20 mA ≤ IOUT ≤ +20 mA
µV/mA
Short-Circuit Current5
Load Impedance at Rails6
Power-Up Time
40
25
2.5
40
25
2.5
mA
Ω
µs
Exiting power-down mode,
VDD = 5 V
REFERENCE INPUT
Reference Input Current
398
789
398
789
µA
µA
V
V
kΩ
kΩ
VREF = VDD = VLOGIC = 5.5 V, gain = 1
VREF = VDD = VLOGIC = 5.5 V, gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Reference Input Range
1
1
VDD
VDD/2
1
1
VDD
VDD/2
Reference Input Impedance
14
7
14
7
Rev. B | Page 3 of 27
AD5676
Data Sheet
A Grade
Typ
B Grade
Typ
Parameter
Min
Max
Min
Max
Unit
Test Conditions/Comments
LOGIC INPUTS3
Input Current
Input Voltage
Low, VINL
1
1
µA
Per pin
0.3 ×
VLOGIC
0.3 ×
VLOGIC
V
High, VINH
0.7 ×
VLOGIC
0.7 ×
VLOGIC
V
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Voltage
Low, VOL
3
4
3
4
pF
0.4
0.4
V
V
ISINK = 200 μA
ISOURCE = 200 μA
High, VOH
VLOGIC
0.4
−
VLOGIC
0.4
−
Floating State Output
Capacitance
pF
POWER REQUIREMENTS
VLOGIC
ILOGIC
1.8
5.5
3
3
3
3
1.8
5.5
3
3
3
3
V
µA
µA
µA
µA
V
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
VDD
2.7
VREF
1.5
5.5
5.5
2.7
VREF
1.5
5.5
5.5
+
+
V
Gain = 2
IDD
Normal Mode7
1.1
1.1
1
1.26
1.3
1.7
1.1
1.1
1
1.26
1.3
1.7
mA
mA
µA
−40°C to +85°C
−40°C to +105°C
Three-state, −40°C to +85°C
All Power-Down Modes8
1
1.7
1
1.7
µA
Power down to 1 kΩ, −40°C to
+85°C
1
1
2.5
2.5
1
1
2.5
2.5
µA
µA
Three-state, −40°C to +105°C
Power down to 1 kΩ, −40°C to
+105°C
1
1
5.5
5.5
1
1
5.5
5.5
µA
µA
Three-state, −40°C to +125°C
Power down to 1 kΩ, −40°C to
+125°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2 See the Terminology section.
3 Guaranteed by design and characterization; not production tested.
4 Channel 0, Channel 1, Channel 2, and Channel 3 can together source/sink 40 mA. Similarly, Channel 4, Channel 5, Channel 6, and Channel 7 can together source/sink
40 mA up to a junction temperature of 125°C.
5 VDD = 5 V. The AD5676 includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
7 Interface inactive. All DACs active. DAC outputs unloaded.
8 All DACs powered down.
Rev. B | Page 4 of 27
Data Sheet
AD5676
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 1.8 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless otherwise
noted. Guaranteed by design and characterization, not production tested.
Table 3.
Parameter
Output Voltage Settling Time1
Min Typ
Max Unit
Test Conditions/Comments
5
8
µs
¼ to ¾ scale settling to 2 LSB
Slew Rate
0.8
1.4
0.13
0.1
V/µs
Digital-to-Analog Glitch Impulse1
Digital Feedthrough1
Digital Crosstalk1
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
dB
1 LSB change around major carry, gain = 1
Analog Crosstalk1
−0.25
Gain = 1
Gain = 2
−1.3
−2.0
−80
300
6
90
83
80
DAC-to-DAC Crosstalk1
Total Harmonic Distortion (THD)1, 2
Output Noise Spectral Density (NSD)1
Output Noise
TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
nV/√Hz DAC code = midscale, bandwidth = 10 kHz, gain = 2
µV p-p
dB
dB
dB
0.1 Hz to 10 Hz, gain = 1
Signal-to-Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
Signal-to-Noise-and-Distortion Ratio (SINAD)
TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = 1 kHz
1 See the Terminology section.
2 Digitally generated sine wave at 1 kHz.
Rev. B | Page 5 of 27
AD5676
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
DD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V, all specifications −40°C to +125°C, unless otherwise noted.
V
Table 4.
1.8 V ≤ VLOGIC < 2.7 V
Symbol Min Max
2.7 V ≤ VLOGIC ≤ 5.5 V
Parameter1
Min
20
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
t1
20
t2
4
1.7
4.3
t3
4.5
t4
15.1
0.8
10.1
0.8
−0.8
1.25
6.75
9.7
t5
Data Hold Time
t6
t7
+0.1
0.95
9.65
4.75
4.85
41.25
26.35
4.8
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single, Combined, or All Channel Update)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
t8
t9
t10
t11
t12
t13
t14
5.45
25
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
Power-Up Time2
20.3
6.2
132
5.15
80
5.18
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
2 Time to exit power-down to normal mode of AD5676 operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
t9
t1
SCLK
t2
t8
t7
t3
t4
SYNC
SDI
t6
t5
DB23
DB0
t12
t10
1
LDAC
t11
2
LDAC
t13
RESET
t14
V
x
OUT
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. B | Page 6 of 27
Data Sheet
AD5676
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4.
DD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V, all specifications −40°C to +125°C, unless otherwise noted.
V
Table 5.
1.8 V ≤ VLOGIC < 2.7 V
Min Max
2.7 V ≤ VLOGIC ≤ 5.5 V
Min Max
Parameter1
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t10
t11
120
33
2.8
83.3
25.3
3.25
50
75
1.2
0.3
16.2
55.1
21.5
24.4
0.5
0.4
13
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SDO Data Valid from SCLK Rising Edge
SCLK Falling Edge to SYNC Rising Edge
45
22.7
20.3
SYNC Rising Edge to SCLK Rising Edge
t12
85.5
54
ns
1 Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit Diagram and Daisy-Chain and Readback Timing Diagrams
200µA
I
OL
TO OUTPUT
PIN
V
(MIN)
OH
C
L
20pF
200µA
I
OH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
24
48
t11
t8
t12
t4
SYNC
SDI
t6
t5
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t10
DB23
DB0
SDO
UNDEFINED
Figure 4. Daisy-Chain Timing Diagram
Rev. B | Page 7 of 27
AD5676
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
The design of the thermal board requires close attention. Thermal
resistance is highly impacted by the printed circuit board (PCB)
being used, layout, and environmental conditions.
Table 5.
Parameter
Rating
VDD to GND
VLOGIC to GND
VOUTx to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak Temperature,
Pb-Free (J-STD-020)
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +125°C
−65°C to +150°C
125°C
Table 6. Thermal Resistance
Package Type
θJA
θJB
θJC
ΨJT
ΨJB
Unit
20-Lead TSSOP
(RU-20)1
98.65 44.39 17.58 1.77 43.9
°C/W
20-Lead LFCSP
(CP-20-8)2
82
16.67 32.5
0.43 22
°C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51
260°C
2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD51.
ESD Ratings
Human Body Model (HBM)
2 kV
Field-Induced Charged Device Model
(FICDM)
1.5 kV
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 8 of 27
Data Sheet
AD5676
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
20
19
18
17
16
15
14
13
12
11
V
1
V
2
OUT
OUT
2
V
0
V
3
OUT
OUT
REF
3
V
V
DD
AD5676
4
V
RESET
SDO
LOGIC
TOP VIEW
(Not to Scale)
5
SYNC
SCLK
SDI
6
LDAC
RSTSEL
GND
7
8
GAIN
9
V
7
V
V
4
OUT
OUT
OUT
OUT
10
V
6
5
Figure 5. 20-Lead TSSOP Pin Configuration
Table 7. 20-Lead TSSOP Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
VOUT
VOUT
VDD
1
0
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
Power Supply Input. The AD5676 operates from 2.7 V to 5.5 V. Decouple VDD with a 10 µF capacitor in parallel with
a 0.1 µF capacitor to GND.
4
5
VLOGIC
SYNC
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data
transfers in on the falling edges of the next 24 clocks.
6
7
8
SCLK
SDI
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
transfers at rates of up to 50 MHz.
Serial Data Input. The AD5676 has a 24-bit input shift register. Data is clocked into the register on the falling edge
of the serial clock input.
GAIN
Span Set. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC,
all eight DACs output a span of 0 V to 2 × VREF
.
9
VOUT
VOUT
VOUT
VOUT
GND
RSTSEL
7
6
5
4
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Device.
10
11
12
13
14
Power-On Reset. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to power up all
eight DACs to midscale.
15
LDAC
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all
DAC registers to be updated if the input registers have new data. This allows all DAC outputs to update
simultaneously. This pin can also be tied permanently low.
16
17
SDO
Serial Data Output. Use this pin to daisy-chain a number of devices together, or use it for readback. The serial data
transfers on the rising edge of SCLK and is valid on the falling edge.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are
ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale,
depending on the state of the RSTSEL pin.
RESET
18
19
20
VREF
VOUT
VOUT
Reference Input Voltage.
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
3
2
Rev. B | Page 9 of 27
AD5676
Data Sheet
15
V
REF
V
1
2
3
4
5
DD
14 RESET
13 SDO
V
LOGIC
AD5676
TOP VIEW
(Not to Scale)
SYNC
SCLK
SDI
12 LDAC
11 GND
NIC = NOT INTERNALLY CONNECTED
Figure 6. 20-Lead LFCSP Pin Configuration
Table 8. 20-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD
Power Supply Input. The AD5676 operate from 2.7 V to 5.5 V. Decouple VDD with a 10 µF capacitor in parallel with a
0.1 µF capacitor to GND.
2
3
VLOGIC
SYNC
Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data
transfers in on the falling edges of the next 24 clocks.
4
5
SCLK
SDI
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
transfers at rates of up to 50 MHz.
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.
6
7
8
9
VOUT
VOUT
VOUT
VOUT
NIC
7
6
5
4
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
Not Internally Connected
10, 16
11
GND
Ground Reference Point for All Circuitry on the Device.
12
LDAC
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all
DAC registers to be updated if the input registers have new data. That allows all DAC outputs to simultaneously
update. This pin can also be tied permanently low.
13
14
SDO
Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for
readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored.
When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending
on the state of the RSTSEL pin.
RESET
15
17
18
19
20
VREF
Reference Input Voltage.
VOUT
VOUT
VOUT
VOUT
3
2
1
0
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
EPAD
Rev. B | Page 10 of 27
Data Sheet
AD5676
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
10
8
1.5
1.0
6
4
0.5
2
0
0
–2
–4
–6
–8
–10
–0.5
–1.0
–1.5
–2.0
V
= 5V
= 25°C
= 2.5V
DD
T
A
V
REF
0
10000
20000
30000
40000
50000
60000
70000
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
CODE
Figure 7. INL Error vs. Code
Figure 10. INL Error vs. Temperature
1.0
10
8
0.8
0.6
6
0.4
4
0.2
2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
–10
V
= 5V
= 25°C
= 2.5V
DD
T
A
V
REF
0
10000
20000
30000
40000
50000
60000
70000
–40
–20
0
20
40
60
80
100
120
CODE
TEMPERATURE (°C)
Figure 8. DNL Error vs. Code
Figure 11. DNL Error vs. Temperature
0.04
0.03
0.02
0.01
0
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
V
= 5V
= 25°C
= 2.5V
DD
T
A
V
REF
–0.01
–0.02
–40
–20
0
20
40
60
80
100
120
0
10000
20000
30000
40000
50000
60000
70000
TEMPERATURE (°C)
CODE
Figure 12. TUE vs. Temperature
Figure 9. TUE vs. Code
Rev. B | Page 11 of 27
AD5676
Data Sheet
10
0.10
0.08
0.06
0.04
0.02
0
V
= 5V
= 25°C
DD
8
6
T
A
V
= 2.5V
REF
4
2
FULL-SCALE ERROR
GAIN ERROR
0
–2
–4
–6
–8
–10
–0.02
–0.04
–0.06
–0.08
–0.10
V
= 5V
= 25°C
DD
T
A
V
= 2.5V
REF
–40
–20
0
20
40
60
80
100
120
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 13. INL Error vs. Supply Voltage
Figure 16. Gain Error and Full-Scale Error vs. Temperature
10
8
0.10
0.08
0.06
0.04
0.02
0
V
= 5V
= 25°C
= 2.5V
DD
T
A
V
6
REF
4
2
GAIN ERROR
0
–2
–4
–6
–8
–10
–0.02
–0.04
–0.06
–0.08
–0.10
FULL-SCALE ERROR
V
= 5V
= 25°C
= 2.5V
DD
T
A
V
REF
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage
Figure 14. DNL Error vs. Supply Voltage
1.8
0.10
V
= 5V
DD
0.08
0.06
0.04
0.02
0
1.5
1.2
0.9
0.6
0.3
0
T = 25°C
A
V
= 2.5V
REF
ZERO CODE ERROR
–0.02
–0.04
–0.06
–0.08
–0.10
OFFSET ERROR
V
= 5V
= 25°C
= 2.5V
DD
–0.3
T
A
V
REF
–0.6
–40
–20
0
20
40
60
80
100
120
2.7
3.2
3.7
4.2
4.7
5.2
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 18. Zero Code Error and Offset Error vs. Temperature
Figure 15. TUE vs. Supply Voltage
Rev. B | Page 12 of 27
Data Sheet
AD5676
6
5
1.5
1.0
0.5
0
ZERO CODE ERROR
4
3
OFFSET ERROR
2
1
–0.5
0
V
T
V
= 5V
= 25°C
V
T
= 5V
–1.0
DD
DD
= 25°C
0xFFFF
0xC000
0x8000
0x4000
0x0000
–1
A
A
GAIN = 2
= 2.5V
REF
V
= 2.5V
REF
–1.5
–2
2.7
3.2
3.7
4.2
4.7
5.2
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
SUPPLY VOLTAGE (V)
LOAD CURRENT (A)
Figure 19. Zero Code Error and Offset Error vs. Supply Voltage
Figure 22. Source and Sink Capability at 5 V
120
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
T
= 3V
0xFFFF
0xC000
0x8000
0x4000
0x0000
DD
= 25°C
V
T
V
= 5V
= 25°C
DD
A
GAIN = 1
A
100
80
60
40
20
0
= 2.5V
V
= 2.5V
REF
REF
–0.5
–1.0
0.83 0.85 0.87 0.89 0.91 0.93 0.95 0.97 0.99 1.01
FULL SCALE (mA)
–
0.06
–0.04
–0.02
0
0.02
0.04
0.06
I
DD
LOAD CURRENT (A)
Figure 20. IDD Histogram with External Reference
Figure 23. Source and Sink Capability at 3 V
1.4
1.0
1.6
1.5
1.4
1.3
1.2
1.1
1.0
DEVICE 1
DEVICE 2
DEVICE 3
0.6
0.2
–0.2
–0.6
–1.0
–1.4
SINKING –2.7V
SINKING –3V
SINKING –5V
SOURCING –5V
SOURCING –3V
SOURCING –2.7V
0
10000
20000
30000
40000
50000
60000
70000
0
0.005
0.010
0.015
0.020
0.025
0.030
CODE
LOAD CURRENT (A)
Figure 24. Supply Current (IDD) vs. Code
Figure 21. Headroom/Footroom (∆VOUT) vs. Load Current
Rev. B | Page 13 of 27
AD5676
Data Sheet
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
FULL SCALE
ZERO CODE
EXTERNAL REFERENCE, FULL SCALE
V
= 5V
DD
GAIN = 1
T
= 25°C
= 2.5V
A
V
REF
1/4 TO 3/4 SCALE
0.4
–40
80
100
120
140
160 180
200
–20
0
20
40
60
80
100
120
TIME (µs)
TEMPERATURE (°C)
Figure 25. Supply Current (IDD) vs. Temperature
Figure 28. Full-Scale Settling Time
0.006
0.005
0.004
0.003
0.002
0.001
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
6
5
V
V
V
V
V
V
V
V
V
(V)
DD
0 (V)
1 (V)
2 (V)
3 (V)
4 (V)
5 (V)
6 (V)
7 (V)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
4
FULL SCALE
3
ZERO CODE
2
1
EXTERNAL REFERENCE, FULL SCALE
0
–1
–0.001
0.010
0.4
2.7
0
0.002
0.004
0.006
0.008
3.2
3.7
4.2
4.7
5.2
TIME (Seconds)
LOGIC INPUT VOLTAGE (V)
Figure 26. Supply Current (IDD) vs. Supply Voltage
Figure 29. Power-On Reset to 0 V and Midscale
3.00
2.50
2.00
1.50
1.00
0.50
0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
MIDSCALE, GAIN = 2
FULL SCALE
SYNC
ZERO CODE
MIDSCALE, GAIN = 1
EXTERNAL REFERENCE, FULL SCALE
V
= 5V
DD
T
= 25°C
A
V
= 2.5V
REF
0.4
2.7
3.2
3.7
4.2
4.7
5.2
–5
0
5
10
LOGIC INPUT VOLTAGE (V)
TIME (µs)
Figure 27. Supply Current (IDD) vs. Logic Input Voltage
Figure 30. Exiting Power-Down to Midscale
Rev. B | Page 14 of 27
Data Sheet
AD5676
0.004
0.003
0.002
0.001
0
1
–0.001
–0.002
–0.003
V
= 5V
DD
GAIN = 1
T
= 25°C
A
V
= 2.5V
REF
CODE = 0x7FFF TO 0x8000
ENERGY = 1.209376nV-sec
–0.004
CH1 5µV
M1.0sec
A CH1
401mV
15
16
17
18
19
20
21
22
TIME (µs)
Figure 31. Digital-to-Analog Glitch Impulse
Figure 34. 0.1 Hz to 10 Hz Output Noise
0.003
1200
V
= 5V
= 25°C
DD
0.002
0.001
0
T
A
1000
800
600
400
200
0
GAIN = 1
= 2.5V
V
REF
FULL SCALE
MIDSCALE
ZERO SCALE
–0.001
–0.002
–0.003
–0.004
–0.005
–0.006
ATTACK CHANNEL 1
ATTACK CHANNEL 2
ATTACK CHANNEL 3
ATTACK CHANNEL 4
ATTACK CHANNEL 5
ATTACK CHANNEL 6
ATTACK CHANNEL 7
0
2
4
6
8
10
12
14
16
18
20
10
100
1k
10k
100k
1M
TIME (µs)
FREQUENCY (Hz)
Figure 35. Noise Spectral Density (NSD)
Figure 32. Analog Crosstalk
0
–20
0.012
0.010
V
T
= 5V
= 25°C
= 2.5V
DD
ATTACK CHANNEL 1
ATTACK CHANNEL 2
ATTACK CHANNEL 3
ATTACK CHANNEL 4
ATTACK CHANNEL 5
ATTACK CHANNEL 6
ATTACK CHANNEL 7
A
V
REF
0.008
0.006
0.004
0.002
–40
–60
–80
0
–100
–120
–140
–160
–180
–0.002
–0.004
–0.006
–0.008
–0.010
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
TIME (µs)
Figure 36. THD at 1 kHz
Figure 33. DAC-to-DAC Crosstalk
Rev. B | Page 15 of 27
AD5676
Data Sheet
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.3
3
2
1
0
0nF
0.1nF
1nF
RESET
4.7nF
10nF
0.2
MIDSCALE, GAIN = 1
0.1
V
= 5V
DD
GAIN = 1
= 25°C
T
A
V
= 2.5V
REF
ZERO SCALE, GAIN = 1
0
60
0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20
–20
0
20
40
TIME (ms)
TIME (µs)
Figure 37. Settling Time vs. Capacitive Load
Figure 39. Hardware Reset
2.0
0
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–10
–20
–30
V
T
= 5V
= 25°C
DD
V
= 5.5V
A
DD
GAIN = 1
= 25°C
EXTERNAL REFERENCE = 2.5V, ±0.1V
GAIN = 1
p-p
T
A
V
= 2.5V
REF
V
= FULL SCALE
OUT
1/4 TO 3/4 SCALE
80
100
120
140
160
180
200
1K
10K
100K
FREQUENCY (Hz)
1M
10M
TIME (µs)
Figure 38. Settling Time, 5.5 V
Figure 40. Multiplying Bandwidth, External Reference
Rev. B | Page 16 of 27
Data Sheet
AD5676
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000).
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of 1 LSB maximum ensures monotonicity. The AD5676
is guaranteed monotonic by design.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
is 0 V. The zero code error is always positive because the output
of the DAC cannot go below 0 V due to a combination of the offset
errors in the DAC and the output amplifier. Zero code error is
expressed in mV.
Noise Spectral Density (NSD)
NSD is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range (% of FSR).
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed i n μ V.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another DAC.
It is measured in standalone mode and is expressed in nV-sec.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured with Code 256
loaded in the DAC register. It can be negative or positive.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. To
measure analog crosstalk, load one of the input registers with a full-
scale code change (all 0s to all 1s and vice versa). Then, execute
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
the change in VDD for full-scale output of the DAC. It is measured
in mV/V. VREF is held at 2 V, and VDD is varied by 10%.
LDAC
a software
and monitor the output of the DAC whose digital
code was not changed. The area of the glitch is expressed in nV-sec.
DAC-to-DAC Crosstalk
Output Voltage Settling Time
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa), using the write to and update
commands while monitoring the output of the victim channel
that is at midscale. The energy of the glitch is expressed in nV-sec.
Output voltage settling time is the amount of time it takes for the
output of a DAC to settle to a specified level for a ¼ to ¾ full-scale
SYNC
input change and is measured from the rising edge of
.
Rev. B | Page 17 of 27
AD5676
Data Sheet
Multiplying Bandwidth
Total Harmonic Distortion (THD)
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference with full-scale code loaded to the DAC appears on the
output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. THD is measured in
decibels.
Rev. B | Page 18 of 27
Data Sheet
AD5676
THEORY OF OPERATION
Figure 42 shows the simplified segmented resistor string DAC
structure. The code loaded to the DAC register determines the
switch on the string that is connected to the output buffer.
DIGITAL-TO-ANALOG CONVERTER
The AD5676 is an octal 16-bit, serial input, voltage output DAC.
The device operates from supply voltages of 2.7 V to 5.5 V. Data
is written to the AD5676 in a 24-bit word format via a 3-wire
serial interface. The AD5676 incorporates a power-on reset
circuit to ensure that the DAC output powers up to a known
output state. The device also has a software power-down mode that
reduces the typical current consumption to typically 1 µA.
Because each resistance in the string has the same value, R, the
string DAC is guaranteed monotonic.
V
REF
R
R
TRANSFER FUNCTION
The gain of the output amplifier can be set to ×1 or ×2 using the
gain select pin (GAIN) on the TSSOP package or the gain bit on
the LFCSP package. When the GAIN pin is tied to GND, all eight
DAC outputs have a span from 0 V to VREF. When the GAIN pin
TO OUTPUT
R
AMPLIFIER
is tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF
When using the LFCSP package, the gain bit in the gain setup
register is used to set the gain of the output amplifier. The gain
bit is 0 by default. When the gain bit is 0 the output span of all
eight DACs is 0 V to VREF. When the gain bit is 1 the output
.
R
R
span of all eight DACs is 0 V to 2 × VREF. The gain bit is ignored
on the TSSOP package.
DAC ARCHITECTURE
Figure 42. Simplified Resistor String Structure
The DAC architecture implements a segmented string DAC
with an internal output buffer. Figure 41 shows the internal
block diagram.
Output Amplifiers
The output buffer amplifier generates rail-to-rail voltages on its
output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the gain setting, the offset error,
and the gain error.
V
REF
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
x
OUT
The output amplifiers can drive a load of 1 kΩ in parallel with
10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾
scale settling time of 5 µs.
REF (–)
GAIN
(GAIN = 1 OR 2)
GND
Figure 41. Single DAC Channel Architecture Block Diagram
Rev. B | Page 19 of 27
AD5676
Data Sheet
Table 9. Command Bit Definitions
Command
SERIAL INTERFACE
SYNC
The AD5676 has a 3-wire serial interface (
, SCLK, and
C3 C2 C1 C0 Description
SDI) that is compatible with SPI, QSPI™, and MICROWIRE
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence. The AD5676 contains
an SDO pin that allows the user to daisy chain multiple devices
together (see the Daisy-Chain Operation section) or for readback.
0
0
0
0
0
0
0
1
No operation
Write to Input Register n (where n = 1 to 8,
depending on the DAC selected from the
address bits in Table 10), dependent
on LDAC
0
0
1
0
Update the DAC register with contents of
Input Register n
Write to and update DAC Channel n
Power down/power up the DAC
Hardware LDAC mask register
Input Shift Register
The input shift register of the AD5676 is 24 bits wide. Data
is loaded MSB first (DB23), and the first four bits are the
command bits, C3 to C0 (see Table 9), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 10), and finally, the 16-
bit data-word.
0
0
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
Software reset (power-on reset)
Gain setup register (LFCSP package only)
Set up the DCEN register (daisy-chain
enable)
Set up the readback register (readback
enable)
Update all channels of the input register
simultaneously with the input data
The data-word comprises 16-bit input code, followed by zero, two,
or four don’t care bits. These data bits are transferred to the input
register on the 24 falling edges of SCLK and are updated on the
SYNC
1
1
1
0
0
0
0
1
1
1
0
1
rising edge of
.
Commands execute on individual DAC channels, combined DAC
channels, or on all DACs, depending on the address bits selected.
Update all channels of the DAC register
and input register simultaneously with
the input data
1
1
0
0
Reserved
…
1
…
1
…
1
…
1
Reserved
Table 10. Address Bits and Selected DACs
Address Bits
Selected Output DAC
Channel1
A3
0
A2
0
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1 Any combination of DAC channels can be selected using the address bits.
DB23 (MSB)
DB0 (LSB)
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 43. Input Shift Register Content
Rev. B | Page 20 of 27
Data Sheet
AD5676
STANDALONE OPERATION
AD5676
68HC11*
SYNC
The write sequence begins by bringing the
from the SDI line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of the 24 data bits is
line low. Data
SDI
MOSI
SCK
PC7
PC6
SCLK
SYNC
LDAC
SYNC
clocked in, bring
high. The programmed function is then
LDAC
executed, that is, an
dependent change in the DAC
SDO
SDI
MISO
register contents and/or a change in the mode of operation
occurs.
th
SYNC
If
is taken high at a clock before the 24 clock, it is
AD5676
considered a valid frame, and invalid data may be loaded to the
SYNC
DAC. Bring
channel, see t8 in Table 4) before the next write sequence so that
SYNC
high for a minimum of 9.65 ns (single
SCLK
SYNC
LDAC
a falling edge of
can initiate the next write sequence.
at the rails between write sequences for even lower
SYNC
SYNC
Idle
power operation. The
of SCLK, and the DAC is updated on the rising edge of
When data is transferred into the input register of the addressed
LDAC
SDO
SDI
line is kept low for 24 falling edges
SYNC
.
AD5676
DAC, all DAC registers and outputs update by taking
SYNC
low
while the
line is high.
SCLK
SYNC
LDAC
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on
)
LDAC
SDO
Command 0001 allows the user to write to the dedicated input
LDAC
register for each DAC individually. When
input register is transparent (if not controlled by the
mask register).
is low, the
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. Daisy-Chaining the AD5676
Update DAC Register with Contents of Input Register n
The SCLK pin is continuously applied to the input shift register
SYNC
when
is low. If more than 24 clock pulses are applied, the
Command 0010 loads the DAC registers and outputs with the
contents of the selected input registers and updates the DAC
outputs directly.
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting this line to the
SDI input on the next DAC in the chain, a daisy-chain interface is
constructed. Each DAC in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,
Write to and Update DAC Channel n (Independent of
)
LDAC
Command 0011 allows the user to write to the DAC registers
and updates the DAC outputs directly. Bit D7 to Bit D0
determine which DACs have data from the input register
transferred to the DAC register. Setting a bit to 1 transfers data
from the input register to the appropriate DAC register.
SYNC
where N is the total number of devices updated. If
is
taken high at a clock that is not a multiple of 24, it is considered
a valid frame, and invalid data may be loaded to the DAC.
SYNC
When the serial transfer to all devices is complete,
goes
DAISY-CHAIN OPERATION
high, which latches the input data in each device in the daisy
chain and prevents any further data from being clocked into the
input shift register. The serial clock can be continuous or a gated
For systems that contain several DACs, the SDO pin can daisy
chain several devices together and is enabled through a software
executable daisy-chain enable (DCEN) command. Command 1000
is reserved for this DCEN function (see Table 9). The daisy-chain
mode is enabled by setting Bit DB0 in the DCEN register. The
default setting is standalone mode, where DB0 = 0. Table 11
shows how the state of the bit corresponds to the mode of
operation of the device.
SYNC
clock. If
is held low for the correct number of clock
cycles, a continuous SCLK source is used. In gated clock mode,
use a burst clock containing the exact number of clock cycles,
SYNC
and take
high after the final clock to latch the data.
Table 11. Daisy-Chain Enable (DCEN) Register
DB0
Description
0
1
Standalone mode (default)
DCEN mode
Rev. B | Page 21 of 27
AD5676
Data Sheet
Table 12. Modes of Operation
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
READBACK OPERATION
PD1
PD0
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisy-
chain mode disable bit in the control register, it is enabled
automatically for the duration of the read operation, after which
it is disabled again. Command 1001 is reserved for the readback
function. This command, in association with the address bits,
A3 to A0, selects the DAC input register to read. Note that,
during readback, only one DAC register can be selected. The
remaining data bits in the write sequence are don’t care bits.
During the next SPI write, the data appearing on the SDO output
contains the data from the previously addressed register.
0
0
0
1
1
1
Three-State
Any or all DACs (DAC 0 to DAC 7) power down to the selected
mode by setting the corresponding bits. See Table 13 for the
contents of the input shift register during the power-down/
power-up operation.
When both Bit PD1 and Bit PD0 in the input shift register are set to
0, the device works normally with its normal power consumption
of 1.1 mA typically. However, for the two power-down modes,
the supply current falls to 1 µA typically. Not only does the
supply current fall, but the output stage is also internally switched
from the output of the amplifier to a resistor network of known
values. This has the advantage that the output impedance of the
devices are known while the devices are in power-down mode.
There are two different power-down options. The output is
connected internally to GND through either a 1 kΩ resistor, or
it is left open-circuited (three-state). The output stage is shown in
Figure 45.
For example, to read back the DAC register for Channel 0,
implement the following sequence:
1. Write 0x900000 to the AD5676 input register. This
configures the device for read mode with the DAC register
of Channel 0 selected. Note that all data bits, DB15 to DB0,
are don’t care bits.
2. Follow this with a second write, a no operation (NOP)
condition, 0x000000. During this write, the data from the
register is clocked out on the SDO line. DB23 to DB20
contain undefined data, and the last 16 bits contain the
DB19 to DB4 DAC register contents.
AMPLIFIER
When
is high the SDO pin is driven by a weak latch
V
x
OUT
SYNC
DAC
which holds the last data bit. The SDO pin can be overdriven by
the SDO pin of another device, thus allowing multiple devices
to be read using the same SPI interface.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
POWER-DOWN OPERATION
The AD5676 provides two separate power-down modes.
Command 0100 is designated for the power-down function (see
Table 9). These power-down modes are software programmable
by setting 16 bits, Bit DB15 to Bit DB0, in the input shift register.
There are two bits associated with each DAC channel. Table 12
shows how the state of the two bits corresponds to the mode of
operation of the device.
Figure 45. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry shut down when power-down mode is
activated. However, the contents of the DAC register are
unaffected when in power-down. The DAC register updates
while the device is in power-down mode. The time required to
exit power-down is typically 5 µs for VDD = 5 V.
Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1
DAC 7
DAC 6
DAC 5
DAC 4
DAC 3
DAC 2
DAC 1
DAC 0
[DB23:DB20] DB19 [DB18:DB16] [DB15: B14]
[DB13: B12]
[PD1:PD0]
[DB11: B10]
[PD1:PD0]
[DB9:DB8]
[PD1:PD0]
[DB7:DB6]
[PD1:PD0]
[DB5:DB4]
[PD1:PD0]
[DB3:DB2]
[PD1:PD0]
[DB1:DB0]
[PD1:PD0]
0100
0
XXX
[PD1:PD0]
1 X means don’t care.
Rev. B | Page 22 of 27
Data Sheet
AD5676
LOAD DAC (HARDWARE LDAC PIN)
LDAC MASK REGISTER
The AD5676 DAC has a double buffered interface consisting of
two banks of registers: input registers and DAC registers. The
user can write to any combination of the input registers.
LDAC
function.
Address bits are ignored. Writing to the DAC using
Command 0101 is reserved for this hardware
LDAC
Command 0101 loads the 8-bit
register (DB7 to DB0).
LDAC
Updates to the DAC register are controlled by the
pin.
LDAC
The default for each channel is 0; that is, the
normally. Setting the bits to 1 forces this DAC channel to ignore
LDAC
pin works
OUTPUT
AMPLIFIER
transitions on the
pin, regardless of the state of the
pin. This flexibility is useful in applications
where the user wants to select which channels respond to
16-BIT
DAC
V
REF
V
x
OUT
LDAC
hardware
DAC
REGISTER
LDAC
the
pin.
LDAC
LDAC
Table 14.
Overwrite Definition
Load LDAC Register
INPUT
REGISTER
LDAC Bits
(DB7 to DB0)
00000000
LDAC Pin LDAC Operation
SCLK
SYNC
SDI
1 or 0
X1
Determined by the LDAC pin.
INTERFACE
LOGIC
SDO
11111111
DAC channels update and
override the LDAC pin. DAC
channels see LDAC as 1.
Figure 46. Simplified Diagram of Input Loading Circuitry for a Single DAC
LDAC
Instantaneous DAC Updating (
Held Low)
is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
1 X means don’t care.
LDAC
LDAC
The
register gives the user extra flexibility and control
LDAC
LDAC
pin (see Table 14). Setting the
over the hardware
bits (DB0 to DB7) to 0 for a DAC channel means that the
update for this channel is controlled by the hardware
SYNC
the DAC register are updated on the rising edge of
the output begins to change (see Table 15).
and
LDAC
pin.
LDAC
Deferred DAC Updating (
is Pulsed Low)
is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
LDAC SYNC
LDAC
updated by taking
update occurs on the falling edge of
low after
is taken high. The
LDAC
.
1
LDAC
Table 15. Write Commands and
Pin Truth Table
Hardware LDAC Pin State
Command Description
Input Register Contents DAC Register Contents
0001
0010
Write to Input Register n
(dependent on LDAC)
VLOGIC
GND2
VLOGIC
GND
Data update
Data update
No change
No change
No change (no update)
Data update
Update the DAC register
with contents of Input
Register n
Updated with input register contents
Updated with input register contents
0011
Write to and update DAC
Channel n
VLOGIC
GND
Data update
Data update
Data update
Data update
1
LDAC
A high to low hardware
pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
mask register.
is permanently tied low, the
LDAC
(blocked) by the
2
LDAC
LDAC
mask bits are ignored.
When
Rev. B | Page 23 of 27
AD5676
Data Sheet
The RSTSEL pin is only available on the TSSOP package. When
the AD5676 LFCSP package is used the outputs power up to 0 V.
HARDWARE RESET (
)
RESET
RESET
The
be cleared to either zero scale or midscale. The clear code value
RESET
pin is an active low reset that allows the outputs to
AMPLIFIER GAIN SELECTION ON LFCSP PACKAGE
is user selectable via the
select pin. It is necessary to keep
pin low for a minimum time (see Table 4) to complete
RESET
The output amplifier gain setting for the LFCSP package is
determined by the state of Bit DB2 in the Gain setup register
(see Table 16 and Table 17).
RESET
the
the operation (see Figure 2). When the
high, the output remains at the cleared value until a new value is
RESET
signal is returned
Table 16. Gain Setup Register
programmed. While the
pin is low, the outputs cannot be
Bit
Description
updated with a new value. A software executable reset function
is also available that resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function
(see Table 9). Any events on the
power-on reset are ignored.
DB2
Amplifier gain setting
DB2 = 0; amplifier gain = 1 (default)
DB2 = 1; amplifier gain = 2
LDAC RESET
or
pins during
RESET SELECT PIN (RSTSEL)
The AD5676 contains a power-on reset circuit that controls the
output voltage during power-up. By connecting the RSTSEL pin
low, the output powers up to zero scale. Note that this is outside
the linear region of the DAC; by connecting the RSTSEL pin
high, VOUTx power up to midscale. The output remains powered
up at this level until a valid write sequence is made to the DAC.
Table 17. 24-Bit Input Shift Register Contents for Gain Setup Command
DB23 (MSB)
DB22
DB21
DB20
DB19 to DB3
DB2
DB1
DB0 (LSB)
Reserved; set to 0
0
1
1
1
Don’t care
Gain
Reserved; set to 0
Rev. B | Page 24 of 27
Data Sheet
AD5676
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
AD5676 TO SPORT INTERFACE
The AD5676 is typically powered by the following supplies: VDD
3.3 V and VLOGIC = 1.8 V.
=
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 49 shows how a SPORT interface controls the AD5676.
The ADP7118 can be used to power the VDD pin. The ADP160
can be used to power the VLOGIC pin. This setup is shown in
Figure 47. The ADP7118 can operate from input voltages up to
20 V. The ADP160 can operate from input voltages up to 5.5 V.
AD5676
ADSP-BF527
SPORT_TFS
SPORT_TSCK
SPORT_DTO
SYNC
SCLK
SDI
ADP7118
3.3V: V
5V INPUT
DD
LDO
GPIO0
GPIO1
LDAC
ADP160
LDO
1.8V: V
LOGIC
RESET
Figure 47. Low Noise Power Solution for the AD5676
Figure 49. SPORT Interface
MICROPROCESSOR INTERFACING
LAYOUT GUIDELINES
Microprocessor interfacing to the AD5676 is via a serial bus
that uses a standard protocol that is compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire or 4-wire interface consisting of a clock signal,
a data signal, and a synchronization signal. The AD5676 requires a
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. Design the printed circuit board (PCB) on
which the AD5676 is mounted so that the AD5676 lies on the
analog plane.
SYNC
24-bit data-word with data valid on the rising edge of
.
The AD5676 must have ample supply bypassing of 10 μF in
parallel with 0.1 μF on each supply, located as close to the package
as possible, ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. The 0.1 μF capacitor
must have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
AD5676 TO ADSP-BF531 INTERFACE
The SPI interface of the AD5676 can easily connect to industry-
standard DSPs and microcontrollers. Figure 48 shows the
AD5676 connected to the Analog Devices, Inc. Blackfin® DSP.
The Blackfin has an integrated SPI port that can connect
directly to the SPI pins of the AD5676.
In systems where many devices are on one board, it is often useful
to provide some heat sinking capability to allow the power to
dissipate easily.
AD5676
ADSP-BF531
The GND plane on the device can be increased (as shown in
Figure 50) to provide a natural heat sinking effect.
SPISELx
SCK
SYNC
SCLK
SDI
MOSI
AD5676
PF9
PF8
LDAC
RESET
Figure 48. ADSP-BF531 Interface
GND
PLANE
BOARD
Figure 50. Pad Connection to Board
Rev. B | Page 25 of 27
AD5676
Data Sheet
ADuM14001
CONTROLLER
GALVANICALLY ISOLATED INTERFACE
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
TO
SERIAL
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. iCoupler®
products from Analog Devices provide voltage isolation in excess
of 2.5 kV. The serial loading structure of the AD5676 makes the
device ideal for isolated interfaces because the number of interface
lines is kept to a minimum. Figure 51 shows a 4-channel
isolated interface to the AD5676 using an ADuM1400. For
further information, visit www.analog.com/icoupler.
ENCODE
DECODE
DECODE
DECODE
DECODE
SCLK
CLOCK IN
TO
SDI
SERIAL
DATA OUT
ENCODE
ENCODE
ENCODE
TO
SYNC
SYNC OUT
LOAD DAC
OUT
TO
LDAC
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 51. Isolated Interface
Rev. B | Page 26 of 27
Data Sheet
AD5676
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 52. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.75
2.60 SQ
2.35
11
5
6
BOTTOM VIEW
10
0.50
0.40
0.30
0.25 MIN
TOP VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 53. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model1
Resolution
Accuracy
8 LSB INL
8 LSB INL
3 LSB INL
3 LSB INL
8 LSB INL
8 LSB INL
3 LSB INL
8 LSB INL
Package Description
AD5676ARUZ
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
RU-20
AD5676ARUZ-REEL7
AD5676BRUZ
RU-20
RU-20
AD5676BRUZ-REEL7
AD5676ACPZ-REEL7
AD5676ACPZ-RL
AD5676BCPZ-REEL7
AD5676BCPZ-RL
EVAL-AD5676SDZ
RU-20
CP-20-8
CP-20-8
CP-20-8
CP-20-8
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12549-0-10/15(B)
Rev. B | Page 27 of 27
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SI9137LG
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SI9122E
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